netxen_nic_init.c 31 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  163. rds_ring = &recv_ctx->rds_rings[ring];
  164. if (rds_ring->rx_buf_arr) {
  165. vfree(rds_ring->rx_buf_arr);
  166. rds_ring->rx_buf_arr = NULL;
  167. }
  168. }
  169. tx_ring = &adapter->tx_ring;
  170. if (tx_ring->cmd_buf_arr)
  171. vfree(tx_ring->cmd_buf_arr);
  172. return;
  173. }
  174. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  175. {
  176. struct netxen_recv_context *recv_ctx;
  177. struct nx_host_rds_ring *rds_ring;
  178. struct nx_host_sds_ring *sds_ring;
  179. struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
  180. struct netxen_rx_buffer *rx_buf;
  181. int ring, i, num_rx_bufs;
  182. struct netxen_cmd_buffer *cmd_buf_arr;
  183. struct net_device *netdev = adapter->netdev;
  184. struct pci_dev *pdev = adapter->pdev;
  185. tx_ring->num_desc = adapter->num_txd;
  186. cmd_buf_arr =
  187. (struct netxen_cmd_buffer *)vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  188. if (cmd_buf_arr == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  194. tx_ring->cmd_buf_arr = cmd_buf_arr;
  195. recv_ctx = &adapter->recv_ctx;
  196. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  197. rds_ring = &recv_ctx->rds_rings[ring];
  198. switch (ring) {
  199. case RCV_RING_NORMAL:
  200. rds_ring->num_desc = adapter->num_rxd;
  201. if (adapter->ahw.cut_through) {
  202. rds_ring->dma_size =
  203. NX_CT_DEFAULT_RX_BUF_LEN;
  204. rds_ring->skb_size =
  205. NX_CT_DEFAULT_RX_BUF_LEN;
  206. } else {
  207. rds_ring->dma_size = RX_DMA_MAP_LEN;
  208. rds_ring->skb_size =
  209. MAX_RX_BUFFER_LENGTH;
  210. }
  211. break;
  212. case RCV_RING_JUMBO:
  213. rds_ring->num_desc = adapter->num_jumbo_rxd;
  214. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  215. rds_ring->dma_size =
  216. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  217. else
  218. rds_ring->dma_size =
  219. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  220. rds_ring->skb_size =
  221. rds_ring->dma_size + NET_IP_ALIGN;
  222. break;
  223. case RCV_RING_LRO:
  224. rds_ring->num_desc = adapter->num_lro_rxd;
  225. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  226. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  227. break;
  228. }
  229. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  230. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  231. if (rds_ring->rx_buf_arr == NULL) {
  232. printk(KERN_ERR "%s: Failed to allocate "
  233. "rx buffer ring %d\n",
  234. netdev->name, ring);
  235. /* free whatever was already allocated */
  236. goto err_out;
  237. }
  238. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  239. INIT_LIST_HEAD(&rds_ring->free_list);
  240. /*
  241. * Now go through all of them, set reference handles
  242. * and put them in the queues.
  243. */
  244. num_rx_bufs = rds_ring->num_desc;
  245. rx_buf = rds_ring->rx_buf_arr;
  246. for (i = 0; i < num_rx_bufs; i++) {
  247. list_add_tail(&rx_buf->list,
  248. &rds_ring->free_list);
  249. rx_buf->ref_handle = i;
  250. rx_buf->state = NETXEN_BUFFER_FREE;
  251. rx_buf++;
  252. }
  253. spin_lock_init(&rds_ring->lock);
  254. }
  255. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  256. sds_ring = &recv_ctx->sds_rings[ring];
  257. sds_ring->irq = adapter->msix_entries[ring].vector;
  258. sds_ring->adapter = adapter;
  259. sds_ring->num_desc = adapter->num_rxd;
  260. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  261. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  262. }
  263. return 0;
  264. err_out:
  265. netxen_free_sw_resources(adapter);
  266. return -ENOMEM;
  267. }
  268. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  269. {
  270. switch (adapter->ahw.port_type) {
  271. case NETXEN_NIC_GBE:
  272. adapter->enable_phy_interrupts =
  273. netxen_niu_gbe_enable_phy_interrupts;
  274. adapter->disable_phy_interrupts =
  275. netxen_niu_gbe_disable_phy_interrupts;
  276. adapter->macaddr_set = netxen_niu_macaddr_set;
  277. adapter->set_mtu = netxen_nic_set_mtu_gb;
  278. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  279. adapter->phy_read = netxen_niu_gbe_phy_read;
  280. adapter->phy_write = netxen_niu_gbe_phy_write;
  281. adapter->init_port = netxen_niu_gbe_init_port;
  282. adapter->stop_port = netxen_niu_disable_gbe_port;
  283. break;
  284. case NETXEN_NIC_XGBE:
  285. adapter->enable_phy_interrupts =
  286. netxen_niu_xgbe_enable_phy_interrupts;
  287. adapter->disable_phy_interrupts =
  288. netxen_niu_xgbe_disable_phy_interrupts;
  289. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  290. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  291. adapter->init_port = netxen_niu_xg_init_port;
  292. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  293. adapter->stop_port = netxen_niu_disable_xg_port;
  294. break;
  295. default:
  296. break;
  297. }
  298. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  299. adapter->set_mtu = nx_fw_cmd_set_mtu;
  300. adapter->set_promisc = netxen_p3_nic_set_promisc;
  301. }
  302. }
  303. /*
  304. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  305. * address to external PCI CRB address.
  306. */
  307. static u32 netxen_decode_crb_addr(u32 addr)
  308. {
  309. int i;
  310. u32 base_addr, offset, pci_base;
  311. crb_addr_transform_setup();
  312. pci_base = NETXEN_ADDR_ERROR;
  313. base_addr = addr & 0xfff00000;
  314. offset = addr & 0x000fffff;
  315. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  316. if (crb_addr_xform[i] == base_addr) {
  317. pci_base = i << 20;
  318. break;
  319. }
  320. }
  321. if (pci_base == NETXEN_ADDR_ERROR)
  322. return pci_base;
  323. else
  324. return (pci_base + offset);
  325. }
  326. static long rom_max_timeout = 100;
  327. static long rom_lock_timeout = 10000;
  328. static int rom_lock(struct netxen_adapter *adapter)
  329. {
  330. int iter;
  331. u32 done = 0;
  332. int timeout = 0;
  333. while (!done) {
  334. /* acquire semaphore2 from PCI HW block */
  335. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  336. if (done == 1)
  337. break;
  338. if (timeout >= rom_lock_timeout)
  339. return -EIO;
  340. timeout++;
  341. /*
  342. * Yield CPU
  343. */
  344. if (!in_atomic())
  345. schedule();
  346. else {
  347. for (iter = 0; iter < 20; iter++)
  348. cpu_relax(); /*This a nop instr on i386 */
  349. }
  350. }
  351. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  352. return 0;
  353. }
  354. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  355. {
  356. long timeout = 0;
  357. long done = 0;
  358. cond_resched();
  359. while (done == 0) {
  360. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  361. done &= 2;
  362. timeout++;
  363. if (timeout >= rom_max_timeout) {
  364. printk("Timeout reached waiting for rom done");
  365. return -EIO;
  366. }
  367. }
  368. return 0;
  369. }
  370. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  371. {
  372. /* release semaphore2 */
  373. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  374. }
  375. static int do_rom_fast_read(struct netxen_adapter *adapter,
  376. int addr, int *valp)
  377. {
  378. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  379. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  380. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  381. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  382. if (netxen_wait_rom_done(adapter)) {
  383. printk("Error waiting for rom done\n");
  384. return -EIO;
  385. }
  386. /* reset abyte_cnt and dummy_byte_cnt */
  387. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  388. udelay(10);
  389. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  390. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  391. return 0;
  392. }
  393. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  394. u8 *bytes, size_t size)
  395. {
  396. int addridx;
  397. int ret = 0;
  398. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  399. int v;
  400. ret = do_rom_fast_read(adapter, addridx, &v);
  401. if (ret != 0)
  402. break;
  403. *(__le32 *)bytes = cpu_to_le32(v);
  404. bytes += 4;
  405. }
  406. return ret;
  407. }
  408. int
  409. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  410. u8 *bytes, size_t size)
  411. {
  412. int ret;
  413. ret = rom_lock(adapter);
  414. if (ret < 0)
  415. return ret;
  416. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  417. netxen_rom_unlock(adapter);
  418. return ret;
  419. }
  420. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  421. {
  422. int ret;
  423. if (rom_lock(adapter) != 0)
  424. return -EIO;
  425. ret = do_rom_fast_read(adapter, addr, valp);
  426. netxen_rom_unlock(adapter);
  427. return ret;
  428. }
  429. #define NETXEN_BOARDTYPE 0x4008
  430. #define NETXEN_BOARDNUM 0x400c
  431. #define NETXEN_CHIPNUM 0x4010
  432. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  433. {
  434. int addr, val;
  435. int i, n, init_delay = 0;
  436. struct crb_addr_pair *buf;
  437. unsigned offset;
  438. u32 off;
  439. /* resetall */
  440. rom_lock(adapter);
  441. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  442. netxen_rom_unlock(adapter);
  443. if (verbose) {
  444. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  445. printk("P2 ROM board type: 0x%08x\n", val);
  446. else
  447. printk("Could not read board type\n");
  448. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  449. printk("P2 ROM board num: 0x%08x\n", val);
  450. else
  451. printk("Could not read board number\n");
  452. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  453. printk("P2 ROM chip num: 0x%08x\n", val);
  454. else
  455. printk("Could not read chip number\n");
  456. }
  457. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  458. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  459. (n != 0xcafecafe) ||
  460. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  461. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  462. "n: %08x\n", netxen_nic_driver_name, n);
  463. return -EIO;
  464. }
  465. offset = n & 0xffffU;
  466. n = (n >> 16) & 0xffffU;
  467. } else {
  468. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  469. !(n & 0x80000000)) {
  470. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  471. "n: %08x\n", netxen_nic_driver_name, n);
  472. return -EIO;
  473. }
  474. offset = 1;
  475. n &= ~0x80000000;
  476. }
  477. if (n < 1024) {
  478. if (verbose)
  479. printk(KERN_DEBUG "%s: %d CRB init values found"
  480. " in ROM.\n", netxen_nic_driver_name, n);
  481. } else {
  482. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  483. " initialized.\n", __func__, n);
  484. return -EIO;
  485. }
  486. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  487. if (buf == NULL) {
  488. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  489. netxen_nic_driver_name);
  490. return -ENOMEM;
  491. }
  492. for (i = 0; i < n; i++) {
  493. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  494. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  495. kfree(buf);
  496. return -EIO;
  497. }
  498. buf[i].addr = addr;
  499. buf[i].data = val;
  500. if (verbose)
  501. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  502. netxen_nic_driver_name,
  503. (u32)netxen_decode_crb_addr(addr), val);
  504. }
  505. for (i = 0; i < n; i++) {
  506. off = netxen_decode_crb_addr(buf[i].addr);
  507. if (off == NETXEN_ADDR_ERROR) {
  508. printk(KERN_ERR"CRB init value out of range %x\n",
  509. buf[i].addr);
  510. continue;
  511. }
  512. off += NETXEN_PCI_CRBSPACE;
  513. /* skipping cold reboot MAGIC */
  514. if (off == NETXEN_CAM_RAM(0x1fc))
  515. continue;
  516. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  517. /* do not reset PCI */
  518. if (off == (ROMUSB_GLB + 0xbc))
  519. continue;
  520. if (off == (ROMUSB_GLB + 0xa8))
  521. continue;
  522. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  523. continue;
  524. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  525. continue;
  526. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  527. continue;
  528. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  529. buf[i].data = 0x1020;
  530. /* skip the function enable register */
  531. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  532. continue;
  533. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  534. continue;
  535. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  536. continue;
  537. }
  538. if (off == NETXEN_ADDR_ERROR) {
  539. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  540. netxen_nic_driver_name, buf[i].addr);
  541. continue;
  542. }
  543. init_delay = 1;
  544. /* After writing this register, HW needs time for CRB */
  545. /* to quiet down (else crb_window returns 0xffffffff) */
  546. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  547. init_delay = 1000;
  548. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  549. /* hold xdma in reset also */
  550. buf[i].data = NETXEN_NIC_XDMA_RESET;
  551. buf[i].data = 0x8000ff;
  552. }
  553. }
  554. NXWR32(adapter, off, buf[i].data);
  555. msleep(init_delay);
  556. }
  557. kfree(buf);
  558. /* disable_peg_cache_all */
  559. /* unreset_net_cache */
  560. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  561. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  562. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  563. }
  564. /* p2dn replyCount */
  565. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  566. /* disable_peg_cache 0 */
  567. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  568. /* disable_peg_cache 1 */
  569. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  570. /* peg_clr_all */
  571. /* peg_clr 0 */
  572. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  573. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  574. /* peg_clr 1 */
  575. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  576. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  577. /* peg_clr 2 */
  578. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  579. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  580. /* peg_clr 3 */
  581. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  582. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  583. return 0;
  584. }
  585. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  586. {
  587. uint64_t addr;
  588. uint32_t hi;
  589. uint32_t lo;
  590. adapter->dummy_dma.addr =
  591. pci_alloc_consistent(adapter->pdev,
  592. NETXEN_HOST_DUMMY_DMA_SIZE,
  593. &adapter->dummy_dma.phys_addr);
  594. if (adapter->dummy_dma.addr == NULL) {
  595. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  596. __func__);
  597. return -ENOMEM;
  598. }
  599. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  600. hi = (addr >> 32) & 0xffffffff;
  601. lo = addr & 0xffffffff;
  602. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  603. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  604. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  605. uint32_t temp = 0;
  606. NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp);
  607. }
  608. return 0;
  609. }
  610. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  611. {
  612. int i = 100;
  613. if (!adapter->dummy_dma.addr)
  614. return;
  615. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  616. do {
  617. if (dma_watchdog_shutdown_request(adapter) == 1)
  618. break;
  619. msleep(50);
  620. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  621. break;
  622. } while (--i);
  623. }
  624. if (i) {
  625. pci_free_consistent(adapter->pdev,
  626. NETXEN_HOST_DUMMY_DMA_SIZE,
  627. adapter->dummy_dma.addr,
  628. adapter->dummy_dma.phys_addr);
  629. adapter->dummy_dma.addr = NULL;
  630. } else {
  631. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  632. adapter->netdev->name);
  633. }
  634. }
  635. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  636. {
  637. u32 val = 0;
  638. int retries = 60;
  639. if (!pegtune_val) {
  640. do {
  641. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  642. if (val == PHAN_INITIALIZE_COMPLETE ||
  643. val == PHAN_INITIALIZE_ACK)
  644. return 0;
  645. msleep(500);
  646. } while (--retries);
  647. if (!retries) {
  648. pegtune_val = NXRD32(adapter,
  649. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  650. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  651. "pegtune_val=%x\n", pegtune_val);
  652. return -1;
  653. }
  654. }
  655. return 0;
  656. }
  657. static int
  658. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  659. {
  660. u32 val = 0;
  661. int retries = 2000;
  662. do {
  663. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  664. if (val == PHAN_PEG_RCV_INITIALIZED)
  665. return 0;
  666. msleep(10);
  667. } while (--retries);
  668. if (!retries) {
  669. printk(KERN_ERR "Receive Peg initialization not "
  670. "complete, state: 0x%x.\n", val);
  671. return -EIO;
  672. }
  673. return 0;
  674. }
  675. int netxen_init_firmware(struct netxen_adapter *adapter)
  676. {
  677. int err;
  678. err = netxen_receive_peg_ready(adapter);
  679. if (err)
  680. return err;
  681. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  682. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  683. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  684. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  685. if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) {
  686. adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
  687. }
  688. return err;
  689. }
  690. static void
  691. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  692. {
  693. u32 cable_OUI;
  694. u16 cable_len;
  695. u16 link_speed;
  696. u8 link_status, module, duplex, autoneg;
  697. struct net_device *netdev = adapter->netdev;
  698. adapter->has_link_events = 1;
  699. cable_OUI = msg->body[1] & 0xffffffff;
  700. cable_len = (msg->body[1] >> 32) & 0xffff;
  701. link_speed = (msg->body[1] >> 48) & 0xffff;
  702. link_status = msg->body[2] & 0xff;
  703. duplex = (msg->body[2] >> 16) & 0xff;
  704. autoneg = (msg->body[2] >> 24) & 0xff;
  705. module = (msg->body[2] >> 8) & 0xff;
  706. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  707. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  708. netdev->name, cable_OUI, cable_len);
  709. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  710. printk(KERN_INFO "%s: unsupported cable length %d\n",
  711. netdev->name, cable_len);
  712. }
  713. netxen_advert_link_change(adapter, link_status);
  714. /* update link parameters */
  715. if (duplex == LINKEVENT_FULL_DUPLEX)
  716. adapter->link_duplex = DUPLEX_FULL;
  717. else
  718. adapter->link_duplex = DUPLEX_HALF;
  719. adapter->module_type = module;
  720. adapter->link_autoneg = autoneg;
  721. adapter->link_speed = link_speed;
  722. }
  723. static void
  724. netxen_handle_fw_message(int desc_cnt, int index,
  725. struct nx_host_sds_ring *sds_ring)
  726. {
  727. nx_fw_msg_t msg;
  728. struct status_desc *desc;
  729. int i = 0, opcode;
  730. while (desc_cnt > 0 && i < 8) {
  731. desc = &sds_ring->desc_head[index];
  732. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  733. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  734. index = get_next_index(index, sds_ring->num_desc);
  735. desc_cnt--;
  736. }
  737. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  738. switch (opcode) {
  739. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  740. netxen_handle_linkevent(sds_ring->adapter, &msg);
  741. break;
  742. default:
  743. break;
  744. }
  745. }
  746. static int
  747. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  748. struct nx_host_rds_ring *rds_ring,
  749. struct netxen_rx_buffer *buffer)
  750. {
  751. struct sk_buff *skb;
  752. dma_addr_t dma;
  753. struct pci_dev *pdev = adapter->pdev;
  754. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  755. if (!buffer->skb)
  756. return 1;
  757. skb = buffer->skb;
  758. if (!adapter->ahw.cut_through)
  759. skb_reserve(skb, 2);
  760. dma = pci_map_single(pdev, skb->data,
  761. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  762. if (pci_dma_mapping_error(pdev, dma)) {
  763. dev_kfree_skb_any(skb);
  764. buffer->skb = NULL;
  765. return 1;
  766. }
  767. buffer->skb = skb;
  768. buffer->dma = dma;
  769. buffer->state = NETXEN_BUFFER_BUSY;
  770. return 0;
  771. }
  772. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  773. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  774. {
  775. struct netxen_rx_buffer *buffer;
  776. struct sk_buff *skb;
  777. buffer = &rds_ring->rx_buf_arr[index];
  778. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  779. PCI_DMA_FROMDEVICE);
  780. skb = buffer->skb;
  781. if (!skb)
  782. goto no_skb;
  783. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  784. adapter->stats.csummed++;
  785. skb->ip_summed = CHECKSUM_UNNECESSARY;
  786. } else
  787. skb->ip_summed = CHECKSUM_NONE;
  788. skb->dev = adapter->netdev;
  789. buffer->skb = NULL;
  790. no_skb:
  791. buffer->state = NETXEN_BUFFER_FREE;
  792. return skb;
  793. }
  794. static struct netxen_rx_buffer *
  795. netxen_process_rcv(struct netxen_adapter *adapter,
  796. int ring, int index, int length, int cksum, int pkt_offset,
  797. struct nx_host_sds_ring *sds_ring)
  798. {
  799. struct net_device *netdev = adapter->netdev;
  800. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  801. struct netxen_rx_buffer *buffer;
  802. struct sk_buff *skb;
  803. struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
  804. if (unlikely(index > rds_ring->num_desc))
  805. return NULL;
  806. buffer = &rds_ring->rx_buf_arr[index];
  807. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  808. if (!skb)
  809. return buffer;
  810. if (length > rds_ring->skb_size)
  811. skb_put(skb, rds_ring->skb_size);
  812. else
  813. skb_put(skb, length);
  814. if (pkt_offset)
  815. skb_pull(skb, pkt_offset);
  816. skb->protocol = eth_type_trans(skb, netdev);
  817. napi_gro_receive(&sds_ring->napi, skb);
  818. adapter->stats.no_rcv++;
  819. adapter->stats.rxbytes += length;
  820. return buffer;
  821. }
  822. #define netxen_merge_rx_buffers(list, head) \
  823. do { list_splice_tail_init(list, head); } while (0);
  824. int
  825. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  826. {
  827. struct netxen_adapter *adapter = sds_ring->adapter;
  828. struct list_head *cur;
  829. struct status_desc *desc;
  830. struct netxen_rx_buffer *rxbuf;
  831. u32 consumer = sds_ring->consumer;
  832. int count = 0;
  833. u64 sts_data;
  834. int opcode, ring, index, length, cksum, pkt_offset, desc_cnt;
  835. while (count < max) {
  836. desc = &sds_ring->desc_head[consumer];
  837. sts_data = le64_to_cpu(desc->status_desc_data[0]);
  838. if (!(sts_data & STATUS_OWNER_HOST))
  839. break;
  840. desc_cnt = netxen_get_sts_desc_cnt(sts_data);
  841. ring = netxen_get_sts_type(sts_data);
  842. if (ring > RCV_RING_JUMBO)
  843. goto skip;
  844. opcode = netxen_get_sts_opcode(sts_data);
  845. switch (opcode) {
  846. case NETXEN_NIC_RXPKT_DESC:
  847. case NETXEN_OLD_RXPKT_DESC:
  848. break;
  849. case NETXEN_NIC_RESPONSE_DESC:
  850. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  851. default:
  852. goto skip;
  853. }
  854. WARN_ON(desc_cnt > 1);
  855. index = netxen_get_sts_refhandle(sts_data);
  856. length = netxen_get_sts_totallength(sts_data);
  857. cksum = netxen_get_sts_status(sts_data);
  858. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  859. rxbuf = netxen_process_rcv(adapter, ring, index,
  860. length, cksum, pkt_offset, sds_ring);
  861. if (rxbuf)
  862. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  863. skip:
  864. for (; desc_cnt > 0; desc_cnt--) {
  865. desc = &sds_ring->desc_head[consumer];
  866. desc->status_desc_data[0] =
  867. cpu_to_le64(STATUS_OWNER_PHANTOM);
  868. consumer = get_next_index(consumer, sds_ring->num_desc);
  869. }
  870. count++;
  871. }
  872. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  873. struct nx_host_rds_ring *rds_ring =
  874. &adapter->recv_ctx.rds_rings[ring];
  875. if (!list_empty(&sds_ring->free_list[ring])) {
  876. list_for_each(cur, &sds_ring->free_list[ring]) {
  877. rxbuf = list_entry(cur,
  878. struct netxen_rx_buffer, list);
  879. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  880. }
  881. spin_lock(&rds_ring->lock);
  882. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  883. &rds_ring->free_list);
  884. spin_unlock(&rds_ring->lock);
  885. }
  886. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  887. }
  888. if (count) {
  889. sds_ring->consumer = consumer;
  890. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  891. }
  892. return count;
  893. }
  894. /* Process Command status ring */
  895. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  896. {
  897. u32 sw_consumer, hw_consumer;
  898. int count = 0, i;
  899. struct netxen_cmd_buffer *buffer;
  900. struct pci_dev *pdev = adapter->pdev;
  901. struct net_device *netdev = adapter->netdev;
  902. struct netxen_skb_frag *frag;
  903. int done = 0;
  904. struct nx_host_tx_ring *tx_ring = &adapter->tx_ring;
  905. if (!spin_trylock(&adapter->tx_clean_lock))
  906. return 1;
  907. sw_consumer = tx_ring->sw_consumer;
  908. barrier(); /* hw_consumer can change underneath */
  909. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  910. while (sw_consumer != hw_consumer) {
  911. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  912. if (buffer->skb) {
  913. frag = &buffer->frag_array[0];
  914. pci_unmap_single(pdev, frag->dma, frag->length,
  915. PCI_DMA_TODEVICE);
  916. frag->dma = 0ULL;
  917. for (i = 1; i < buffer->frag_count; i++) {
  918. frag++; /* Get the next frag */
  919. pci_unmap_page(pdev, frag->dma, frag->length,
  920. PCI_DMA_TODEVICE);
  921. frag->dma = 0ULL;
  922. }
  923. adapter->stats.xmitfinished++;
  924. dev_kfree_skb_any(buffer->skb);
  925. buffer->skb = NULL;
  926. }
  927. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  928. if (++count >= MAX_STATUS_HANDLE)
  929. break;
  930. }
  931. if (count) {
  932. tx_ring->sw_consumer = sw_consumer;
  933. smp_mb();
  934. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  935. netif_tx_lock(netdev);
  936. netif_wake_queue(netdev);
  937. smp_mb();
  938. netif_tx_unlock(netdev);
  939. }
  940. }
  941. /*
  942. * If everything is freed up to consumer then check if the ring is full
  943. * If the ring is full then check if more needs to be freed and
  944. * schedule the call back again.
  945. *
  946. * This happens when there are 2 CPUs. One could be freeing and the
  947. * other filling it. If the ring is full when we get out of here and
  948. * the card has already interrupted the host then the host can miss the
  949. * interrupt.
  950. *
  951. * There is still a possible race condition and the host could miss an
  952. * interrupt. The card has to take care of this.
  953. */
  954. barrier(); /* hw_consumer can change underneath */
  955. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  956. done = (sw_consumer == hw_consumer);
  957. spin_unlock(&adapter->tx_clean_lock);
  958. return (done);
  959. }
  960. void
  961. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  962. struct nx_host_rds_ring *rds_ring)
  963. {
  964. struct rcv_desc *pdesc;
  965. struct netxen_rx_buffer *buffer;
  966. int producer, count = 0;
  967. netxen_ctx_msg msg = 0;
  968. struct list_head *head;
  969. producer = rds_ring->producer;
  970. spin_lock(&rds_ring->lock);
  971. head = &rds_ring->free_list;
  972. while (!list_empty(head)) {
  973. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  974. if (!buffer->skb) {
  975. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  976. break;
  977. }
  978. count++;
  979. list_del(&buffer->list);
  980. /* make a rcv descriptor */
  981. pdesc = &rds_ring->desc_head[producer];
  982. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  983. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  984. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  985. producer = get_next_index(producer, rds_ring->num_desc);
  986. }
  987. spin_unlock(&rds_ring->lock);
  988. if (count) {
  989. rds_ring->producer = producer;
  990. NXWR32(adapter, rds_ring->crb_rcv_producer,
  991. (producer-1) & (rds_ring->num_desc-1));
  992. if (adapter->fw_major < 4) {
  993. /*
  994. * Write a doorbell msg to tell phanmon of change in
  995. * receive ring producer
  996. * Only for firmware version < 4.0.0
  997. */
  998. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  999. netxen_set_msg_privid(msg);
  1000. netxen_set_msg_count(msg,
  1001. ((producer - 1) &
  1002. (rds_ring->num_desc - 1)));
  1003. netxen_set_msg_ctxid(msg, adapter->portnum);
  1004. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1005. writel(msg,
  1006. DB_NORMALIZE(adapter,
  1007. NETXEN_RCV_PRODUCER_OFFSET));
  1008. }
  1009. }
  1010. }
  1011. static void
  1012. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1013. struct nx_host_rds_ring *rds_ring)
  1014. {
  1015. struct rcv_desc *pdesc;
  1016. struct netxen_rx_buffer *buffer;
  1017. int producer, count = 0;
  1018. struct list_head *head;
  1019. producer = rds_ring->producer;
  1020. if (!spin_trylock(&rds_ring->lock))
  1021. return;
  1022. head = &rds_ring->free_list;
  1023. while (!list_empty(head)) {
  1024. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1025. if (!buffer->skb) {
  1026. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1027. break;
  1028. }
  1029. count++;
  1030. list_del(&buffer->list);
  1031. /* make a rcv descriptor */
  1032. pdesc = &rds_ring->desc_head[producer];
  1033. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1034. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1035. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1036. producer = get_next_index(producer, rds_ring->num_desc);
  1037. }
  1038. if (count) {
  1039. rds_ring->producer = producer;
  1040. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1041. (producer - 1) & (rds_ring->num_desc - 1));
  1042. wmb();
  1043. }
  1044. spin_unlock(&rds_ring->lock);
  1045. }
  1046. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1047. {
  1048. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1049. return;
  1050. }