core.c 6.7 KB

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  1. /*
  2. * arch/arm/mach-ep93xx/core.c
  3. * Core routines for Cirrus EP93xx chips.
  4. *
  5. * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
  6. *
  7. * Thanks go to Michael Burian and Ray Lehtiniemi for their key
  8. * role in the ep93xx linux community.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or (at
  13. * your option) any later version.
  14. */
  15. #include <linux/config.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/sched.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/serial.h>
  22. #include <linux/tty.h>
  23. #include <linux/bitops.h>
  24. #include <linux/serial.h>
  25. #include <linux/serial_8250.h>
  26. #include <linux/serial_core.h>
  27. #include <linux/device.h>
  28. #include <linux/mm.h>
  29. #include <linux/time.h>
  30. #include <linux/timex.h>
  31. #include <linux/delay.h>
  32. #include <linux/amba/bus.h>
  33. #include <asm/types.h>
  34. #include <asm/setup.h>
  35. #include <asm/memory.h>
  36. #include <asm/hardware.h>
  37. #include <asm/irq.h>
  38. #include <asm/system.h>
  39. #include <asm/tlbflush.h>
  40. #include <asm/pgtable.h>
  41. #include <asm/io.h>
  42. #include <asm/mach/map.h>
  43. #include <asm/mach/time.h>
  44. #include <asm/mach/irq.h>
  45. #include <asm/arch/gpio.h>
  46. #include <asm/hardware/vic.h>
  47. /*************************************************************************
  48. * Static I/O mappings that are needed for all EP93xx platforms
  49. *************************************************************************/
  50. static struct map_desc ep93xx_io_desc[] __initdata = {
  51. {
  52. .virtual = EP93XX_AHB_VIRT_BASE,
  53. .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
  54. .length = EP93XX_AHB_SIZE,
  55. .type = MT_DEVICE,
  56. }, {
  57. .virtual = EP93XX_APB_VIRT_BASE,
  58. .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
  59. .length = EP93XX_APB_SIZE,
  60. .type = MT_DEVICE,
  61. },
  62. };
  63. void __init ep93xx_map_io(void)
  64. {
  65. iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
  66. }
  67. /*************************************************************************
  68. * Timer handling for EP93xx
  69. *************************************************************************
  70. * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
  71. * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  72. * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
  73. * is free-running, and can't generate interrupts.
  74. *
  75. * The 508 kHz timers are ideal for use for the timer interrupt, as the
  76. * most common values of HZ divide 508 kHz nicely. We pick one of the 16
  77. * bit timers (timer 1) since we don't need more than 16 bits of reload
  78. * value as long as HZ >= 8.
  79. *
  80. * The higher clock rate of timer 4 makes it a better choice than the
  81. * other timers for use in gettimeoffset(), while the fact that it can't
  82. * generate interrupts means we don't have to worry about not being able
  83. * to use this timer for something else. We also use timer 4 for keeping
  84. * track of lost jiffies.
  85. */
  86. static unsigned int last_jiffy_time;
  87. #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
  88. static int ep93xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  89. {
  90. write_seqlock(&xtime_lock);
  91. __raw_writel(1, EP93XX_TIMER1_CLEAR);
  92. while (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time
  93. >= TIMER4_TICKS_PER_JIFFY) {
  94. last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
  95. timer_tick(regs);
  96. }
  97. write_sequnlock(&xtime_lock);
  98. return IRQ_HANDLED;
  99. }
  100. static struct irqaction ep93xx_timer_irq = {
  101. .name = "ep93xx timer",
  102. .flags = SA_INTERRUPT | SA_TIMER,
  103. .handler = ep93xx_timer_interrupt,
  104. };
  105. static void __init ep93xx_timer_init(void)
  106. {
  107. /* Enable periodic HZ timer. */
  108. __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
  109. __raw_writel((508000 / HZ) - 1, EP93XX_TIMER1_LOAD);
  110. __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
  111. /* Enable lost jiffy timer. */
  112. __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
  113. setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
  114. }
  115. static unsigned long ep93xx_gettimeoffset(void)
  116. {
  117. int offset;
  118. offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
  119. /* Calculate (1000000 / 983040) * offset. */
  120. return offset + (53 * offset / 3072);
  121. }
  122. struct sys_timer ep93xx_timer = {
  123. .init = ep93xx_timer_init,
  124. .offset = ep93xx_gettimeoffset,
  125. };
  126. /*************************************************************************
  127. * GPIO handling for EP93xx
  128. *************************************************************************/
  129. static unsigned char data_register_offset[8] = {
  130. 0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
  131. };
  132. static unsigned char data_direction_register_offset[8] = {
  133. 0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
  134. };
  135. void gpio_line_config(int line, int direction)
  136. {
  137. unsigned int data_direction_register;
  138. unsigned long flags;
  139. unsigned char v;
  140. data_direction_register =
  141. EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
  142. local_irq_save(flags);
  143. if (direction == GPIO_OUT) {
  144. v = __raw_readb(data_direction_register);
  145. v |= 1 << (line & 7);
  146. __raw_writeb(v, data_direction_register);
  147. } else if (direction == GPIO_IN) {
  148. v = __raw_readb(data_direction_register);
  149. v &= ~(1 << (line & 7));
  150. __raw_writeb(v, data_direction_register);
  151. }
  152. local_irq_restore(flags);
  153. }
  154. EXPORT_SYMBOL(gpio_line_config);
  155. int gpio_line_get(int line)
  156. {
  157. unsigned int data_register;
  158. data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
  159. return !!(__raw_readb(data_register) & (1 << (line & 7)));
  160. }
  161. EXPORT_SYMBOL(gpio_line_get);
  162. void gpio_line_set(int line, int value)
  163. {
  164. unsigned int data_register;
  165. unsigned long flags;
  166. unsigned char v;
  167. data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
  168. local_irq_save(flags);
  169. if (value == EP93XX_GPIO_HIGH) {
  170. v = __raw_readb(data_register);
  171. v |= 1 << (line & 7);
  172. __raw_writeb(v, data_register);
  173. } else if (value == EP93XX_GPIO_LOW) {
  174. v = __raw_readb(data_register);
  175. v &= ~(1 << (line & 7));
  176. __raw_writeb(v, data_register);
  177. }
  178. local_irq_restore(flags);
  179. }
  180. EXPORT_SYMBOL(gpio_line_set);
  181. /*************************************************************************
  182. * EP93xx IRQ handling
  183. *************************************************************************/
  184. void __init ep93xx_init_irq(void)
  185. {
  186. vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
  187. vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
  188. }
  189. /*************************************************************************
  190. * EP93xx peripheral handling
  191. *************************************************************************/
  192. void __init ep93xx_init_devices(void)
  193. {
  194. unsigned int v;
  195. /*
  196. * Disallow access to MaverickCrunch initially.
  197. */
  198. v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
  199. v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
  200. __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
  201. __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
  202. }