sdhci.c 35 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/highmem.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mmc/protocol.h>
  16. #include <asm/scatterlist.h>
  17. #include "sdhci.h"
  18. #define DRIVER_NAME "sdhci"
  19. #define DRIVER_VERSION "0.12"
  20. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  21. #define DBG(f, x...) \
  22. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  23. static unsigned int debug_nodma = 0;
  24. static unsigned int debug_forcedma = 0;
  25. static unsigned int debug_quirks = 0;
  26. static const struct pci_device_id pci_ids[] __devinitdata = {
  27. /* handle any SD host controller */
  28. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  29. { /* end: all zeroes */ },
  30. };
  31. MODULE_DEVICE_TABLE(pci, pci_ids);
  32. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  33. static void sdhci_finish_data(struct sdhci_host *);
  34. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  35. static void sdhci_finish_command(struct sdhci_host *);
  36. static void sdhci_dumpregs(struct sdhci_host *host)
  37. {
  38. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  39. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  40. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  41. readw(host->ioaddr + SDHCI_HOST_VERSION));
  42. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  43. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  44. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  45. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  46. readl(host->ioaddr + SDHCI_ARGUMENT),
  47. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  48. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  49. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  50. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  51. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  52. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  53. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  54. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  55. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  56. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  57. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  58. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  59. readl(host->ioaddr + SDHCI_INT_STATUS));
  60. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  61. readl(host->ioaddr + SDHCI_INT_ENABLE),
  62. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  63. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  64. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  65. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  66. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  67. readl(host->ioaddr + SDHCI_CAPABILITIES),
  68. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  69. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  70. }
  71. /*****************************************************************************\
  72. * *
  73. * Low level functions *
  74. * *
  75. \*****************************************************************************/
  76. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  77. {
  78. unsigned long timeout;
  79. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  80. if (mask & SDHCI_RESET_ALL)
  81. host->clock = 0;
  82. /* Wait max 100 ms */
  83. timeout = 100;
  84. /* hw clears the bit when it's done */
  85. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  86. if (timeout == 0) {
  87. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  88. "Please report this to " BUGMAIL ".\n",
  89. mmc_hostname(host->mmc), (int)mask);
  90. sdhci_dumpregs(host);
  91. return;
  92. }
  93. timeout--;
  94. mdelay(1);
  95. }
  96. }
  97. static void sdhci_init(struct sdhci_host *host)
  98. {
  99. u32 intmask;
  100. sdhci_reset(host, SDHCI_RESET_ALL);
  101. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  102. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  103. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  104. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  105. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  106. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  107. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  108. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  109. }
  110. static void sdhci_activate_led(struct sdhci_host *host)
  111. {
  112. u8 ctrl;
  113. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  114. ctrl |= SDHCI_CTRL_LED;
  115. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  116. }
  117. static void sdhci_deactivate_led(struct sdhci_host *host)
  118. {
  119. u8 ctrl;
  120. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  121. ctrl &= ~SDHCI_CTRL_LED;
  122. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  123. }
  124. /*****************************************************************************\
  125. * *
  126. * Core functions *
  127. * *
  128. \*****************************************************************************/
  129. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  130. {
  131. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  132. return host->mapped_sg + host->cur_sg->offset;
  133. }
  134. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  135. {
  136. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  137. }
  138. static inline int sdhci_next_sg(struct sdhci_host* host)
  139. {
  140. /*
  141. * Skip to next SG entry.
  142. */
  143. host->cur_sg++;
  144. host->num_sg--;
  145. /*
  146. * Any entries left?
  147. */
  148. if (host->num_sg > 0) {
  149. host->offset = 0;
  150. host->remain = host->cur_sg->length;
  151. }
  152. return host->num_sg;
  153. }
  154. static void sdhci_read_block_pio(struct sdhci_host *host)
  155. {
  156. int blksize, chunk_remain;
  157. u32 data;
  158. char *buffer;
  159. int size;
  160. DBG("PIO reading\n");
  161. blksize = host->data->blksz;
  162. chunk_remain = 0;
  163. data = 0;
  164. buffer = sdhci_kmap_sg(host) + host->offset;
  165. while (blksize) {
  166. if (chunk_remain == 0) {
  167. data = readl(host->ioaddr + SDHCI_BUFFER);
  168. chunk_remain = min(blksize, 4);
  169. }
  170. size = min(host->size, host->remain);
  171. size = min(size, chunk_remain);
  172. chunk_remain -= size;
  173. blksize -= size;
  174. host->offset += size;
  175. host->remain -= size;
  176. host->size -= size;
  177. while (size) {
  178. *buffer = data & 0xFF;
  179. buffer++;
  180. data >>= 8;
  181. size--;
  182. }
  183. if (host->remain == 0) {
  184. sdhci_kunmap_sg(host);
  185. if (sdhci_next_sg(host) == 0) {
  186. BUG_ON(blksize != 0);
  187. return;
  188. }
  189. buffer = sdhci_kmap_sg(host);
  190. }
  191. }
  192. sdhci_kunmap_sg(host);
  193. }
  194. static void sdhci_write_block_pio(struct sdhci_host *host)
  195. {
  196. int blksize, chunk_remain;
  197. u32 data;
  198. char *buffer;
  199. int bytes, size;
  200. DBG("PIO writing\n");
  201. blksize = host->data->blksz;
  202. chunk_remain = 4;
  203. data = 0;
  204. bytes = 0;
  205. buffer = sdhci_kmap_sg(host) + host->offset;
  206. while (blksize) {
  207. size = min(host->size, host->remain);
  208. size = min(size, chunk_remain);
  209. chunk_remain -= size;
  210. blksize -= size;
  211. host->offset += size;
  212. host->remain -= size;
  213. host->size -= size;
  214. while (size) {
  215. data >>= 8;
  216. data |= (u32)*buffer << 24;
  217. buffer++;
  218. size--;
  219. }
  220. if (chunk_remain == 0) {
  221. writel(data, host->ioaddr + SDHCI_BUFFER);
  222. chunk_remain = min(blksize, 4);
  223. }
  224. if (host->remain == 0) {
  225. sdhci_kunmap_sg(host);
  226. if (sdhci_next_sg(host) == 0) {
  227. BUG_ON(blksize != 0);
  228. return;
  229. }
  230. buffer = sdhci_kmap_sg(host);
  231. }
  232. }
  233. sdhci_kunmap_sg(host);
  234. }
  235. static void sdhci_transfer_pio(struct sdhci_host *host)
  236. {
  237. u32 mask;
  238. BUG_ON(!host->data);
  239. if (host->size == 0)
  240. return;
  241. if (host->data->flags & MMC_DATA_READ)
  242. mask = SDHCI_DATA_AVAILABLE;
  243. else
  244. mask = SDHCI_SPACE_AVAILABLE;
  245. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  246. if (host->data->flags & MMC_DATA_READ)
  247. sdhci_read_block_pio(host);
  248. else
  249. sdhci_write_block_pio(host);
  250. if (host->size == 0)
  251. break;
  252. BUG_ON(host->num_sg == 0);
  253. }
  254. DBG("PIO transfer complete.\n");
  255. }
  256. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  257. {
  258. u8 count;
  259. unsigned target_timeout, current_timeout;
  260. WARN_ON(host->data);
  261. if (data == NULL)
  262. return;
  263. DBG("blksz %04x blks %04x flags %08x\n",
  264. data->blksz, data->blocks, data->flags);
  265. DBG("tsac %d ms nsac %d clk\n",
  266. data->timeout_ns / 1000000, data->timeout_clks);
  267. /* Sanity checks */
  268. BUG_ON(data->blksz * data->blocks > 524288);
  269. BUG_ON(data->blksz > host->max_block);
  270. BUG_ON(data->blocks > 65535);
  271. /* timeout in us */
  272. target_timeout = data->timeout_ns / 1000 +
  273. data->timeout_clks / host->clock;
  274. /*
  275. * Figure out needed cycles.
  276. * We do this in steps in order to fit inside a 32 bit int.
  277. * The first step is the minimum timeout, which will have a
  278. * minimum resolution of 6 bits:
  279. * (1) 2^13*1000 > 2^22,
  280. * (2) host->timeout_clk < 2^16
  281. * =>
  282. * (1) / (2) > 2^6
  283. */
  284. count = 0;
  285. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  286. while (current_timeout < target_timeout) {
  287. count++;
  288. current_timeout <<= 1;
  289. if (count >= 0xF)
  290. break;
  291. }
  292. if (count >= 0xF) {
  293. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  294. mmc_hostname(host->mmc));
  295. count = 0xE;
  296. }
  297. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  298. if (host->flags & SDHCI_USE_DMA) {
  299. int count;
  300. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  301. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  302. BUG_ON(count != 1);
  303. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  304. } else {
  305. host->size = data->blksz * data->blocks;
  306. host->cur_sg = data->sg;
  307. host->num_sg = data->sg_len;
  308. host->offset = 0;
  309. host->remain = host->cur_sg->length;
  310. }
  311. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  312. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  313. host->ioaddr + SDHCI_BLOCK_SIZE);
  314. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  315. }
  316. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  317. struct mmc_data *data)
  318. {
  319. u16 mode;
  320. WARN_ON(host->data);
  321. if (data == NULL)
  322. return;
  323. mode = SDHCI_TRNS_BLK_CNT_EN;
  324. if (data->blocks > 1)
  325. mode |= SDHCI_TRNS_MULTI;
  326. if (data->flags & MMC_DATA_READ)
  327. mode |= SDHCI_TRNS_READ;
  328. if (host->flags & SDHCI_USE_DMA)
  329. mode |= SDHCI_TRNS_DMA;
  330. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  331. }
  332. static void sdhci_finish_data(struct sdhci_host *host)
  333. {
  334. struct mmc_data *data;
  335. u16 blocks;
  336. BUG_ON(!host->data);
  337. data = host->data;
  338. host->data = NULL;
  339. if (host->flags & SDHCI_USE_DMA) {
  340. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  341. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  342. }
  343. /*
  344. * Controller doesn't count down when in single block mode.
  345. */
  346. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  347. blocks = 0;
  348. else
  349. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  350. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  351. if ((data->error == MMC_ERR_NONE) && blocks) {
  352. printk(KERN_ERR "%s: Controller signalled completion even "
  353. "though there were blocks left. Please report this "
  354. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  355. data->error = MMC_ERR_FAILED;
  356. }
  357. if (host->size != 0) {
  358. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  359. "Please report this to " BUGMAIL ".\n",
  360. mmc_hostname(host->mmc), host->size);
  361. data->error = MMC_ERR_FAILED;
  362. }
  363. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  364. if (data->stop) {
  365. /*
  366. * The controller needs a reset of internal state machines
  367. * upon error conditions.
  368. */
  369. if (data->error != MMC_ERR_NONE) {
  370. sdhci_reset(host, SDHCI_RESET_CMD);
  371. sdhci_reset(host, SDHCI_RESET_DATA);
  372. }
  373. sdhci_send_command(host, data->stop);
  374. } else
  375. tasklet_schedule(&host->finish_tasklet);
  376. }
  377. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  378. {
  379. int flags;
  380. u32 mask;
  381. unsigned long timeout;
  382. WARN_ON(host->cmd);
  383. DBG("Sending cmd (%x)\n", cmd->opcode);
  384. /* Wait max 10 ms */
  385. timeout = 10;
  386. mask = SDHCI_CMD_INHIBIT;
  387. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  388. mask |= SDHCI_DATA_INHIBIT;
  389. /* We shouldn't wait for data inihibit for stop commands, even
  390. though they might use busy signaling */
  391. if (host->mrq->data && (cmd == host->mrq->data->stop))
  392. mask &= ~SDHCI_DATA_INHIBIT;
  393. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  394. if (timeout == 0) {
  395. printk(KERN_ERR "%s: Controller never released "
  396. "inhibit bit(s). Please report this to "
  397. BUGMAIL ".\n", mmc_hostname(host->mmc));
  398. sdhci_dumpregs(host);
  399. cmd->error = MMC_ERR_FAILED;
  400. tasklet_schedule(&host->finish_tasklet);
  401. return;
  402. }
  403. timeout--;
  404. mdelay(1);
  405. }
  406. mod_timer(&host->timer, jiffies + 10 * HZ);
  407. host->cmd = cmd;
  408. sdhci_prepare_data(host, cmd->data);
  409. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  410. sdhci_set_transfer_mode(host, cmd->data);
  411. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  412. printk(KERN_ERR "%s: Unsupported response type! "
  413. "Please report this to " BUGMAIL ".\n",
  414. mmc_hostname(host->mmc));
  415. cmd->error = MMC_ERR_INVALID;
  416. tasklet_schedule(&host->finish_tasklet);
  417. return;
  418. }
  419. if (!(cmd->flags & MMC_RSP_PRESENT))
  420. flags = SDHCI_CMD_RESP_NONE;
  421. else if (cmd->flags & MMC_RSP_136)
  422. flags = SDHCI_CMD_RESP_LONG;
  423. else if (cmd->flags & MMC_RSP_BUSY)
  424. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  425. else
  426. flags = SDHCI_CMD_RESP_SHORT;
  427. if (cmd->flags & MMC_RSP_CRC)
  428. flags |= SDHCI_CMD_CRC;
  429. if (cmd->flags & MMC_RSP_OPCODE)
  430. flags |= SDHCI_CMD_INDEX;
  431. if (cmd->data)
  432. flags |= SDHCI_CMD_DATA;
  433. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  434. host->ioaddr + SDHCI_COMMAND);
  435. }
  436. static void sdhci_finish_command(struct sdhci_host *host)
  437. {
  438. int i;
  439. BUG_ON(host->cmd == NULL);
  440. if (host->cmd->flags & MMC_RSP_PRESENT) {
  441. if (host->cmd->flags & MMC_RSP_136) {
  442. /* CRC is stripped so we need to do some shifting. */
  443. for (i = 0;i < 4;i++) {
  444. host->cmd->resp[i] = readl(host->ioaddr +
  445. SDHCI_RESPONSE + (3-i)*4) << 8;
  446. if (i != 3)
  447. host->cmd->resp[i] |=
  448. readb(host->ioaddr +
  449. SDHCI_RESPONSE + (3-i)*4-1);
  450. }
  451. } else {
  452. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  453. }
  454. }
  455. host->cmd->error = MMC_ERR_NONE;
  456. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  457. if (host->cmd->data)
  458. host->data = host->cmd->data;
  459. else
  460. tasklet_schedule(&host->finish_tasklet);
  461. host->cmd = NULL;
  462. }
  463. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  464. {
  465. int div;
  466. u16 clk;
  467. unsigned long timeout;
  468. if (clock == host->clock)
  469. return;
  470. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  471. if (clock == 0)
  472. goto out;
  473. for (div = 1;div < 256;div *= 2) {
  474. if ((host->max_clk / div) <= clock)
  475. break;
  476. }
  477. div >>= 1;
  478. clk = div << SDHCI_DIVIDER_SHIFT;
  479. clk |= SDHCI_CLOCK_INT_EN;
  480. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  481. /* Wait max 10 ms */
  482. timeout = 10;
  483. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  484. & SDHCI_CLOCK_INT_STABLE)) {
  485. if (timeout == 0) {
  486. printk(KERN_ERR "%s: Internal clock never stabilised. "
  487. "Please report this to " BUGMAIL ".\n",
  488. mmc_hostname(host->mmc));
  489. sdhci_dumpregs(host);
  490. return;
  491. }
  492. timeout--;
  493. mdelay(1);
  494. }
  495. clk |= SDHCI_CLOCK_CARD_EN;
  496. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  497. out:
  498. host->clock = clock;
  499. }
  500. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  501. {
  502. u8 pwr;
  503. if (host->power == power)
  504. return;
  505. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  506. if (power == (unsigned short)-1)
  507. goto out;
  508. pwr = SDHCI_POWER_ON;
  509. switch (power) {
  510. case MMC_VDD_170:
  511. case MMC_VDD_180:
  512. case MMC_VDD_190:
  513. pwr |= SDHCI_POWER_180;
  514. break;
  515. case MMC_VDD_290:
  516. case MMC_VDD_300:
  517. case MMC_VDD_310:
  518. pwr |= SDHCI_POWER_300;
  519. break;
  520. case MMC_VDD_320:
  521. case MMC_VDD_330:
  522. case MMC_VDD_340:
  523. pwr |= SDHCI_POWER_330;
  524. break;
  525. default:
  526. BUG();
  527. }
  528. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  529. out:
  530. host->power = power;
  531. }
  532. /*****************************************************************************\
  533. * *
  534. * MMC callbacks *
  535. * *
  536. \*****************************************************************************/
  537. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  538. {
  539. struct sdhci_host *host;
  540. unsigned long flags;
  541. host = mmc_priv(mmc);
  542. spin_lock_irqsave(&host->lock, flags);
  543. WARN_ON(host->mrq != NULL);
  544. sdhci_activate_led(host);
  545. host->mrq = mrq;
  546. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  547. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  548. tasklet_schedule(&host->finish_tasklet);
  549. } else
  550. sdhci_send_command(host, mrq->cmd);
  551. spin_unlock_irqrestore(&host->lock, flags);
  552. }
  553. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  554. {
  555. struct sdhci_host *host;
  556. unsigned long flags;
  557. u8 ctrl;
  558. host = mmc_priv(mmc);
  559. spin_lock_irqsave(&host->lock, flags);
  560. /*
  561. * Reset the chip on each power off.
  562. * Should clear out any weird states.
  563. */
  564. if (ios->power_mode == MMC_POWER_OFF) {
  565. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  566. sdhci_init(host);
  567. }
  568. sdhci_set_clock(host, ios->clock);
  569. if (ios->power_mode == MMC_POWER_OFF)
  570. sdhci_set_power(host, -1);
  571. else
  572. sdhci_set_power(host, ios->vdd);
  573. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  574. if (ios->bus_width == MMC_BUS_WIDTH_4)
  575. ctrl |= SDHCI_CTRL_4BITBUS;
  576. else
  577. ctrl &= ~SDHCI_CTRL_4BITBUS;
  578. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  579. spin_unlock_irqrestore(&host->lock, flags);
  580. }
  581. static int sdhci_get_ro(struct mmc_host *mmc)
  582. {
  583. struct sdhci_host *host;
  584. unsigned long flags;
  585. int present;
  586. host = mmc_priv(mmc);
  587. spin_lock_irqsave(&host->lock, flags);
  588. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  589. spin_unlock_irqrestore(&host->lock, flags);
  590. return !(present & SDHCI_WRITE_PROTECT);
  591. }
  592. static struct mmc_host_ops sdhci_ops = {
  593. .request = sdhci_request,
  594. .set_ios = sdhci_set_ios,
  595. .get_ro = sdhci_get_ro,
  596. };
  597. /*****************************************************************************\
  598. * *
  599. * Tasklets *
  600. * *
  601. \*****************************************************************************/
  602. static void sdhci_tasklet_card(unsigned long param)
  603. {
  604. struct sdhci_host *host;
  605. unsigned long flags;
  606. host = (struct sdhci_host*)param;
  607. spin_lock_irqsave(&host->lock, flags);
  608. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  609. if (host->mrq) {
  610. printk(KERN_ERR "%s: Card removed during transfer!\n",
  611. mmc_hostname(host->mmc));
  612. printk(KERN_ERR "%s: Resetting controller.\n",
  613. mmc_hostname(host->mmc));
  614. sdhci_reset(host, SDHCI_RESET_CMD);
  615. sdhci_reset(host, SDHCI_RESET_DATA);
  616. host->mrq->cmd->error = MMC_ERR_FAILED;
  617. tasklet_schedule(&host->finish_tasklet);
  618. }
  619. }
  620. spin_unlock_irqrestore(&host->lock, flags);
  621. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  622. }
  623. static void sdhci_tasklet_finish(unsigned long param)
  624. {
  625. struct sdhci_host *host;
  626. unsigned long flags;
  627. struct mmc_request *mrq;
  628. host = (struct sdhci_host*)param;
  629. spin_lock_irqsave(&host->lock, flags);
  630. del_timer(&host->timer);
  631. mrq = host->mrq;
  632. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  633. /*
  634. * The controller needs a reset of internal state machines
  635. * upon error conditions.
  636. */
  637. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  638. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  639. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  640. sdhci_reset(host, SDHCI_RESET_CMD);
  641. sdhci_reset(host, SDHCI_RESET_DATA);
  642. }
  643. host->mrq = NULL;
  644. host->cmd = NULL;
  645. host->data = NULL;
  646. sdhci_deactivate_led(host);
  647. spin_unlock_irqrestore(&host->lock, flags);
  648. mmc_request_done(host->mmc, mrq);
  649. }
  650. static void sdhci_timeout_timer(unsigned long data)
  651. {
  652. struct sdhci_host *host;
  653. unsigned long flags;
  654. host = (struct sdhci_host*)data;
  655. spin_lock_irqsave(&host->lock, flags);
  656. if (host->mrq) {
  657. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  658. "Please report this to " BUGMAIL ".\n",
  659. mmc_hostname(host->mmc));
  660. sdhci_dumpregs(host);
  661. if (host->data) {
  662. host->data->error = MMC_ERR_TIMEOUT;
  663. sdhci_finish_data(host);
  664. } else {
  665. if (host->cmd)
  666. host->cmd->error = MMC_ERR_TIMEOUT;
  667. else
  668. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  669. tasklet_schedule(&host->finish_tasklet);
  670. }
  671. }
  672. spin_unlock_irqrestore(&host->lock, flags);
  673. }
  674. /*****************************************************************************\
  675. * *
  676. * Interrupt handling *
  677. * *
  678. \*****************************************************************************/
  679. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  680. {
  681. BUG_ON(intmask == 0);
  682. if (!host->cmd) {
  683. printk(KERN_ERR "%s: Got command interrupt even though no "
  684. "command operation was in progress.\n",
  685. mmc_hostname(host->mmc));
  686. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  687. mmc_hostname(host->mmc));
  688. sdhci_dumpregs(host);
  689. return;
  690. }
  691. if (intmask & SDHCI_INT_RESPONSE)
  692. sdhci_finish_command(host);
  693. else {
  694. if (intmask & SDHCI_INT_TIMEOUT)
  695. host->cmd->error = MMC_ERR_TIMEOUT;
  696. else if (intmask & SDHCI_INT_CRC)
  697. host->cmd->error = MMC_ERR_BADCRC;
  698. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  699. host->cmd->error = MMC_ERR_FAILED;
  700. else
  701. host->cmd->error = MMC_ERR_INVALID;
  702. tasklet_schedule(&host->finish_tasklet);
  703. }
  704. }
  705. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  706. {
  707. BUG_ON(intmask == 0);
  708. if (!host->data) {
  709. /*
  710. * A data end interrupt is sent together with the response
  711. * for the stop command.
  712. */
  713. if (intmask & SDHCI_INT_DATA_END)
  714. return;
  715. printk(KERN_ERR "%s: Got data interrupt even though no "
  716. "data operation was in progress.\n",
  717. mmc_hostname(host->mmc));
  718. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  719. mmc_hostname(host->mmc));
  720. sdhci_dumpregs(host);
  721. return;
  722. }
  723. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  724. host->data->error = MMC_ERR_TIMEOUT;
  725. else if (intmask & SDHCI_INT_DATA_CRC)
  726. host->data->error = MMC_ERR_BADCRC;
  727. else if (intmask & SDHCI_INT_DATA_END_BIT)
  728. host->data->error = MMC_ERR_FAILED;
  729. if (host->data->error != MMC_ERR_NONE)
  730. sdhci_finish_data(host);
  731. else {
  732. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  733. sdhci_transfer_pio(host);
  734. if (intmask & SDHCI_INT_DATA_END)
  735. sdhci_finish_data(host);
  736. }
  737. }
  738. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  739. {
  740. irqreturn_t result;
  741. struct sdhci_host* host = dev_id;
  742. u32 intmask;
  743. spin_lock(&host->lock);
  744. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  745. if (!intmask) {
  746. result = IRQ_NONE;
  747. goto out;
  748. }
  749. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  750. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  751. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  752. host->ioaddr + SDHCI_INT_STATUS);
  753. tasklet_schedule(&host->card_tasklet);
  754. }
  755. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  756. if (intmask & SDHCI_INT_CMD_MASK) {
  757. writel(intmask & SDHCI_INT_CMD_MASK,
  758. host->ioaddr + SDHCI_INT_STATUS);
  759. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  760. }
  761. if (intmask & SDHCI_INT_DATA_MASK) {
  762. writel(intmask & SDHCI_INT_DATA_MASK,
  763. host->ioaddr + SDHCI_INT_STATUS);
  764. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  765. }
  766. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  767. if (intmask & SDHCI_INT_BUS_POWER) {
  768. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  769. mmc_hostname(host->mmc));
  770. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  771. }
  772. intmask &= SDHCI_INT_BUS_POWER;
  773. if (intmask) {
  774. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  775. "report this to " BUGMAIL ".\n",
  776. mmc_hostname(host->mmc), intmask);
  777. sdhci_dumpregs(host);
  778. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  779. }
  780. result = IRQ_HANDLED;
  781. out:
  782. spin_unlock(&host->lock);
  783. return result;
  784. }
  785. /*****************************************************************************\
  786. * *
  787. * Suspend/resume *
  788. * *
  789. \*****************************************************************************/
  790. #ifdef CONFIG_PM
  791. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  792. {
  793. struct sdhci_chip *chip;
  794. int i, ret;
  795. chip = pci_get_drvdata(pdev);
  796. if (!chip)
  797. return 0;
  798. DBG("Suspending...\n");
  799. for (i = 0;i < chip->num_slots;i++) {
  800. if (!chip->hosts[i])
  801. continue;
  802. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  803. if (ret) {
  804. for (i--;i >= 0;i--)
  805. mmc_resume_host(chip->hosts[i]->mmc);
  806. return ret;
  807. }
  808. }
  809. pci_save_state(pdev);
  810. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  811. pci_disable_device(pdev);
  812. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  813. return 0;
  814. }
  815. static int sdhci_resume (struct pci_dev *pdev)
  816. {
  817. struct sdhci_chip *chip;
  818. int i, ret;
  819. chip = pci_get_drvdata(pdev);
  820. if (!chip)
  821. return 0;
  822. DBG("Resuming...\n");
  823. pci_set_power_state(pdev, PCI_D0);
  824. pci_restore_state(pdev);
  825. pci_enable_device(pdev);
  826. for (i = 0;i < chip->num_slots;i++) {
  827. if (!chip->hosts[i])
  828. continue;
  829. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  830. pci_set_master(pdev);
  831. sdhci_init(chip->hosts[i]);
  832. ret = mmc_resume_host(chip->hosts[i]->mmc);
  833. if (ret)
  834. return ret;
  835. }
  836. return 0;
  837. }
  838. #else /* CONFIG_PM */
  839. #define sdhci_suspend NULL
  840. #define sdhci_resume NULL
  841. #endif /* CONFIG_PM */
  842. /*****************************************************************************\
  843. * *
  844. * Device probing/removal *
  845. * *
  846. \*****************************************************************************/
  847. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  848. {
  849. int ret;
  850. unsigned int version;
  851. struct sdhci_chip *chip;
  852. struct mmc_host *mmc;
  853. struct sdhci_host *host;
  854. u8 first_bar;
  855. unsigned int caps;
  856. chip = pci_get_drvdata(pdev);
  857. BUG_ON(!chip);
  858. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  859. if (ret)
  860. return ret;
  861. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  862. if (first_bar > 5) {
  863. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  864. return -ENODEV;
  865. }
  866. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  867. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  868. return -ENODEV;
  869. }
  870. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  871. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  872. return -ENODEV;
  873. }
  874. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  875. printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
  876. return -ENODEV;
  877. }
  878. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  879. printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
  880. return -ENODEV;
  881. }
  882. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  883. if (!mmc)
  884. return -ENOMEM;
  885. host = mmc_priv(mmc);
  886. host->mmc = mmc;
  887. host->bar = first_bar + slot;
  888. host->addr = pci_resource_start(pdev, host->bar);
  889. host->irq = pdev->irq;
  890. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  891. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  892. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  893. if (ret)
  894. goto free;
  895. host->ioaddr = ioremap_nocache(host->addr,
  896. pci_resource_len(pdev, host->bar));
  897. if (!host->ioaddr) {
  898. ret = -ENOMEM;
  899. goto release;
  900. }
  901. sdhci_reset(host, SDHCI_RESET_ALL);
  902. version = readw(host->ioaddr + SDHCI_HOST_VERSION);
  903. version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  904. if (version != 0) {
  905. printk(KERN_ERR "%s: Unknown controller version (%d). "
  906. "Cowardly refusing to continue.\n", host->slot_descr,
  907. version);
  908. ret = -ENODEV;
  909. goto unmap;
  910. }
  911. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  912. if (debug_nodma)
  913. DBG("DMA forced off\n");
  914. else if (debug_forcedma) {
  915. DBG("DMA forced on\n");
  916. host->flags |= SDHCI_USE_DMA;
  917. } else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
  918. DBG("Controller doesn't have DMA interface\n");
  919. else if (!(caps & SDHCI_CAN_DO_DMA))
  920. DBG("Controller doesn't have DMA capability\n");
  921. else
  922. host->flags |= SDHCI_USE_DMA;
  923. if (host->flags & SDHCI_USE_DMA) {
  924. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  925. printk(KERN_WARNING "%s: No suitable DMA available. "
  926. "Falling back to PIO.\n", host->slot_descr);
  927. host->flags &= ~SDHCI_USE_DMA;
  928. }
  929. }
  930. if (host->flags & SDHCI_USE_DMA)
  931. pci_set_master(pdev);
  932. else /* XXX: Hack to get MMC layer to avoid highmem */
  933. pdev->dma_mask = 0;
  934. host->max_clk =
  935. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  936. if (host->max_clk == 0) {
  937. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  938. "frequency.\n", host->slot_descr);
  939. ret = -ENODEV;
  940. goto unmap;
  941. }
  942. host->max_clk *= 1000000;
  943. host->timeout_clk =
  944. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  945. if (host->timeout_clk == 0) {
  946. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  947. "frequency.\n", host->slot_descr);
  948. ret = -ENODEV;
  949. goto unmap;
  950. }
  951. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  952. host->timeout_clk *= 1000;
  953. host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  954. if (host->max_block >= 3) {
  955. printk(KERN_ERR "%s: Invalid maximum block size.\n",
  956. host->slot_descr);
  957. ret = -ENODEV;
  958. goto unmap;
  959. }
  960. host->max_block = 512 << host->max_block;
  961. /*
  962. * Set host parameters.
  963. */
  964. mmc->ops = &sdhci_ops;
  965. mmc->f_min = host->max_clk / 256;
  966. mmc->f_max = host->max_clk;
  967. mmc->caps = MMC_CAP_4_BIT_DATA;
  968. mmc->ocr_avail = 0;
  969. if (caps & SDHCI_CAN_VDD_330)
  970. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  971. else if (caps & SDHCI_CAN_VDD_300)
  972. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  973. else if (caps & SDHCI_CAN_VDD_180)
  974. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  975. if (mmc->ocr_avail == 0) {
  976. printk(KERN_ERR "%s: Hardware doesn't report any "
  977. "support voltages.\n", host->slot_descr);
  978. ret = -ENODEV;
  979. goto unmap;
  980. }
  981. spin_lock_init(&host->lock);
  982. /*
  983. * Maximum number of segments. Hardware cannot do scatter lists.
  984. */
  985. if (host->flags & SDHCI_USE_DMA)
  986. mmc->max_hw_segs = 1;
  987. else
  988. mmc->max_hw_segs = 16;
  989. mmc->max_phys_segs = 16;
  990. /*
  991. * Maximum number of sectors in one transfer. Limited by DMA boundary
  992. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  993. */
  994. mmc->max_sectors = 1024;
  995. /*
  996. * Maximum segment size. Could be one segment with the maximum number
  997. * of sectors.
  998. */
  999. mmc->max_seg_size = mmc->max_sectors * 512;
  1000. /*
  1001. * Init tasklets.
  1002. */
  1003. tasklet_init(&host->card_tasklet,
  1004. sdhci_tasklet_card, (unsigned long)host);
  1005. tasklet_init(&host->finish_tasklet,
  1006. sdhci_tasklet_finish, (unsigned long)host);
  1007. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  1008. ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
  1009. host->slot_descr, host);
  1010. if (ret)
  1011. goto untasklet;
  1012. sdhci_init(host);
  1013. #ifdef CONFIG_MMC_DEBUG
  1014. sdhci_dumpregs(host);
  1015. #endif
  1016. host->chip = chip;
  1017. chip->hosts[slot] = host;
  1018. mmc_add_host(mmc);
  1019. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  1020. host->addr, host->irq,
  1021. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  1022. return 0;
  1023. untasklet:
  1024. tasklet_kill(&host->card_tasklet);
  1025. tasklet_kill(&host->finish_tasklet);
  1026. unmap:
  1027. iounmap(host->ioaddr);
  1028. release:
  1029. pci_release_region(pdev, host->bar);
  1030. free:
  1031. mmc_free_host(mmc);
  1032. return ret;
  1033. }
  1034. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  1035. {
  1036. struct sdhci_chip *chip;
  1037. struct mmc_host *mmc;
  1038. struct sdhci_host *host;
  1039. chip = pci_get_drvdata(pdev);
  1040. host = chip->hosts[slot];
  1041. mmc = host->mmc;
  1042. chip->hosts[slot] = NULL;
  1043. mmc_remove_host(mmc);
  1044. sdhci_reset(host, SDHCI_RESET_ALL);
  1045. free_irq(host->irq, host);
  1046. del_timer_sync(&host->timer);
  1047. tasklet_kill(&host->card_tasklet);
  1048. tasklet_kill(&host->finish_tasklet);
  1049. iounmap(host->ioaddr);
  1050. pci_release_region(pdev, host->bar);
  1051. mmc_free_host(mmc);
  1052. }
  1053. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1054. const struct pci_device_id *ent)
  1055. {
  1056. int ret, i;
  1057. u8 slots, rev;
  1058. struct sdhci_chip *chip;
  1059. BUG_ON(pdev == NULL);
  1060. BUG_ON(ent == NULL);
  1061. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1062. printk(KERN_INFO DRIVER_NAME
  1063. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1064. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1065. (int)rev);
  1066. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1067. if (ret)
  1068. return ret;
  1069. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1070. DBG("found %d slot(s)\n", slots);
  1071. if (slots == 0)
  1072. return -ENODEV;
  1073. ret = pci_enable_device(pdev);
  1074. if (ret)
  1075. return ret;
  1076. chip = kzalloc(sizeof(struct sdhci_chip) +
  1077. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1078. if (!chip) {
  1079. ret = -ENOMEM;
  1080. goto err;
  1081. }
  1082. chip->pdev = pdev;
  1083. chip->quirks = ent->driver_data;
  1084. if (debug_quirks)
  1085. chip->quirks = debug_quirks;
  1086. chip->num_slots = slots;
  1087. pci_set_drvdata(pdev, chip);
  1088. for (i = 0;i < slots;i++) {
  1089. ret = sdhci_probe_slot(pdev, i);
  1090. if (ret) {
  1091. for (i--;i >= 0;i--)
  1092. sdhci_remove_slot(pdev, i);
  1093. goto free;
  1094. }
  1095. }
  1096. return 0;
  1097. free:
  1098. pci_set_drvdata(pdev, NULL);
  1099. kfree(chip);
  1100. err:
  1101. pci_disable_device(pdev);
  1102. return ret;
  1103. }
  1104. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1105. {
  1106. int i;
  1107. struct sdhci_chip *chip;
  1108. chip = pci_get_drvdata(pdev);
  1109. if (chip) {
  1110. for (i = 0;i < chip->num_slots;i++)
  1111. sdhci_remove_slot(pdev, i);
  1112. pci_set_drvdata(pdev, NULL);
  1113. kfree(chip);
  1114. }
  1115. pci_disable_device(pdev);
  1116. }
  1117. static struct pci_driver sdhci_driver = {
  1118. .name = DRIVER_NAME,
  1119. .id_table = pci_ids,
  1120. .probe = sdhci_probe,
  1121. .remove = __devexit_p(sdhci_remove),
  1122. .suspend = sdhci_suspend,
  1123. .resume = sdhci_resume,
  1124. };
  1125. /*****************************************************************************\
  1126. * *
  1127. * Driver init/exit *
  1128. * *
  1129. \*****************************************************************************/
  1130. static int __init sdhci_drv_init(void)
  1131. {
  1132. printk(KERN_INFO DRIVER_NAME
  1133. ": Secure Digital Host Controller Interface driver, "
  1134. DRIVER_VERSION "\n");
  1135. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1136. return pci_register_driver(&sdhci_driver);
  1137. }
  1138. static void __exit sdhci_drv_exit(void)
  1139. {
  1140. DBG("Exiting\n");
  1141. pci_unregister_driver(&sdhci_driver);
  1142. }
  1143. module_init(sdhci_drv_init);
  1144. module_exit(sdhci_drv_exit);
  1145. module_param(debug_nodma, uint, 0444);
  1146. module_param(debug_forcedma, uint, 0444);
  1147. module_param(debug_quirks, uint, 0444);
  1148. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1149. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1150. MODULE_VERSION(DRIVER_VERSION);
  1151. MODULE_LICENSE("GPL");
  1152. MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
  1153. MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
  1154. MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");