radeon_fence.c 17 KB

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  1. /*
  2. * Copyright 2009 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20. *
  21. * The above copyright notice and this permission notice (including the
  22. * next paragraph) shall be included in all copies or substantial portions
  23. * of the Software.
  24. *
  25. */
  26. /*
  27. * Authors:
  28. * Jerome Glisse <glisse@freedesktop.org>
  29. * Dave Airlie
  30. */
  31. #include <linux/seq_file.h>
  32. #include <linux/atomic.h>
  33. #include <linux/wait.h>
  34. #include <linux/list.h>
  35. #include <linux/kref.h>
  36. #include <linux/slab.h>
  37. #include "drmP.h"
  38. #include "drm.h"
  39. #include "radeon_reg.h"
  40. #include "radeon.h"
  41. #include "radeon_trace.h"
  42. static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  43. {
  44. if (rdev->wb.enabled) {
  45. *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
  46. } else {
  47. WREG32(rdev->fence_drv[ring].scratch_reg, seq);
  48. }
  49. }
  50. static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  51. {
  52. u32 seq = 0;
  53. if (rdev->wb.enabled) {
  54. seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
  55. } else {
  56. seq = RREG32(rdev->fence_drv[ring].scratch_reg);
  57. }
  58. return seq;
  59. }
  60. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
  61. {
  62. /* we are protected by the ring emission mutex */
  63. if (fence->seq && fence->seq < RADEON_FENCE_NOTEMITED_SEQ) {
  64. return 0;
  65. }
  66. fence->seq = ++rdev->fence_drv[fence->ring].seq;
  67. radeon_fence_ring_emit(rdev, fence->ring, fence);
  68. trace_radeon_fence_emit(rdev->ddev, fence->seq);
  69. return 0;
  70. }
  71. void radeon_fence_process(struct radeon_device *rdev, int ring)
  72. {
  73. uint64_t seq, last_seq;
  74. unsigned count_loop = 0;
  75. bool wake = false;
  76. /* Note there is a scenario here for an infinite loop but it's
  77. * very unlikely to happen. For it to happen, the current polling
  78. * process need to be interrupted by another process and another
  79. * process needs to update the last_seq btw the atomic read and
  80. * xchg of the current process.
  81. *
  82. * More over for this to go in infinite loop there need to be
  83. * continuously new fence signaled ie radeon_fence_read needs
  84. * to return a different value each time for both the currently
  85. * polling process and the other process that xchg the last_seq
  86. * btw atomic read and xchg of the current process. And the
  87. * value the other process set as last seq must be higher than
  88. * the seq value we just read. Which means that current process
  89. * need to be interrupted after radeon_fence_read and before
  90. * atomic xchg.
  91. *
  92. * To be even more safe we count the number of time we loop and
  93. * we bail after 10 loop just accepting the fact that we might
  94. * have temporarly set the last_seq not to the true real last
  95. * seq but to an older one.
  96. */
  97. last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
  98. do {
  99. seq = radeon_fence_read(rdev, ring);
  100. seq |= last_seq & 0xffffffff00000000LL;
  101. if (seq < last_seq) {
  102. seq += 0x100000000LL;
  103. }
  104. if (seq == last_seq) {
  105. break;
  106. }
  107. /* If we loop over we don't want to return without
  108. * checking if a fence is signaled as it means that the
  109. * seq we just read is different from the previous on.
  110. */
  111. wake = true;
  112. last_seq = seq;
  113. if ((count_loop++) > 10) {
  114. /* We looped over too many time leave with the
  115. * fact that we might have set an older fence
  116. * seq then the current real last seq as signaled
  117. * by the hw.
  118. */
  119. break;
  120. }
  121. } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
  122. if (wake) {
  123. rdev->fence_drv[ring].last_activity = jiffies;
  124. wake_up_all(&rdev->fence_queue);
  125. }
  126. }
  127. static void radeon_fence_destroy(struct kref *kref)
  128. {
  129. struct radeon_fence *fence;
  130. fence = container_of(kref, struct radeon_fence, kref);
  131. fence->seq = RADEON_FENCE_NOTEMITED_SEQ;
  132. if (fence->semaphore)
  133. radeon_semaphore_free(fence->rdev, fence->semaphore, NULL);
  134. kfree(fence);
  135. }
  136. int radeon_fence_create(struct radeon_device *rdev,
  137. struct radeon_fence **fence,
  138. int ring)
  139. {
  140. *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
  141. if ((*fence) == NULL) {
  142. return -ENOMEM;
  143. }
  144. kref_init(&((*fence)->kref));
  145. (*fence)->rdev = rdev;
  146. (*fence)->seq = RADEON_FENCE_NOTEMITED_SEQ;
  147. (*fence)->ring = ring;
  148. (*fence)->semaphore = NULL;
  149. return 0;
  150. }
  151. static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
  152. u64 seq, unsigned ring)
  153. {
  154. if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
  155. return true;
  156. }
  157. /* poll new last sequence at least once */
  158. radeon_fence_process(rdev, ring);
  159. if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
  160. return true;
  161. }
  162. return false;
  163. }
  164. bool radeon_fence_signaled(struct radeon_fence *fence)
  165. {
  166. if (!fence) {
  167. return true;
  168. }
  169. if (fence->seq == RADEON_FENCE_NOTEMITED_SEQ) {
  170. WARN(1, "Querying an unemitted fence : %p !\n", fence);
  171. return true;
  172. }
  173. if (fence->seq == RADEON_FENCE_SIGNALED_SEQ) {
  174. return true;
  175. }
  176. if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
  177. fence->seq = RADEON_FENCE_SIGNALED_SEQ;
  178. return true;
  179. }
  180. return false;
  181. }
  182. static int radeon_fence_wait_seq(struct radeon_device *rdev, u64 target_seq,
  183. unsigned ring, bool intr, bool lock_ring)
  184. {
  185. unsigned long timeout, last_activity;
  186. uint64_t seq;
  187. unsigned i;
  188. bool signaled;
  189. int r;
  190. while (target_seq > atomic64_read(&rdev->fence_drv[ring].last_seq)) {
  191. if (!rdev->ring[ring].ready) {
  192. return -EBUSY;
  193. }
  194. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  195. if (time_after(rdev->fence_drv[ring].last_activity, timeout)) {
  196. /* the normal case, timeout is somewhere before last_activity */
  197. timeout = rdev->fence_drv[ring].last_activity - timeout;
  198. } else {
  199. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  200. * anyway we will just wait for the minimum amount and then check for a lockup
  201. */
  202. timeout = 1;
  203. }
  204. seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
  205. /* Save current last activity valuee, used to check for GPU lockups */
  206. last_activity = rdev->fence_drv[ring].last_activity;
  207. trace_radeon_fence_wait_begin(rdev->ddev, seq);
  208. radeon_irq_kms_sw_irq_get(rdev, ring);
  209. if (intr) {
  210. r = wait_event_interruptible_timeout(rdev->fence_queue,
  211. (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
  212. timeout);
  213. } else {
  214. r = wait_event_timeout(rdev->fence_queue,
  215. (signaled = radeon_fence_seq_signaled(rdev, target_seq, ring)),
  216. timeout);
  217. }
  218. radeon_irq_kms_sw_irq_put(rdev, ring);
  219. if (unlikely(r < 0)) {
  220. return r;
  221. }
  222. trace_radeon_fence_wait_end(rdev->ddev, seq);
  223. if (unlikely(!signaled)) {
  224. /* we were interrupted for some reason and fence
  225. * isn't signaled yet, resume waiting */
  226. if (r) {
  227. continue;
  228. }
  229. /* check if sequence value has changed since last_activity */
  230. if (seq != atomic64_read(&rdev->fence_drv[ring].last_seq)) {
  231. continue;
  232. }
  233. if (lock_ring) {
  234. mutex_lock(&rdev->ring_lock);
  235. }
  236. /* test if somebody else has already decided that this is a lockup */
  237. if (last_activity != rdev->fence_drv[ring].last_activity) {
  238. if (lock_ring) {
  239. mutex_unlock(&rdev->ring_lock);
  240. }
  241. continue;
  242. }
  243. if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
  244. /* good news we believe it's a lockup */
  245. dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx last fence id 0x%016llx)\n",
  246. target_seq, seq);
  247. /* change last activity so nobody else think there is a lockup */
  248. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  249. rdev->fence_drv[i].last_activity = jiffies;
  250. }
  251. /* mark the ring as not ready any more */
  252. rdev->ring[ring].ready = false;
  253. if (lock_ring) {
  254. mutex_unlock(&rdev->ring_lock);
  255. }
  256. return -EDEADLK;
  257. }
  258. if (lock_ring) {
  259. mutex_unlock(&rdev->ring_lock);
  260. }
  261. }
  262. }
  263. return 0;
  264. }
  265. int radeon_fence_wait(struct radeon_fence *fence, bool intr)
  266. {
  267. int r;
  268. if (fence == NULL) {
  269. WARN(1, "Querying an invalid fence : %p !\n", fence);
  270. return -EINVAL;
  271. }
  272. r = radeon_fence_wait_seq(fence->rdev, fence->seq,
  273. fence->ring, intr, true);
  274. if (r) {
  275. return r;
  276. }
  277. fence->seq = RADEON_FENCE_SIGNALED_SEQ;
  278. return 0;
  279. }
  280. bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
  281. {
  282. unsigned i;
  283. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  284. if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i)) {
  285. return true;
  286. }
  287. }
  288. return false;
  289. }
  290. static int radeon_fence_wait_any_seq(struct radeon_device *rdev,
  291. u64 *target_seq, bool intr)
  292. {
  293. unsigned long timeout, last_activity, tmp;
  294. unsigned i, ring = RADEON_NUM_RINGS;
  295. bool signaled;
  296. int r;
  297. for (i = 0, last_activity = 0; i < RADEON_NUM_RINGS; ++i) {
  298. if (!target_seq[i]) {
  299. continue;
  300. }
  301. /* use the most recent one as indicator */
  302. if (time_after(rdev->fence_drv[i].last_activity, last_activity)) {
  303. last_activity = rdev->fence_drv[i].last_activity;
  304. }
  305. /* For lockup detection just pick the lowest ring we are
  306. * actively waiting for
  307. */
  308. if (i < ring) {
  309. ring = i;
  310. }
  311. }
  312. /* nothing to wait for ? */
  313. if (ring == RADEON_NUM_RINGS) {
  314. return 0;
  315. }
  316. while (!radeon_fence_any_seq_signaled(rdev, target_seq)) {
  317. timeout = jiffies - RADEON_FENCE_JIFFIES_TIMEOUT;
  318. if (time_after(last_activity, timeout)) {
  319. /* the normal case, timeout is somewhere before last_activity */
  320. timeout = last_activity - timeout;
  321. } else {
  322. /* either jiffies wrapped around, or no fence was signaled in the last 500ms
  323. * anyway we will just wait for the minimum amount and then check for a lockup
  324. */
  325. timeout = 1;
  326. }
  327. trace_radeon_fence_wait_begin(rdev->ddev, target_seq[ring]);
  328. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  329. if (target_seq[i]) {
  330. radeon_irq_kms_sw_irq_get(rdev, i);
  331. }
  332. }
  333. if (intr) {
  334. r = wait_event_interruptible_timeout(rdev->fence_queue,
  335. (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
  336. timeout);
  337. } else {
  338. r = wait_event_timeout(rdev->fence_queue,
  339. (signaled = radeon_fence_any_seq_signaled(rdev, target_seq)),
  340. timeout);
  341. }
  342. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  343. if (target_seq[i]) {
  344. radeon_irq_kms_sw_irq_put(rdev, i);
  345. }
  346. }
  347. if (unlikely(r < 0)) {
  348. return r;
  349. }
  350. trace_radeon_fence_wait_end(rdev->ddev, target_seq[ring]);
  351. if (unlikely(!signaled)) {
  352. /* we were interrupted for some reason and fence
  353. * isn't signaled yet, resume waiting */
  354. if (r) {
  355. continue;
  356. }
  357. mutex_lock(&rdev->ring_lock);
  358. for (i = 0, tmp = 0; i < RADEON_NUM_RINGS; ++i) {
  359. if (time_after(rdev->fence_drv[i].last_activity, tmp)) {
  360. tmp = rdev->fence_drv[i].last_activity;
  361. }
  362. }
  363. /* test if somebody else has already decided that this is a lockup */
  364. if (last_activity != tmp) {
  365. last_activity = tmp;
  366. mutex_unlock(&rdev->ring_lock);
  367. continue;
  368. }
  369. if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
  370. /* good news we believe it's a lockup */
  371. dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx)\n",
  372. target_seq[ring]);
  373. /* change last activity so nobody else think there is a lockup */
  374. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  375. rdev->fence_drv[i].last_activity = jiffies;
  376. }
  377. /* mark the ring as not ready any more */
  378. rdev->ring[ring].ready = false;
  379. mutex_unlock(&rdev->ring_lock);
  380. return -EDEADLK;
  381. }
  382. mutex_unlock(&rdev->ring_lock);
  383. }
  384. }
  385. return 0;
  386. }
  387. int radeon_fence_wait_any(struct radeon_device *rdev,
  388. struct radeon_fence **fences,
  389. bool intr)
  390. {
  391. uint64_t seq[RADEON_NUM_RINGS];
  392. unsigned i;
  393. int r;
  394. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  395. seq[i] = 0;
  396. if (!fences[i]) {
  397. continue;
  398. }
  399. if (fences[i]->seq == RADEON_FENCE_SIGNALED_SEQ) {
  400. /* something was allready signaled */
  401. return 0;
  402. }
  403. if (fences[i]->seq < RADEON_FENCE_NOTEMITED_SEQ) {
  404. seq[i] = fences[i]->seq;
  405. }
  406. }
  407. r = radeon_fence_wait_any_seq(rdev, seq, intr);
  408. if (r) {
  409. return r;
  410. }
  411. return 0;
  412. }
  413. int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring)
  414. {
  415. uint64_t seq;
  416. /* We are not protected by ring lock when reading current seq but
  417. * it's ok as worst case is we return to early while we could have
  418. * wait.
  419. */
  420. seq = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
  421. if (seq >= rdev->fence_drv[ring].seq) {
  422. /* nothing to wait for, last_seq is
  423. already the last emited fence */
  424. return -ENOENT;
  425. }
  426. return radeon_fence_wait_seq(rdev, seq, ring, false, false);
  427. }
  428. int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring)
  429. {
  430. /* We are not protected by ring lock when reading current seq
  431. * but it's ok as wait empty is call from place where no more
  432. * activity can be scheduled so there won't be concurrent access
  433. * to seq value.
  434. */
  435. return radeon_fence_wait_seq(rdev, rdev->fence_drv[ring].seq,
  436. ring, false, false);
  437. }
  438. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
  439. {
  440. kref_get(&fence->kref);
  441. return fence;
  442. }
  443. void radeon_fence_unref(struct radeon_fence **fence)
  444. {
  445. struct radeon_fence *tmp = *fence;
  446. *fence = NULL;
  447. if (tmp) {
  448. kref_put(&tmp->kref, radeon_fence_destroy);
  449. }
  450. }
  451. unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
  452. {
  453. uint64_t emitted;
  454. /* We are not protected by ring lock when reading the last sequence
  455. * but it's ok to report slightly wrong fence count here.
  456. */
  457. radeon_fence_process(rdev, ring);
  458. emitted = rdev->fence_drv[ring].seq - atomic64_read(&rdev->fence_drv[ring].last_seq);
  459. /* to avoid 32bits warp around */
  460. if (emitted > 0x10000000) {
  461. emitted = 0x10000000;
  462. }
  463. return (unsigned)emitted;
  464. }
  465. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
  466. {
  467. uint64_t index;
  468. int r;
  469. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  470. if (rdev->wb.use_event) {
  471. rdev->fence_drv[ring].scratch_reg = 0;
  472. index = R600_WB_EVENT_OFFSET + ring * 4;
  473. } else {
  474. r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
  475. if (r) {
  476. dev_err(rdev->dev, "fence failed to get scratch register\n");
  477. return r;
  478. }
  479. index = RADEON_WB_SCRATCH_OFFSET +
  480. rdev->fence_drv[ring].scratch_reg -
  481. rdev->scratch.reg_base;
  482. }
  483. rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
  484. rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
  485. radeon_fence_write(rdev, rdev->fence_drv[ring].seq, ring);
  486. rdev->fence_drv[ring].initialized = true;
  487. dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
  488. ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
  489. return 0;
  490. }
  491. static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
  492. {
  493. rdev->fence_drv[ring].scratch_reg = -1;
  494. rdev->fence_drv[ring].cpu_addr = NULL;
  495. rdev->fence_drv[ring].gpu_addr = 0;
  496. rdev->fence_drv[ring].seq = 0;
  497. atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
  498. rdev->fence_drv[ring].last_activity = jiffies;
  499. rdev->fence_drv[ring].initialized = false;
  500. }
  501. int radeon_fence_driver_init(struct radeon_device *rdev)
  502. {
  503. int ring;
  504. init_waitqueue_head(&rdev->fence_queue);
  505. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  506. radeon_fence_driver_init_ring(rdev, ring);
  507. }
  508. if (radeon_debugfs_fence_init(rdev)) {
  509. dev_err(rdev->dev, "fence debugfs file creation failed\n");
  510. }
  511. return 0;
  512. }
  513. void radeon_fence_driver_fini(struct radeon_device *rdev)
  514. {
  515. int ring;
  516. mutex_lock(&rdev->ring_lock);
  517. for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
  518. if (!rdev->fence_drv[ring].initialized)
  519. continue;
  520. radeon_fence_wait_empty_locked(rdev, ring);
  521. wake_up_all(&rdev->fence_queue);
  522. radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
  523. rdev->fence_drv[ring].initialized = false;
  524. }
  525. mutex_unlock(&rdev->ring_lock);
  526. }
  527. /*
  528. * Fence debugfs
  529. */
  530. #if defined(CONFIG_DEBUG_FS)
  531. static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
  532. {
  533. struct drm_info_node *node = (struct drm_info_node *)m->private;
  534. struct drm_device *dev = node->minor->dev;
  535. struct radeon_device *rdev = dev->dev_private;
  536. int i;
  537. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  538. if (!rdev->fence_drv[i].initialized)
  539. continue;
  540. seq_printf(m, "--- ring %d ---\n", i);
  541. seq_printf(m, "Last signaled fence 0x%016lx\n",
  542. atomic64_read(&rdev->fence_drv[i].last_seq));
  543. seq_printf(m, "Last emitted 0x%016llx\n",
  544. rdev->fence_drv[i].seq);
  545. }
  546. return 0;
  547. }
  548. static struct drm_info_list radeon_debugfs_fence_list[] = {
  549. {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
  550. };
  551. #endif
  552. int radeon_debugfs_fence_init(struct radeon_device *rdev)
  553. {
  554. #if defined(CONFIG_DEBUG_FS)
  555. return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
  556. #else
  557. return 0;
  558. #endif
  559. }