main.c 226 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/pci_ids.h>
  17. #include <linux/if_ether.h>
  18. #include <net/mac80211.h>
  19. #include <brcm_hw_ids.h>
  20. #include <aiutils.h>
  21. #include <chipcommon.h>
  22. #include "rate.h"
  23. #include "scb.h"
  24. #include "phy/phy_hal.h"
  25. #include "channel.h"
  26. #include "antsel.h"
  27. #include "stf.h"
  28. #include "ampdu.h"
  29. #include "mac80211_if.h"
  30. #include "ucode_loader.h"
  31. #include "main.h"
  32. #include "soc.h"
  33. /*
  34. * Indication for txflowcontrol that all priority bits in
  35. * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
  36. */
  37. #define ALLPRIO -1
  38. /* watchdog timer, in unit of ms */
  39. #define TIMER_INTERVAL_WATCHDOG 1000
  40. /* radio monitor timer, in unit of ms */
  41. #define TIMER_INTERVAL_RADIOCHK 800
  42. /* beacon interval, in unit of 1024TU */
  43. #define BEACON_INTERVAL_DEFAULT 100
  44. /* n-mode support capability */
  45. /* 2x2 includes both 1x1 & 2x2 devices
  46. * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
  47. * control it independently
  48. */
  49. #define WL_11N_2x2 1
  50. #define WL_11N_3x3 3
  51. #define WL_11N_4x4 4
  52. #define EDCF_ACI_MASK 0x60
  53. #define EDCF_ACI_SHIFT 5
  54. #define EDCF_ECWMIN_MASK 0x0f
  55. #define EDCF_ECWMAX_SHIFT 4
  56. #define EDCF_AIFSN_MASK 0x0f
  57. #define EDCF_AIFSN_MAX 15
  58. #define EDCF_ECWMAX_MASK 0xf0
  59. #define EDCF_AC_BE_TXOP_STA 0x0000
  60. #define EDCF_AC_BK_TXOP_STA 0x0000
  61. #define EDCF_AC_VO_ACI_STA 0x62
  62. #define EDCF_AC_VO_ECW_STA 0x32
  63. #define EDCF_AC_VI_ACI_STA 0x42
  64. #define EDCF_AC_VI_ECW_STA 0x43
  65. #define EDCF_AC_BK_ECW_STA 0xA4
  66. #define EDCF_AC_VI_TXOP_STA 0x005e
  67. #define EDCF_AC_VO_TXOP_STA 0x002f
  68. #define EDCF_AC_BE_ACI_STA 0x03
  69. #define EDCF_AC_BE_ECW_STA 0xA4
  70. #define EDCF_AC_BK_ACI_STA 0x27
  71. #define EDCF_AC_VO_TXOP_AP 0x002f
  72. #define EDCF_TXOP2USEC(txop) ((txop) << 5)
  73. #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
  74. #define APHY_SYMBOL_TIME 4
  75. #define APHY_PREAMBLE_TIME 16
  76. #define APHY_SIGNAL_TIME 4
  77. #define APHY_SIFS_TIME 16
  78. #define APHY_SERVICE_NBITS 16
  79. #define APHY_TAIL_NBITS 6
  80. #define BPHY_SIFS_TIME 10
  81. #define BPHY_PLCP_SHORT_TIME 96
  82. #define PREN_PREAMBLE 24
  83. #define PREN_MM_EXT 12
  84. #define PREN_PREAMBLE_EXT 4
  85. #define DOT11_MAC_HDR_LEN 24
  86. #define DOT11_ACK_LEN 10
  87. #define DOT11_BA_LEN 4
  88. #define DOT11_OFDM_SIGNAL_EXTENSION 6
  89. #define DOT11_MIN_FRAG_LEN 256
  90. #define DOT11_RTS_LEN 16
  91. #define DOT11_CTS_LEN 10
  92. #define DOT11_BA_BITMAP_LEN 128
  93. #define DOT11_MIN_BEACON_PERIOD 1
  94. #define DOT11_MAX_BEACON_PERIOD 0xFFFF
  95. #define DOT11_MAXNUMFRAGS 16
  96. #define DOT11_MAX_FRAG_LEN 2346
  97. #define BPHY_PLCP_TIME 192
  98. #define RIFS_11N_TIME 2
  99. /* length of the BCN template area */
  100. #define BCN_TMPL_LEN 512
  101. /* brcms_bss_info flag bit values */
  102. #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
  103. /* chip rx buffer offset */
  104. #define BRCMS_HWRXOFF 38
  105. /* rfdisable delay timer 500 ms, runs of ALP clock */
  106. #define RFDISABLE_DEFAULT 10000000
  107. #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
  108. /* precedences numbers for wlc queues. These are twice as may levels as
  109. * 802.1D priorities.
  110. * Odd numbers are used for HI priority traffic at same precedence levels
  111. * These constants are used ONLY by wlc_prio2prec_map. Do not use them
  112. * elsewhere.
  113. */
  114. #define _BRCMS_PREC_NONE 0 /* None = - */
  115. #define _BRCMS_PREC_BK 2 /* BK - Background */
  116. #define _BRCMS_PREC_BE 4 /* BE - Best-effort */
  117. #define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
  118. #define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
  119. #define _BRCMS_PREC_VI 10 /* Vi - Video */
  120. #define _BRCMS_PREC_VO 12 /* Vo - Voice */
  121. #define _BRCMS_PREC_NC 14 /* NC - Network Control */
  122. /* synthpu_dly times in us */
  123. #define SYNTHPU_DLY_APHY_US 3700
  124. #define SYNTHPU_DLY_BPHY_US 1050
  125. #define SYNTHPU_DLY_NPHY_US 2048
  126. #define SYNTHPU_DLY_LPPHY_US 300
  127. #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
  128. /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
  129. #define EDCF_SHORT_S 0
  130. #define EDCF_SFB_S 4
  131. #define EDCF_LONG_S 8
  132. #define EDCF_LFB_S 12
  133. #define EDCF_SHORT_M BITFIELD_MASK(4)
  134. #define EDCF_SFB_M BITFIELD_MASK(4)
  135. #define EDCF_LONG_M BITFIELD_MASK(4)
  136. #define EDCF_LFB_M BITFIELD_MASK(4)
  137. #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
  138. #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
  139. #define RETRY_LONG_DEF 4 /* Default Long retry count */
  140. #define RETRY_SHORT_FB 3 /* Short count for fb rate */
  141. #define RETRY_LONG_FB 2 /* Long count for fb rate */
  142. #define APHY_CWMIN 15
  143. #define PHY_CWMAX 1023
  144. #define EDCF_AIFSN_MIN 1
  145. #define FRAGNUM_MASK 0xF
  146. #define APHY_SLOT_TIME 9
  147. #define BPHY_SLOT_TIME 20
  148. #define WL_SPURAVOID_OFF 0
  149. #define WL_SPURAVOID_ON1 1
  150. #define WL_SPURAVOID_ON2 2
  151. /* invalid core flags, use the saved coreflags */
  152. #define BRCMS_USE_COREFLAGS 0xffffffff
  153. /* values for PLCPHdr_override */
  154. #define BRCMS_PLCP_AUTO -1
  155. #define BRCMS_PLCP_SHORT 0
  156. #define BRCMS_PLCP_LONG 1
  157. /* values for g_protection_override and n_protection_override */
  158. #define BRCMS_PROTECTION_AUTO -1
  159. #define BRCMS_PROTECTION_OFF 0
  160. #define BRCMS_PROTECTION_ON 1
  161. #define BRCMS_PROTECTION_MMHDR_ONLY 2
  162. #define BRCMS_PROTECTION_CTS_ONLY 3
  163. /* values for g_protection_control and n_protection_control */
  164. #define BRCMS_PROTECTION_CTL_OFF 0
  165. #define BRCMS_PROTECTION_CTL_LOCAL 1
  166. #define BRCMS_PROTECTION_CTL_OVERLAP 2
  167. /* values for n_protection */
  168. #define BRCMS_N_PROTECTION_OFF 0
  169. #define BRCMS_N_PROTECTION_OPTIONAL 1
  170. #define BRCMS_N_PROTECTION_20IN40 2
  171. #define BRCMS_N_PROTECTION_MIXEDMODE 3
  172. /* values for band specific 40MHz capabilities */
  173. #define BRCMS_N_BW_20ALL 0
  174. #define BRCMS_N_BW_40ALL 1
  175. #define BRCMS_N_BW_20IN2G_40IN5G 2
  176. /* bitflags for SGI support (sgi_rx iovar) */
  177. #define BRCMS_N_SGI_20 0x01
  178. #define BRCMS_N_SGI_40 0x02
  179. /* defines used by the nrate iovar */
  180. /* MSC in use,indicates b0-6 holds an mcs */
  181. #define NRATE_MCS_INUSE 0x00000080
  182. /* rate/mcs value */
  183. #define NRATE_RATE_MASK 0x0000007f
  184. /* stf mode mask: siso, cdd, stbc, sdm */
  185. #define NRATE_STF_MASK 0x0000ff00
  186. /* stf mode shift */
  187. #define NRATE_STF_SHIFT 8
  188. /* bit indicate to override mcs only */
  189. #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
  190. #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
  191. #define NRATE_SGI_SHIFT 23 /* sgi mode */
  192. #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
  193. #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
  194. #define NRATE_STF_SISO 0 /* stf mode SISO */
  195. #define NRATE_STF_CDD 1 /* stf mode CDD */
  196. #define NRATE_STF_STBC 2 /* stf mode STBC */
  197. #define NRATE_STF_SDM 3 /* stf mode SDM */
  198. #define MAX_DMA_SEGS 4
  199. /* Max # of entries in Tx FIFO based on 4kb page size */
  200. #define NTXD 256
  201. /* Max # of entries in Rx FIFO based on 4kb page size */
  202. #define NRXD 256
  203. /* try to keep this # rbufs posted to the chip */
  204. #define NRXBUFPOST 32
  205. /* data msg txq hiwat mark */
  206. #define BRCMS_DATAHIWAT 50
  207. /* max # frames to process in brcms_c_recv() */
  208. #define RXBND 8
  209. /* max # tx status to process in wlc_txstatus() */
  210. #define TXSBND 8
  211. /* brcmu_format_flags() bit description structure */
  212. struct brcms_c_bit_desc {
  213. u32 bit;
  214. const char *name;
  215. };
  216. /*
  217. * The following table lists the buffer memory allocated to xmt fifos in HW.
  218. * the size is in units of 256bytes(one block), total size is HW dependent
  219. * ucode has default fifo partition, sw can overwrite if necessary
  220. *
  221. * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  222. * the twiki is updated before making changes.
  223. */
  224. /* Starting corerev for the fifo size table */
  225. #define XMTFIFOTBL_STARTREV 20
  226. struct d11init {
  227. __le16 addr;
  228. __le16 size;
  229. __le32 value;
  230. };
  231. struct edcf_acparam {
  232. u8 ACI;
  233. u8 ECW;
  234. u16 TXOP;
  235. } __packed;
  236. const u8 prio2fifo[NUMPRIO] = {
  237. TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
  238. TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
  239. TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
  240. TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
  241. TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
  242. TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
  243. TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
  244. TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
  245. };
  246. /* debug/trace */
  247. uint brcm_msg_level =
  248. #if defined(BCMDBG)
  249. LOG_ERROR_VAL;
  250. #else
  251. 0;
  252. #endif /* BCMDBG */
  253. /* TX FIFO number to WME/802.1E Access Category */
  254. static const u8 wme_fifo2ac[] = {
  255. IEEE80211_AC_BK,
  256. IEEE80211_AC_BE,
  257. IEEE80211_AC_VI,
  258. IEEE80211_AC_VO,
  259. IEEE80211_AC_BE,
  260. IEEE80211_AC_BE
  261. };
  262. /* ieee80211 Access Category to TX FIFO number */
  263. static const u8 wme_ac2fifo[] = {
  264. TX_AC_VO_FIFO,
  265. TX_AC_VI_FIFO,
  266. TX_AC_BE_FIFO,
  267. TX_AC_BK_FIFO
  268. };
  269. /* 802.1D Priority to precedence queue mapping */
  270. const u8 wlc_prio2prec_map[] = {
  271. _BRCMS_PREC_BE, /* 0 BE - Best-effort */
  272. _BRCMS_PREC_BK, /* 1 BK - Background */
  273. _BRCMS_PREC_NONE, /* 2 None = - */
  274. _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */
  275. _BRCMS_PREC_CL, /* 4 CL - Controlled Load */
  276. _BRCMS_PREC_VI, /* 5 Vi - Video */
  277. _BRCMS_PREC_VO, /* 6 Vo - Voice */
  278. _BRCMS_PREC_NC, /* 7 NC - Network Control */
  279. };
  280. static const u16 xmtfifo_sz[][NFIFO] = {
  281. /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  282. {20, 192, 192, 21, 17, 5},
  283. /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  284. {9, 58, 22, 14, 14, 5},
  285. /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  286. {20, 192, 192, 21, 17, 5},
  287. /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  288. {20, 192, 192, 21, 17, 5},
  289. /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  290. {9, 58, 22, 14, 14, 5},
  291. };
  292. #ifdef BCMDBG
  293. static const char * const fifo_names[] = {
  294. "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
  295. #else
  296. static const char fifo_names[6][0];
  297. #endif
  298. #ifdef BCMDBG
  299. /* pointer to most recently allocated wl/wlc */
  300. static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
  301. #endif
  302. /* Find basic rate for a given rate */
  303. static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
  304. {
  305. if (is_mcs_rate(rspec))
  306. return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
  307. .leg_ofdm];
  308. return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
  309. }
  310. static u16 frametype(u32 rspec, u8 mimoframe)
  311. {
  312. if (is_mcs_rate(rspec))
  313. return mimoframe;
  314. return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
  315. }
  316. /* currently the best mechanism for determining SIFS is the band in use */
  317. static u16 get_sifs(struct brcms_band *band)
  318. {
  319. return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
  320. BPHY_SIFS_TIME;
  321. }
  322. /*
  323. * Detect Card removed.
  324. * Even checking an sbconfig register read will not false trigger when the core
  325. * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
  326. * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
  327. * reg with fixed 0/1 pattern (some platforms return all 0).
  328. * If clocks are present, call the sb routine which will figure out if the
  329. * device is removed.
  330. */
  331. static bool brcms_deviceremoved(struct brcms_c_info *wlc)
  332. {
  333. u32 macctrl;
  334. if (!wlc->hw->clk)
  335. return ai_deviceremoved(wlc->hw->sih);
  336. macctrl = bcma_read32(wlc->hw->d11core,
  337. D11REGOFFS(maccontrol));
  338. return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
  339. }
  340. /* sum the individual fifo tx pending packet counts */
  341. static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
  342. {
  343. return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
  344. wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
  345. }
  346. static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
  347. {
  348. return wlc->pub->_nbands > 1 && !wlc->bandlocked;
  349. }
  350. static int brcms_chspec_bw(u16 chanspec)
  351. {
  352. if (CHSPEC_IS40(chanspec))
  353. return BRCMS_40_MHZ;
  354. if (CHSPEC_IS20(chanspec))
  355. return BRCMS_20_MHZ;
  356. return BRCMS_10_MHZ;
  357. }
  358. static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
  359. {
  360. if (cfg == NULL)
  361. return;
  362. kfree(cfg->current_bss);
  363. kfree(cfg);
  364. }
  365. static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
  366. {
  367. if (wlc == NULL)
  368. return;
  369. brcms_c_bsscfg_mfree(wlc->bsscfg);
  370. kfree(wlc->pub);
  371. kfree(wlc->modulecb);
  372. kfree(wlc->default_bss);
  373. kfree(wlc->protection);
  374. kfree(wlc->stf);
  375. kfree(wlc->bandstate[0]);
  376. kfree(wlc->corestate->macstat_snapshot);
  377. kfree(wlc->corestate);
  378. kfree(wlc->hw->bandstate[0]);
  379. kfree(wlc->hw);
  380. /* free the wlc */
  381. kfree(wlc);
  382. wlc = NULL;
  383. }
  384. static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
  385. {
  386. struct brcms_bss_cfg *cfg;
  387. cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
  388. if (cfg == NULL)
  389. goto fail;
  390. cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  391. if (cfg->current_bss == NULL)
  392. goto fail;
  393. return cfg;
  394. fail:
  395. brcms_c_bsscfg_mfree(cfg);
  396. return NULL;
  397. }
  398. static struct brcms_c_info *
  399. brcms_c_attach_malloc(uint unit, uint *err, uint devid)
  400. {
  401. struct brcms_c_info *wlc;
  402. wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
  403. if (wlc == NULL) {
  404. *err = 1002;
  405. goto fail;
  406. }
  407. /* allocate struct brcms_c_pub state structure */
  408. wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
  409. if (wlc->pub == NULL) {
  410. *err = 1003;
  411. goto fail;
  412. }
  413. wlc->pub->wlc = wlc;
  414. /* allocate struct brcms_hardware state structure */
  415. wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
  416. if (wlc->hw == NULL) {
  417. *err = 1005;
  418. goto fail;
  419. }
  420. wlc->hw->wlc = wlc;
  421. wlc->hw->bandstate[0] =
  422. kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
  423. if (wlc->hw->bandstate[0] == NULL) {
  424. *err = 1006;
  425. goto fail;
  426. } else {
  427. int i;
  428. for (i = 1; i < MAXBANDS; i++)
  429. wlc->hw->bandstate[i] = (struct brcms_hw_band *)
  430. ((unsigned long)wlc->hw->bandstate[0] +
  431. (sizeof(struct brcms_hw_band) * i));
  432. }
  433. wlc->modulecb =
  434. kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
  435. if (wlc->modulecb == NULL) {
  436. *err = 1009;
  437. goto fail;
  438. }
  439. wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  440. if (wlc->default_bss == NULL) {
  441. *err = 1010;
  442. goto fail;
  443. }
  444. wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
  445. if (wlc->bsscfg == NULL) {
  446. *err = 1011;
  447. goto fail;
  448. }
  449. wlc->protection = kzalloc(sizeof(struct brcms_protection),
  450. GFP_ATOMIC);
  451. if (wlc->protection == NULL) {
  452. *err = 1016;
  453. goto fail;
  454. }
  455. wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
  456. if (wlc->stf == NULL) {
  457. *err = 1017;
  458. goto fail;
  459. }
  460. wlc->bandstate[0] =
  461. kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
  462. if (wlc->bandstate[0] == NULL) {
  463. *err = 1025;
  464. goto fail;
  465. } else {
  466. int i;
  467. for (i = 1; i < MAXBANDS; i++)
  468. wlc->bandstate[i] = (struct brcms_band *)
  469. ((unsigned long)wlc->bandstate[0]
  470. + (sizeof(struct brcms_band)*i));
  471. }
  472. wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
  473. if (wlc->corestate == NULL) {
  474. *err = 1026;
  475. goto fail;
  476. }
  477. wlc->corestate->macstat_snapshot =
  478. kzalloc(sizeof(struct macstat), GFP_ATOMIC);
  479. if (wlc->corestate->macstat_snapshot == NULL) {
  480. *err = 1027;
  481. goto fail;
  482. }
  483. return wlc;
  484. fail:
  485. brcms_c_detach_mfree(wlc);
  486. return NULL;
  487. }
  488. /*
  489. * Update the slot timing for standard 11b/g (20us slots)
  490. * or shortslot 11g (9us slots)
  491. * The PSM needs to be suspended for this call.
  492. */
  493. static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
  494. bool shortslot)
  495. {
  496. struct bcma_device *core = wlc_hw->d11core;
  497. if (shortslot) {
  498. /* 11g short slot: 11a timing */
  499. bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
  500. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
  501. } else {
  502. /* 11g long slot: 11b timing */
  503. bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
  504. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
  505. }
  506. }
  507. /*
  508. * calculate frame duration of a given rate and length, return
  509. * time in usec unit
  510. */
  511. static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
  512. u8 preamble_type, uint mac_len)
  513. {
  514. uint nsyms, dur = 0, Ndps, kNdps;
  515. uint rate = rspec2rate(ratespec);
  516. if (rate == 0) {
  517. wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
  518. wlc->pub->unit);
  519. rate = BRCM_RATE_1M;
  520. }
  521. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
  522. wlc->pub->unit, ratespec, preamble_type, mac_len);
  523. if (is_mcs_rate(ratespec)) {
  524. uint mcs = ratespec & RSPEC_RATE_MASK;
  525. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  526. dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  527. if (preamble_type == BRCMS_MM_PREAMBLE)
  528. dur += PREN_MM_EXT;
  529. /* 1000Ndbps = kbps * 4 */
  530. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  531. rspec_issgi(ratespec)) * 4;
  532. if (rspec_stc(ratespec) == 0)
  533. nsyms =
  534. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  535. APHY_TAIL_NBITS) * 1000, kNdps);
  536. else
  537. /* STBC needs to have even number of symbols */
  538. nsyms =
  539. 2 *
  540. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  541. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  542. dur += APHY_SYMBOL_TIME * nsyms;
  543. if (wlc->band->bandtype == BRCM_BAND_2G)
  544. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  545. } else if (is_ofdm_rate(rate)) {
  546. dur = APHY_PREAMBLE_TIME;
  547. dur += APHY_SIGNAL_TIME;
  548. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  549. Ndps = rate * 2;
  550. /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
  551. nsyms =
  552. CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
  553. Ndps);
  554. dur += APHY_SYMBOL_TIME * nsyms;
  555. if (wlc->band->bandtype == BRCM_BAND_2G)
  556. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  557. } else {
  558. /*
  559. * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
  560. * will divide out
  561. */
  562. mac_len = mac_len * 8 * 2;
  563. /* calc ceiling of bits/rate = microseconds of air time */
  564. dur = (mac_len + rate - 1) / rate;
  565. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  566. dur += BPHY_PLCP_SHORT_TIME;
  567. else
  568. dur += BPHY_PLCP_TIME;
  569. }
  570. return dur;
  571. }
  572. static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
  573. const struct d11init *inits)
  574. {
  575. struct bcma_device *core = wlc_hw->d11core;
  576. int i;
  577. uint offset;
  578. u16 size;
  579. u32 value;
  580. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  581. for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
  582. size = le16_to_cpu(inits[i].size);
  583. offset = le16_to_cpu(inits[i].addr);
  584. value = le32_to_cpu(inits[i].value);
  585. if (size == 2)
  586. bcma_write16(core, offset, value);
  587. else if (size == 4)
  588. bcma_write32(core, offset, value);
  589. else
  590. break;
  591. }
  592. }
  593. static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
  594. {
  595. u8 idx;
  596. u16 addr[] = {
  597. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  598. M_HOST_FLAGS5
  599. };
  600. for (idx = 0; idx < MHFMAX; idx++)
  601. brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
  602. }
  603. static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
  604. {
  605. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  606. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  607. /* init microcode host flags */
  608. brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
  609. /* do band-specific ucode IHR, SHM, and SCR inits */
  610. if (D11REV_IS(wlc_hw->corerev, 23)) {
  611. if (BRCMS_ISNPHY(wlc_hw->band))
  612. brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
  613. else
  614. wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
  615. " %d\n", __func__, wlc_hw->unit,
  616. wlc_hw->corerev);
  617. } else {
  618. if (D11REV_IS(wlc_hw->corerev, 24)) {
  619. if (BRCMS_ISLCNPHY(wlc_hw->band))
  620. brcms_c_write_inits(wlc_hw,
  621. ucode->d11lcn0bsinitvals24);
  622. else
  623. wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
  624. " core rev %d\n", __func__,
  625. wlc_hw->unit, wlc_hw->corerev);
  626. } else {
  627. wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
  628. __func__, wlc_hw->unit, wlc_hw->corerev);
  629. }
  630. }
  631. }
  632. static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
  633. {
  634. struct bcma_device *core = wlc_hw->d11core;
  635. u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
  636. bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
  637. }
  638. static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
  639. {
  640. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
  641. wlc_hw->phyclk = clk;
  642. if (OFF == clk) { /* clear gmode bit, put phy into reset */
  643. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
  644. (SICF_PRST | SICF_FGC));
  645. udelay(1);
  646. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
  647. udelay(1);
  648. } else { /* take phy out of reset */
  649. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
  650. udelay(1);
  651. brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
  652. udelay(1);
  653. }
  654. }
  655. /* low-level band switch utility routine */
  656. static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
  657. {
  658. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  659. bandunit);
  660. wlc_hw->band = wlc_hw->bandstate[bandunit];
  661. /*
  662. * BMAC_NOTE:
  663. * until we eliminate need for wlc->band refs in low level code
  664. */
  665. wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
  666. /* set gmode core flag */
  667. if (wlc_hw->sbclk && !wlc_hw->noreset) {
  668. u32 gmode = 0;
  669. if (bandunit == 0)
  670. gmode = SICF_GMODE;
  671. brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
  672. }
  673. }
  674. /* switch to new band but leave it inactive */
  675. static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
  676. {
  677. struct brcms_hardware *wlc_hw = wlc->hw;
  678. u32 macintmask;
  679. u32 macctrl;
  680. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  681. macctrl = bcma_read32(wlc_hw->d11core,
  682. D11REGOFFS(maccontrol));
  683. WARN_ON((macctrl & MCTL_EN_MAC) != 0);
  684. /* disable interrupts */
  685. macintmask = brcms_intrsoff(wlc->wl);
  686. /* radio off */
  687. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  688. brcms_b_core_phy_clk(wlc_hw, OFF);
  689. brcms_c_setxband(wlc_hw, bandunit);
  690. return macintmask;
  691. }
  692. /* process an individual struct tx_status */
  693. static bool
  694. brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
  695. {
  696. struct sk_buff *p;
  697. uint queue;
  698. struct d11txh *txh;
  699. struct scb *scb = NULL;
  700. bool free_pdu;
  701. int tx_rts, tx_frame_count, tx_rts_count;
  702. uint totlen, supr_status;
  703. bool lastframe;
  704. struct ieee80211_hdr *h;
  705. u16 mcl;
  706. struct ieee80211_tx_info *tx_info;
  707. struct ieee80211_tx_rate *txrate;
  708. int i;
  709. /* discard intermediate indications for ucode with one legitimate case:
  710. * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
  711. * but the subsequent tx of DATA failed. so it will start rts/cts
  712. * from the beginning (resetting the rts transmission count)
  713. */
  714. if (!(txs->status & TX_STATUS_AMPDU)
  715. && (txs->status & TX_STATUS_INTERMEDIATE)) {
  716. wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
  717. __func__);
  718. return false;
  719. }
  720. queue = txs->frameid & TXFID_QUEUE_MASK;
  721. if (queue >= NFIFO) {
  722. p = NULL;
  723. goto fatal;
  724. }
  725. p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
  726. if (p == NULL)
  727. goto fatal;
  728. txh = (struct d11txh *) (p->data);
  729. mcl = le16_to_cpu(txh->MacTxControlLow);
  730. if (txs->phyerr) {
  731. if (brcm_msg_level & LOG_ERROR_VAL) {
  732. wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
  733. txs->phyerr, txh->MainRates);
  734. brcms_c_print_txdesc(txh);
  735. }
  736. brcms_c_print_txstatus(txs);
  737. }
  738. if (txs->frameid != le16_to_cpu(txh->TxFrameID))
  739. goto fatal;
  740. tx_info = IEEE80211_SKB_CB(p);
  741. h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
  742. if (tx_info->control.sta)
  743. scb = &wlc->pri_scb;
  744. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  745. brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
  746. return false;
  747. }
  748. supr_status = txs->status & TX_STATUS_SUPR_MASK;
  749. if (supr_status == TX_STATUS_SUPR_BADCH)
  750. BCMMSG(wlc->wiphy,
  751. "%s: Pkt tx suppressed, possibly channel %d\n",
  752. __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
  753. tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
  754. tx_frame_count =
  755. (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
  756. tx_rts_count =
  757. (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
  758. lastframe = !ieee80211_has_morefrags(h->frame_control);
  759. if (!lastframe) {
  760. wiphy_err(wlc->wiphy, "Not last frame!\n");
  761. } else {
  762. /*
  763. * Set information to be consumed by Minstrel ht.
  764. *
  765. * The "fallback limit" is the number of tx attempts a given
  766. * MPDU is sent at the "primary" rate. Tx attempts beyond that
  767. * limit are sent at the "secondary" rate.
  768. * A 'short frame' does not exceed RTS treshold.
  769. */
  770. u16 sfbl, /* Short Frame Rate Fallback Limit */
  771. lfbl, /* Long Frame Rate Fallback Limit */
  772. fbl;
  773. if (queue < IEEE80211_NUM_ACS) {
  774. sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  775. EDCF_SFB);
  776. lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  777. EDCF_LFB);
  778. } else {
  779. sfbl = wlc->SFBL;
  780. lfbl = wlc->LFBL;
  781. }
  782. txrate = tx_info->status.rates;
  783. if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
  784. fbl = lfbl;
  785. else
  786. fbl = sfbl;
  787. ieee80211_tx_info_clear_status(tx_info);
  788. if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
  789. /*
  790. * rate selection requested a fallback rate
  791. * and we used it
  792. */
  793. txrate[0].count = fbl;
  794. txrate[1].count = tx_frame_count - fbl;
  795. } else {
  796. /*
  797. * rate selection did not request fallback rate, or
  798. * we didn't need it
  799. */
  800. txrate[0].count = tx_frame_count;
  801. /*
  802. * rc80211_minstrel.c:minstrel_tx_status() expects
  803. * unused rates to be marked with idx = -1
  804. */
  805. txrate[1].idx = -1;
  806. txrate[1].count = 0;
  807. }
  808. /* clear the rest of the rates */
  809. for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
  810. txrate[i].idx = -1;
  811. txrate[i].count = 0;
  812. }
  813. if (txs->status & TX_STATUS_ACK_RCV)
  814. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  815. }
  816. totlen = p->len;
  817. free_pdu = true;
  818. brcms_c_txfifo_complete(wlc, queue, 1);
  819. if (lastframe) {
  820. /* remove PLCP & Broadcom tx descriptor header */
  821. skb_pull(p, D11_PHY_HDR_LEN);
  822. skb_pull(p, D11_TXH_LEN);
  823. ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
  824. } else {
  825. wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
  826. "tx_status\n", __func__);
  827. }
  828. return false;
  829. fatal:
  830. if (p)
  831. brcmu_pkt_buf_free_skb(p);
  832. return true;
  833. }
  834. /* process tx completion events in BMAC
  835. * Return true if more tx status need to be processed. false otherwise.
  836. */
  837. static bool
  838. brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
  839. {
  840. bool morepending = false;
  841. struct brcms_c_info *wlc = wlc_hw->wlc;
  842. struct bcma_device *core;
  843. struct tx_status txstatus, *txs;
  844. u32 s1, s2;
  845. uint n = 0;
  846. /*
  847. * Param 'max_tx_num' indicates max. # tx status to process before
  848. * break out.
  849. */
  850. uint max_tx_num = bound ? TXSBND : -1;
  851. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  852. txs = &txstatus;
  853. core = wlc_hw->d11core;
  854. *fatal = false;
  855. s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
  856. while (!(*fatal)
  857. && (s1 & TXS_V)) {
  858. if (s1 == 0xffffffff) {
  859. wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
  860. wlc_hw->unit, __func__);
  861. return morepending;
  862. }
  863. s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
  864. txs->status = s1 & TXS_STATUS_MASK;
  865. txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
  866. txs->sequence = s2 & TXS_SEQ_MASK;
  867. txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
  868. txs->lasttxtime = 0;
  869. *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
  870. /* !give others some time to run! */
  871. if (++n >= max_tx_num)
  872. break;
  873. s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
  874. }
  875. if (*fatal)
  876. return 0;
  877. if (n >= max_tx_num)
  878. morepending = true;
  879. if (!pktq_empty(&wlc->pkt_queue->q))
  880. brcms_c_send_q(wlc);
  881. return morepending;
  882. }
  883. static void brcms_c_tbtt(struct brcms_c_info *wlc)
  884. {
  885. if (!wlc->bsscfg->BSS)
  886. /*
  887. * DirFrmQ is now valid...defer setting until end
  888. * of ATIM window
  889. */
  890. wlc->qvalid |= MCMD_DIRFRMQVAL;
  891. }
  892. /* set initial host flags value */
  893. static void
  894. brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
  895. {
  896. struct brcms_hardware *wlc_hw = wlc->hw;
  897. memset(mhfs, 0, MHFMAX * sizeof(u16));
  898. mhfs[MHF2] |= mhf2_init;
  899. /* prohibit use of slowclock on multifunction boards */
  900. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  901. mhfs[MHF1] |= MHF1_FORCEFASTCLK;
  902. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
  903. mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
  904. mhfs[MHF1] |= MHF1_IQSWAP_WAR;
  905. }
  906. }
  907. static uint
  908. dmareg(uint direction, uint fifonum)
  909. {
  910. if (direction == DMA_TX)
  911. return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
  912. return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
  913. }
  914. static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
  915. {
  916. uint i;
  917. char name[8];
  918. /*
  919. * ucode host flag 2 needed for pio mode, independent of band and fifo
  920. */
  921. u16 pio_mhf2 = 0;
  922. struct brcms_hardware *wlc_hw = wlc->hw;
  923. uint unit = wlc_hw->unit;
  924. struct wiphy *wiphy = wlc->wiphy;
  925. /* name and offsets for dma_attach */
  926. snprintf(name, sizeof(name), "wl%d", unit);
  927. if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
  928. int dma_attach_err = 0;
  929. /*
  930. * FIFO 0
  931. * TX: TX_AC_BK_FIFO (TX AC Background data packets)
  932. * RX: RX_FIFO (RX data packets)
  933. */
  934. wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
  935. (wme ? dmareg(DMA_TX, 0) : 0),
  936. dmareg(DMA_RX, 0),
  937. (wme ? NTXD : 0), NRXD,
  938. RXBUFSZ, -1, NRXBUFPOST,
  939. BRCMS_HWRXOFF, &brcm_msg_level);
  940. dma_attach_err |= (NULL == wlc_hw->di[0]);
  941. /*
  942. * FIFO 1
  943. * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
  944. * (legacy) TX_DATA_FIFO (TX data packets)
  945. * RX: UNUSED
  946. */
  947. wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
  948. dmareg(DMA_TX, 1), 0,
  949. NTXD, 0, 0, -1, 0, 0,
  950. &brcm_msg_level);
  951. dma_attach_err |= (NULL == wlc_hw->di[1]);
  952. /*
  953. * FIFO 2
  954. * TX: TX_AC_VI_FIFO (TX AC Video data packets)
  955. * RX: UNUSED
  956. */
  957. wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
  958. dmareg(DMA_TX, 2), 0,
  959. NTXD, 0, 0, -1, 0, 0,
  960. &brcm_msg_level);
  961. dma_attach_err |= (NULL == wlc_hw->di[2]);
  962. /*
  963. * FIFO 3
  964. * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
  965. * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
  966. */
  967. wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
  968. dmareg(DMA_TX, 3),
  969. 0, NTXD, 0, 0, -1,
  970. 0, 0, &brcm_msg_level);
  971. dma_attach_err |= (NULL == wlc_hw->di[3]);
  972. /* Cleaner to leave this as if with AP defined */
  973. if (dma_attach_err) {
  974. wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
  975. "\n", unit);
  976. return false;
  977. }
  978. /* get pointer to dma engine tx flow control variable */
  979. for (i = 0; i < NFIFO; i++)
  980. if (wlc_hw->di[i])
  981. wlc_hw->txavail[i] =
  982. (uint *) dma_getvar(wlc_hw->di[i],
  983. "&txavail");
  984. }
  985. /* initial ucode host flags */
  986. brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
  987. return true;
  988. }
  989. static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
  990. {
  991. uint j;
  992. for (j = 0; j < NFIFO; j++) {
  993. if (wlc_hw->di[j]) {
  994. dma_detach(wlc_hw->di[j]);
  995. wlc_hw->di[j] = NULL;
  996. }
  997. }
  998. }
  999. /*
  1000. * Initialize brcms_c_info default values ...
  1001. * may get overrides later in this function
  1002. * BMAC_NOTES, move low out and resolve the dangling ones
  1003. */
  1004. static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
  1005. {
  1006. struct brcms_c_info *wlc = wlc_hw->wlc;
  1007. /* set default sw macintmask value */
  1008. wlc->defmacintmask = DEF_MACINTMASK;
  1009. /* various 802.11g modes */
  1010. wlc_hw->shortslot = false;
  1011. wlc_hw->SFBL = RETRY_SHORT_FB;
  1012. wlc_hw->LFBL = RETRY_LONG_FB;
  1013. /* default mac retry limits */
  1014. wlc_hw->SRL = RETRY_SHORT_DEF;
  1015. wlc_hw->LRL = RETRY_LONG_DEF;
  1016. wlc_hw->chanspec = ch20mhz_chspec(1);
  1017. }
  1018. static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
  1019. {
  1020. /* delay before first read of ucode state */
  1021. udelay(40);
  1022. /* wait until ucode is no longer asleep */
  1023. SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
  1024. DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
  1025. }
  1026. /* control chip clock to save power, enable dynamic clock or force fast clock */
  1027. static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
  1028. {
  1029. if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
  1030. /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
  1031. * on backplane, but mac core will still run on ALP(not HT) when
  1032. * it enters powersave mode, which means the FCA bit may not be
  1033. * set. Should wakeup mac if driver wants it to run on HT.
  1034. */
  1035. if (wlc_hw->clk) {
  1036. if (mode == CLK_FAST) {
  1037. bcma_set32(wlc_hw->d11core,
  1038. D11REGOFFS(clk_ctl_st),
  1039. CCS_FORCEHT);
  1040. udelay(64);
  1041. SPINWAIT(
  1042. ((bcma_read32(wlc_hw->d11core,
  1043. D11REGOFFS(clk_ctl_st)) &
  1044. CCS_HTAVAIL) == 0),
  1045. PMU_MAX_TRANSITION_DLY);
  1046. WARN_ON(!(bcma_read32(wlc_hw->d11core,
  1047. D11REGOFFS(clk_ctl_st)) &
  1048. CCS_HTAVAIL));
  1049. } else {
  1050. if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
  1051. (bcma_read32(wlc_hw->d11core,
  1052. D11REGOFFS(clk_ctl_st)) &
  1053. (CCS_FORCEHT | CCS_HTAREQ)))
  1054. SPINWAIT(
  1055. ((bcma_read32(wlc_hw->d11core,
  1056. offsetof(struct d11regs,
  1057. clk_ctl_st)) &
  1058. CCS_HTAVAIL) == 0),
  1059. PMU_MAX_TRANSITION_DLY);
  1060. bcma_mask32(wlc_hw->d11core,
  1061. D11REGOFFS(clk_ctl_st),
  1062. ~CCS_FORCEHT);
  1063. }
  1064. }
  1065. wlc_hw->forcefastclk = (mode == CLK_FAST);
  1066. } else {
  1067. /* old chips w/o PMU, force HT through cc,
  1068. * then use FCA to verify mac is running fast clock
  1069. */
  1070. wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
  1071. /* check fast clock is available (if core is not in reset) */
  1072. if (wlc_hw->forcefastclk && wlc_hw->clk)
  1073. WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
  1074. SISF_FCLKA));
  1075. /*
  1076. * keep the ucode wake bit on if forcefastclk is on since we
  1077. * do not want ucode to put us back to slow clock when it dozes
  1078. * for PM mode. Code below matches the wake override bit with
  1079. * current forcefastclk state. Only setting bit in wake_override
  1080. * instead of waking ucode immediately since old code had this
  1081. * behavior. Older code set wlc->forcefastclk but only had the
  1082. * wake happen if the wakup_ucode work (protected by an up
  1083. * check) was executed just below.
  1084. */
  1085. if (wlc_hw->forcefastclk)
  1086. mboolset(wlc_hw->wake_override,
  1087. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1088. else
  1089. mboolclr(wlc_hw->wake_override,
  1090. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1091. }
  1092. }
  1093. /* set or clear ucode host flag bits
  1094. * it has an optimization for no-change write
  1095. * it only writes through shared memory when the core has clock;
  1096. * pre-CLK changes should use wlc_write_mhf to get around the optimization
  1097. *
  1098. *
  1099. * bands values are: BRCM_BAND_AUTO <--- Current band only
  1100. * BRCM_BAND_5G <--- 5G band only
  1101. * BRCM_BAND_2G <--- 2G band only
  1102. * BRCM_BAND_ALL <--- All bands
  1103. */
  1104. void
  1105. brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
  1106. int bands)
  1107. {
  1108. u16 save;
  1109. u16 addr[MHFMAX] = {
  1110. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  1111. M_HOST_FLAGS5
  1112. };
  1113. struct brcms_hw_band *band;
  1114. if ((val & ~mask) || idx >= MHFMAX)
  1115. return; /* error condition */
  1116. switch (bands) {
  1117. /* Current band only or all bands,
  1118. * then set the band to current band
  1119. */
  1120. case BRCM_BAND_AUTO:
  1121. case BRCM_BAND_ALL:
  1122. band = wlc_hw->band;
  1123. break;
  1124. case BRCM_BAND_5G:
  1125. band = wlc_hw->bandstate[BAND_5G_INDEX];
  1126. break;
  1127. case BRCM_BAND_2G:
  1128. band = wlc_hw->bandstate[BAND_2G_INDEX];
  1129. break;
  1130. default:
  1131. band = NULL; /* error condition */
  1132. }
  1133. if (band) {
  1134. save = band->mhfs[idx];
  1135. band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
  1136. /* optimization: only write through if changed, and
  1137. * changed band is the current band
  1138. */
  1139. if (wlc_hw->clk && (band->mhfs[idx] != save)
  1140. && (band == wlc_hw->band))
  1141. brcms_b_write_shm(wlc_hw, addr[idx],
  1142. (u16) band->mhfs[idx]);
  1143. }
  1144. if (bands == BRCM_BAND_ALL) {
  1145. wlc_hw->bandstate[0]->mhfs[idx] =
  1146. (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
  1147. wlc_hw->bandstate[1]->mhfs[idx] =
  1148. (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
  1149. }
  1150. }
  1151. /* set the maccontrol register to desired reset state and
  1152. * initialize the sw cache of the register
  1153. */
  1154. static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
  1155. {
  1156. /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
  1157. wlc_hw->maccontrol = 0;
  1158. wlc_hw->suspended_fifos = 0;
  1159. wlc_hw->wake_override = 0;
  1160. wlc_hw->mute_override = 0;
  1161. brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
  1162. }
  1163. /*
  1164. * write the software state of maccontrol and
  1165. * overrides to the maccontrol register
  1166. */
  1167. static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
  1168. {
  1169. u32 maccontrol = wlc_hw->maccontrol;
  1170. /* OR in the wake bit if overridden */
  1171. if (wlc_hw->wake_override)
  1172. maccontrol |= MCTL_WAKE;
  1173. /* set AP and INFRA bits for mute if needed */
  1174. if (wlc_hw->mute_override) {
  1175. maccontrol &= ~(MCTL_AP);
  1176. maccontrol |= MCTL_INFRA;
  1177. }
  1178. bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
  1179. maccontrol);
  1180. }
  1181. /* set or clear maccontrol bits */
  1182. void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
  1183. {
  1184. u32 maccontrol;
  1185. u32 new_maccontrol;
  1186. if (val & ~mask)
  1187. return; /* error condition */
  1188. maccontrol = wlc_hw->maccontrol;
  1189. new_maccontrol = (maccontrol & ~mask) | val;
  1190. /* if the new maccontrol value is the same as the old, nothing to do */
  1191. if (new_maccontrol == maccontrol)
  1192. return;
  1193. /* something changed, cache the new value */
  1194. wlc_hw->maccontrol = new_maccontrol;
  1195. /* write the new values with overrides applied */
  1196. brcms_c_mctrl_write(wlc_hw);
  1197. }
  1198. void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
  1199. u32 override_bit)
  1200. {
  1201. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
  1202. mboolset(wlc_hw->wake_override, override_bit);
  1203. return;
  1204. }
  1205. mboolset(wlc_hw->wake_override, override_bit);
  1206. brcms_c_mctrl_write(wlc_hw);
  1207. brcms_b_wait_for_wake(wlc_hw);
  1208. }
  1209. void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
  1210. u32 override_bit)
  1211. {
  1212. mboolclr(wlc_hw->wake_override, override_bit);
  1213. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
  1214. return;
  1215. brcms_c_mctrl_write(wlc_hw);
  1216. }
  1217. /* When driver needs ucode to stop beaconing, it has to make sure that
  1218. * MCTL_AP is clear and MCTL_INFRA is set
  1219. * Mode MCTL_AP MCTL_INFRA
  1220. * AP 1 1
  1221. * STA 0 1 <--- This will ensure no beacons
  1222. * IBSS 0 0
  1223. */
  1224. static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
  1225. {
  1226. wlc_hw->mute_override = 1;
  1227. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1228. * override, then there is no change to write
  1229. */
  1230. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1231. return;
  1232. brcms_c_mctrl_write(wlc_hw);
  1233. }
  1234. /* Clear the override on AP and INFRA bits */
  1235. static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
  1236. {
  1237. if (wlc_hw->mute_override == 0)
  1238. return;
  1239. wlc_hw->mute_override = 0;
  1240. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1241. * override, then there is no change to write
  1242. */
  1243. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1244. return;
  1245. brcms_c_mctrl_write(wlc_hw);
  1246. }
  1247. /*
  1248. * Write a MAC address to the given match reg offset in the RXE match engine.
  1249. */
  1250. static void
  1251. brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
  1252. const u8 *addr)
  1253. {
  1254. struct bcma_device *core = wlc_hw->d11core;
  1255. u16 mac_l;
  1256. u16 mac_m;
  1257. u16 mac_h;
  1258. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
  1259. wlc_hw->unit);
  1260. mac_l = addr[0] | (addr[1] << 8);
  1261. mac_m = addr[2] | (addr[3] << 8);
  1262. mac_h = addr[4] | (addr[5] << 8);
  1263. /* enter the MAC addr into the RXE match registers */
  1264. bcma_write16(core, D11REGOFFS(rcm_ctl),
  1265. RCM_INC_DATA | match_reg_offset);
  1266. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
  1267. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
  1268. bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
  1269. }
  1270. void
  1271. brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
  1272. void *buf)
  1273. {
  1274. struct bcma_device *core = wlc_hw->d11core;
  1275. u32 word;
  1276. __le32 word_le;
  1277. __be32 word_be;
  1278. bool be_bit;
  1279. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1280. bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
  1281. /* if MCTL_BIGEND bit set in mac control register,
  1282. * the chip swaps data in fifo, as well as data in
  1283. * template ram
  1284. */
  1285. be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
  1286. while (len > 0) {
  1287. memcpy(&word, buf, sizeof(u32));
  1288. if (be_bit) {
  1289. word_be = cpu_to_be32(word);
  1290. word = *(u32 *)&word_be;
  1291. } else {
  1292. word_le = cpu_to_le32(word);
  1293. word = *(u32 *)&word_le;
  1294. }
  1295. bcma_write32(core, D11REGOFFS(tplatewrdata), word);
  1296. buf = (u8 *) buf + sizeof(u32);
  1297. len -= sizeof(u32);
  1298. }
  1299. }
  1300. static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
  1301. {
  1302. wlc_hw->band->CWmin = newmin;
  1303. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  1304. OBJADDR_SCR_SEL | S_DOT11_CWMIN);
  1305. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  1306. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
  1307. }
  1308. static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
  1309. {
  1310. wlc_hw->band->CWmax = newmax;
  1311. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  1312. OBJADDR_SCR_SEL | S_DOT11_CWMAX);
  1313. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  1314. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
  1315. }
  1316. void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
  1317. {
  1318. bool fastclk;
  1319. /* request FAST clock if not on */
  1320. fastclk = wlc_hw->forcefastclk;
  1321. if (!fastclk)
  1322. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  1323. wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
  1324. brcms_b_phy_reset(wlc_hw);
  1325. wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
  1326. /* restore the clk */
  1327. if (!fastclk)
  1328. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  1329. }
  1330. static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
  1331. {
  1332. u16 v;
  1333. struct brcms_c_info *wlc = wlc_hw->wlc;
  1334. /* update SYNTHPU_DLY */
  1335. if (BRCMS_ISLCNPHY(wlc->band))
  1336. v = SYNTHPU_DLY_LPPHY_US;
  1337. else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
  1338. v = SYNTHPU_DLY_NPHY_US;
  1339. else
  1340. v = SYNTHPU_DLY_BPHY_US;
  1341. brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
  1342. }
  1343. static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
  1344. {
  1345. u16 phyctl;
  1346. u16 phytxant = wlc_hw->bmac_phytxant;
  1347. u16 mask = PHY_TXC_ANT_MASK;
  1348. /* set the Probe Response frame phy control word */
  1349. phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
  1350. phyctl = (phyctl & ~mask) | phytxant;
  1351. brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
  1352. /* set the Response (ACK/CTS) frame phy control word */
  1353. phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
  1354. phyctl = (phyctl & ~mask) | phytxant;
  1355. brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
  1356. }
  1357. static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
  1358. u8 rate)
  1359. {
  1360. uint i;
  1361. u8 plcp_rate = 0;
  1362. struct plcp_signal_rate_lookup {
  1363. u8 rate;
  1364. u8 signal_rate;
  1365. };
  1366. /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
  1367. const struct plcp_signal_rate_lookup rate_lookup[] = {
  1368. {BRCM_RATE_6M, 0xB},
  1369. {BRCM_RATE_9M, 0xF},
  1370. {BRCM_RATE_12M, 0xA},
  1371. {BRCM_RATE_18M, 0xE},
  1372. {BRCM_RATE_24M, 0x9},
  1373. {BRCM_RATE_36M, 0xD},
  1374. {BRCM_RATE_48M, 0x8},
  1375. {BRCM_RATE_54M, 0xC}
  1376. };
  1377. for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
  1378. if (rate == rate_lookup[i].rate) {
  1379. plcp_rate = rate_lookup[i].signal_rate;
  1380. break;
  1381. }
  1382. }
  1383. /* Find the SHM pointer to the rate table entry by looking in the
  1384. * Direct-map Table
  1385. */
  1386. return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
  1387. }
  1388. static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
  1389. {
  1390. u8 rate;
  1391. u8 rates[8] = {
  1392. BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
  1393. BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
  1394. };
  1395. u16 entry_ptr;
  1396. u16 pctl1;
  1397. uint i;
  1398. if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
  1399. return;
  1400. /* walk the phy rate table and update the entries */
  1401. for (i = 0; i < ARRAY_SIZE(rates); i++) {
  1402. rate = rates[i];
  1403. entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
  1404. /* read the SHM Rate Table entry OFDM PCTL1 values */
  1405. pctl1 =
  1406. brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
  1407. /* modify the value */
  1408. pctl1 &= ~PHY_TXC1_MODE_MASK;
  1409. pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
  1410. /* Update the SHM Rate Table entry OFDM PCTL1 values */
  1411. brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
  1412. pctl1);
  1413. }
  1414. }
  1415. /* band-specific init */
  1416. static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
  1417. {
  1418. struct brcms_hardware *wlc_hw = wlc->hw;
  1419. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  1420. wlc_hw->band->bandunit);
  1421. brcms_c_ucode_bsinit(wlc_hw);
  1422. wlc_phy_init(wlc_hw->band->pi, chanspec);
  1423. brcms_c_ucode_txant_set(wlc_hw);
  1424. /*
  1425. * cwmin is band-specific, update hardware
  1426. * with value for current band
  1427. */
  1428. brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
  1429. brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
  1430. brcms_b_update_slot_timing(wlc_hw,
  1431. wlc_hw->band->bandtype == BRCM_BAND_5G ?
  1432. true : wlc_hw->shortslot);
  1433. /* write phytype and phyvers */
  1434. brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
  1435. brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
  1436. /*
  1437. * initialize the txphyctl1 rate table since
  1438. * shmem is shared between bands
  1439. */
  1440. brcms_upd_ofdm_pctl1_table(wlc_hw);
  1441. brcms_b_upd_synthpu(wlc_hw);
  1442. }
  1443. /* Perform a soft reset of the PHY PLL */
  1444. void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
  1445. {
  1446. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1447. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
  1448. ~0, 0);
  1449. udelay(1);
  1450. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1451. 0x4, 0);
  1452. udelay(1);
  1453. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1454. 0x4, 4);
  1455. udelay(1);
  1456. ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
  1457. 0x4, 0);
  1458. udelay(1);
  1459. }
  1460. /* light way to turn on phy clock without reset for NPHY only
  1461. * refer to brcms_b_core_phy_clk for full version
  1462. */
  1463. void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
  1464. {
  1465. /* support(necessary for NPHY and HYPHY) only */
  1466. if (!BRCMS_ISNPHY(wlc_hw->band))
  1467. return;
  1468. if (ON == clk)
  1469. brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
  1470. else
  1471. brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
  1472. }
  1473. void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
  1474. {
  1475. if (ON == clk)
  1476. brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
  1477. else
  1478. brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
  1479. }
  1480. void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
  1481. {
  1482. struct brcms_phy_pub *pih = wlc_hw->band->pi;
  1483. u32 phy_bw_clkbits;
  1484. bool phy_in_reset = false;
  1485. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1486. if (pih == NULL)
  1487. return;
  1488. phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
  1489. /* Specific reset sequence required for NPHY rev 3 and 4 */
  1490. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
  1491. NREV_LE(wlc_hw->band->phyrev, 4)) {
  1492. /* Set the PHY bandwidth */
  1493. brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
  1494. udelay(1);
  1495. /* Perform a soft reset of the PHY PLL */
  1496. brcms_b_core_phypll_reset(wlc_hw);
  1497. /* reset the PHY */
  1498. brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
  1499. (SICF_PRST | SICF_PCLKE));
  1500. phy_in_reset = true;
  1501. } else {
  1502. brcms_b_core_ioctl(wlc_hw,
  1503. (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
  1504. (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
  1505. }
  1506. udelay(2);
  1507. brcms_b_core_phy_clk(wlc_hw, ON);
  1508. if (pih)
  1509. wlc_phy_anacore(pih, ON);
  1510. }
  1511. /* switch to and initialize new band */
  1512. static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
  1513. u16 chanspec) {
  1514. struct brcms_c_info *wlc = wlc_hw->wlc;
  1515. u32 macintmask;
  1516. /* Enable the d11 core before accessing it */
  1517. if (!bcma_core_is_enabled(wlc_hw->d11core)) {
  1518. bcma_core_enable(wlc_hw->d11core, 0);
  1519. brcms_c_mctrl_reset(wlc_hw);
  1520. }
  1521. macintmask = brcms_c_setband_inact(wlc, bandunit);
  1522. if (!wlc_hw->up)
  1523. return;
  1524. brcms_b_core_phy_clk(wlc_hw, ON);
  1525. /* band-specific initializations */
  1526. brcms_b_bsinit(wlc, chanspec);
  1527. /*
  1528. * If there are any pending software interrupt bits,
  1529. * then replace these with a harmless nonzero value
  1530. * so brcms_c_dpc() will re-enable interrupts when done.
  1531. */
  1532. if (wlc->macintstatus)
  1533. wlc->macintstatus = MI_DMAINT;
  1534. /* restore macintmask */
  1535. brcms_intrsrestore(wlc->wl, macintmask);
  1536. /* ucode should still be suspended.. */
  1537. WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
  1538. MCTL_EN_MAC) != 0);
  1539. }
  1540. static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
  1541. {
  1542. /* reject unsupported corerev */
  1543. if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
  1544. wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
  1545. wlc_hw->corerev);
  1546. return false;
  1547. }
  1548. return true;
  1549. }
  1550. /* Validate some board info parameters */
  1551. static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
  1552. {
  1553. uint boardrev = wlc_hw->boardrev;
  1554. /* 4 bits each for board type, major, minor, and tiny version */
  1555. uint brt = (boardrev & 0xf000) >> 12;
  1556. uint b0 = (boardrev & 0xf00) >> 8;
  1557. uint b1 = (boardrev & 0xf0) >> 4;
  1558. uint b2 = boardrev & 0xf;
  1559. /* voards from other vendors are always considered valid */
  1560. if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
  1561. return true;
  1562. /* do some boardrev sanity checks when boardvendor is Broadcom */
  1563. if (boardrev == 0)
  1564. return false;
  1565. if (boardrev <= 0xff)
  1566. return true;
  1567. if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
  1568. || (b2 > 9))
  1569. return false;
  1570. return true;
  1571. }
  1572. static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw)
  1573. {
  1574. enum brcms_srom_id var_id = BRCMS_SROM_MACADDR;
  1575. char *macaddr;
  1576. /* If macaddr exists, use it (Sromrev4, CIS, ...). */
  1577. macaddr = getvar(wlc_hw->sih, var_id);
  1578. if (macaddr != NULL)
  1579. return macaddr;
  1580. if (wlc_hw->_nbands > 1)
  1581. var_id = BRCMS_SROM_ET1MACADDR;
  1582. else
  1583. var_id = BRCMS_SROM_IL0MACADDR;
  1584. macaddr = getvar(wlc_hw->sih, var_id);
  1585. if (macaddr == NULL)
  1586. wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
  1587. "getvar(%d) not found\n", wlc_hw->unit, var_id);
  1588. return macaddr;
  1589. }
  1590. /* power both the pll and external oscillator on/off */
  1591. static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
  1592. {
  1593. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
  1594. /*
  1595. * dont power down if plldown is false or
  1596. * we must poll hw radio disable
  1597. */
  1598. if (!want && wlc_hw->pllreq)
  1599. return;
  1600. if (wlc_hw->sih)
  1601. ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
  1602. wlc_hw->sbclk = want;
  1603. if (!wlc_hw->sbclk) {
  1604. wlc_hw->clk = false;
  1605. if (wlc_hw->band && wlc_hw->band->pi)
  1606. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  1607. }
  1608. }
  1609. /*
  1610. * Return true if radio is disabled, otherwise false.
  1611. * hw radio disable signal is an external pin, users activate it asynchronously
  1612. * this function could be called when driver is down and w/o clock
  1613. * it operates on different registers depending on corerev and boardflag.
  1614. */
  1615. static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
  1616. {
  1617. bool v, clk, xtal;
  1618. u32 flags = 0;
  1619. xtal = wlc_hw->sbclk;
  1620. if (!xtal)
  1621. brcms_b_xtal(wlc_hw, ON);
  1622. /* may need to take core out of reset first */
  1623. clk = wlc_hw->clk;
  1624. if (!clk) {
  1625. /*
  1626. * mac no longer enables phyclk automatically when driver
  1627. * accesses phyreg throughput mac. This can be skipped since
  1628. * only mac reg is accessed below
  1629. */
  1630. flags |= SICF_PCLKE;
  1631. /*
  1632. * AI chip doesn't restore bar0win2 on
  1633. * hibernation/resume, need sw fixup
  1634. */
  1635. if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
  1636. (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
  1637. (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
  1638. bcma_core_enable(wlc_hw->d11core, flags);
  1639. brcms_c_mctrl_reset(wlc_hw);
  1640. }
  1641. v = ((bcma_read32(wlc_hw->d11core,
  1642. D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
  1643. /* put core back into reset */
  1644. if (!clk)
  1645. bcma_core_disable(wlc_hw->d11core, 0);
  1646. if (!xtal)
  1647. brcms_b_xtal(wlc_hw, OFF);
  1648. return v;
  1649. }
  1650. static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
  1651. {
  1652. struct dma_pub *di = wlc_hw->di[fifo];
  1653. return dma_rxreset(di);
  1654. }
  1655. /* d11 core reset
  1656. * ensure fask clock during reset
  1657. * reset dma
  1658. * reset d11(out of reset)
  1659. * reset phy(out of reset)
  1660. * clear software macintstatus for fresh new start
  1661. * one testing hack wlc_hw->noreset will bypass the d11/phy reset
  1662. */
  1663. void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
  1664. {
  1665. uint i;
  1666. bool fastclk;
  1667. if (flags == BRCMS_USE_COREFLAGS)
  1668. flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
  1669. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1670. /* request FAST clock if not on */
  1671. fastclk = wlc_hw->forcefastclk;
  1672. if (!fastclk)
  1673. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  1674. /* reset the dma engines except first time thru */
  1675. if (bcma_core_is_enabled(wlc_hw->d11core)) {
  1676. for (i = 0; i < NFIFO; i++)
  1677. if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
  1678. wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
  1679. "dma_txreset[%d]: cannot stop dma\n",
  1680. wlc_hw->unit, __func__, i);
  1681. if ((wlc_hw->di[RX_FIFO])
  1682. && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
  1683. wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
  1684. "[%d]: cannot stop dma\n",
  1685. wlc_hw->unit, __func__, RX_FIFO);
  1686. }
  1687. /* if noreset, just stop the psm and return */
  1688. if (wlc_hw->noreset) {
  1689. wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
  1690. brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
  1691. return;
  1692. }
  1693. /*
  1694. * mac no longer enables phyclk automatically when driver accesses
  1695. * phyreg throughput mac, AND phy_reset is skipped at early stage when
  1696. * band->pi is invalid. need to enable PHY CLK
  1697. */
  1698. flags |= SICF_PCLKE;
  1699. /*
  1700. * reset the core
  1701. * In chips with PMU, the fastclk request goes through d11 core
  1702. * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
  1703. *
  1704. * This adds some delay and we can optimize it by also requesting
  1705. * fastclk through chipcommon during this period if necessary. But
  1706. * that has to work coordinate with other driver like mips/arm since
  1707. * they may touch chipcommon as well.
  1708. */
  1709. wlc_hw->clk = false;
  1710. bcma_core_enable(wlc_hw->d11core, flags);
  1711. wlc_hw->clk = true;
  1712. if (wlc_hw->band && wlc_hw->band->pi)
  1713. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
  1714. brcms_c_mctrl_reset(wlc_hw);
  1715. if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
  1716. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  1717. brcms_b_phy_reset(wlc_hw);
  1718. /* turn on PHY_PLL */
  1719. brcms_b_core_phypll_ctl(wlc_hw, true);
  1720. /* clear sw intstatus */
  1721. wlc_hw->wlc->macintstatus = 0;
  1722. /* restore the clk setting */
  1723. if (!fastclk)
  1724. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  1725. }
  1726. /* txfifo sizes needs to be modified(increased) since the newer cores
  1727. * have more memory.
  1728. */
  1729. static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
  1730. {
  1731. struct bcma_device *core = wlc_hw->d11core;
  1732. u16 fifo_nu;
  1733. u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
  1734. u16 txfifo_def, txfifo_def1;
  1735. u16 txfifo_cmd;
  1736. /* tx fifos start at TXFIFO_START_BLK from the Base address */
  1737. txfifo_startblk = TXFIFO_START_BLK;
  1738. /* sequence of operations: reset fifo, set fifo size, reset fifo */
  1739. for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
  1740. txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
  1741. txfifo_def = (txfifo_startblk & 0xff) |
  1742. (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
  1743. txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
  1744. ((((txfifo_endblk -
  1745. 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
  1746. txfifo_cmd =
  1747. TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
  1748. bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
  1749. bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
  1750. bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
  1751. bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
  1752. txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
  1753. }
  1754. /*
  1755. * need to propagate to shm location to be in sync since ucode/hw won't
  1756. * do this
  1757. */
  1758. brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
  1759. wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
  1760. brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
  1761. wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
  1762. brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
  1763. ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
  1764. xmtfifo_sz[TX_AC_BK_FIFO]));
  1765. brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
  1766. ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
  1767. xmtfifo_sz[TX_BCMC_FIFO]));
  1768. }
  1769. /* This function is used for changing the tsf frac register
  1770. * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
  1771. * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
  1772. * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
  1773. * HTPHY Formula is 2^26/freq(MHz) e.g.
  1774. * For spuron2 - 126MHz -> 2^26/126 = 532610.0
  1775. * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
  1776. * For spuron: 123MHz -> 2^26/123 = 545600.5
  1777. * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
  1778. * For spur off: 120MHz -> 2^26/120 = 559240.5
  1779. * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
  1780. */
  1781. void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
  1782. {
  1783. struct bcma_device *core = wlc_hw->d11core;
  1784. if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
  1785. (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
  1786. if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
  1787. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
  1788. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1789. } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
  1790. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
  1791. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1792. } else { /* 120Mhz */
  1793. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
  1794. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
  1795. }
  1796. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1797. if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
  1798. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
  1799. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
  1800. } else { /* 80Mhz */
  1801. bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
  1802. bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
  1803. }
  1804. }
  1805. }
  1806. /* Initialize GPIOs that are controlled by D11 core */
  1807. static void brcms_c_gpio_init(struct brcms_c_info *wlc)
  1808. {
  1809. struct brcms_hardware *wlc_hw = wlc->hw;
  1810. u32 gc, gm;
  1811. /* use GPIO select 0 to get all gpio signals from the gpio out reg */
  1812. brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
  1813. /*
  1814. * Common GPIO setup:
  1815. * G0 = LED 0 = WLAN Activity
  1816. * G1 = LED 1 = WLAN 2.4 GHz Radio State
  1817. * G2 = LED 2 = WLAN 5 GHz Radio State
  1818. * G4 = radio disable input (HI enabled, LO disabled)
  1819. */
  1820. gc = gm = 0;
  1821. /* Allocate GPIOs for mimo antenna diversity feature */
  1822. if (wlc_hw->antsel_type == ANTSEL_2x3) {
  1823. /* Enable antenna diversity, use 2x3 mode */
  1824. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1825. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1826. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
  1827. MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
  1828. /* init superswitch control */
  1829. wlc_phy_antsel_init(wlc_hw->band->pi, false);
  1830. } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
  1831. gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
  1832. /*
  1833. * The board itself is powered by these GPIOs
  1834. * (when not sending pattern) so set them high
  1835. */
  1836. bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
  1837. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1838. bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
  1839. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1840. /* Enable antenna diversity, use 2x4 mode */
  1841. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1842. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1843. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
  1844. BRCM_BAND_ALL);
  1845. /* Configure the desired clock to be 4Mhz */
  1846. brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
  1847. ANTSEL_CLKDIV_4MHZ);
  1848. }
  1849. /*
  1850. * gpio 9 controls the PA. ucode is responsible
  1851. * for wiggling out and oe
  1852. */
  1853. if (wlc_hw->boardflags & BFL_PACTRL)
  1854. gm |= gc |= BOARD_GPIO_PACTRL;
  1855. /* apply to gpiocontrol register */
  1856. ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
  1857. }
  1858. static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
  1859. const __le32 ucode[], const size_t nbytes)
  1860. {
  1861. struct bcma_device *core = wlc_hw->d11core;
  1862. uint i;
  1863. uint count;
  1864. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1865. count = (nbytes / sizeof(u32));
  1866. bcma_write32(core, D11REGOFFS(objaddr),
  1867. OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
  1868. (void)bcma_read32(core, D11REGOFFS(objaddr));
  1869. for (i = 0; i < count; i++)
  1870. bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
  1871. }
  1872. static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
  1873. {
  1874. struct brcms_c_info *wlc;
  1875. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  1876. wlc = wlc_hw->wlc;
  1877. if (wlc_hw->ucode_loaded)
  1878. return;
  1879. if (D11REV_IS(wlc_hw->corerev, 23)) {
  1880. if (BRCMS_ISNPHY(wlc_hw->band)) {
  1881. brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
  1882. ucode->bcm43xx_16_mimosz);
  1883. wlc_hw->ucode_loaded = true;
  1884. } else
  1885. wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
  1886. "corerev %d\n",
  1887. __func__, wlc_hw->unit, wlc_hw->corerev);
  1888. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  1889. if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1890. brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
  1891. ucode->bcm43xx_24_lcnsz);
  1892. wlc_hw->ucode_loaded = true;
  1893. } else {
  1894. wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
  1895. "corerev %d\n",
  1896. __func__, wlc_hw->unit, wlc_hw->corerev);
  1897. }
  1898. }
  1899. }
  1900. void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
  1901. {
  1902. /* update sw state */
  1903. wlc_hw->bmac_phytxant = phytxant;
  1904. /* push to ucode if up */
  1905. if (!wlc_hw->up)
  1906. return;
  1907. brcms_c_ucode_txant_set(wlc_hw);
  1908. }
  1909. u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
  1910. {
  1911. return (u16) wlc_hw->wlc->stf->txant;
  1912. }
  1913. void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
  1914. {
  1915. wlc_hw->antsel_type = antsel_type;
  1916. /* Update the antsel type for phy module to use */
  1917. wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
  1918. }
  1919. static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
  1920. {
  1921. bool fatal = false;
  1922. uint unit;
  1923. uint intstatus, idx;
  1924. struct bcma_device *core = wlc_hw->d11core;
  1925. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  1926. unit = wlc_hw->unit;
  1927. for (idx = 0; idx < NFIFO; idx++) {
  1928. /* read intstatus register and ignore any non-error bits */
  1929. intstatus =
  1930. bcma_read32(core,
  1931. D11REGOFFS(intctrlregs[idx].intstatus)) &
  1932. I_ERRORS;
  1933. if (!intstatus)
  1934. continue;
  1935. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
  1936. unit, idx, intstatus);
  1937. if (intstatus & I_RO) {
  1938. wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
  1939. "overflow\n", unit, idx);
  1940. fatal = true;
  1941. }
  1942. if (intstatus & I_PC) {
  1943. wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
  1944. unit, idx);
  1945. fatal = true;
  1946. }
  1947. if (intstatus & I_PD) {
  1948. wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
  1949. idx);
  1950. fatal = true;
  1951. }
  1952. if (intstatus & I_DE) {
  1953. wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
  1954. "error\n", unit, idx);
  1955. fatal = true;
  1956. }
  1957. if (intstatus & I_RU)
  1958. wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
  1959. "underflow\n", idx, unit);
  1960. if (intstatus & I_XU) {
  1961. wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
  1962. "underflow\n", idx, unit);
  1963. fatal = true;
  1964. }
  1965. if (fatal) {
  1966. brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
  1967. break;
  1968. } else
  1969. bcma_write32(core,
  1970. D11REGOFFS(intctrlregs[idx].intstatus),
  1971. intstatus);
  1972. }
  1973. }
  1974. void brcms_c_intrson(struct brcms_c_info *wlc)
  1975. {
  1976. struct brcms_hardware *wlc_hw = wlc->hw;
  1977. wlc->macintmask = wlc->defmacintmask;
  1978. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
  1979. }
  1980. /*
  1981. * callback for siutils.c, which has only wlc handler, no wl they both check
  1982. * up, not only because there is no need to off/restore d11 interrupt but also
  1983. * because per-port code may require sync with valid interrupt.
  1984. */
  1985. static u32 brcms_c_wlintrsoff(struct brcms_c_info *wlc)
  1986. {
  1987. if (!wlc->hw->up)
  1988. return 0;
  1989. return brcms_intrsoff(wlc->wl);
  1990. }
  1991. static void brcms_c_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask)
  1992. {
  1993. if (!wlc->hw->up)
  1994. return;
  1995. brcms_intrsrestore(wlc->wl, macintmask);
  1996. }
  1997. u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
  1998. {
  1999. struct brcms_hardware *wlc_hw = wlc->hw;
  2000. u32 macintmask;
  2001. if (!wlc_hw->clk)
  2002. return 0;
  2003. macintmask = wlc->macintmask; /* isr can still happen */
  2004. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
  2005. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
  2006. udelay(1); /* ensure int line is no longer driven */
  2007. wlc->macintmask = 0;
  2008. /* return previous macintmask; resolve race between us and our isr */
  2009. return wlc->macintstatus ? 0 : macintmask;
  2010. }
  2011. void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
  2012. {
  2013. struct brcms_hardware *wlc_hw = wlc->hw;
  2014. if (!wlc_hw->clk)
  2015. return;
  2016. wlc->macintmask = macintmask;
  2017. bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
  2018. }
  2019. /* assumes that the d11 MAC is enabled */
  2020. static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
  2021. uint tx_fifo)
  2022. {
  2023. u8 fifo = 1 << tx_fifo;
  2024. /* Two clients of this code, 11h Quiet period and scanning. */
  2025. /* only suspend if not already suspended */
  2026. if ((wlc_hw->suspended_fifos & fifo) == fifo)
  2027. return;
  2028. /* force the core awake only if not already */
  2029. if (wlc_hw->suspended_fifos == 0)
  2030. brcms_c_ucode_wake_override_set(wlc_hw,
  2031. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2032. wlc_hw->suspended_fifos |= fifo;
  2033. if (wlc_hw->di[tx_fifo]) {
  2034. /*
  2035. * Suspending AMPDU transmissions in the middle can cause
  2036. * underflow which may result in mismatch between ucode and
  2037. * driver so suspend the mac before suspending the FIFO
  2038. */
  2039. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2040. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  2041. dma_txsuspend(wlc_hw->di[tx_fifo]);
  2042. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2043. brcms_c_enable_mac(wlc_hw->wlc);
  2044. }
  2045. }
  2046. static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
  2047. uint tx_fifo)
  2048. {
  2049. /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
  2050. * but need to be done here for PIO otherwise the watchdog will catch
  2051. * the inconsistency and fire
  2052. */
  2053. /* Two clients of this code, 11h Quiet period and scanning. */
  2054. if (wlc_hw->di[tx_fifo])
  2055. dma_txresume(wlc_hw->di[tx_fifo]);
  2056. /* allow core to sleep again */
  2057. if (wlc_hw->suspended_fifos == 0)
  2058. return;
  2059. else {
  2060. wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
  2061. if (wlc_hw->suspended_fifos == 0)
  2062. brcms_c_ucode_wake_override_clear(wlc_hw,
  2063. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2064. }
  2065. }
  2066. /* precondition: requires the mac core to be enabled */
  2067. static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
  2068. {
  2069. static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
  2070. if (mute_tx) {
  2071. /* suspend tx fifos */
  2072. brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
  2073. brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
  2074. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
  2075. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
  2076. /* zero the address match register so we do not send ACKs */
  2077. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
  2078. null_ether_addr);
  2079. } else {
  2080. /* resume tx fifos */
  2081. brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
  2082. brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
  2083. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
  2084. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
  2085. /* Restore address */
  2086. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
  2087. wlc_hw->etheraddr);
  2088. }
  2089. wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
  2090. if (mute_tx)
  2091. brcms_c_ucode_mute_override_set(wlc_hw);
  2092. else
  2093. brcms_c_ucode_mute_override_clear(wlc_hw);
  2094. }
  2095. void
  2096. brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
  2097. {
  2098. brcms_b_mute(wlc->hw, mute_tx);
  2099. }
  2100. /*
  2101. * Read and clear macintmask and macintstatus and intstatus registers.
  2102. * This routine should be called with interrupts off
  2103. * Return:
  2104. * -1 if brcms_deviceremoved(wlc) evaluates to true;
  2105. * 0 if the interrupt is not for us, or we are in some special cases;
  2106. * device interrupt status bits otherwise.
  2107. */
  2108. static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
  2109. {
  2110. struct brcms_hardware *wlc_hw = wlc->hw;
  2111. struct bcma_device *core = wlc_hw->d11core;
  2112. u32 macintstatus;
  2113. /* macintstatus includes a DMA interrupt summary bit */
  2114. macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
  2115. BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
  2116. macintstatus);
  2117. /* detect cardbus removed, in power down(suspend) and in reset */
  2118. if (brcms_deviceremoved(wlc))
  2119. return -1;
  2120. /* brcms_deviceremoved() succeeds even when the core is still resetting,
  2121. * handle that case here.
  2122. */
  2123. if (macintstatus == 0xffffffff)
  2124. return 0;
  2125. /* defer unsolicited interrupts */
  2126. macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
  2127. /* if not for us */
  2128. if (macintstatus == 0)
  2129. return 0;
  2130. /* interrupts are already turned off for CFE build
  2131. * Caution: For CFE Turning off the interrupts again has some undesired
  2132. * consequences
  2133. */
  2134. /* turn off the interrupts */
  2135. bcma_write32(core, D11REGOFFS(macintmask), 0);
  2136. (void)bcma_read32(core, D11REGOFFS(macintmask));
  2137. wlc->macintmask = 0;
  2138. /* clear device interrupts */
  2139. bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
  2140. /* MI_DMAINT is indication of non-zero intstatus */
  2141. if (macintstatus & MI_DMAINT)
  2142. /*
  2143. * only fifo interrupt enabled is I_RI in
  2144. * RX_FIFO. If MI_DMAINT is set, assume it
  2145. * is set and clear the interrupt.
  2146. */
  2147. bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
  2148. DEF_RXINTMASK);
  2149. return macintstatus;
  2150. }
  2151. /* Update wlc->macintstatus and wlc->intstatus[]. */
  2152. /* Return true if they are updated successfully. false otherwise */
  2153. bool brcms_c_intrsupd(struct brcms_c_info *wlc)
  2154. {
  2155. u32 macintstatus;
  2156. /* read and clear macintstatus and intstatus registers */
  2157. macintstatus = wlc_intstatus(wlc, false);
  2158. /* device is removed */
  2159. if (macintstatus == 0xffffffff)
  2160. return false;
  2161. /* update interrupt status in software */
  2162. wlc->macintstatus |= macintstatus;
  2163. return true;
  2164. }
  2165. /*
  2166. * First-level interrupt processing.
  2167. * Return true if this was our interrupt, false otherwise.
  2168. * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
  2169. * false otherwise.
  2170. */
  2171. bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
  2172. {
  2173. struct brcms_hardware *wlc_hw = wlc->hw;
  2174. u32 macintstatus;
  2175. *wantdpc = false;
  2176. if (!wlc_hw->up || !wlc->macintmask)
  2177. return false;
  2178. /* read and clear macintstatus and intstatus registers */
  2179. macintstatus = wlc_intstatus(wlc, true);
  2180. if (macintstatus == 0xffffffff)
  2181. wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
  2182. " path\n");
  2183. /* it is not for us */
  2184. if (macintstatus == 0)
  2185. return false;
  2186. *wantdpc = true;
  2187. /* save interrupt status bits */
  2188. wlc->macintstatus = macintstatus;
  2189. return true;
  2190. }
  2191. void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
  2192. {
  2193. struct brcms_hardware *wlc_hw = wlc->hw;
  2194. struct bcma_device *core = wlc_hw->d11core;
  2195. u32 mc, mi;
  2196. struct wiphy *wiphy = wlc->wiphy;
  2197. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  2198. wlc_hw->band->bandunit);
  2199. /*
  2200. * Track overlapping suspend requests
  2201. */
  2202. wlc_hw->mac_suspend_depth++;
  2203. if (wlc_hw->mac_suspend_depth > 1)
  2204. return;
  2205. /* force the core awake */
  2206. brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2207. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2208. if (mc == 0xffffffff) {
  2209. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2210. __func__);
  2211. brcms_down(wlc->wl);
  2212. return;
  2213. }
  2214. WARN_ON(mc & MCTL_PSM_JMP_0);
  2215. WARN_ON(!(mc & MCTL_PSM_RUN));
  2216. WARN_ON(!(mc & MCTL_EN_MAC));
  2217. mi = bcma_read32(core, D11REGOFFS(macintstatus));
  2218. if (mi == 0xffffffff) {
  2219. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2220. __func__);
  2221. brcms_down(wlc->wl);
  2222. return;
  2223. }
  2224. WARN_ON(mi & MI_MACSSPNDD);
  2225. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
  2226. SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
  2227. BRCMS_MAX_MAC_SUSPEND);
  2228. if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
  2229. wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
  2230. " and MI_MACSSPNDD is still not on.\n",
  2231. wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
  2232. wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
  2233. "psm_brc 0x%04x\n", wlc_hw->unit,
  2234. bcma_read32(core, D11REGOFFS(psmdebug)),
  2235. bcma_read32(core, D11REGOFFS(phydebug)),
  2236. bcma_read16(core, D11REGOFFS(psm_brc)));
  2237. }
  2238. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2239. if (mc == 0xffffffff) {
  2240. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2241. __func__);
  2242. brcms_down(wlc->wl);
  2243. return;
  2244. }
  2245. WARN_ON(mc & MCTL_PSM_JMP_0);
  2246. WARN_ON(!(mc & MCTL_PSM_RUN));
  2247. WARN_ON(mc & MCTL_EN_MAC);
  2248. }
  2249. void brcms_c_enable_mac(struct brcms_c_info *wlc)
  2250. {
  2251. struct brcms_hardware *wlc_hw = wlc->hw;
  2252. struct bcma_device *core = wlc_hw->d11core;
  2253. u32 mc, mi;
  2254. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  2255. wlc->band->bandunit);
  2256. /*
  2257. * Track overlapping suspend requests
  2258. */
  2259. wlc_hw->mac_suspend_depth--;
  2260. if (wlc_hw->mac_suspend_depth > 0)
  2261. return;
  2262. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2263. WARN_ON(mc & MCTL_PSM_JMP_0);
  2264. WARN_ON(mc & MCTL_EN_MAC);
  2265. WARN_ON(!(mc & MCTL_PSM_RUN));
  2266. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
  2267. bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
  2268. mc = bcma_read32(core, D11REGOFFS(maccontrol));
  2269. WARN_ON(mc & MCTL_PSM_JMP_0);
  2270. WARN_ON(!(mc & MCTL_EN_MAC));
  2271. WARN_ON(!(mc & MCTL_PSM_RUN));
  2272. mi = bcma_read32(core, D11REGOFFS(macintstatus));
  2273. WARN_ON(mi & MI_MACSSPNDD);
  2274. brcms_c_ucode_wake_override_clear(wlc_hw,
  2275. BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2276. }
  2277. void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
  2278. {
  2279. wlc_hw->hw_stf_ss_opmode = stf_mode;
  2280. if (wlc_hw->clk)
  2281. brcms_upd_ofdm_pctl1_table(wlc_hw);
  2282. }
  2283. static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
  2284. {
  2285. struct bcma_device *core = wlc_hw->d11core;
  2286. u32 w, val;
  2287. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  2288. BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
  2289. /* Validate dchip register access */
  2290. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2291. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2292. w = bcma_read32(core, D11REGOFFS(objdata));
  2293. /* Can we write and read back a 32bit register? */
  2294. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2295. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2296. bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
  2297. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2298. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2299. val = bcma_read32(core, D11REGOFFS(objdata));
  2300. if (val != (u32) 0xaa5555aa) {
  2301. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2302. "expected 0xaa5555aa\n", wlc_hw->unit, val);
  2303. return false;
  2304. }
  2305. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2306. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2307. bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
  2308. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2309. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2310. val = bcma_read32(core, D11REGOFFS(objdata));
  2311. if (val != (u32) 0x55aaaa55) {
  2312. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2313. "expected 0x55aaaa55\n", wlc_hw->unit, val);
  2314. return false;
  2315. }
  2316. bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
  2317. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2318. bcma_write32(core, D11REGOFFS(objdata), w);
  2319. /* clear CFPStart */
  2320. bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
  2321. w = bcma_read32(core, D11REGOFFS(maccontrol));
  2322. if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
  2323. (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
  2324. wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
  2325. "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
  2326. (MCTL_IHR_EN | MCTL_WAKE),
  2327. (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
  2328. return false;
  2329. }
  2330. return true;
  2331. }
  2332. #define PHYPLL_WAIT_US 100000
  2333. void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
  2334. {
  2335. struct bcma_device *core = wlc_hw->d11core;
  2336. u32 tmp;
  2337. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2338. tmp = 0;
  2339. if (on) {
  2340. if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
  2341. bcma_set32(core, D11REGOFFS(clk_ctl_st),
  2342. CCS_ERSRC_REQ_HT |
  2343. CCS_ERSRC_REQ_D11PLL |
  2344. CCS_ERSRC_REQ_PHYPLL);
  2345. SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
  2346. CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
  2347. PHYPLL_WAIT_US);
  2348. tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2349. if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
  2350. wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
  2351. " PLL failed\n", __func__);
  2352. } else {
  2353. bcma_set32(core, D11REGOFFS(clk_ctl_st),
  2354. tmp | CCS_ERSRC_REQ_D11PLL |
  2355. CCS_ERSRC_REQ_PHYPLL);
  2356. SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
  2357. (CCS_ERSRC_AVAIL_D11PLL |
  2358. CCS_ERSRC_AVAIL_PHYPLL)) !=
  2359. (CCS_ERSRC_AVAIL_D11PLL |
  2360. CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
  2361. tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2362. if ((tmp &
  2363. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2364. !=
  2365. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2366. wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
  2367. "PHY PLL failed\n", __func__);
  2368. }
  2369. } else {
  2370. /*
  2371. * Since the PLL may be shared, other cores can still
  2372. * be requesting it; so we'll deassert the request but
  2373. * not wait for status to comply.
  2374. */
  2375. bcma_mask32(core, D11REGOFFS(clk_ctl_st),
  2376. ~CCS_ERSRC_REQ_PHYPLL);
  2377. (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
  2378. }
  2379. }
  2380. static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
  2381. {
  2382. bool dev_gone;
  2383. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2384. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  2385. if (dev_gone)
  2386. return;
  2387. if (wlc_hw->noreset)
  2388. return;
  2389. /* radio off */
  2390. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  2391. /* turn off analog core */
  2392. wlc_phy_anacore(wlc_hw->band->pi, OFF);
  2393. /* turn off PHYPLL to save power */
  2394. brcms_b_core_phypll_ctl(wlc_hw, false);
  2395. wlc_hw->clk = false;
  2396. bcma_core_disable(wlc_hw->d11core, 0);
  2397. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  2398. }
  2399. static void brcms_c_flushqueues(struct brcms_c_info *wlc)
  2400. {
  2401. struct brcms_hardware *wlc_hw = wlc->hw;
  2402. uint i;
  2403. /* free any posted tx packets */
  2404. for (i = 0; i < NFIFO; i++)
  2405. if (wlc_hw->di[i]) {
  2406. dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
  2407. wlc->core->txpktpend[i] = 0;
  2408. BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
  2409. }
  2410. /* free any posted rx packets */
  2411. dma_rxreclaim(wlc_hw->di[RX_FIFO]);
  2412. }
  2413. static u16
  2414. brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
  2415. {
  2416. struct bcma_device *core = wlc_hw->d11core;
  2417. u16 objoff = D11REGOFFS(objdata);
  2418. bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
  2419. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2420. if (offset & 2)
  2421. objoff += 2;
  2422. return bcma_read16(core, objoff);
  2423. ;
  2424. }
  2425. static void
  2426. brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
  2427. u32 sel)
  2428. {
  2429. struct bcma_device *core = wlc_hw->d11core;
  2430. u16 objoff = D11REGOFFS(objdata);
  2431. bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
  2432. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2433. if (offset & 2)
  2434. objoff += 2;
  2435. bcma_write16(core, objoff, v);
  2436. }
  2437. /*
  2438. * Read a single u16 from shared memory.
  2439. * SHM 'offset' needs to be an even address
  2440. */
  2441. u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
  2442. {
  2443. return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
  2444. }
  2445. /*
  2446. * Write a single u16 to shared memory.
  2447. * SHM 'offset' needs to be an even address
  2448. */
  2449. void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
  2450. {
  2451. brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
  2452. }
  2453. /*
  2454. * Copy a buffer to shared memory of specified type .
  2455. * SHM 'offset' needs to be an even address and
  2456. * Buffer length 'len' must be an even number of bytes
  2457. * 'sel' selects the type of memory
  2458. */
  2459. void
  2460. brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
  2461. const void *buf, int len, u32 sel)
  2462. {
  2463. u16 v;
  2464. const u8 *p = (const u8 *)buf;
  2465. int i;
  2466. if (len <= 0 || (offset & 1) || (len & 1))
  2467. return;
  2468. for (i = 0; i < len; i += 2) {
  2469. v = p[i] | (p[i + 1] << 8);
  2470. brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
  2471. }
  2472. }
  2473. /*
  2474. * Copy a piece of shared memory of specified type to a buffer .
  2475. * SHM 'offset' needs to be an even address and
  2476. * Buffer length 'len' must be an even number of bytes
  2477. * 'sel' selects the type of memory
  2478. */
  2479. void
  2480. brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
  2481. int len, u32 sel)
  2482. {
  2483. u16 v;
  2484. u8 *p = (u8 *) buf;
  2485. int i;
  2486. if (len <= 0 || (offset & 1) || (len & 1))
  2487. return;
  2488. for (i = 0; i < len; i += 2) {
  2489. v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
  2490. p[i] = v & 0xFF;
  2491. p[i + 1] = (v >> 8) & 0xFF;
  2492. }
  2493. }
  2494. /* Copy a buffer to shared memory.
  2495. * SHM 'offset' needs to be an even address and
  2496. * Buffer length 'len' must be an even number of bytes
  2497. */
  2498. static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
  2499. const void *buf, int len)
  2500. {
  2501. brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
  2502. }
  2503. static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
  2504. u16 SRL, u16 LRL)
  2505. {
  2506. wlc_hw->SRL = SRL;
  2507. wlc_hw->LRL = LRL;
  2508. /* write retry limit to SCR, shouldn't need to suspend */
  2509. if (wlc_hw->up) {
  2510. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  2511. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2512. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  2513. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
  2514. bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
  2515. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2516. (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
  2517. bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
  2518. }
  2519. }
  2520. static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
  2521. {
  2522. if (set) {
  2523. if (mboolisset(wlc_hw->pllreq, req_bit))
  2524. return;
  2525. mboolset(wlc_hw->pllreq, req_bit);
  2526. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2527. if (!wlc_hw->sbclk)
  2528. brcms_b_xtal(wlc_hw, ON);
  2529. }
  2530. } else {
  2531. if (!mboolisset(wlc_hw->pllreq, req_bit))
  2532. return;
  2533. mboolclr(wlc_hw->pllreq, req_bit);
  2534. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2535. if (wlc_hw->sbclk)
  2536. brcms_b_xtal(wlc_hw, OFF);
  2537. }
  2538. }
  2539. }
  2540. static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
  2541. {
  2542. wlc_hw->antsel_avail = antsel_avail;
  2543. }
  2544. /*
  2545. * conditions under which the PM bit should be set in outgoing frames
  2546. * and STAY_AWAKE is meaningful
  2547. */
  2548. static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
  2549. {
  2550. struct brcms_bss_cfg *cfg = wlc->bsscfg;
  2551. /* disallow PS when one of the following global conditions meets */
  2552. if (!wlc->pub->associated)
  2553. return false;
  2554. /* disallow PS when one of these meets when not scanning */
  2555. if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
  2556. return false;
  2557. if (cfg->associated) {
  2558. /*
  2559. * disallow PS when one of the following
  2560. * bsscfg specific conditions meets
  2561. */
  2562. if (!cfg->BSS)
  2563. return false;
  2564. return false;
  2565. }
  2566. return true;
  2567. }
  2568. static void brcms_c_statsupd(struct brcms_c_info *wlc)
  2569. {
  2570. int i;
  2571. struct macstat macstats;
  2572. #ifdef BCMDBG
  2573. u16 delta;
  2574. u16 rxf0ovfl;
  2575. u16 txfunfl[NFIFO];
  2576. #endif /* BCMDBG */
  2577. /* if driver down, make no sense to update stats */
  2578. if (!wlc->pub->up)
  2579. return;
  2580. #ifdef BCMDBG
  2581. /* save last rx fifo 0 overflow count */
  2582. rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
  2583. /* save last tx fifo underflow count */
  2584. for (i = 0; i < NFIFO; i++)
  2585. txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
  2586. #endif /* BCMDBG */
  2587. /* Read mac stats from contiguous shared memory */
  2588. brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
  2589. sizeof(struct macstat), OBJADDR_SHM_SEL);
  2590. #ifdef BCMDBG
  2591. /* check for rx fifo 0 overflow */
  2592. delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
  2593. if (delta)
  2594. wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
  2595. wlc->pub->unit, delta);
  2596. /* check for tx fifo underflows */
  2597. for (i = 0; i < NFIFO; i++) {
  2598. delta =
  2599. (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
  2600. txfunfl[i]);
  2601. if (delta)
  2602. wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
  2603. "\n", wlc->pub->unit, delta, i);
  2604. }
  2605. #endif /* BCMDBG */
  2606. /* merge counters from dma module */
  2607. for (i = 0; i < NFIFO; i++) {
  2608. if (wlc->hw->di[i])
  2609. dma_counterreset(wlc->hw->di[i]);
  2610. }
  2611. }
  2612. static void brcms_b_reset(struct brcms_hardware *wlc_hw)
  2613. {
  2614. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2615. /* reset the core */
  2616. if (!brcms_deviceremoved(wlc_hw->wlc))
  2617. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  2618. /* purge the dma rings */
  2619. brcms_c_flushqueues(wlc_hw->wlc);
  2620. }
  2621. void brcms_c_reset(struct brcms_c_info *wlc)
  2622. {
  2623. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  2624. /* slurp up hw mac counters before core reset */
  2625. brcms_c_statsupd(wlc);
  2626. /* reset our snapshot of macstat counters */
  2627. memset((char *)wlc->core->macstat_snapshot, 0,
  2628. sizeof(struct macstat));
  2629. brcms_b_reset(wlc->hw);
  2630. }
  2631. /* Return the channel the driver should initialize during brcms_c_init.
  2632. * the channel may have to be changed from the currently configured channel
  2633. * if other configurations are in conflict (bandlocked, 11n mode disabled,
  2634. * invalid channel for current country, etc.)
  2635. */
  2636. static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc)
  2637. {
  2638. u16 chanspec =
  2639. 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
  2640. WL_CHANSPEC_BAND_2G;
  2641. return chanspec;
  2642. }
  2643. void brcms_c_init_scb(struct scb *scb)
  2644. {
  2645. int i;
  2646. memset(scb, 0, sizeof(struct scb));
  2647. scb->flags = SCB_WMECAP | SCB_HTCAP;
  2648. for (i = 0; i < NUMPRIO; i++) {
  2649. scb->seqnum[i] = 0;
  2650. scb->seqctl[i] = 0xFFFF;
  2651. }
  2652. scb->seqctl_nonqos = 0xFFFF;
  2653. scb->magic = SCB_MAGIC;
  2654. }
  2655. /* d11 core init
  2656. * reset PSM
  2657. * download ucode/PCM
  2658. * let ucode run to suspended
  2659. * download ucode inits
  2660. * config other core registers
  2661. * init dma
  2662. */
  2663. static void brcms_b_coreinit(struct brcms_c_info *wlc)
  2664. {
  2665. struct brcms_hardware *wlc_hw = wlc->hw;
  2666. struct bcma_device *core = wlc_hw->d11core;
  2667. u32 sflags;
  2668. u32 bcnint_us;
  2669. uint i = 0;
  2670. bool fifosz_fixup = false;
  2671. int err = 0;
  2672. u16 buf[NFIFO];
  2673. struct wiphy *wiphy = wlc->wiphy;
  2674. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  2675. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2676. /* reset PSM */
  2677. brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
  2678. brcms_ucode_download(wlc_hw);
  2679. /*
  2680. * FIFOSZ fixup. driver wants to controls the fifo allocation.
  2681. */
  2682. fifosz_fixup = true;
  2683. /* let the PSM run to the suspended state, set mode to BSS STA */
  2684. bcma_write32(core, D11REGOFFS(macintstatus), -1);
  2685. brcms_b_mctrl(wlc_hw, ~0,
  2686. (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
  2687. /* wait for ucode to self-suspend after auto-init */
  2688. SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
  2689. MI_MACSSPNDD) == 0), 1000 * 1000);
  2690. if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
  2691. wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
  2692. "suspend!\n", wlc_hw->unit);
  2693. brcms_c_gpio_init(wlc);
  2694. sflags = bcma_aread32(core, BCMA_IOST);
  2695. if (D11REV_IS(wlc_hw->corerev, 23)) {
  2696. if (BRCMS_ISNPHY(wlc_hw->band))
  2697. brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
  2698. else
  2699. wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
  2700. " %d\n", __func__, wlc_hw->unit,
  2701. wlc_hw->corerev);
  2702. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  2703. if (BRCMS_ISLCNPHY(wlc_hw->band))
  2704. brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
  2705. else
  2706. wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
  2707. " %d\n", __func__, wlc_hw->unit,
  2708. wlc_hw->corerev);
  2709. } else {
  2710. wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
  2711. __func__, wlc_hw->unit, wlc_hw->corerev);
  2712. }
  2713. /* For old ucode, txfifo sizes needs to be modified(increased) */
  2714. if (fifosz_fixup == true)
  2715. brcms_b_corerev_fifofixup(wlc_hw);
  2716. /* check txfifo allocations match between ucode and driver */
  2717. buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
  2718. if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
  2719. i = TX_AC_BE_FIFO;
  2720. err = -1;
  2721. }
  2722. buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
  2723. if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
  2724. i = TX_AC_VI_FIFO;
  2725. err = -1;
  2726. }
  2727. buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
  2728. buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
  2729. buf[TX_AC_BK_FIFO] &= 0xff;
  2730. if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
  2731. i = TX_AC_BK_FIFO;
  2732. err = -1;
  2733. }
  2734. if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
  2735. i = TX_AC_VO_FIFO;
  2736. err = -1;
  2737. }
  2738. buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
  2739. buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
  2740. buf[TX_BCMC_FIFO] &= 0xff;
  2741. if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
  2742. i = TX_BCMC_FIFO;
  2743. err = -1;
  2744. }
  2745. if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
  2746. i = TX_ATIM_FIFO;
  2747. err = -1;
  2748. }
  2749. if (err != 0)
  2750. wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
  2751. " driver size %d index %d\n", buf[i],
  2752. wlc_hw->xmtfifo_sz[i], i);
  2753. /* make sure we can still talk to the mac */
  2754. WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
  2755. /* band-specific inits done by wlc_bsinit() */
  2756. /* Set up frame burst size and antenna swap threshold init values */
  2757. brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
  2758. brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
  2759. /* enable one rx interrupt per received frame */
  2760. bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
  2761. /* set the station mode (BSS STA) */
  2762. brcms_b_mctrl(wlc_hw,
  2763. (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
  2764. (MCTL_INFRA | MCTL_DISCARD_PMQ));
  2765. /* set up Beacon interval */
  2766. bcnint_us = 0x8000 << 10;
  2767. bcma_write32(core, D11REGOFFS(tsf_cfprep),
  2768. (bcnint_us << CFPREP_CBI_SHIFT));
  2769. bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
  2770. bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
  2771. /* write interrupt mask */
  2772. bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
  2773. DEF_RXINTMASK);
  2774. /* allow the MAC to control the PHY clock (dynamic on/off) */
  2775. brcms_b_macphyclk_set(wlc_hw, ON);
  2776. /* program dynamic clock control fast powerup delay register */
  2777. wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
  2778. bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
  2779. /* tell the ucode the corerev */
  2780. brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
  2781. /* tell the ucode MAC capabilities */
  2782. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
  2783. (u16) (wlc_hw->machwcap & 0xffff));
  2784. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
  2785. (u16) ((wlc_hw->
  2786. machwcap >> 16) & 0xffff));
  2787. /* write retry limits to SCR, this done after PSM init */
  2788. bcma_write32(core, D11REGOFFS(objaddr),
  2789. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2790. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2791. bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
  2792. bcma_write32(core, D11REGOFFS(objaddr),
  2793. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2794. (void)bcma_read32(core, D11REGOFFS(objaddr));
  2795. bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
  2796. /* write rate fallback retry limits */
  2797. brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
  2798. brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
  2799. bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
  2800. bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
  2801. /* init the tx dma engines */
  2802. for (i = 0; i < NFIFO; i++) {
  2803. if (wlc_hw->di[i])
  2804. dma_txinit(wlc_hw->di[i]);
  2805. }
  2806. /* init the rx dma engine(s) and post receive buffers */
  2807. dma_rxinit(wlc_hw->di[RX_FIFO]);
  2808. dma_rxfill(wlc_hw->di[RX_FIFO]);
  2809. }
  2810. void
  2811. static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
  2812. u32 macintmask;
  2813. bool fastclk;
  2814. struct brcms_c_info *wlc = wlc_hw->wlc;
  2815. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2816. /* request FAST clock if not on */
  2817. fastclk = wlc_hw->forcefastclk;
  2818. if (!fastclk)
  2819. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  2820. /* disable interrupts */
  2821. macintmask = brcms_intrsoff(wlc->wl);
  2822. /* set up the specified band and chanspec */
  2823. brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
  2824. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  2825. /* do one-time phy inits and calibration */
  2826. wlc_phy_cal_init(wlc_hw->band->pi);
  2827. /* core-specific initialization */
  2828. brcms_b_coreinit(wlc);
  2829. /* band-specific inits */
  2830. brcms_b_bsinit(wlc, chanspec);
  2831. /* restore macintmask */
  2832. brcms_intrsrestore(wlc->wl, macintmask);
  2833. /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
  2834. * is suspended and brcms_c_enable_mac() will clear this override bit.
  2835. */
  2836. mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2837. /*
  2838. * initialize mac_suspend_depth to 1 to match ucode
  2839. * initial suspended state
  2840. */
  2841. wlc_hw->mac_suspend_depth = 1;
  2842. /* restore the clk */
  2843. if (!fastclk)
  2844. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  2845. }
  2846. static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
  2847. u16 chanspec)
  2848. {
  2849. /* Save our copy of the chanspec */
  2850. wlc->chanspec = chanspec;
  2851. /* Set the chanspec and power limits for this locale */
  2852. brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
  2853. if (wlc->stf->ss_algosel_auto)
  2854. brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
  2855. chanspec);
  2856. brcms_c_stf_ss_update(wlc, wlc->band);
  2857. }
  2858. static void
  2859. brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
  2860. {
  2861. brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
  2862. wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
  2863. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  2864. brcms_chspec_bw(wlc->default_bss->chanspec),
  2865. wlc->stf->txstreams);
  2866. }
  2867. /* derive wlc->band->basic_rate[] table from 'rateset' */
  2868. static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
  2869. struct brcms_c_rateset *rateset)
  2870. {
  2871. u8 rate;
  2872. u8 mandatory;
  2873. u8 cck_basic = 0;
  2874. u8 ofdm_basic = 0;
  2875. u8 *br = wlc->band->basic_rate;
  2876. uint i;
  2877. /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
  2878. memset(br, 0, BRCM_MAXRATE + 1);
  2879. /* For each basic rate in the rates list, make an entry in the
  2880. * best basic lookup.
  2881. */
  2882. for (i = 0; i < rateset->count; i++) {
  2883. /* only make an entry for a basic rate */
  2884. if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
  2885. continue;
  2886. /* mask off basic bit */
  2887. rate = (rateset->rates[i] & BRCMS_RATE_MASK);
  2888. if (rate > BRCM_MAXRATE) {
  2889. wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
  2890. "invalid rate 0x%X in rate set\n",
  2891. rateset->rates[i]);
  2892. continue;
  2893. }
  2894. br[rate] = rate;
  2895. }
  2896. /* The rate lookup table now has non-zero entries for each
  2897. * basic rate, equal to the basic rate: br[basicN] = basicN
  2898. *
  2899. * To look up the best basic rate corresponding to any
  2900. * particular rate, code can use the basic_rate table
  2901. * like this
  2902. *
  2903. * basic_rate = wlc->band->basic_rate[tx_rate]
  2904. *
  2905. * Make sure there is a best basic rate entry for
  2906. * every rate by walking up the table from low rates
  2907. * to high, filling in holes in the lookup table
  2908. */
  2909. for (i = 0; i < wlc->band->hw_rateset.count; i++) {
  2910. rate = wlc->band->hw_rateset.rates[i];
  2911. if (br[rate] != 0) {
  2912. /* This rate is a basic rate.
  2913. * Keep track of the best basic rate so far by
  2914. * modulation type.
  2915. */
  2916. if (is_ofdm_rate(rate))
  2917. ofdm_basic = rate;
  2918. else
  2919. cck_basic = rate;
  2920. continue;
  2921. }
  2922. /* This rate is not a basic rate so figure out the
  2923. * best basic rate less than this rate and fill in
  2924. * the hole in the table
  2925. */
  2926. br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
  2927. if (br[rate] != 0)
  2928. continue;
  2929. if (is_ofdm_rate(rate)) {
  2930. /*
  2931. * In 11g and 11a, the OFDM mandatory rates
  2932. * are 6, 12, and 24 Mbps
  2933. */
  2934. if (rate >= BRCM_RATE_24M)
  2935. mandatory = BRCM_RATE_24M;
  2936. else if (rate >= BRCM_RATE_12M)
  2937. mandatory = BRCM_RATE_12M;
  2938. else
  2939. mandatory = BRCM_RATE_6M;
  2940. } else {
  2941. /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
  2942. mandatory = rate;
  2943. }
  2944. br[rate] = mandatory;
  2945. }
  2946. }
  2947. static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
  2948. u16 chanspec)
  2949. {
  2950. struct brcms_c_rateset default_rateset;
  2951. uint parkband;
  2952. uint i, band_order[2];
  2953. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  2954. /*
  2955. * We might have been bandlocked during down and the chip
  2956. * power-cycled (hibernate). Figure out the right band to park on
  2957. */
  2958. if (wlc->bandlocked || wlc->pub->_nbands == 1) {
  2959. /* updated in brcms_c_bandlock() */
  2960. parkband = wlc->band->bandunit;
  2961. band_order[0] = band_order[1] = parkband;
  2962. } else {
  2963. /* park on the band of the specified chanspec */
  2964. parkband = chspec_bandunit(chanspec);
  2965. /* order so that parkband initialize last */
  2966. band_order[0] = parkband ^ 1;
  2967. band_order[1] = parkband;
  2968. }
  2969. /* make each band operational, software state init */
  2970. for (i = 0; i < wlc->pub->_nbands; i++) {
  2971. uint j = band_order[i];
  2972. wlc->band = wlc->bandstate[j];
  2973. brcms_default_rateset(wlc, &default_rateset);
  2974. /* fill in hw_rate */
  2975. brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
  2976. false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  2977. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  2978. /* init basic rate lookup */
  2979. brcms_c_rate_lookup_init(wlc, &default_rateset);
  2980. }
  2981. /* sync up phy/radio chanspec */
  2982. brcms_c_set_phy_chanspec(wlc, chanspec);
  2983. }
  2984. /*
  2985. * Set or clear filtering related maccontrol bits based on
  2986. * specified filter flags
  2987. */
  2988. void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
  2989. {
  2990. u32 promisc_bits = 0;
  2991. wlc->filter_flags = filter_flags;
  2992. if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
  2993. promisc_bits |= MCTL_PROMISC;
  2994. if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
  2995. promisc_bits |= MCTL_BCNS_PROMISC;
  2996. if (filter_flags & FIF_FCSFAIL)
  2997. promisc_bits |= MCTL_KEEPBADFCS;
  2998. if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
  2999. promisc_bits |= MCTL_KEEPCONTROL;
  3000. brcms_b_mctrl(wlc->hw,
  3001. MCTL_PROMISC | MCTL_BCNS_PROMISC |
  3002. MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
  3003. promisc_bits);
  3004. }
  3005. /*
  3006. * ucode, hwmac update
  3007. * Channel dependent updates for ucode and hw
  3008. */
  3009. static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
  3010. {
  3011. /* enable or disable any active IBSSs depending on whether or not
  3012. * we are on the home channel
  3013. */
  3014. if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
  3015. if (wlc->pub->associated) {
  3016. /*
  3017. * BMAC_NOTE: This is something that should be fixed
  3018. * in ucode inits. I think that the ucode inits set
  3019. * up the bcn templates and shm values with a bogus
  3020. * beacon. This should not be done in the inits. If
  3021. * ucode needs to set up a beacon for testing, the
  3022. * test routines should write it down, not expect the
  3023. * inits to populate a bogus beacon.
  3024. */
  3025. if (BRCMS_PHY_11N_CAP(wlc->band))
  3026. brcms_b_write_shm(wlc->hw,
  3027. M_BCN_TXTSF_OFFSET, 0);
  3028. }
  3029. } else {
  3030. /* disable an active IBSS if we are not on the home channel */
  3031. }
  3032. }
  3033. static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
  3034. u8 basic_rate)
  3035. {
  3036. u8 phy_rate, index;
  3037. u8 basic_phy_rate, basic_index;
  3038. u16 dir_table, basic_table;
  3039. u16 basic_ptr;
  3040. /* Shared memory address for the table we are reading */
  3041. dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
  3042. /* Shared memory address for the table we are writing */
  3043. basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
  3044. /*
  3045. * for a given rate, the LS-nibble of the PLCP SIGNAL field is
  3046. * the index into the rate table.
  3047. */
  3048. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  3049. basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
  3050. index = phy_rate & 0xf;
  3051. basic_index = basic_phy_rate & 0xf;
  3052. /* Find the SHM pointer to the ACK rate entry by looking in the
  3053. * Direct-map Table
  3054. */
  3055. basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
  3056. /* Update the SHM BSS-basic-rate-set mapping table with the pointer
  3057. * to the correct basic rate for the given incoming rate
  3058. */
  3059. brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
  3060. }
  3061. static const struct brcms_c_rateset *
  3062. brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
  3063. {
  3064. const struct brcms_c_rateset *rs_dflt;
  3065. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  3066. if (wlc->band->bandtype == BRCM_BAND_5G)
  3067. rs_dflt = &ofdm_mimo_rates;
  3068. else
  3069. rs_dflt = &cck_ofdm_mimo_rates;
  3070. } else if (wlc->band->gmode)
  3071. rs_dflt = &cck_ofdm_rates;
  3072. else
  3073. rs_dflt = &cck_rates;
  3074. return rs_dflt;
  3075. }
  3076. static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
  3077. {
  3078. const struct brcms_c_rateset *rs_dflt;
  3079. struct brcms_c_rateset rs;
  3080. u8 rate, basic_rate;
  3081. uint i;
  3082. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  3083. brcms_c_rateset_copy(rs_dflt, &rs);
  3084. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  3085. /* walk the phy rate table and update SHM basic rate lookup table */
  3086. for (i = 0; i < rs.count; i++) {
  3087. rate = rs.rates[i] & BRCMS_RATE_MASK;
  3088. /* for a given rate brcms_basic_rate returns the rate at
  3089. * which a response ACK/CTS should be sent.
  3090. */
  3091. basic_rate = brcms_basic_rate(wlc, rate);
  3092. if (basic_rate == 0)
  3093. /* This should only happen if we are using a
  3094. * restricted rateset.
  3095. */
  3096. basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
  3097. brcms_c_write_rate_shm(wlc, rate, basic_rate);
  3098. }
  3099. }
  3100. /* band-specific init */
  3101. static void brcms_c_bsinit(struct brcms_c_info *wlc)
  3102. {
  3103. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
  3104. wlc->pub->unit, wlc->band->bandunit);
  3105. /* write ucode ACK/CTS rate table */
  3106. brcms_c_set_ratetable(wlc);
  3107. /* update some band specific mac configuration */
  3108. brcms_c_ucode_mac_upd(wlc);
  3109. /* init antenna selection */
  3110. brcms_c_antsel_init(wlc->asi);
  3111. }
  3112. /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
  3113. static int
  3114. brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
  3115. bool writeToShm)
  3116. {
  3117. int idle_busy_ratio_x_16 = 0;
  3118. uint offset =
  3119. isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
  3120. M_TX_IDLE_BUSY_RATIO_X_16_CCK;
  3121. if (duty_cycle > 100 || duty_cycle < 0) {
  3122. wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
  3123. wlc->pub->unit);
  3124. return -EINVAL;
  3125. }
  3126. if (duty_cycle)
  3127. idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
  3128. /* Only write to shared memory when wl is up */
  3129. if (writeToShm)
  3130. brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
  3131. if (isOFDM)
  3132. wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
  3133. else
  3134. wlc->tx_duty_cycle_cck = (u16) duty_cycle;
  3135. return 0;
  3136. }
  3137. /*
  3138. * Initialize the base precedence map for dequeueing
  3139. * from txq based on WME settings
  3140. */
  3141. static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
  3142. {
  3143. wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
  3144. memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
  3145. wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK;
  3146. wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE;
  3147. wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI;
  3148. wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO;
  3149. }
  3150. static void
  3151. brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc,
  3152. struct brcms_txq_info *qi, bool on, int prio)
  3153. {
  3154. /* transmit flowcontrol is not yet implemented */
  3155. }
  3156. static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc)
  3157. {
  3158. struct brcms_txq_info *qi;
  3159. for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
  3160. if (qi->stopped) {
  3161. brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
  3162. qi->stopped = 0;
  3163. }
  3164. }
  3165. }
  3166. /* push sw hps and wake state through hardware */
  3167. static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
  3168. {
  3169. u32 v1, v2;
  3170. bool hps;
  3171. bool awake_before;
  3172. hps = brcms_c_ps_allowed(wlc);
  3173. BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
  3174. v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
  3175. v2 = MCTL_WAKE;
  3176. if (hps)
  3177. v2 |= MCTL_HPS;
  3178. brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
  3179. awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
  3180. if (!awake_before)
  3181. brcms_b_wait_for_wake(wlc->hw);
  3182. }
  3183. /*
  3184. * Write this BSS config's MAC address to core.
  3185. * Updates RXE match engine.
  3186. */
  3187. static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
  3188. {
  3189. int err = 0;
  3190. struct brcms_c_info *wlc = bsscfg->wlc;
  3191. /* enter the MAC addr into the RXE match registers */
  3192. brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
  3193. brcms_c_ampdu_macaddr_upd(wlc);
  3194. return err;
  3195. }
  3196. /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
  3197. * Updates RXE match engine.
  3198. */
  3199. static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
  3200. {
  3201. /* we need to update BSSID in RXE match registers */
  3202. brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
  3203. }
  3204. static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
  3205. {
  3206. wlc_hw->shortslot = shortslot;
  3207. if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
  3208. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  3209. brcms_b_update_slot_timing(wlc_hw, shortslot);
  3210. brcms_c_enable_mac(wlc_hw->wlc);
  3211. }
  3212. }
  3213. /*
  3214. * Suspend the the MAC and update the slot timing
  3215. * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
  3216. */
  3217. static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
  3218. {
  3219. /* use the override if it is set */
  3220. if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
  3221. shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
  3222. if (wlc->shortslot == shortslot)
  3223. return;
  3224. wlc->shortslot = shortslot;
  3225. brcms_b_set_shortslot(wlc->hw, shortslot);
  3226. }
  3227. static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3228. {
  3229. if (wlc->home_chanspec != chanspec) {
  3230. wlc->home_chanspec = chanspec;
  3231. if (wlc->bsscfg->associated)
  3232. wlc->bsscfg->current_bss->chanspec = chanspec;
  3233. }
  3234. }
  3235. void
  3236. brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
  3237. bool mute_tx, struct txpwr_limits *txpwr)
  3238. {
  3239. uint bandunit;
  3240. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
  3241. wlc_hw->chanspec = chanspec;
  3242. /* Switch bands if necessary */
  3243. if (wlc_hw->_nbands > 1) {
  3244. bandunit = chspec_bandunit(chanspec);
  3245. if (wlc_hw->band->bandunit != bandunit) {
  3246. /* brcms_b_setband disables other bandunit,
  3247. * use light band switch if not up yet
  3248. */
  3249. if (wlc_hw->up) {
  3250. wlc_phy_chanspec_radio_set(wlc_hw->
  3251. bandstate[bandunit]->
  3252. pi, chanspec);
  3253. brcms_b_setband(wlc_hw, bandunit, chanspec);
  3254. } else {
  3255. brcms_c_setxband(wlc_hw, bandunit);
  3256. }
  3257. }
  3258. }
  3259. wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
  3260. if (!wlc_hw->up) {
  3261. if (wlc_hw->clk)
  3262. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
  3263. chanspec);
  3264. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  3265. } else {
  3266. wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
  3267. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
  3268. /* Update muting of the channel */
  3269. brcms_b_mute(wlc_hw, mute_tx);
  3270. }
  3271. }
  3272. /* switch to and initialize new band */
  3273. static void brcms_c_setband(struct brcms_c_info *wlc,
  3274. uint bandunit)
  3275. {
  3276. wlc->band = wlc->bandstate[bandunit];
  3277. if (!wlc->pub->up)
  3278. return;
  3279. /* wait for at least one beacon before entering sleeping state */
  3280. brcms_c_set_ps_ctrl(wlc);
  3281. /* band-specific initializations */
  3282. brcms_c_bsinit(wlc);
  3283. }
  3284. static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3285. {
  3286. uint bandunit;
  3287. bool switchband = false;
  3288. u16 old_chanspec = wlc->chanspec;
  3289. if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
  3290. wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
  3291. wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
  3292. return;
  3293. }
  3294. /* Switch bands if necessary */
  3295. if (wlc->pub->_nbands > 1) {
  3296. bandunit = chspec_bandunit(chanspec);
  3297. if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
  3298. switchband = true;
  3299. if (wlc->bandlocked) {
  3300. wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
  3301. "band is locked!\n",
  3302. wlc->pub->unit, __func__,
  3303. CHSPEC_CHANNEL(chanspec));
  3304. return;
  3305. }
  3306. /*
  3307. * should the setband call come after the
  3308. * brcms_b_chanspec() ? if the setband updates
  3309. * (brcms_c_bsinit) use low level calls to inspect and
  3310. * set state, the state inspected may be from the wrong
  3311. * band, or the following brcms_b_set_chanspec() may
  3312. * undo the work.
  3313. */
  3314. brcms_c_setband(wlc, bandunit);
  3315. }
  3316. }
  3317. /* sync up phy/radio chanspec */
  3318. brcms_c_set_phy_chanspec(wlc, chanspec);
  3319. /* init antenna selection */
  3320. if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
  3321. brcms_c_antsel_init(wlc->asi);
  3322. /* Fix the hardware rateset based on bw.
  3323. * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
  3324. */
  3325. brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
  3326. wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
  3327. }
  3328. /* update some mac configuration since chanspec changed */
  3329. brcms_c_ucode_mac_upd(wlc);
  3330. }
  3331. /*
  3332. * This function changes the phytxctl for beacon based on current
  3333. * beacon ratespec AND txant setting as per this table:
  3334. * ratespec CCK ant = wlc->stf->txant
  3335. * OFDM ant = 3
  3336. */
  3337. void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
  3338. u32 bcn_rspec)
  3339. {
  3340. u16 phyctl;
  3341. u16 phytxant = wlc->stf->phytxant;
  3342. u16 mask = PHY_TXC_ANT_MASK;
  3343. /* for non-siso rates or default setting, use the available chains */
  3344. if (BRCMS_PHY_11N_CAP(wlc->band))
  3345. phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
  3346. phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
  3347. phyctl = (phyctl & ~mask) | phytxant;
  3348. brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
  3349. }
  3350. /*
  3351. * centralized protection config change function to simplify debugging, no
  3352. * consistency checking this should be called only on changes to avoid overhead
  3353. * in periodic function
  3354. */
  3355. void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
  3356. {
  3357. BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
  3358. switch (idx) {
  3359. case BRCMS_PROT_G_SPEC:
  3360. wlc->protection->_g = (bool) val;
  3361. break;
  3362. case BRCMS_PROT_G_OVR:
  3363. wlc->protection->g_override = (s8) val;
  3364. break;
  3365. case BRCMS_PROT_G_USER:
  3366. wlc->protection->gmode_user = (u8) val;
  3367. break;
  3368. case BRCMS_PROT_OVERLAP:
  3369. wlc->protection->overlap = (s8) val;
  3370. break;
  3371. case BRCMS_PROT_N_USER:
  3372. wlc->protection->nmode_user = (s8) val;
  3373. break;
  3374. case BRCMS_PROT_N_CFG:
  3375. wlc->protection->n_cfg = (s8) val;
  3376. break;
  3377. case BRCMS_PROT_N_CFG_OVR:
  3378. wlc->protection->n_cfg_override = (s8) val;
  3379. break;
  3380. case BRCMS_PROT_N_NONGF:
  3381. wlc->protection->nongf = (bool) val;
  3382. break;
  3383. case BRCMS_PROT_N_NONGF_OVR:
  3384. wlc->protection->nongf_override = (s8) val;
  3385. break;
  3386. case BRCMS_PROT_N_PAM_OVR:
  3387. wlc->protection->n_pam_override = (s8) val;
  3388. break;
  3389. case BRCMS_PROT_N_OBSS:
  3390. wlc->protection->n_obss = (bool) val;
  3391. break;
  3392. default:
  3393. break;
  3394. }
  3395. }
  3396. static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
  3397. {
  3398. if (wlc->pub->up) {
  3399. brcms_c_update_beacon(wlc);
  3400. brcms_c_update_probe_resp(wlc, true);
  3401. }
  3402. }
  3403. static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
  3404. {
  3405. wlc->stf->ldpc = val;
  3406. if (wlc->pub->up) {
  3407. brcms_c_update_beacon(wlc);
  3408. brcms_c_update_probe_resp(wlc, true);
  3409. wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
  3410. }
  3411. }
  3412. void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
  3413. const struct ieee80211_tx_queue_params *params,
  3414. bool suspend)
  3415. {
  3416. int i;
  3417. struct shm_acparams acp_shm;
  3418. u16 *shm_entry;
  3419. /* Only apply params if the core is out of reset and has clocks */
  3420. if (!wlc->clk) {
  3421. wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
  3422. __func__);
  3423. return;
  3424. }
  3425. memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
  3426. /* fill in shm ac params struct */
  3427. acp_shm.txop = params->txop;
  3428. /* convert from units of 32us to us for ucode */
  3429. wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
  3430. EDCF_TXOP2USEC(acp_shm.txop);
  3431. acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
  3432. if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
  3433. && acp_shm.aifs < EDCF_AIFSN_MAX)
  3434. acp_shm.aifs++;
  3435. if (acp_shm.aifs < EDCF_AIFSN_MIN
  3436. || acp_shm.aifs > EDCF_AIFSN_MAX) {
  3437. wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
  3438. "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
  3439. } else {
  3440. acp_shm.cwmin = params->cw_min;
  3441. acp_shm.cwmax = params->cw_max;
  3442. acp_shm.cwcur = acp_shm.cwmin;
  3443. acp_shm.bslots =
  3444. bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
  3445. acp_shm.cwcur;
  3446. acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
  3447. /* Indicate the new params to the ucode */
  3448. acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
  3449. wme_ac2fifo[aci] *
  3450. M_EDCF_QLEN +
  3451. M_EDCF_STATUS_OFF));
  3452. acp_shm.status |= WME_STATUS_NEWAC;
  3453. /* Fill in shm acparam table */
  3454. shm_entry = (u16 *) &acp_shm;
  3455. for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
  3456. brcms_b_write_shm(wlc->hw,
  3457. M_EDCF_QINFO +
  3458. wme_ac2fifo[aci] * M_EDCF_QLEN + i,
  3459. *shm_entry++);
  3460. }
  3461. if (suspend) {
  3462. brcms_c_suspend_mac_and_wait(wlc);
  3463. brcms_c_enable_mac(wlc);
  3464. }
  3465. }
  3466. static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
  3467. {
  3468. u16 aci;
  3469. int i_ac;
  3470. struct ieee80211_tx_queue_params txq_pars;
  3471. static const struct edcf_acparam default_edcf_acparams[] = {
  3472. {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
  3473. {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
  3474. {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
  3475. {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
  3476. }; /* ucode needs these parameters during its initialization */
  3477. const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
  3478. for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
  3479. /* find out which ac this set of params applies to */
  3480. aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
  3481. /* fill in shm ac params struct */
  3482. txq_pars.txop = edcf_acp->TXOP;
  3483. txq_pars.aifs = edcf_acp->ACI;
  3484. /* CWmin = 2^(ECWmin) - 1 */
  3485. txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
  3486. /* CWmax = 2^(ECWmax) - 1 */
  3487. txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
  3488. >> EDCF_ECWMAX_SHIFT);
  3489. brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
  3490. }
  3491. if (suspend) {
  3492. brcms_c_suspend_mac_and_wait(wlc);
  3493. brcms_c_enable_mac(wlc);
  3494. }
  3495. }
  3496. static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
  3497. {
  3498. /* Don't start the timer if HWRADIO feature is disabled */
  3499. if (wlc->radio_monitor)
  3500. return;
  3501. wlc->radio_monitor = true;
  3502. brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
  3503. brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
  3504. }
  3505. static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
  3506. {
  3507. if (!wlc->radio_monitor)
  3508. return true;
  3509. wlc->radio_monitor = false;
  3510. brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
  3511. return brcms_del_timer(wlc->radio_timer);
  3512. }
  3513. /* read hwdisable state and propagate to wlc flag */
  3514. static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
  3515. {
  3516. if (wlc->pub->hw_off)
  3517. return;
  3518. if (brcms_b_radio_read_hwdisabled(wlc->hw))
  3519. mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3520. else
  3521. mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3522. }
  3523. /* update hwradio status and return it */
  3524. bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
  3525. {
  3526. brcms_c_radio_hwdisable_upd(wlc);
  3527. return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
  3528. true : false;
  3529. }
  3530. /* periodical query hw radio button while driver is "down" */
  3531. static void brcms_c_radio_timer(void *arg)
  3532. {
  3533. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3534. if (brcms_deviceremoved(wlc)) {
  3535. wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
  3536. __func__);
  3537. brcms_down(wlc->wl);
  3538. return;
  3539. }
  3540. brcms_c_radio_hwdisable_upd(wlc);
  3541. }
  3542. /* common low-level watchdog code */
  3543. static void brcms_b_watchdog(void *arg)
  3544. {
  3545. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3546. struct brcms_hardware *wlc_hw = wlc->hw;
  3547. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  3548. if (!wlc_hw->up)
  3549. return;
  3550. /* increment second count */
  3551. wlc_hw->now++;
  3552. /* Check for FIFO error interrupts */
  3553. brcms_b_fifoerrors(wlc_hw);
  3554. /* make sure RX dma has buffers */
  3555. dma_rxfill(wlc->hw->di[RX_FIFO]);
  3556. wlc_phy_watchdog(wlc_hw->band->pi);
  3557. }
  3558. /* common watchdog code */
  3559. static void brcms_c_watchdog(void *arg)
  3560. {
  3561. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3562. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  3563. if (!wlc->pub->up)
  3564. return;
  3565. if (brcms_deviceremoved(wlc)) {
  3566. wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
  3567. __func__);
  3568. brcms_down(wlc->wl);
  3569. return;
  3570. }
  3571. /* increment second count */
  3572. wlc->pub->now++;
  3573. brcms_c_radio_hwdisable_upd(wlc);
  3574. /* if radio is disable, driver may be down, quit here */
  3575. if (wlc->pub->radio_disabled)
  3576. return;
  3577. brcms_b_watchdog(wlc);
  3578. /*
  3579. * occasionally sample mac stat counters to
  3580. * detect 16-bit counter wrap
  3581. */
  3582. if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
  3583. brcms_c_statsupd(wlc);
  3584. if (BRCMS_ISNPHY(wlc->band) &&
  3585. ((wlc->pub->now - wlc->tempsense_lasttime) >=
  3586. BRCMS_TEMPSENSE_PERIOD)) {
  3587. wlc->tempsense_lasttime = wlc->pub->now;
  3588. brcms_c_tempsense_upd(wlc);
  3589. }
  3590. }
  3591. static void brcms_c_watchdog_by_timer(void *arg)
  3592. {
  3593. brcms_c_watchdog(arg);
  3594. }
  3595. static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
  3596. {
  3597. wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
  3598. wlc, "watchdog");
  3599. if (!wlc->wdtimer) {
  3600. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
  3601. "failed\n", unit);
  3602. goto fail;
  3603. }
  3604. wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
  3605. wlc, "radio");
  3606. if (!wlc->radio_timer) {
  3607. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
  3608. "failed\n", unit);
  3609. goto fail;
  3610. }
  3611. return true;
  3612. fail:
  3613. return false;
  3614. }
  3615. /*
  3616. * Initialize brcms_c_info default values ...
  3617. * may get overrides later in this function
  3618. */
  3619. static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
  3620. {
  3621. int i;
  3622. /* Save our copy of the chanspec */
  3623. wlc->chanspec = ch20mhz_chspec(1);
  3624. /* various 802.11g modes */
  3625. wlc->shortslot = false;
  3626. wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
  3627. brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
  3628. brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
  3629. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
  3630. BRCMS_PROTECTION_AUTO);
  3631. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
  3632. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
  3633. BRCMS_PROTECTION_AUTO);
  3634. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
  3635. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
  3636. brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
  3637. BRCMS_PROTECTION_CTL_OVERLAP);
  3638. /* 802.11g draft 4.0 NonERP elt advertisement */
  3639. wlc->include_legacy_erp = true;
  3640. wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
  3641. wlc->stf->txant = ANT_TX_DEF;
  3642. wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
  3643. wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
  3644. for (i = 0; i < NFIFO; i++)
  3645. wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
  3646. wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
  3647. /* default rate fallback retry limits */
  3648. wlc->SFBL = RETRY_SHORT_FB;
  3649. wlc->LFBL = RETRY_LONG_FB;
  3650. /* default mac retry limits */
  3651. wlc->SRL = RETRY_SHORT_DEF;
  3652. wlc->LRL = RETRY_LONG_DEF;
  3653. /* WME QoS mode is Auto by default */
  3654. wlc->pub->_ampdu = AMPDU_AGG_HOST;
  3655. wlc->pub->bcmerror = 0;
  3656. }
  3657. static uint brcms_c_attach_module(struct brcms_c_info *wlc)
  3658. {
  3659. uint err = 0;
  3660. uint unit;
  3661. unit = wlc->pub->unit;
  3662. wlc->asi = brcms_c_antsel_attach(wlc);
  3663. if (wlc->asi == NULL) {
  3664. wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
  3665. "failed\n", unit);
  3666. err = 44;
  3667. goto fail;
  3668. }
  3669. wlc->ampdu = brcms_c_ampdu_attach(wlc);
  3670. if (wlc->ampdu == NULL) {
  3671. wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
  3672. "failed\n", unit);
  3673. err = 50;
  3674. goto fail;
  3675. }
  3676. if ((brcms_c_stf_attach(wlc) != 0)) {
  3677. wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
  3678. "failed\n", unit);
  3679. err = 68;
  3680. goto fail;
  3681. }
  3682. fail:
  3683. return err;
  3684. }
  3685. struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
  3686. {
  3687. return wlc->pub;
  3688. }
  3689. /* low level attach
  3690. * run backplane attach, init nvram
  3691. * run phy attach
  3692. * initialize software state for each core and band
  3693. * put the whole chip in reset(driver down state), no clock
  3694. */
  3695. static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
  3696. uint unit, bool piomode)
  3697. {
  3698. struct brcms_hardware *wlc_hw;
  3699. char *macaddr = NULL;
  3700. uint err = 0;
  3701. uint j;
  3702. bool wme = false;
  3703. struct shared_phy_params sha_params;
  3704. struct wiphy *wiphy = wlc->wiphy;
  3705. struct pci_dev *pcidev = core->bus->host_pci;
  3706. BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
  3707. pcidev->vendor,
  3708. pcidev->device);
  3709. wme = true;
  3710. wlc_hw = wlc->hw;
  3711. wlc_hw->wlc = wlc;
  3712. wlc_hw->unit = unit;
  3713. wlc_hw->band = wlc_hw->bandstate[0];
  3714. wlc_hw->_piomode = piomode;
  3715. /* populate struct brcms_hardware with default values */
  3716. brcms_b_info_init(wlc_hw);
  3717. /*
  3718. * Do the hardware portion of the attach. Also initialize software
  3719. * state that depends on the particular hardware we are running.
  3720. */
  3721. wlc_hw->sih = ai_attach(core->bus);
  3722. if (wlc_hw->sih == NULL) {
  3723. wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
  3724. unit);
  3725. err = 11;
  3726. goto fail;
  3727. }
  3728. /* verify again the device is supported */
  3729. if (!brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
  3730. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
  3731. "vendor/device (0x%x/0x%x)\n",
  3732. unit, pcidev->vendor, pcidev->device);
  3733. err = 12;
  3734. goto fail;
  3735. }
  3736. wlc_hw->vendorid = pcidev->vendor;
  3737. wlc_hw->deviceid = pcidev->device;
  3738. /* set bar0 window to point at D11 core */
  3739. (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
  3740. wlc_hw->d11core = core;
  3741. wlc_hw->corerev = core->id.rev;
  3742. /* validate chip, chiprev and corerev */
  3743. if (!brcms_c_isgoodchip(wlc_hw)) {
  3744. err = 13;
  3745. goto fail;
  3746. }
  3747. /* initialize power control registers */
  3748. ai_clkctl_init(wlc_hw->sih);
  3749. /* request fastclock and force fastclock for the rest of attach
  3750. * bring the d11 core out of reset.
  3751. * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
  3752. * is still false; But it will be called again inside wlc_corereset,
  3753. * after d11 is out of reset.
  3754. */
  3755. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  3756. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  3757. if (!brcms_b_validate_chip_access(wlc_hw)) {
  3758. wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
  3759. "failed\n", unit);
  3760. err = 14;
  3761. goto fail;
  3762. }
  3763. /* get the board rev, used just below */
  3764. j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV);
  3765. /* promote srom boardrev of 0xFF to 1 */
  3766. if (j == BOARDREV_PROMOTABLE)
  3767. j = BOARDREV_PROMOTED;
  3768. wlc_hw->boardrev = (u16) j;
  3769. if (!brcms_c_validboardtype(wlc_hw)) {
  3770. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
  3771. "board type (0x%x)" " or revision level (0x%x)\n",
  3772. unit, ai_get_boardtype(wlc_hw->sih),
  3773. wlc_hw->boardrev);
  3774. err = 15;
  3775. goto fail;
  3776. }
  3777. wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV);
  3778. wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih,
  3779. BRCMS_SROM_BOARDFLAGS);
  3780. wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih,
  3781. BRCMS_SROM_BOARDFLAGS2);
  3782. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  3783. brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
  3784. /* check device id(srom, nvram etc.) to set bands */
  3785. if (wlc_hw->deviceid == BCM43224_D11N_ID ||
  3786. wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
  3787. /* Dualband boards */
  3788. wlc_hw->_nbands = 2;
  3789. else
  3790. wlc_hw->_nbands = 1;
  3791. if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
  3792. wlc_hw->_nbands = 1;
  3793. /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
  3794. * unconditionally does the init of these values
  3795. */
  3796. wlc->vendorid = wlc_hw->vendorid;
  3797. wlc->deviceid = wlc_hw->deviceid;
  3798. wlc->pub->sih = wlc_hw->sih;
  3799. wlc->pub->corerev = wlc_hw->corerev;
  3800. wlc->pub->sromrev = wlc_hw->sromrev;
  3801. wlc->pub->boardrev = wlc_hw->boardrev;
  3802. wlc->pub->boardflags = wlc_hw->boardflags;
  3803. wlc->pub->boardflags2 = wlc_hw->boardflags2;
  3804. wlc->pub->_nbands = wlc_hw->_nbands;
  3805. wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
  3806. if (wlc_hw->physhim == NULL) {
  3807. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
  3808. "failed\n", unit);
  3809. err = 25;
  3810. goto fail;
  3811. }
  3812. /* pass all the parameters to wlc_phy_shared_attach in one struct */
  3813. sha_params.sih = wlc_hw->sih;
  3814. sha_params.physhim = wlc_hw->physhim;
  3815. sha_params.unit = unit;
  3816. sha_params.corerev = wlc_hw->corerev;
  3817. sha_params.vid = wlc_hw->vendorid;
  3818. sha_params.did = wlc_hw->deviceid;
  3819. sha_params.chip = ai_get_chip_id(wlc_hw->sih);
  3820. sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
  3821. sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
  3822. sha_params.sromrev = wlc_hw->sromrev;
  3823. sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
  3824. sha_params.boardrev = wlc_hw->boardrev;
  3825. sha_params.boardflags = wlc_hw->boardflags;
  3826. sha_params.boardflags2 = wlc_hw->boardflags2;
  3827. /* alloc and save pointer to shared phy state area */
  3828. wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
  3829. if (!wlc_hw->phy_sh) {
  3830. err = 16;
  3831. goto fail;
  3832. }
  3833. /* initialize software state for each core and band */
  3834. for (j = 0; j < wlc_hw->_nbands; j++) {
  3835. /*
  3836. * band0 is always 2.4Ghz
  3837. * band1, if present, is 5Ghz
  3838. */
  3839. brcms_c_setxband(wlc_hw, j);
  3840. wlc_hw->band->bandunit = j;
  3841. wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3842. wlc->band->bandunit = j;
  3843. wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3844. wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
  3845. wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
  3846. wlc_hw->machwcap_backup = wlc_hw->machwcap;
  3847. /* init tx fifo size */
  3848. wlc_hw->xmtfifo_sz =
  3849. xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
  3850. /* Get a phy for this band */
  3851. wlc_hw->band->pi =
  3852. wlc_phy_attach(wlc_hw->phy_sh, core,
  3853. wlc_hw->band->bandtype,
  3854. wlc->wiphy);
  3855. if (wlc_hw->band->pi == NULL) {
  3856. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
  3857. "attach failed\n", unit);
  3858. err = 17;
  3859. goto fail;
  3860. }
  3861. wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
  3862. wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
  3863. &wlc_hw->band->phyrev,
  3864. &wlc_hw->band->radioid,
  3865. &wlc_hw->band->radiorev);
  3866. wlc_hw->band->abgphy_encore =
  3867. wlc_phy_get_encore(wlc_hw->band->pi);
  3868. wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
  3869. wlc_hw->band->core_flags =
  3870. wlc_phy_get_coreflags(wlc_hw->band->pi);
  3871. /* verify good phy_type & supported phy revision */
  3872. if (BRCMS_ISNPHY(wlc_hw->band)) {
  3873. if (NCONF_HAS(wlc_hw->band->phyrev))
  3874. goto good_phy;
  3875. else
  3876. goto bad_phy;
  3877. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  3878. if (LCNCONF_HAS(wlc_hw->band->phyrev))
  3879. goto good_phy;
  3880. else
  3881. goto bad_phy;
  3882. } else {
  3883. bad_phy:
  3884. wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
  3885. "phy type/rev (%d/%d)\n", unit,
  3886. wlc_hw->band->phytype, wlc_hw->band->phyrev);
  3887. err = 18;
  3888. goto fail;
  3889. }
  3890. good_phy:
  3891. /*
  3892. * BMAC_NOTE: wlc->band->pi should not be set below and should
  3893. * be done in the high level attach. However we can not make
  3894. * that change until all low level access is changed to
  3895. * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
  3896. * keeping wlc_hw->band->pi as well for incremental update of
  3897. * low level fns, and cut over low only init when all fns
  3898. * updated.
  3899. */
  3900. wlc->band->pi = wlc_hw->band->pi;
  3901. wlc->band->phytype = wlc_hw->band->phytype;
  3902. wlc->band->phyrev = wlc_hw->band->phyrev;
  3903. wlc->band->radioid = wlc_hw->band->radioid;
  3904. wlc->band->radiorev = wlc_hw->band->radiorev;
  3905. /* default contention windows size limits */
  3906. wlc_hw->band->CWmin = APHY_CWMIN;
  3907. wlc_hw->band->CWmax = PHY_CWMAX;
  3908. if (!brcms_b_attach_dmapio(wlc, j, wme)) {
  3909. err = 19;
  3910. goto fail;
  3911. }
  3912. }
  3913. /* disable core to match driver "down" state */
  3914. brcms_c_coredisable(wlc_hw);
  3915. /* Match driver "down" state */
  3916. ai_pci_down(wlc_hw->sih);
  3917. /* register sb interrupt callback functions */
  3918. ai_register_intr_callback(wlc_hw->sih, (void *)brcms_c_wlintrsoff,
  3919. (void *)brcms_c_wlintrsrestore, NULL, wlc);
  3920. /* turn off pll and xtal to match driver "down" state */
  3921. brcms_b_xtal(wlc_hw, OFF);
  3922. /* *******************************************************************
  3923. * The hardware is in the DOWN state at this point. D11 core
  3924. * or cores are in reset with clocks off, and the board PLLs
  3925. * are off if possible.
  3926. *
  3927. * Beyond this point, wlc->sbclk == false and chip registers
  3928. * should not be touched.
  3929. *********************************************************************
  3930. */
  3931. /* init etheraddr state variables */
  3932. macaddr = brcms_c_get_macaddr(wlc_hw);
  3933. if (macaddr == NULL) {
  3934. wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
  3935. unit);
  3936. err = 21;
  3937. goto fail;
  3938. }
  3939. if (!mac_pton(macaddr, wlc_hw->etheraddr) ||
  3940. is_broadcast_ether_addr(wlc_hw->etheraddr) ||
  3941. is_zero_ether_addr(wlc_hw->etheraddr)) {
  3942. wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
  3943. unit, macaddr);
  3944. err = 22;
  3945. goto fail;
  3946. }
  3947. BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
  3948. wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih),
  3949. macaddr);
  3950. return err;
  3951. fail:
  3952. wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
  3953. err);
  3954. return err;
  3955. }
  3956. static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
  3957. {
  3958. uint unit;
  3959. unit = wlc->pub->unit;
  3960. if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
  3961. /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
  3962. wlc->band->antgain = 8;
  3963. } else if (wlc->band->antgain == -1) {
  3964. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3965. " srom, using 2dB\n", unit, __func__);
  3966. wlc->band->antgain = 8;
  3967. } else {
  3968. s8 gain, fract;
  3969. /* Older sroms specified gain in whole dbm only. In order
  3970. * be able to specify qdbm granularity and remain backward
  3971. * compatible the whole dbms are now encoded in only
  3972. * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
  3973. * 6 bit signed number ranges from -32 - 31.
  3974. *
  3975. * Examples:
  3976. * 0x1 = 1 db,
  3977. * 0xc1 = 1.75 db (1 + 3 quarters),
  3978. * 0x3f = -1 (-1 + 0 quarters),
  3979. * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
  3980. * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
  3981. */
  3982. gain = wlc->band->antgain & 0x3f;
  3983. gain <<= 2; /* Sign extend */
  3984. gain >>= 2;
  3985. fract = (wlc->band->antgain & 0xc0) >> 6;
  3986. wlc->band->antgain = 4 * gain + fract;
  3987. }
  3988. }
  3989. static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
  3990. {
  3991. int aa;
  3992. uint unit;
  3993. int bandtype;
  3994. struct si_pub *sih = wlc->hw->sih;
  3995. unit = wlc->pub->unit;
  3996. bandtype = wlc->band->bandtype;
  3997. /* get antennas available */
  3998. if (bandtype == BRCM_BAND_5G)
  3999. aa = (s8) getintvar(sih, BRCMS_SROM_AA5G);
  4000. else
  4001. aa = (s8) getintvar(sih, BRCMS_SROM_AA2G);
  4002. if ((aa < 1) || (aa > 15)) {
  4003. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  4004. " srom (0x%x), using 3\n", unit, __func__, aa);
  4005. aa = 3;
  4006. }
  4007. /* reset the defaults if we have a single antenna */
  4008. if (aa == 1) {
  4009. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
  4010. wlc->stf->txant = ANT_TX_FORCE_0;
  4011. } else if (aa == 2) {
  4012. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
  4013. wlc->stf->txant = ANT_TX_FORCE_1;
  4014. } else {
  4015. }
  4016. /* Compute Antenna Gain */
  4017. if (bandtype == BRCM_BAND_5G)
  4018. wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1);
  4019. else
  4020. wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0);
  4021. brcms_c_attach_antgain_init(wlc);
  4022. return true;
  4023. }
  4024. static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
  4025. {
  4026. u16 chanspec;
  4027. struct brcms_band *band;
  4028. struct brcms_bss_info *bi = wlc->default_bss;
  4029. /* init default and target BSS with some sane initial values */
  4030. memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
  4031. bi->beacon_period = BEACON_INTERVAL_DEFAULT;
  4032. /* fill the default channel as the first valid channel
  4033. * starting from the 2G channels
  4034. */
  4035. chanspec = ch20mhz_chspec(1);
  4036. wlc->home_chanspec = bi->chanspec = chanspec;
  4037. /* find the band of our default channel */
  4038. band = wlc->band;
  4039. if (wlc->pub->_nbands > 1 &&
  4040. band->bandunit != chspec_bandunit(chanspec))
  4041. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  4042. /* init bss rates to the band specific default rate set */
  4043. brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
  4044. band->bandtype, false, BRCMS_RATE_MASK_FULL,
  4045. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  4046. brcms_chspec_bw(chanspec), wlc->stf->txstreams);
  4047. if (wlc->pub->_n_enab & SUPPORT_11N)
  4048. bi->flags |= BRCMS_BSS_HT;
  4049. }
  4050. static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
  4051. {
  4052. struct brcms_txq_info *qi, *p;
  4053. qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
  4054. if (qi != NULL) {
  4055. /*
  4056. * Have enough room for control packets along with HI watermark
  4057. * Also, add room to txq for total psq packets if all the SCBs
  4058. * leave PS mode. The watermark for flowcontrol to OS packets
  4059. * will remain the same
  4060. */
  4061. brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
  4062. 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
  4063. /* add this queue to the the global list */
  4064. p = wlc->tx_queues;
  4065. if (p == NULL) {
  4066. wlc->tx_queues = qi;
  4067. } else {
  4068. while (p->next != NULL)
  4069. p = p->next;
  4070. p->next = qi;
  4071. }
  4072. }
  4073. return qi;
  4074. }
  4075. static void brcms_c_txq_free(struct brcms_c_info *wlc,
  4076. struct brcms_txq_info *qi)
  4077. {
  4078. struct brcms_txq_info *p;
  4079. if (qi == NULL)
  4080. return;
  4081. /* remove the queue from the linked list */
  4082. p = wlc->tx_queues;
  4083. if (p == qi)
  4084. wlc->tx_queues = p->next;
  4085. else {
  4086. while (p != NULL && p->next != qi)
  4087. p = p->next;
  4088. if (p != NULL)
  4089. p->next = p->next->next;
  4090. }
  4091. kfree(qi);
  4092. }
  4093. static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
  4094. {
  4095. uint i;
  4096. struct brcms_band *band;
  4097. for (i = 0; i < wlc->pub->_nbands; i++) {
  4098. band = wlc->bandstate[i];
  4099. if (band->bandtype == BRCM_BAND_5G) {
  4100. if ((bwcap == BRCMS_N_BW_40ALL)
  4101. || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
  4102. band->mimo_cap_40 = true;
  4103. else
  4104. band->mimo_cap_40 = false;
  4105. } else {
  4106. if (bwcap == BRCMS_N_BW_40ALL)
  4107. band->mimo_cap_40 = true;
  4108. else
  4109. band->mimo_cap_40 = false;
  4110. }
  4111. }
  4112. }
  4113. static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
  4114. {
  4115. /* free timer state */
  4116. if (wlc->wdtimer) {
  4117. brcms_free_timer(wlc->wdtimer);
  4118. wlc->wdtimer = NULL;
  4119. }
  4120. if (wlc->radio_timer) {
  4121. brcms_free_timer(wlc->radio_timer);
  4122. wlc->radio_timer = NULL;
  4123. }
  4124. }
  4125. static void brcms_c_detach_module(struct brcms_c_info *wlc)
  4126. {
  4127. if (wlc->asi) {
  4128. brcms_c_antsel_detach(wlc->asi);
  4129. wlc->asi = NULL;
  4130. }
  4131. if (wlc->ampdu) {
  4132. brcms_c_ampdu_detach(wlc->ampdu);
  4133. wlc->ampdu = NULL;
  4134. }
  4135. brcms_c_stf_detach(wlc);
  4136. }
  4137. /*
  4138. * low level detach
  4139. */
  4140. static int brcms_b_detach(struct brcms_c_info *wlc)
  4141. {
  4142. uint i;
  4143. struct brcms_hw_band *band;
  4144. struct brcms_hardware *wlc_hw = wlc->hw;
  4145. int callbacks;
  4146. callbacks = 0;
  4147. if (wlc_hw->sih) {
  4148. /*
  4149. * detach interrupt sync mechanism since interrupt is disabled
  4150. * and per-port interrupt object may has been freed. this must
  4151. * be done before sb core switch
  4152. */
  4153. ai_deregister_intr_callback(wlc_hw->sih);
  4154. ai_pci_sleep(wlc_hw->sih);
  4155. }
  4156. brcms_b_detach_dmapio(wlc_hw);
  4157. band = wlc_hw->band;
  4158. for (i = 0; i < wlc_hw->_nbands; i++) {
  4159. if (band->pi) {
  4160. /* Detach this band's phy */
  4161. wlc_phy_detach(band->pi);
  4162. band->pi = NULL;
  4163. }
  4164. band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
  4165. }
  4166. /* Free shared phy state */
  4167. kfree(wlc_hw->phy_sh);
  4168. wlc_phy_shim_detach(wlc_hw->physhim);
  4169. if (wlc_hw->sih) {
  4170. ai_detach(wlc_hw->sih);
  4171. wlc_hw->sih = NULL;
  4172. }
  4173. return callbacks;
  4174. }
  4175. /*
  4176. * Return a count of the number of driver callbacks still pending.
  4177. *
  4178. * General policy is that brcms_c_detach can only dealloc/free software states.
  4179. * It can NOT touch hardware registers since the d11core may be in reset and
  4180. * clock may not be available.
  4181. * One exception is sb register access, which is possible if crystal is turned
  4182. * on after "down" state, driver should avoid software timer with the exception
  4183. * of radio_monitor.
  4184. */
  4185. uint brcms_c_detach(struct brcms_c_info *wlc)
  4186. {
  4187. uint callbacks = 0;
  4188. if (wlc == NULL)
  4189. return 0;
  4190. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  4191. callbacks += brcms_b_detach(wlc);
  4192. /* delete software timers */
  4193. if (!brcms_c_radio_monitor_stop(wlc))
  4194. callbacks++;
  4195. brcms_c_channel_mgr_detach(wlc->cmi);
  4196. brcms_c_timers_deinit(wlc);
  4197. brcms_c_detach_module(wlc);
  4198. while (wlc->tx_queues != NULL)
  4199. brcms_c_txq_free(wlc, wlc->tx_queues);
  4200. brcms_c_detach_mfree(wlc);
  4201. return callbacks;
  4202. }
  4203. /* update state that depends on the current value of "ap" */
  4204. static void brcms_c_ap_upd(struct brcms_c_info *wlc)
  4205. {
  4206. /* STA-BSS; short capable */
  4207. wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
  4208. }
  4209. /* Initialize just the hardware when coming out of POR or S3/S5 system states */
  4210. static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
  4211. {
  4212. if (wlc_hw->wlc->pub->hw_up)
  4213. return;
  4214. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4215. /*
  4216. * Enable pll and xtal, initialize the power control registers,
  4217. * and force fastclock for the remainder of brcms_c_up().
  4218. */
  4219. brcms_b_xtal(wlc_hw, ON);
  4220. ai_clkctl_init(wlc_hw->sih);
  4221. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  4222. ai_pci_fixcfg(wlc_hw->sih);
  4223. /*
  4224. * AI chip doesn't restore bar0win2 on
  4225. * hibernation/resume, need sw fixup
  4226. */
  4227. if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
  4228. (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
  4229. (void)ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
  4230. /*
  4231. * Inform phy that a POR reset has occurred so
  4232. * it does a complete phy init
  4233. */
  4234. wlc_phy_por_inform(wlc_hw->band->pi);
  4235. wlc_hw->ucode_loaded = false;
  4236. wlc_hw->wlc->pub->hw_up = true;
  4237. if ((wlc_hw->boardflags & BFL_FEM)
  4238. && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
  4239. if (!
  4240. (wlc_hw->boardrev >= 0x1250
  4241. && (wlc_hw->boardflags & BFL_FEM_BT)))
  4242. ai_epa_4313war(wlc_hw->sih);
  4243. }
  4244. }
  4245. static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
  4246. {
  4247. uint coremask;
  4248. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4249. /*
  4250. * Enable pll and xtal, initialize the power control registers,
  4251. * and force fastclock for the remainder of brcms_c_up().
  4252. */
  4253. brcms_b_xtal(wlc_hw, ON);
  4254. ai_clkctl_init(wlc_hw->sih);
  4255. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  4256. /*
  4257. * Configure pci/pcmcia here instead of in brcms_c_attach()
  4258. * to allow mfg hotswap: down, hotswap (chip power cycle), up.
  4259. */
  4260. coremask = (1 << wlc_hw->wlc->core->coreidx);
  4261. ai_pci_setup(wlc_hw->sih, coremask);
  4262. /*
  4263. * Need to read the hwradio status here to cover the case where the
  4264. * system is loaded with the hw radio disabled. We do not want to
  4265. * bring the driver up in this case.
  4266. */
  4267. if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
  4268. /* put SB PCI in down state again */
  4269. ai_pci_down(wlc_hw->sih);
  4270. brcms_b_xtal(wlc_hw, OFF);
  4271. return -ENOMEDIUM;
  4272. }
  4273. ai_pci_up(wlc_hw->sih);
  4274. /* reset the d11 core */
  4275. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  4276. return 0;
  4277. }
  4278. static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
  4279. {
  4280. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4281. wlc_hw->up = true;
  4282. wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
  4283. /* FULLY enable dynamic power control and d11 core interrupt */
  4284. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  4285. brcms_intrson(wlc_hw->wlc->wl);
  4286. return 0;
  4287. }
  4288. /*
  4289. * Write WME tunable parameters for retransmit/max rate
  4290. * from wlc struct to ucode
  4291. */
  4292. static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
  4293. {
  4294. int ac;
  4295. /* Need clock to do this */
  4296. if (!wlc->clk)
  4297. return;
  4298. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  4299. brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
  4300. wlc->wme_retries[ac]);
  4301. }
  4302. /* make interface operational */
  4303. int brcms_c_up(struct brcms_c_info *wlc)
  4304. {
  4305. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  4306. /* HW is turned off so don't try to access it */
  4307. if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
  4308. return -ENOMEDIUM;
  4309. if (!wlc->pub->hw_up) {
  4310. brcms_b_hw_up(wlc->hw);
  4311. wlc->pub->hw_up = true;
  4312. }
  4313. if ((wlc->pub->boardflags & BFL_FEM)
  4314. && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
  4315. if (wlc->pub->boardrev >= 0x1250
  4316. && (wlc->pub->boardflags & BFL_FEM_BT))
  4317. brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
  4318. MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
  4319. else
  4320. brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
  4321. MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
  4322. }
  4323. /*
  4324. * Need to read the hwradio status here to cover the case where the
  4325. * system is loaded with the hw radio disabled. We do not want to bring
  4326. * the driver up in this case. If radio is disabled, abort up, lower
  4327. * power, start radio timer and return 0(for NDIS) don't call
  4328. * radio_update to avoid looping brcms_c_up.
  4329. *
  4330. * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
  4331. */
  4332. if (!wlc->pub->radio_disabled) {
  4333. int status = brcms_b_up_prep(wlc->hw);
  4334. if (status == -ENOMEDIUM) {
  4335. if (!mboolisset
  4336. (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
  4337. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  4338. mboolset(wlc->pub->radio_disabled,
  4339. WL_RADIO_HW_DISABLE);
  4340. if (bsscfg->enable && bsscfg->BSS)
  4341. wiphy_err(wlc->wiphy, "wl%d: up"
  4342. ": rfdisable -> "
  4343. "bsscfg_disable()\n",
  4344. wlc->pub->unit);
  4345. }
  4346. }
  4347. }
  4348. if (wlc->pub->radio_disabled) {
  4349. brcms_c_radio_monitor_start(wlc);
  4350. return 0;
  4351. }
  4352. /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
  4353. wlc->clk = true;
  4354. brcms_c_radio_monitor_stop(wlc);
  4355. /* Set EDCF hostflags */
  4356. brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
  4357. brcms_init(wlc->wl);
  4358. wlc->pub->up = true;
  4359. if (wlc->bandinit_pending) {
  4360. brcms_c_suspend_mac_and_wait(wlc);
  4361. brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec);
  4362. wlc->bandinit_pending = false;
  4363. brcms_c_enable_mac(wlc);
  4364. }
  4365. brcms_b_up_finish(wlc->hw);
  4366. /* Program the TX wme params with the current settings */
  4367. brcms_c_wme_retries_write(wlc);
  4368. /* start one second watchdog timer */
  4369. brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
  4370. wlc->WDarmed = true;
  4371. /* ensure antenna config is up to date */
  4372. brcms_c_stf_phy_txant_upd(wlc);
  4373. /* ensure LDPC config is in sync */
  4374. brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
  4375. return 0;
  4376. }
  4377. static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
  4378. {
  4379. uint callbacks = 0;
  4380. return callbacks;
  4381. }
  4382. static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
  4383. {
  4384. bool dev_gone;
  4385. uint callbacks = 0;
  4386. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4387. if (!wlc_hw->up)
  4388. return callbacks;
  4389. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4390. /* disable interrupts */
  4391. if (dev_gone)
  4392. wlc_hw->wlc->macintmask = 0;
  4393. else {
  4394. /* now disable interrupts */
  4395. brcms_intrsoff(wlc_hw->wlc->wl);
  4396. /* ensure we're running on the pll clock again */
  4397. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  4398. }
  4399. /* down phy at the last of this stage */
  4400. callbacks += wlc_phy_down(wlc_hw->band->pi);
  4401. return callbacks;
  4402. }
  4403. static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
  4404. {
  4405. uint callbacks = 0;
  4406. bool dev_gone;
  4407. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4408. if (!wlc_hw->up)
  4409. return callbacks;
  4410. wlc_hw->up = false;
  4411. wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
  4412. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4413. if (dev_gone) {
  4414. wlc_hw->sbclk = false;
  4415. wlc_hw->clk = false;
  4416. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  4417. /* reclaim any posted packets */
  4418. brcms_c_flushqueues(wlc_hw->wlc);
  4419. } else {
  4420. /* Reset and disable the core */
  4421. if (bcma_core_is_enabled(wlc_hw->d11core)) {
  4422. if (bcma_read32(wlc_hw->d11core,
  4423. D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
  4424. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  4425. callbacks += brcms_reset(wlc_hw->wlc->wl);
  4426. brcms_c_coredisable(wlc_hw);
  4427. }
  4428. /* turn off primary xtal and pll */
  4429. if (!wlc_hw->noreset) {
  4430. ai_pci_down(wlc_hw->sih);
  4431. brcms_b_xtal(wlc_hw, OFF);
  4432. }
  4433. }
  4434. return callbacks;
  4435. }
  4436. /*
  4437. * Mark the interface nonoperational, stop the software mechanisms,
  4438. * disable the hardware, free any transient buffer state.
  4439. * Return a count of the number of driver callbacks still pending.
  4440. */
  4441. uint brcms_c_down(struct brcms_c_info *wlc)
  4442. {
  4443. uint callbacks = 0;
  4444. int i;
  4445. bool dev_gone = false;
  4446. struct brcms_txq_info *qi;
  4447. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  4448. /* check if we are already in the going down path */
  4449. if (wlc->going_down) {
  4450. wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
  4451. "\n", wlc->pub->unit, __func__);
  4452. return 0;
  4453. }
  4454. if (!wlc->pub->up)
  4455. return callbacks;
  4456. wlc->going_down = true;
  4457. callbacks += brcms_b_bmac_down_prep(wlc->hw);
  4458. dev_gone = brcms_deviceremoved(wlc);
  4459. /* Call any registered down handlers */
  4460. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4461. if (wlc->modulecb[i].down_fn)
  4462. callbacks +=
  4463. wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
  4464. }
  4465. /* cancel the watchdog timer */
  4466. if (wlc->WDarmed) {
  4467. if (!brcms_del_timer(wlc->wdtimer))
  4468. callbacks++;
  4469. wlc->WDarmed = false;
  4470. }
  4471. /* cancel all other timers */
  4472. callbacks += brcms_c_down_del_timer(wlc);
  4473. wlc->pub->up = false;
  4474. wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
  4475. /* clear txq flow control */
  4476. brcms_c_txflowcontrol_reset(wlc);
  4477. /* flush tx queues */
  4478. for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
  4479. brcmu_pktq_flush(&qi->q, true, NULL, NULL);
  4480. callbacks += brcms_b_down_finish(wlc->hw);
  4481. /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
  4482. wlc->clk = false;
  4483. wlc->going_down = false;
  4484. return callbacks;
  4485. }
  4486. /* Set the current gmode configuration */
  4487. int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
  4488. {
  4489. int ret = 0;
  4490. uint i;
  4491. struct brcms_c_rateset rs;
  4492. /* Default to 54g Auto */
  4493. /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
  4494. s8 shortslot = BRCMS_SHORTSLOT_AUTO;
  4495. bool shortslot_restrict = false; /* Restrict association to stations
  4496. * that support shortslot
  4497. */
  4498. bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
  4499. /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
  4500. int preamble = BRCMS_PLCP_LONG;
  4501. bool preamble_restrict = false; /* Restrict association to stations
  4502. * that support short preambles
  4503. */
  4504. struct brcms_band *band;
  4505. /* if N-support is enabled, allow Gmode set as long as requested
  4506. * Gmode is not GMODE_LEGACY_B
  4507. */
  4508. if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
  4509. return -ENOTSUPP;
  4510. /* verify that we are dealing with 2G band and grab the band pointer */
  4511. if (wlc->band->bandtype == BRCM_BAND_2G)
  4512. band = wlc->band;
  4513. else if ((wlc->pub->_nbands > 1) &&
  4514. (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
  4515. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  4516. else
  4517. return -EINVAL;
  4518. /* Legacy or bust when no OFDM is supported by regulatory */
  4519. if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
  4520. BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B))
  4521. return -EINVAL;
  4522. /* update configuration value */
  4523. if (config == true)
  4524. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
  4525. /* Clear rateset override */
  4526. memset(&rs, 0, sizeof(struct brcms_c_rateset));
  4527. switch (gmode) {
  4528. case GMODE_LEGACY_B:
  4529. shortslot = BRCMS_SHORTSLOT_OFF;
  4530. brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
  4531. break;
  4532. case GMODE_LRS:
  4533. break;
  4534. case GMODE_AUTO:
  4535. /* Accept defaults */
  4536. break;
  4537. case GMODE_ONLY:
  4538. ofdm_basic = true;
  4539. preamble = BRCMS_PLCP_SHORT;
  4540. preamble_restrict = true;
  4541. break;
  4542. case GMODE_PERFORMANCE:
  4543. shortslot = BRCMS_SHORTSLOT_ON;
  4544. shortslot_restrict = true;
  4545. ofdm_basic = true;
  4546. preamble = BRCMS_PLCP_SHORT;
  4547. preamble_restrict = true;
  4548. break;
  4549. default:
  4550. /* Error */
  4551. wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
  4552. wlc->pub->unit, __func__, gmode);
  4553. return -ENOTSUPP;
  4554. }
  4555. band->gmode = gmode;
  4556. wlc->shortslot_override = shortslot;
  4557. /* Use the default 11g rateset */
  4558. if (!rs.count)
  4559. brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
  4560. if (ofdm_basic) {
  4561. for (i = 0; i < rs.count; i++) {
  4562. if (rs.rates[i] == BRCM_RATE_6M
  4563. || rs.rates[i] == BRCM_RATE_12M
  4564. || rs.rates[i] == BRCM_RATE_24M)
  4565. rs.rates[i] |= BRCMS_RATE_FLAG;
  4566. }
  4567. }
  4568. /* Set default bss rateset */
  4569. wlc->default_bss->rateset.count = rs.count;
  4570. memcpy(wlc->default_bss->rateset.rates, rs.rates,
  4571. sizeof(wlc->default_bss->rateset.rates));
  4572. return ret;
  4573. }
  4574. int brcms_c_set_nmode(struct brcms_c_info *wlc)
  4575. {
  4576. uint i;
  4577. s32 nmode = AUTO;
  4578. if (wlc->stf->txstreams == WL_11N_3x3)
  4579. nmode = WL_11N_3x3;
  4580. else
  4581. nmode = WL_11N_2x2;
  4582. /* force GMODE_AUTO if NMODE is ON */
  4583. brcms_c_set_gmode(wlc, GMODE_AUTO, true);
  4584. if (nmode == WL_11N_3x3)
  4585. wlc->pub->_n_enab = SUPPORT_HT;
  4586. else
  4587. wlc->pub->_n_enab = SUPPORT_11N;
  4588. wlc->default_bss->flags |= BRCMS_BSS_HT;
  4589. /* add the mcs rates to the default and hw ratesets */
  4590. brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
  4591. wlc->stf->txstreams);
  4592. for (i = 0; i < wlc->pub->_nbands; i++)
  4593. memcpy(wlc->bandstate[i]->hw_rateset.mcs,
  4594. wlc->default_bss->rateset.mcs, MCSSET_LEN);
  4595. return 0;
  4596. }
  4597. static int
  4598. brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
  4599. struct brcms_c_rateset *rs_arg)
  4600. {
  4601. struct brcms_c_rateset rs, new;
  4602. uint bandunit;
  4603. memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
  4604. /* check for bad count value */
  4605. if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
  4606. return -EINVAL;
  4607. /* try the current band */
  4608. bandunit = wlc->band->bandunit;
  4609. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4610. if (brcms_c_rate_hwrs_filter_sort_validate
  4611. (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
  4612. wlc->stf->txstreams))
  4613. goto good;
  4614. /* try the other band */
  4615. if (brcms_is_mband_unlocked(wlc)) {
  4616. bandunit = OTHERBANDUNIT(wlc);
  4617. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4618. if (brcms_c_rate_hwrs_filter_sort_validate(&new,
  4619. &wlc->
  4620. bandstate[bandunit]->
  4621. hw_rateset, true,
  4622. wlc->stf->txstreams))
  4623. goto good;
  4624. }
  4625. return -EBADE;
  4626. good:
  4627. /* apply new rateset */
  4628. memcpy(&wlc->default_bss->rateset, &new,
  4629. sizeof(struct brcms_c_rateset));
  4630. memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
  4631. sizeof(struct brcms_c_rateset));
  4632. return 0;
  4633. }
  4634. static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
  4635. {
  4636. u8 r;
  4637. bool war = false;
  4638. if (wlc->bsscfg->associated)
  4639. r = wlc->bsscfg->current_bss->rateset.rates[0];
  4640. else
  4641. r = wlc->default_bss->rateset.rates[0];
  4642. wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
  4643. }
  4644. int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
  4645. {
  4646. u16 chspec = ch20mhz_chspec(channel);
  4647. if (channel < 0 || channel > MAXCHANNEL)
  4648. return -EINVAL;
  4649. if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
  4650. return -EINVAL;
  4651. if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
  4652. if (wlc->band->bandunit != chspec_bandunit(chspec))
  4653. wlc->bandinit_pending = true;
  4654. else
  4655. wlc->bandinit_pending = false;
  4656. }
  4657. wlc->default_bss->chanspec = chspec;
  4658. /* brcms_c_BSSinit() will sanitize the rateset before
  4659. * using it.. */
  4660. if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
  4661. brcms_c_set_home_chanspec(wlc, chspec);
  4662. brcms_c_suspend_mac_and_wait(wlc);
  4663. brcms_c_set_chanspec(wlc, chspec);
  4664. brcms_c_enable_mac(wlc);
  4665. }
  4666. return 0;
  4667. }
  4668. int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
  4669. {
  4670. int ac;
  4671. if (srl < 1 || srl > RETRY_SHORT_MAX ||
  4672. lrl < 1 || lrl > RETRY_SHORT_MAX)
  4673. return -EINVAL;
  4674. wlc->SRL = srl;
  4675. wlc->LRL = lrl;
  4676. brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
  4677. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
  4678. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4679. EDCF_SHORT, wlc->SRL);
  4680. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4681. EDCF_LONG, wlc->LRL);
  4682. }
  4683. brcms_c_wme_retries_write(wlc);
  4684. return 0;
  4685. }
  4686. void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
  4687. struct brcm_rateset *currs)
  4688. {
  4689. struct brcms_c_rateset *rs;
  4690. if (wlc->pub->associated)
  4691. rs = &wlc->bsscfg->current_bss->rateset;
  4692. else
  4693. rs = &wlc->default_bss->rateset;
  4694. /* Copy only legacy rateset section */
  4695. currs->count = rs->count;
  4696. memcpy(&currs->rates, &rs->rates, rs->count);
  4697. }
  4698. int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
  4699. {
  4700. struct brcms_c_rateset internal_rs;
  4701. int bcmerror;
  4702. if (rs->count > BRCMS_NUMRATES)
  4703. return -ENOBUFS;
  4704. memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
  4705. /* Copy only legacy rateset section */
  4706. internal_rs.count = rs->count;
  4707. memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
  4708. /* merge rateset coming in with the current mcsset */
  4709. if (wlc->pub->_n_enab & SUPPORT_11N) {
  4710. struct brcms_bss_info *mcsset_bss;
  4711. if (wlc->bsscfg->associated)
  4712. mcsset_bss = wlc->bsscfg->current_bss;
  4713. else
  4714. mcsset_bss = wlc->default_bss;
  4715. memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
  4716. MCSSET_LEN);
  4717. }
  4718. bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
  4719. if (!bcmerror)
  4720. brcms_c_ofdm_rateset_war(wlc);
  4721. return bcmerror;
  4722. }
  4723. int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
  4724. {
  4725. if (period < DOT11_MIN_BEACON_PERIOD ||
  4726. period > DOT11_MAX_BEACON_PERIOD)
  4727. return -EINVAL;
  4728. wlc->default_bss->beacon_period = period;
  4729. return 0;
  4730. }
  4731. u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
  4732. {
  4733. return wlc->band->phytype;
  4734. }
  4735. void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
  4736. {
  4737. wlc->shortslot_override = sslot_override;
  4738. /*
  4739. * shortslot is an 11g feature, so no more work if we are
  4740. * currently on the 5G band
  4741. */
  4742. if (wlc->band->bandtype == BRCM_BAND_5G)
  4743. return;
  4744. if (wlc->pub->up && wlc->pub->associated) {
  4745. /* let watchdog or beacon processing update shortslot */
  4746. } else if (wlc->pub->up) {
  4747. /* unassociated shortslot is off */
  4748. brcms_c_switch_shortslot(wlc, false);
  4749. } else {
  4750. /* driver is down, so just update the brcms_c_info
  4751. * value */
  4752. if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
  4753. wlc->shortslot = false;
  4754. else
  4755. wlc->shortslot =
  4756. (wlc->shortslot_override ==
  4757. BRCMS_SHORTSLOT_ON);
  4758. }
  4759. }
  4760. /*
  4761. * register watchdog and down handlers.
  4762. */
  4763. int brcms_c_module_register(struct brcms_pub *pub,
  4764. const char *name, struct brcms_info *hdl,
  4765. int (*d_fn)(void *handle))
  4766. {
  4767. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4768. int i;
  4769. /* find an empty entry and just add, no duplication check! */
  4770. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4771. if (wlc->modulecb[i].name[0] == '\0') {
  4772. strncpy(wlc->modulecb[i].name, name,
  4773. sizeof(wlc->modulecb[i].name) - 1);
  4774. wlc->modulecb[i].hdl = hdl;
  4775. wlc->modulecb[i].down_fn = d_fn;
  4776. return 0;
  4777. }
  4778. }
  4779. return -ENOSR;
  4780. }
  4781. /* unregister module callbacks */
  4782. int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
  4783. struct brcms_info *hdl)
  4784. {
  4785. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4786. int i;
  4787. if (wlc == NULL)
  4788. return -ENODATA;
  4789. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4790. if (!strcmp(wlc->modulecb[i].name, name) &&
  4791. (wlc->modulecb[i].hdl == hdl)) {
  4792. memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
  4793. return 0;
  4794. }
  4795. }
  4796. /* table not found! */
  4797. return -ENODATA;
  4798. }
  4799. #ifdef BCMDBG
  4800. static const char * const supr_reason[] = {
  4801. "None", "PMQ Entry", "Flush request",
  4802. "Previous frag failure", "Channel mismatch",
  4803. "Lifetime Expiry", "Underflow"
  4804. };
  4805. static void brcms_c_print_txs_status(u16 s)
  4806. {
  4807. printk(KERN_DEBUG "[15:12] %d frame attempts\n",
  4808. (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT);
  4809. printk(KERN_DEBUG " [11:8] %d rts attempts\n",
  4810. (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT);
  4811. printk(KERN_DEBUG " [7] %d PM mode indicated\n",
  4812. ((s & TX_STATUS_PMINDCTD) ? 1 : 0));
  4813. printk(KERN_DEBUG " [6] %d intermediate status\n",
  4814. ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0));
  4815. printk(KERN_DEBUG " [5] %d AMPDU\n",
  4816. (s & TX_STATUS_AMPDU) ? 1 : 0);
  4817. printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n",
  4818. ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT),
  4819. supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]);
  4820. printk(KERN_DEBUG " [1] %d acked\n",
  4821. ((s & TX_STATUS_ACK_RCV) ? 1 : 0));
  4822. }
  4823. #endif /* BCMDBG */
  4824. void brcms_c_print_txstatus(struct tx_status *txs)
  4825. {
  4826. #if defined(BCMDBG)
  4827. u16 s = txs->status;
  4828. u16 ackphyrxsh = txs->ackphyrxsh;
  4829. printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n");
  4830. printk(KERN_DEBUG "FrameID: %04x ", txs->frameid);
  4831. printk(KERN_DEBUG "TxStatus: %04x", s);
  4832. printk(KERN_DEBUG "\n");
  4833. brcms_c_print_txs_status(s);
  4834. printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime);
  4835. printk(KERN_DEBUG "Seq: %04x ", txs->sequence);
  4836. printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr);
  4837. printk(KERN_DEBUG "RxAckRSSI: %04x ",
  4838. (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT);
  4839. printk(KERN_DEBUG "RxAckSQ: %04x",
  4840. (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
  4841. printk(KERN_DEBUG "\n");
  4842. #endif /* defined(BCMDBG) */
  4843. }
  4844. bool brcms_c_chipmatch(u16 vendor, u16 device)
  4845. {
  4846. if (vendor != PCI_VENDOR_ID_BROADCOM) {
  4847. pr_err("chipmatch: unknown vendor id %04x\n", vendor);
  4848. return false;
  4849. }
  4850. if (device == BCM43224_D11N_ID_VEN1)
  4851. return true;
  4852. if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
  4853. return true;
  4854. if (device == BCM4313_D11N2G_ID)
  4855. return true;
  4856. if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
  4857. return true;
  4858. pr_err("chipmatch: unknown device id %04x\n", device);
  4859. return false;
  4860. }
  4861. #if defined(BCMDBG)
  4862. void brcms_c_print_txdesc(struct d11txh *txh)
  4863. {
  4864. u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
  4865. u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
  4866. u16 mfc = le16_to_cpu(txh->MacFrameControl);
  4867. u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
  4868. u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
  4869. u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
  4870. u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
  4871. u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
  4872. u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
  4873. u16 mainrates = le16_to_cpu(txh->MainRates);
  4874. u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
  4875. u8 *iv = txh->IV;
  4876. u8 *ra = txh->TxFrameRA;
  4877. u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
  4878. u8 *rtspfb = txh->RTSPLCPFallback;
  4879. u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
  4880. u8 *fragpfb = txh->FragPLCPFallback;
  4881. u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
  4882. u16 mmodelen = le16_to_cpu(txh->MModeLen);
  4883. u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
  4884. u16 tfid = le16_to_cpu(txh->TxFrameID);
  4885. u16 txs = le16_to_cpu(txh->TxStatus);
  4886. u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
  4887. u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
  4888. u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
  4889. u16 mmbyte = le16_to_cpu(txh->MinMBytes);
  4890. u8 *rtsph = txh->RTSPhyHeader;
  4891. struct ieee80211_rts rts = txh->rts_frame;
  4892. /* add plcp header along with txh descriptor */
  4893. printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
  4894. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  4895. txh, sizeof(struct d11txh) + 48);
  4896. printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
  4897. printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
  4898. printk(KERN_DEBUG "FC: %04x ", mfc);
  4899. printk(KERN_DEBUG "FES Time: %04x\n", tfest);
  4900. printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw,
  4901. (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
  4902. printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1);
  4903. printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
  4904. printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
  4905. printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
  4906. printk(KERN_DEBUG "MainRates: %04x ", mainrates);
  4907. printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
  4908. printk(KERN_DEBUG "\n");
  4909. print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
  4910. print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
  4911. ra, sizeof(txh->TxFrameRA));
  4912. printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
  4913. print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
  4914. rtspfb, sizeof(txh->RTSPLCPFallback));
  4915. printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
  4916. print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
  4917. fragpfb, sizeof(txh->FragPLCPFallback));
  4918. printk(KERN_DEBUG "DUR: %04x", fragdfb);
  4919. printk(KERN_DEBUG "\n");
  4920. printk(KERN_DEBUG "MModeLen: %04x ", mmodelen);
  4921. printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen);
  4922. printk(KERN_DEBUG "FrameID: %04x\n", tfid);
  4923. printk(KERN_DEBUG "TxStatus: %04x\n", txs);
  4924. printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu);
  4925. printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte);
  4926. printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
  4927. printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
  4928. print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
  4929. rtsph, sizeof(txh->RTSPhyHeader));
  4930. print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
  4931. (u8 *)&rts, sizeof(txh->rts_frame));
  4932. printk(KERN_DEBUG "\n");
  4933. }
  4934. #endif /* defined(BCMDBG) */
  4935. #if defined(BCMDBG)
  4936. static int
  4937. brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
  4938. int len)
  4939. {
  4940. int i;
  4941. char *p = buf;
  4942. char hexstr[16];
  4943. int slen = 0, nlen = 0;
  4944. u32 bit;
  4945. const char *name;
  4946. if (len < 2 || !buf)
  4947. return 0;
  4948. buf[0] = '\0';
  4949. for (i = 0; flags != 0; i++) {
  4950. bit = bd[i].bit;
  4951. name = bd[i].name;
  4952. if (bit == 0 && flags != 0) {
  4953. /* print any unnamed bits */
  4954. snprintf(hexstr, 16, "0x%X", flags);
  4955. name = hexstr;
  4956. flags = 0; /* exit loop */
  4957. } else if ((flags & bit) == 0)
  4958. continue;
  4959. flags &= ~bit;
  4960. nlen = strlen(name);
  4961. slen += nlen;
  4962. /* count btwn flag space */
  4963. if (flags != 0)
  4964. slen += 1;
  4965. /* need NULL char as well */
  4966. if (len <= slen)
  4967. break;
  4968. /* copy NULL char but don't count it */
  4969. strncpy(p, name, nlen + 1);
  4970. p += nlen;
  4971. /* copy btwn flag space and NULL char */
  4972. if (flags != 0)
  4973. p += snprintf(p, 2, " ");
  4974. len -= slen;
  4975. }
  4976. /* indicate the str was too short */
  4977. if (flags != 0) {
  4978. if (len < 2)
  4979. p -= 2 - len; /* overwrite last char */
  4980. p += snprintf(p, 2, ">");
  4981. }
  4982. return (int)(p - buf);
  4983. }
  4984. #endif /* defined(BCMDBG) */
  4985. #if defined(BCMDBG)
  4986. void brcms_c_print_rxh(struct d11rxhdr *rxh)
  4987. {
  4988. u16 len = rxh->RxFrameSize;
  4989. u16 phystatus_0 = rxh->PhyRxStatus_0;
  4990. u16 phystatus_1 = rxh->PhyRxStatus_1;
  4991. u16 phystatus_2 = rxh->PhyRxStatus_2;
  4992. u16 phystatus_3 = rxh->PhyRxStatus_3;
  4993. u16 macstatus1 = rxh->RxStatus1;
  4994. u16 macstatus2 = rxh->RxStatus2;
  4995. char flagstr[64];
  4996. char lenbuf[20];
  4997. static const struct brcms_c_bit_desc macstat_flags[] = {
  4998. {RXS_FCSERR, "FCSErr"},
  4999. {RXS_RESPFRAMETX, "Reply"},
  5000. {RXS_PBPRES, "PADDING"},
  5001. {RXS_DECATMPT, "DeCr"},
  5002. {RXS_DECERR, "DeCrErr"},
  5003. {RXS_BCNSENT, "Bcn"},
  5004. {0, NULL}
  5005. };
  5006. printk(KERN_DEBUG "Raw RxDesc:\n");
  5007. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh,
  5008. sizeof(struct d11rxhdr));
  5009. brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
  5010. snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
  5011. printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len,
  5012. (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
  5013. printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n",
  5014. phystatus_0, phystatus_1, phystatus_2, phystatus_3);
  5015. printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr);
  5016. printk(KERN_DEBUG "RXMACaggtype: %x\n",
  5017. (macstatus2 & RXS_AGGTYPE_MASK));
  5018. printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime);
  5019. }
  5020. #endif /* defined(BCMDBG) */
  5021. u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
  5022. {
  5023. u16 table_ptr;
  5024. u8 phy_rate, index;
  5025. /* get the phy specific rate encoding for the PLCP SIGNAL field */
  5026. if (is_ofdm_rate(rate))
  5027. table_ptr = M_RT_DIRMAP_A;
  5028. else
  5029. table_ptr = M_RT_DIRMAP_B;
  5030. /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
  5031. * the index into the rate table.
  5032. */
  5033. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  5034. index = phy_rate & 0xf;
  5035. /* Find the SHM pointer to the rate table entry by looking in the
  5036. * Direct-map Table
  5037. */
  5038. return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
  5039. }
  5040. static bool
  5041. brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
  5042. struct sk_buff *pkt, int prec, bool head)
  5043. {
  5044. struct sk_buff *p;
  5045. int eprec = -1; /* precedence to evict from */
  5046. /* Determine precedence from which to evict packet, if any */
  5047. if (pktq_pfull(q, prec))
  5048. eprec = prec;
  5049. else if (pktq_full(q)) {
  5050. p = brcmu_pktq_peek_tail(q, &eprec);
  5051. if (eprec > prec) {
  5052. wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
  5053. "\n", __func__, eprec, prec);
  5054. return false;
  5055. }
  5056. }
  5057. /* Evict if needed */
  5058. if (eprec >= 0) {
  5059. bool discard_oldest;
  5060. discard_oldest = ac_bitmap_tst(0, eprec);
  5061. /* Refuse newer packet unless configured to discard oldest */
  5062. if (eprec == prec && !discard_oldest) {
  5063. wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
  5064. "\n", __func__, prec);
  5065. return false;
  5066. }
  5067. /* Evict packet according to discard policy */
  5068. p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
  5069. brcmu_pktq_pdeq_tail(q, eprec);
  5070. brcmu_pkt_buf_free_skb(p);
  5071. }
  5072. /* Enqueue */
  5073. if (head)
  5074. p = brcmu_pktq_penq_head(q, prec, pkt);
  5075. else
  5076. p = brcmu_pktq_penq(q, prec, pkt);
  5077. return true;
  5078. }
  5079. /*
  5080. * Attempts to queue a packet onto a multiple-precedence queue,
  5081. * if necessary evicting a lower precedence packet from the queue.
  5082. *
  5083. * 'prec' is the precedence number that has already been mapped
  5084. * from the packet priority.
  5085. *
  5086. * Returns true if packet consumed (queued), false if not.
  5087. */
  5088. static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
  5089. struct sk_buff *pkt, int prec)
  5090. {
  5091. return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
  5092. }
  5093. void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
  5094. struct sk_buff *sdu, uint prec)
  5095. {
  5096. struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */
  5097. struct pktq *q = &qi->q;
  5098. int prio;
  5099. prio = sdu->priority;
  5100. if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
  5101. /*
  5102. * we might hit this condtion in case
  5103. * packet flooding from mac80211 stack
  5104. */
  5105. brcmu_pkt_buf_free_skb(sdu);
  5106. }
  5107. }
  5108. /*
  5109. * bcmc_fid_generate:
  5110. * Generate frame ID for a BCMC packet. The frag field is not used
  5111. * for MC frames so is used as part of the sequence number.
  5112. */
  5113. static inline u16
  5114. bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
  5115. struct d11txh *txh)
  5116. {
  5117. u16 frameid;
  5118. frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
  5119. TXFID_QUEUE_MASK);
  5120. frameid |=
  5121. (((wlc->
  5122. mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  5123. TX_BCMC_FIFO;
  5124. return frameid;
  5125. }
  5126. static uint
  5127. brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
  5128. u8 preamble_type)
  5129. {
  5130. uint dur = 0;
  5131. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
  5132. wlc->pub->unit, rspec, preamble_type);
  5133. /*
  5134. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  5135. * is less than or equal to the rate of the immediately previous
  5136. * frame in the FES
  5137. */
  5138. rspec = brcms_basic_rate(wlc, rspec);
  5139. /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
  5140. dur =
  5141. brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  5142. (DOT11_ACK_LEN + FCS_LEN));
  5143. return dur;
  5144. }
  5145. static uint
  5146. brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
  5147. u8 preamble_type)
  5148. {
  5149. BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
  5150. wlc->pub->unit, rspec, preamble_type);
  5151. return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
  5152. }
  5153. static uint
  5154. brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
  5155. u8 preamble_type)
  5156. {
  5157. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
  5158. "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
  5159. /*
  5160. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  5161. * is less than or equal to the rate of the immediately previous
  5162. * frame in the FES
  5163. */
  5164. rspec = brcms_basic_rate(wlc, rspec);
  5165. /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
  5166. return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  5167. (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
  5168. FCS_LEN));
  5169. }
  5170. /* brcms_c_compute_frame_dur()
  5171. *
  5172. * Calculate the 802.11 MAC header DUR field for MPDU
  5173. * DUR for a single frame = 1 SIFS + 1 ACK
  5174. * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
  5175. *
  5176. * rate MPDU rate in unit of 500kbps
  5177. * next_frag_len next MPDU length in bytes
  5178. * preamble_type use short/GF or long/MM PLCP header
  5179. */
  5180. static u16
  5181. brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
  5182. u8 preamble_type, uint next_frag_len)
  5183. {
  5184. u16 dur, sifs;
  5185. sifs = get_sifs(wlc->band);
  5186. dur = sifs;
  5187. dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
  5188. if (next_frag_len) {
  5189. /* Double the current DUR to get 2 SIFS + 2 ACKs */
  5190. dur *= 2;
  5191. /* add another SIFS and the frag time */
  5192. dur += sifs;
  5193. dur +=
  5194. (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
  5195. next_frag_len);
  5196. }
  5197. return dur;
  5198. }
  5199. /* The opposite of brcms_c_calc_frame_time */
  5200. static uint
  5201. brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
  5202. u8 preamble_type, uint dur)
  5203. {
  5204. uint nsyms, mac_len, Ndps, kNdps;
  5205. uint rate = rspec2rate(ratespec);
  5206. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
  5207. wlc->pub->unit, ratespec, preamble_type, dur);
  5208. if (is_mcs_rate(ratespec)) {
  5209. uint mcs = ratespec & RSPEC_RATE_MASK;
  5210. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  5211. dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  5212. /* payload calculation matches that of regular ofdm */
  5213. if (wlc->band->bandtype == BRCM_BAND_2G)
  5214. dur -= DOT11_OFDM_SIGNAL_EXTENSION;
  5215. /* kNdbps = kbps * 4 */
  5216. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  5217. rspec_issgi(ratespec)) * 4;
  5218. nsyms = dur / APHY_SYMBOL_TIME;
  5219. mac_len =
  5220. ((nsyms * kNdps) -
  5221. ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
  5222. } else if (is_ofdm_rate(ratespec)) {
  5223. dur -= APHY_PREAMBLE_TIME;
  5224. dur -= APHY_SIGNAL_TIME;
  5225. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  5226. Ndps = rate * 2;
  5227. nsyms = dur / APHY_SYMBOL_TIME;
  5228. mac_len =
  5229. ((nsyms * Ndps) -
  5230. (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
  5231. } else {
  5232. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  5233. dur -= BPHY_PLCP_SHORT_TIME;
  5234. else
  5235. dur -= BPHY_PLCP_TIME;
  5236. mac_len = dur * rate;
  5237. /* divide out factor of 2 in rate (1/2 mbps) */
  5238. mac_len = mac_len / 8 / 2;
  5239. }
  5240. return mac_len;
  5241. }
  5242. /*
  5243. * Return true if the specified rate is supported by the specified band.
  5244. * BRCM_BAND_AUTO indicates the current band.
  5245. */
  5246. static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
  5247. bool verbose)
  5248. {
  5249. struct brcms_c_rateset *hw_rateset;
  5250. uint i;
  5251. if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
  5252. hw_rateset = &wlc->band->hw_rateset;
  5253. else if (wlc->pub->_nbands > 1)
  5254. hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
  5255. else
  5256. /* other band specified and we are a single band device */
  5257. return false;
  5258. /* check if this is a mimo rate */
  5259. if (is_mcs_rate(rspec)) {
  5260. if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
  5261. goto error;
  5262. return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
  5263. }
  5264. for (i = 0; i < hw_rateset->count; i++)
  5265. if (hw_rateset->rates[i] == rspec2rate(rspec))
  5266. return true;
  5267. error:
  5268. if (verbose)
  5269. wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
  5270. "not in hw_rateset\n", wlc->pub->unit, rspec);
  5271. return false;
  5272. }
  5273. static u32
  5274. mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
  5275. u32 int_val)
  5276. {
  5277. u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
  5278. u8 rate = int_val & NRATE_RATE_MASK;
  5279. u32 rspec;
  5280. bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
  5281. bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
  5282. bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
  5283. == NRATE_OVERRIDE_MCS_ONLY);
  5284. int bcmerror = 0;
  5285. if (!ismcs)
  5286. return (u32) rate;
  5287. /* validate the combination of rate/mcs/stf is allowed */
  5288. if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
  5289. /* mcs only allowed when nmode */
  5290. if (stf > PHY_TXC1_MODE_SDM) {
  5291. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
  5292. wlc->pub->unit, __func__);
  5293. bcmerror = -EINVAL;
  5294. goto done;
  5295. }
  5296. /* mcs 32 is a special case, DUP mode 40 only */
  5297. if (rate == 32) {
  5298. if (!CHSPEC_IS40(wlc->home_chanspec) ||
  5299. ((stf != PHY_TXC1_MODE_SISO)
  5300. && (stf != PHY_TXC1_MODE_CDD))) {
  5301. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
  5302. "32\n", wlc->pub->unit, __func__);
  5303. bcmerror = -EINVAL;
  5304. goto done;
  5305. }
  5306. /* mcs > 7 must use stf SDM */
  5307. } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
  5308. /* mcs > 7 must use stf SDM */
  5309. if (stf != PHY_TXC1_MODE_SDM) {
  5310. BCMMSG(wlc->wiphy, "wl%d: enabling "
  5311. "SDM mode for mcs %d\n",
  5312. wlc->pub->unit, rate);
  5313. stf = PHY_TXC1_MODE_SDM;
  5314. }
  5315. } else {
  5316. /*
  5317. * MCS 0-7 may use SISO, CDD, and for
  5318. * phy_rev >= 3 STBC
  5319. */
  5320. if ((stf > PHY_TXC1_MODE_STBC) ||
  5321. (!BRCMS_STBC_CAP_PHY(wlc)
  5322. && (stf == PHY_TXC1_MODE_STBC))) {
  5323. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
  5324. "\n", wlc->pub->unit, __func__);
  5325. bcmerror = -EINVAL;
  5326. goto done;
  5327. }
  5328. }
  5329. } else if (is_ofdm_rate(rate)) {
  5330. if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
  5331. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
  5332. wlc->pub->unit, __func__);
  5333. bcmerror = -EINVAL;
  5334. goto done;
  5335. }
  5336. } else if (is_cck_rate(rate)) {
  5337. if ((cur_band->bandtype != BRCM_BAND_2G)
  5338. || (stf != PHY_TXC1_MODE_SISO)) {
  5339. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
  5340. wlc->pub->unit, __func__);
  5341. bcmerror = -EINVAL;
  5342. goto done;
  5343. }
  5344. } else {
  5345. wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
  5346. wlc->pub->unit, __func__);
  5347. bcmerror = -EINVAL;
  5348. goto done;
  5349. }
  5350. /* make sure multiple antennae are available for non-siso rates */
  5351. if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
  5352. wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
  5353. "request\n", wlc->pub->unit, __func__);
  5354. bcmerror = -EINVAL;
  5355. goto done;
  5356. }
  5357. rspec = rate;
  5358. if (ismcs) {
  5359. rspec |= RSPEC_MIMORATE;
  5360. /* For STBC populate the STC field of the ratespec */
  5361. if (stf == PHY_TXC1_MODE_STBC) {
  5362. u8 stc;
  5363. stc = 1; /* Nss for single stream is always 1 */
  5364. rspec |= (stc << RSPEC_STC_SHIFT);
  5365. }
  5366. }
  5367. rspec |= (stf << RSPEC_STF_SHIFT);
  5368. if (override_mcs_only)
  5369. rspec |= RSPEC_OVERRIDE_MCS_ONLY;
  5370. if (issgi)
  5371. rspec |= RSPEC_SHORT_GI;
  5372. if ((rate != 0)
  5373. && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
  5374. return rate;
  5375. return rspec;
  5376. done:
  5377. return rate;
  5378. }
  5379. /*
  5380. * Compute PLCP, but only requires actual rate and length of pkt.
  5381. * Rate is given in the driver standard multiple of 500 kbps.
  5382. * le is set for 11 Mbps rate if necessary.
  5383. * Broken out for PRQ.
  5384. */
  5385. static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
  5386. uint length, u8 *plcp)
  5387. {
  5388. u16 usec = 0;
  5389. u8 le = 0;
  5390. switch (rate_500) {
  5391. case BRCM_RATE_1M:
  5392. usec = length << 3;
  5393. break;
  5394. case BRCM_RATE_2M:
  5395. usec = length << 2;
  5396. break;
  5397. case BRCM_RATE_5M5:
  5398. usec = (length << 4) / 11;
  5399. if ((length << 4) - (usec * 11) > 0)
  5400. usec++;
  5401. break;
  5402. case BRCM_RATE_11M:
  5403. usec = (length << 3) / 11;
  5404. if ((length << 3) - (usec * 11) > 0) {
  5405. usec++;
  5406. if ((usec * 11) - (length << 3) >= 8)
  5407. le = D11B_PLCP_SIGNAL_LE;
  5408. }
  5409. break;
  5410. default:
  5411. wiphy_err(wlc->wiphy,
  5412. "brcms_c_cck_plcp_set: unsupported rate %d\n",
  5413. rate_500);
  5414. rate_500 = BRCM_RATE_1M;
  5415. usec = length << 3;
  5416. break;
  5417. }
  5418. /* PLCP signal byte */
  5419. plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
  5420. /* PLCP service byte */
  5421. plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
  5422. /* PLCP length u16, little endian */
  5423. plcp[2] = usec & 0xff;
  5424. plcp[3] = (usec >> 8) & 0xff;
  5425. /* PLCP CRC16 */
  5426. plcp[4] = 0;
  5427. plcp[5] = 0;
  5428. }
  5429. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5430. static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
  5431. {
  5432. u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
  5433. plcp[0] = mcs;
  5434. if (rspec_is40mhz(rspec) || (mcs == 32))
  5435. plcp[0] |= MIMO_PLCP_40MHZ;
  5436. BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
  5437. plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
  5438. plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
  5439. plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
  5440. plcp[5] = 0;
  5441. }
  5442. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5443. static void
  5444. brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
  5445. {
  5446. u8 rate_signal;
  5447. u32 tmp = 0;
  5448. int rate = rspec2rate(rspec);
  5449. /*
  5450. * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
  5451. * transmitted first
  5452. */
  5453. rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
  5454. memset(plcp, 0, D11_PHY_HDR_LEN);
  5455. D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
  5456. tmp = (length & 0xfff) << 5;
  5457. plcp[2] |= (tmp >> 16) & 0xff;
  5458. plcp[1] |= (tmp >> 8) & 0xff;
  5459. plcp[0] |= tmp & 0xff;
  5460. }
  5461. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5462. static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
  5463. uint length, u8 *plcp)
  5464. {
  5465. int rate = rspec2rate(rspec);
  5466. brcms_c_cck_plcp_set(wlc, rate, length, plcp);
  5467. }
  5468. static void
  5469. brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
  5470. uint length, u8 *plcp)
  5471. {
  5472. if (is_mcs_rate(rspec))
  5473. brcms_c_compute_mimo_plcp(rspec, length, plcp);
  5474. else if (is_ofdm_rate(rspec))
  5475. brcms_c_compute_ofdm_plcp(rspec, length, plcp);
  5476. else
  5477. brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
  5478. }
  5479. /* brcms_c_compute_rtscts_dur()
  5480. *
  5481. * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
  5482. * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
  5483. * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
  5484. *
  5485. * cts cts-to-self or rts/cts
  5486. * rts_rate rts or cts rate in unit of 500kbps
  5487. * rate next MPDU rate in unit of 500kbps
  5488. * frame_len next MPDU frame length in bytes
  5489. */
  5490. u16
  5491. brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
  5492. u32 rts_rate,
  5493. u32 frame_rate, u8 rts_preamble_type,
  5494. u8 frame_preamble_type, uint frame_len, bool ba)
  5495. {
  5496. u16 dur, sifs;
  5497. sifs = get_sifs(wlc->band);
  5498. if (!cts_only) {
  5499. /* RTS/CTS */
  5500. dur = 3 * sifs;
  5501. dur +=
  5502. (u16) brcms_c_calc_cts_time(wlc, rts_rate,
  5503. rts_preamble_type);
  5504. } else {
  5505. /* CTS-TO-SELF */
  5506. dur = 2 * sifs;
  5507. }
  5508. dur +=
  5509. (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
  5510. frame_len);
  5511. if (ba)
  5512. dur +=
  5513. (u16) brcms_c_calc_ba_time(wlc, frame_rate,
  5514. BRCMS_SHORT_PREAMBLE);
  5515. else
  5516. dur +=
  5517. (u16) brcms_c_calc_ack_time(wlc, frame_rate,
  5518. frame_preamble_type);
  5519. return dur;
  5520. }
  5521. static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
  5522. {
  5523. u16 phyctl1 = 0;
  5524. u16 bw;
  5525. if (BRCMS_ISLCNPHY(wlc->band)) {
  5526. bw = PHY_TXC1_BW_20MHZ;
  5527. } else {
  5528. bw = rspec_get_bw(rspec);
  5529. /* 10Mhz is not supported yet */
  5530. if (bw < PHY_TXC1_BW_20MHZ) {
  5531. wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
  5532. "not supported yet, set to 20L\n", bw);
  5533. bw = PHY_TXC1_BW_20MHZ;
  5534. }
  5535. }
  5536. if (is_mcs_rate(rspec)) {
  5537. uint mcs = rspec & RSPEC_RATE_MASK;
  5538. /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
  5539. phyctl1 = rspec_phytxbyte2(rspec);
  5540. /* set the upper byte of phyctl1 */
  5541. phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
  5542. } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
  5543. && !BRCMS_ISSSLPNPHY(wlc->band)) {
  5544. /*
  5545. * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
  5546. * Data Rate. Eventually MIMOPHY would also be converted to
  5547. * this format
  5548. */
  5549. /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
  5550. phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5551. } else { /* legacy OFDM/CCK */
  5552. s16 phycfg;
  5553. /* get the phyctl byte from rate phycfg table */
  5554. phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
  5555. if (phycfg == -1) {
  5556. wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
  5557. "legacy OFDM/CCK rate\n");
  5558. phycfg = 0;
  5559. }
  5560. /* set the upper byte of phyctl1 */
  5561. phyctl1 =
  5562. (bw | (phycfg << 8) |
  5563. (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5564. }
  5565. return phyctl1;
  5566. }
  5567. /*
  5568. * Add struct d11txh, struct cck_phy_hdr.
  5569. *
  5570. * 'p' data must start with 802.11 MAC header
  5571. * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
  5572. *
  5573. * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
  5574. *
  5575. */
  5576. static u16
  5577. brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
  5578. struct sk_buff *p, struct scb *scb, uint frag,
  5579. uint nfrags, uint queue, uint next_frag_len)
  5580. {
  5581. struct ieee80211_hdr *h;
  5582. struct d11txh *txh;
  5583. u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
  5584. int len, phylen, rts_phylen;
  5585. u16 mch, phyctl, xfts, mainrates;
  5586. u16 seq = 0, mcl = 0, status = 0, frameid = 0;
  5587. u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5588. u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5589. bool use_rts = false;
  5590. bool use_cts = false;
  5591. bool use_rifs = false;
  5592. bool short_preamble[2] = { false, false };
  5593. u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5594. u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5595. u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
  5596. struct ieee80211_rts *rts = NULL;
  5597. bool qos;
  5598. uint ac;
  5599. bool hwtkmic = false;
  5600. u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
  5601. #define ANTCFG_NONE 0xFF
  5602. u8 antcfg = ANTCFG_NONE;
  5603. u8 fbantcfg = ANTCFG_NONE;
  5604. uint phyctl1_stf = 0;
  5605. u16 durid = 0;
  5606. struct ieee80211_tx_rate *txrate[2];
  5607. int k;
  5608. struct ieee80211_tx_info *tx_info;
  5609. bool is_mcs;
  5610. u16 mimo_txbw;
  5611. u8 mimo_preamble_type;
  5612. /* locate 802.11 MAC header */
  5613. h = (struct ieee80211_hdr *)(p->data);
  5614. qos = ieee80211_is_data_qos(h->frame_control);
  5615. /* compute length of frame in bytes for use in PLCP computations */
  5616. len = p->len;
  5617. phylen = len + FCS_LEN;
  5618. /* Get tx_info */
  5619. tx_info = IEEE80211_SKB_CB(p);
  5620. /* add PLCP */
  5621. plcp = skb_push(p, D11_PHY_HDR_LEN);
  5622. /* add Broadcom tx descriptor header */
  5623. txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
  5624. memset(txh, 0, D11_TXH_LEN);
  5625. /* setup frameid */
  5626. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  5627. /* non-AP STA should never use BCMC queue */
  5628. if (queue == TX_BCMC_FIFO) {
  5629. wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
  5630. "TX_BCMC!\n", wlc->pub->unit, __func__);
  5631. frameid = bcmc_fid_generate(wlc, NULL, txh);
  5632. } else {
  5633. /* Increment the counter for first fragment */
  5634. if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  5635. scb->seqnum[p->priority]++;
  5636. /* extract fragment number from frame first */
  5637. seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
  5638. seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
  5639. h->seq_ctrl = cpu_to_le16(seq);
  5640. frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  5641. (queue & TXFID_QUEUE_MASK);
  5642. }
  5643. }
  5644. frameid |= queue & TXFID_QUEUE_MASK;
  5645. /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
  5646. if (ieee80211_is_beacon(h->frame_control))
  5647. mcl |= TXC_IGNOREPMQ;
  5648. txrate[0] = tx_info->control.rates;
  5649. txrate[1] = txrate[0] + 1;
  5650. /*
  5651. * if rate control algorithm didn't give us a fallback
  5652. * rate, use the primary rate
  5653. */
  5654. if (txrate[1]->idx < 0)
  5655. txrate[1] = txrate[0];
  5656. for (k = 0; k < hw->max_rates; k++) {
  5657. is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
  5658. if (!is_mcs) {
  5659. if ((txrate[k]->idx >= 0)
  5660. && (txrate[k]->idx <
  5661. hw->wiphy->bands[tx_info->band]->n_bitrates)) {
  5662. rspec[k] =
  5663. hw->wiphy->bands[tx_info->band]->
  5664. bitrates[txrate[k]->idx].hw_value;
  5665. short_preamble[k] =
  5666. txrate[k]->
  5667. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
  5668. true : false;
  5669. } else {
  5670. rspec[k] = BRCM_RATE_1M;
  5671. }
  5672. } else {
  5673. rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
  5674. NRATE_MCS_INUSE | txrate[k]->idx);
  5675. }
  5676. /*
  5677. * Currently only support same setting for primay and
  5678. * fallback rates. Unify flags for each rate into a
  5679. * single value for the frame
  5680. */
  5681. use_rts |=
  5682. txrate[k]->
  5683. flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
  5684. use_cts |=
  5685. txrate[k]->
  5686. flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
  5687. /*
  5688. * (1) RATE:
  5689. * determine and validate primary rate
  5690. * and fallback rates
  5691. */
  5692. if (!rspec_active(rspec[k])) {
  5693. rspec[k] = BRCM_RATE_1M;
  5694. } else {
  5695. if (!is_multicast_ether_addr(h->addr1)) {
  5696. /* set tx antenna config */
  5697. brcms_c_antsel_antcfg_get(wlc->asi, false,
  5698. false, 0, 0, &antcfg, &fbantcfg);
  5699. }
  5700. }
  5701. }
  5702. phyctl1_stf = wlc->stf->ss_opmode;
  5703. if (wlc->pub->_n_enab & SUPPORT_11N) {
  5704. for (k = 0; k < hw->max_rates; k++) {
  5705. /*
  5706. * apply siso/cdd to single stream mcs's or ofdm
  5707. * if rspec is auto selected
  5708. */
  5709. if (((is_mcs_rate(rspec[k]) &&
  5710. is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
  5711. is_ofdm_rate(rspec[k]))
  5712. && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
  5713. || !(rspec[k] & RSPEC_OVERRIDE))) {
  5714. rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
  5715. /* For SISO MCS use STBC if possible */
  5716. if (is_mcs_rate(rspec[k])
  5717. && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
  5718. u8 stc;
  5719. /* Nss for single stream is always 1 */
  5720. stc = 1;
  5721. rspec[k] |= (PHY_TXC1_MODE_STBC <<
  5722. RSPEC_STF_SHIFT) |
  5723. (stc << RSPEC_STC_SHIFT);
  5724. } else
  5725. rspec[k] |=
  5726. (phyctl1_stf << RSPEC_STF_SHIFT);
  5727. }
  5728. /*
  5729. * Is the phy configured to use 40MHZ frames? If
  5730. * so then pick the desired txbw
  5731. */
  5732. if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
  5733. /* default txbw is 20in40 SB */
  5734. mimo_ctlchbw = mimo_txbw =
  5735. CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
  5736. wlc->band->pi))
  5737. ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
  5738. if (is_mcs_rate(rspec[k])) {
  5739. /* mcs 32 must be 40b/w DUP */
  5740. if ((rspec[k] & RSPEC_RATE_MASK)
  5741. == 32) {
  5742. mimo_txbw =
  5743. PHY_TXC1_BW_40MHZ_DUP;
  5744. /* use override */
  5745. } else if (wlc->mimo_40txbw != AUTO)
  5746. mimo_txbw = wlc->mimo_40txbw;
  5747. /* else check if dst is using 40 Mhz */
  5748. else if (scb->flags & SCB_IS40)
  5749. mimo_txbw = PHY_TXC1_BW_40MHZ;
  5750. } else if (is_ofdm_rate(rspec[k])) {
  5751. if (wlc->ofdm_40txbw != AUTO)
  5752. mimo_txbw = wlc->ofdm_40txbw;
  5753. } else if (wlc->cck_40txbw != AUTO) {
  5754. mimo_txbw = wlc->cck_40txbw;
  5755. }
  5756. } else {
  5757. /*
  5758. * mcs32 is 40 b/w only.
  5759. * This is possible for probe packets on
  5760. * a STA during SCAN
  5761. */
  5762. if ((rspec[k] & RSPEC_RATE_MASK) == 32)
  5763. /* mcs 0 */
  5764. rspec[k] = RSPEC_MIMORATE;
  5765. mimo_txbw = PHY_TXC1_BW_20MHZ;
  5766. }
  5767. /* Set channel width */
  5768. rspec[k] &= ~RSPEC_BW_MASK;
  5769. if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
  5770. rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
  5771. else
  5772. rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  5773. /* Disable short GI, not supported yet */
  5774. rspec[k] &= ~RSPEC_SHORT_GI;
  5775. mimo_preamble_type = BRCMS_MM_PREAMBLE;
  5776. if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
  5777. mimo_preamble_type = BRCMS_GF_PREAMBLE;
  5778. if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
  5779. && (!is_mcs_rate(rspec[k]))) {
  5780. wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
  5781. "RC_MCS != is_mcs_rate(rspec)\n",
  5782. wlc->pub->unit, __func__);
  5783. }
  5784. if (is_mcs_rate(rspec[k])) {
  5785. preamble_type[k] = mimo_preamble_type;
  5786. /*
  5787. * if SGI is selected, then forced mm
  5788. * for single stream
  5789. */
  5790. if ((rspec[k] & RSPEC_SHORT_GI)
  5791. && is_single_stream(rspec[k] &
  5792. RSPEC_RATE_MASK))
  5793. preamble_type[k] = BRCMS_MM_PREAMBLE;
  5794. }
  5795. /* should be better conditionalized */
  5796. if (!is_mcs_rate(rspec[0])
  5797. && (tx_info->control.rates[0].
  5798. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
  5799. preamble_type[k] = BRCMS_SHORT_PREAMBLE;
  5800. }
  5801. } else {
  5802. for (k = 0; k < hw->max_rates; k++) {
  5803. /* Set ctrlchbw as 20Mhz */
  5804. rspec[k] &= ~RSPEC_BW_MASK;
  5805. rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
  5806. /* for nphy, stf of ofdm frames must follow policies */
  5807. if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
  5808. rspec[k] &= ~RSPEC_STF_MASK;
  5809. rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
  5810. }
  5811. }
  5812. }
  5813. /* Reset these for use with AMPDU's */
  5814. txrate[0]->count = 0;
  5815. txrate[1]->count = 0;
  5816. /* (2) PROTECTION, may change rspec */
  5817. if ((ieee80211_is_data(h->frame_control) ||
  5818. ieee80211_is_mgmt(h->frame_control)) &&
  5819. (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
  5820. use_rts = true;
  5821. /* (3) PLCP: determine PLCP header and MAC duration,
  5822. * fill struct d11txh */
  5823. brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
  5824. brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
  5825. memcpy(&txh->FragPLCPFallback,
  5826. plcp_fallback, sizeof(txh->FragPLCPFallback));
  5827. /* Length field now put in CCK FBR CRC field */
  5828. if (is_cck_rate(rspec[1])) {
  5829. txh->FragPLCPFallback[4] = phylen & 0xff;
  5830. txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
  5831. }
  5832. /* MIMO-RATE: need validation ?? */
  5833. mainrates = is_ofdm_rate(rspec[0]) ?
  5834. D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
  5835. plcp[0];
  5836. /* DUR field for main rate */
  5837. if (!ieee80211_is_pspoll(h->frame_control) &&
  5838. !is_multicast_ether_addr(h->addr1) && !use_rifs) {
  5839. durid =
  5840. brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
  5841. next_frag_len);
  5842. h->duration_id = cpu_to_le16(durid);
  5843. } else if (use_rifs) {
  5844. /* NAV protect to end of next max packet size */
  5845. durid =
  5846. (u16) brcms_c_calc_frame_time(wlc, rspec[0],
  5847. preamble_type[0],
  5848. DOT11_MAX_FRAG_LEN);
  5849. durid += RIFS_11N_TIME;
  5850. h->duration_id = cpu_to_le16(durid);
  5851. }
  5852. /* DUR field for fallback rate */
  5853. if (ieee80211_is_pspoll(h->frame_control))
  5854. txh->FragDurFallback = h->duration_id;
  5855. else if (is_multicast_ether_addr(h->addr1) || use_rifs)
  5856. txh->FragDurFallback = 0;
  5857. else {
  5858. durid = brcms_c_compute_frame_dur(wlc, rspec[1],
  5859. preamble_type[1], next_frag_len);
  5860. txh->FragDurFallback = cpu_to_le16(durid);
  5861. }
  5862. /* (4) MAC-HDR: MacTxControlLow */
  5863. if (frag == 0)
  5864. mcl |= TXC_STARTMSDU;
  5865. if (!is_multicast_ether_addr(h->addr1))
  5866. mcl |= TXC_IMMEDACK;
  5867. if (wlc->band->bandtype == BRCM_BAND_5G)
  5868. mcl |= TXC_FREQBAND_5G;
  5869. if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
  5870. mcl |= TXC_BW_40;
  5871. /* set AMIC bit if using hardware TKIP MIC */
  5872. if (hwtkmic)
  5873. mcl |= TXC_AMIC;
  5874. txh->MacTxControlLow = cpu_to_le16(mcl);
  5875. /* MacTxControlHigh */
  5876. mch = 0;
  5877. /* Set fallback rate preamble type */
  5878. if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
  5879. (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
  5880. if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
  5881. mch |= TXC_PREAMBLE_DATA_FB_SHORT;
  5882. }
  5883. /* MacFrameControl */
  5884. memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
  5885. txh->TxFesTimeNormal = cpu_to_le16(0);
  5886. txh->TxFesTimeFallback = cpu_to_le16(0);
  5887. /* TxFrameRA */
  5888. memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
  5889. /* TxFrameID */
  5890. txh->TxFrameID = cpu_to_le16(frameid);
  5891. /*
  5892. * TxStatus, Note the case of recreating the first frag of a suppressed
  5893. * frame then we may need to reset the retry cnt's via the status reg
  5894. */
  5895. txh->TxStatus = cpu_to_le16(status);
  5896. /*
  5897. * extra fields for ucode AMPDU aggregation, the new fields are added to
  5898. * the END of previous structure so that it's compatible in driver.
  5899. */
  5900. txh->MaxNMpdus = cpu_to_le16(0);
  5901. txh->MaxABytes_MRT = cpu_to_le16(0);
  5902. txh->MaxABytes_FBR = cpu_to_le16(0);
  5903. txh->MinMBytes = cpu_to_le16(0);
  5904. /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
  5905. * furnish struct d11txh */
  5906. /* RTS PLCP header and RTS frame */
  5907. if (use_rts || use_cts) {
  5908. if (use_rts && use_cts)
  5909. use_cts = false;
  5910. for (k = 0; k < 2; k++) {
  5911. rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
  5912. false,
  5913. mimo_ctlchbw);
  5914. }
  5915. if (!is_ofdm_rate(rts_rspec[0]) &&
  5916. !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
  5917. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5918. rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
  5919. mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
  5920. }
  5921. if (!is_ofdm_rate(rts_rspec[1]) &&
  5922. !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
  5923. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5924. rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
  5925. mch |= TXC_PREAMBLE_RTS_FB_SHORT;
  5926. }
  5927. /* RTS/CTS additions to MacTxControlLow */
  5928. if (use_cts) {
  5929. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
  5930. } else {
  5931. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
  5932. txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
  5933. }
  5934. /* RTS PLCP header */
  5935. rts_plcp = txh->RTSPhyHeader;
  5936. if (use_cts)
  5937. rts_phylen = DOT11_CTS_LEN + FCS_LEN;
  5938. else
  5939. rts_phylen = DOT11_RTS_LEN + FCS_LEN;
  5940. brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
  5941. /* fallback rate version of RTS PLCP header */
  5942. brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
  5943. rts_plcp_fallback);
  5944. memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
  5945. sizeof(txh->RTSPLCPFallback));
  5946. /* RTS frame fields... */
  5947. rts = (struct ieee80211_rts *)&txh->rts_frame;
  5948. durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
  5949. rspec[0], rts_preamble_type[0],
  5950. preamble_type[0], phylen, false);
  5951. rts->duration = cpu_to_le16(durid);
  5952. /* fallback rate version of RTS DUR field */
  5953. durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
  5954. rts_rspec[1], rspec[1],
  5955. rts_preamble_type[1],
  5956. preamble_type[1], phylen, false);
  5957. txh->RTSDurFallback = cpu_to_le16(durid);
  5958. if (use_cts) {
  5959. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5960. IEEE80211_STYPE_CTS);
  5961. memcpy(&rts->ra, &h->addr2, ETH_ALEN);
  5962. } else {
  5963. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5964. IEEE80211_STYPE_RTS);
  5965. memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
  5966. }
  5967. /* mainrate
  5968. * low 8 bits: main frag rate/mcs,
  5969. * high 8 bits: rts/cts rate/mcs
  5970. */
  5971. mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
  5972. D11A_PHY_HDR_GRATE(
  5973. (struct ofdm_phy_hdr *) rts_plcp) :
  5974. rts_plcp[0]) << 8;
  5975. } else {
  5976. memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
  5977. memset((char *)&txh->rts_frame, 0,
  5978. sizeof(struct ieee80211_rts));
  5979. memset((char *)txh->RTSPLCPFallback, 0,
  5980. sizeof(txh->RTSPLCPFallback));
  5981. txh->RTSDurFallback = 0;
  5982. }
  5983. #ifdef SUPPORT_40MHZ
  5984. /* add null delimiter count */
  5985. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
  5986. txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
  5987. brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
  5988. #endif
  5989. /*
  5990. * Now that RTS/RTS FB preamble types are updated, write
  5991. * the final value
  5992. */
  5993. txh->MacTxControlHigh = cpu_to_le16(mch);
  5994. /*
  5995. * MainRates (both the rts and frag plcp rates have
  5996. * been calculated now)
  5997. */
  5998. txh->MainRates = cpu_to_le16(mainrates);
  5999. /* XtraFrameTypes */
  6000. xfts = frametype(rspec[1], wlc->mimoft);
  6001. xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
  6002. xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
  6003. xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
  6004. XFTS_CHANNEL_SHIFT;
  6005. txh->XtraFrameTypes = cpu_to_le16(xfts);
  6006. /* PhyTxControlWord */
  6007. phyctl = frametype(rspec[0], wlc->mimoft);
  6008. if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
  6009. (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
  6010. if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
  6011. phyctl |= PHY_TXC_SHORT_HDR;
  6012. }
  6013. /* phytxant is properly bit shifted */
  6014. phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
  6015. txh->PhyTxControlWord = cpu_to_le16(phyctl);
  6016. /* PhyTxControlWord_1 */
  6017. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  6018. u16 phyctl1 = 0;
  6019. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
  6020. txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
  6021. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
  6022. txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
  6023. if (use_rts || use_cts) {
  6024. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
  6025. txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
  6026. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
  6027. txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
  6028. }
  6029. /*
  6030. * For mcs frames, if mixedmode(overloaded with long preamble)
  6031. * is going to be set, fill in non-zero MModeLen and/or
  6032. * MModeFbrLen it will be unnecessary if they are separated
  6033. */
  6034. if (is_mcs_rate(rspec[0]) &&
  6035. (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
  6036. u16 mmodelen =
  6037. brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
  6038. txh->MModeLen = cpu_to_le16(mmodelen);
  6039. }
  6040. if (is_mcs_rate(rspec[1]) &&
  6041. (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
  6042. u16 mmodefbrlen =
  6043. brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
  6044. txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
  6045. }
  6046. }
  6047. ac = skb_get_queue_mapping(p);
  6048. if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
  6049. uint frag_dur, dur, dur_fallback;
  6050. /* WME: Update TXOP threshold */
  6051. if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
  6052. frag_dur =
  6053. brcms_c_calc_frame_time(wlc, rspec[0],
  6054. preamble_type[0], phylen);
  6055. if (rts) {
  6056. /* 1 RTS or CTS-to-self frame */
  6057. dur =
  6058. brcms_c_calc_cts_time(wlc, rts_rspec[0],
  6059. rts_preamble_type[0]);
  6060. dur_fallback =
  6061. brcms_c_calc_cts_time(wlc, rts_rspec[1],
  6062. rts_preamble_type[1]);
  6063. /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
  6064. dur += le16_to_cpu(rts->duration);
  6065. dur_fallback +=
  6066. le16_to_cpu(txh->RTSDurFallback);
  6067. } else if (use_rifs) {
  6068. dur = frag_dur;
  6069. dur_fallback = 0;
  6070. } else {
  6071. /* frame + SIFS + ACK */
  6072. dur = frag_dur;
  6073. dur +=
  6074. brcms_c_compute_frame_dur(wlc, rspec[0],
  6075. preamble_type[0], 0);
  6076. dur_fallback =
  6077. brcms_c_calc_frame_time(wlc, rspec[1],
  6078. preamble_type[1],
  6079. phylen);
  6080. dur_fallback +=
  6081. brcms_c_compute_frame_dur(wlc, rspec[1],
  6082. preamble_type[1], 0);
  6083. }
  6084. /* NEED to set TxFesTimeNormal (hard) */
  6085. txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
  6086. /*
  6087. * NEED to set fallback rate version of
  6088. * TxFesTimeNormal (hard)
  6089. */
  6090. txh->TxFesTimeFallback =
  6091. cpu_to_le16((u16) dur_fallback);
  6092. /*
  6093. * update txop byte threshold (txop minus intraframe
  6094. * overhead)
  6095. */
  6096. if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
  6097. uint newfragthresh;
  6098. newfragthresh =
  6099. brcms_c_calc_frame_len(wlc,
  6100. rspec[0], preamble_type[0],
  6101. (wlc->edcf_txop[ac] -
  6102. (dur - frag_dur)));
  6103. /* range bound the fragthreshold */
  6104. if (newfragthresh < DOT11_MIN_FRAG_LEN)
  6105. newfragthresh =
  6106. DOT11_MIN_FRAG_LEN;
  6107. else if (newfragthresh >
  6108. wlc->usr_fragthresh)
  6109. newfragthresh =
  6110. wlc->usr_fragthresh;
  6111. /* update the fragthresh and do txc update */
  6112. if (wlc->fragthresh[queue] !=
  6113. (u16) newfragthresh)
  6114. wlc->fragthresh[queue] =
  6115. (u16) newfragthresh;
  6116. } else {
  6117. wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
  6118. "for rate %d\n",
  6119. wlc->pub->unit, fifo_names[queue],
  6120. rspec2rate(rspec[0]));
  6121. }
  6122. if (dur > wlc->edcf_txop[ac])
  6123. wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
  6124. "exceeded phylen %d/%d dur %d/%d\n",
  6125. wlc->pub->unit, __func__,
  6126. fifo_names[queue],
  6127. phylen, wlc->fragthresh[queue],
  6128. dur, wlc->edcf_txop[ac]);
  6129. }
  6130. }
  6131. return 0;
  6132. }
  6133. void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
  6134. struct ieee80211_hw *hw)
  6135. {
  6136. u8 prio;
  6137. uint fifo;
  6138. struct scb *scb = &wlc->pri_scb;
  6139. struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
  6140. /*
  6141. * 802.11 standard requires management traffic
  6142. * to go at highest priority
  6143. */
  6144. prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
  6145. MAXPRIO;
  6146. fifo = prio2fifo[prio];
  6147. if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
  6148. return;
  6149. brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio));
  6150. brcms_c_send_q(wlc);
  6151. }
  6152. void brcms_c_send_q(struct brcms_c_info *wlc)
  6153. {
  6154. struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
  6155. int prec;
  6156. u16 prec_map;
  6157. int err = 0, i, count;
  6158. uint fifo;
  6159. struct brcms_txq_info *qi = wlc->pkt_queue;
  6160. struct pktq *q = &qi->q;
  6161. struct ieee80211_tx_info *tx_info;
  6162. prec_map = wlc->tx_prec_map;
  6163. /* Send all the enq'd pkts that we can.
  6164. * Dequeue packets with precedence with empty HW fifo only
  6165. */
  6166. while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
  6167. tx_info = IEEE80211_SKB_CB(pkt[0]);
  6168. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  6169. err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec);
  6170. } else {
  6171. count = 1;
  6172. err = brcms_c_prep_pdu(wlc, pkt[0], &fifo);
  6173. if (!err) {
  6174. for (i = 0; i < count; i++)
  6175. brcms_c_txfifo(wlc, fifo, pkt[i], true,
  6176. 1);
  6177. }
  6178. }
  6179. if (err == -EBUSY) {
  6180. brcmu_pktq_penq_head(q, prec, pkt[0]);
  6181. /*
  6182. * If send failed due to any other reason than a
  6183. * change in HW FIFO condition, quit. Otherwise,
  6184. * read the new prec_map!
  6185. */
  6186. if (prec_map == wlc->tx_prec_map)
  6187. break;
  6188. prec_map = wlc->tx_prec_map;
  6189. }
  6190. }
  6191. }
  6192. void
  6193. brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p,
  6194. bool commit, s8 txpktpend)
  6195. {
  6196. u16 frameid = INVALIDFID;
  6197. struct d11txh *txh;
  6198. txh = (struct d11txh *) (p->data);
  6199. /* When a BC/MC frame is being committed to the BCMC fifo
  6200. * via DMA (NOT PIO), update ucode or BSS info as appropriate.
  6201. */
  6202. if (fifo == TX_BCMC_FIFO)
  6203. frameid = le16_to_cpu(txh->TxFrameID);
  6204. /*
  6205. * Bump up pending count for if not using rpc. If rpc is
  6206. * used, this will be handled in brcms_b_txfifo()
  6207. */
  6208. if (commit) {
  6209. wlc->core->txpktpend[fifo] += txpktpend;
  6210. BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
  6211. txpktpend, wlc->core->txpktpend[fifo]);
  6212. }
  6213. /* Commit BCMC sequence number in the SHM frame ID location */
  6214. if (frameid != INVALIDFID) {
  6215. /*
  6216. * To inform the ucode of the last mcast frame posted
  6217. * so that it can clear moredata bit
  6218. */
  6219. brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
  6220. }
  6221. if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0)
  6222. wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
  6223. }
  6224. u32
  6225. brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
  6226. bool use_rspec, u16 mimo_ctlchbw)
  6227. {
  6228. u32 rts_rspec = 0;
  6229. if (use_rspec)
  6230. /* use frame rate as rts rate */
  6231. rts_rspec = rspec;
  6232. else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
  6233. /* Use 11Mbps as the g protection RTS target rate and fallback.
  6234. * Use the brcms_basic_rate() lookup to find the best basic rate
  6235. * under the target in case 11 Mbps is not Basic.
  6236. * 6 and 9 Mbps are not usually selected by rate selection, but
  6237. * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
  6238. * is more robust.
  6239. */
  6240. rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
  6241. else
  6242. /* calculate RTS rate and fallback rate based on the frame rate
  6243. * RTS must be sent at a basic rate since it is a
  6244. * control frame, sec 9.6 of 802.11 spec
  6245. */
  6246. rts_rspec = brcms_basic_rate(wlc, rspec);
  6247. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  6248. /* set rts txbw to correct side band */
  6249. rts_rspec &= ~RSPEC_BW_MASK;
  6250. /*
  6251. * if rspec/rspec_fallback is 40MHz, then send RTS on both
  6252. * 20MHz channel (DUP), otherwise send RTS on control channel
  6253. */
  6254. if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
  6255. rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
  6256. else
  6257. rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  6258. /* pick siso/cdd as default for ofdm */
  6259. if (is_ofdm_rate(rts_rspec)) {
  6260. rts_rspec &= ~RSPEC_STF_MASK;
  6261. rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
  6262. }
  6263. }
  6264. return rts_rspec;
  6265. }
  6266. void
  6267. brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend)
  6268. {
  6269. wlc->core->txpktpend[fifo] -= txpktpend;
  6270. BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
  6271. wlc->core->txpktpend[fifo]);
  6272. /* There is more room; mark precedences related to this FIFO sendable */
  6273. wlc->tx_prec_map |= wlc->fifo2prec_map[fifo];
  6274. /* figure out which bsscfg is being worked on... */
  6275. }
  6276. /* Update beacon listen interval in shared memory */
  6277. static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
  6278. {
  6279. /* wake up every DTIM is the default */
  6280. if (wlc->bcn_li_dtim == 1)
  6281. brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
  6282. else
  6283. brcms_b_write_shm(wlc->hw, M_BCN_LI,
  6284. (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
  6285. }
  6286. static void
  6287. brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
  6288. u32 *tsf_h_ptr)
  6289. {
  6290. struct bcma_device *core = wlc_hw->d11core;
  6291. /* read the tsf timer low, then high to get an atomic read */
  6292. *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
  6293. *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
  6294. }
  6295. /*
  6296. * recover 64bit TSF value from the 16bit TSF value in the rx header
  6297. * given the assumption that the TSF passed in header is within 65ms
  6298. * of the current tsf.
  6299. *
  6300. * 6 5 4 4 3 2 1
  6301. * 3.......6.......8.......0.......2.......4.......6.......8......0
  6302. * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
  6303. *
  6304. * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
  6305. * tsf_l is filled in by brcms_b_recv, which is done earlier in the
  6306. * receive call sequence after rx interrupt. Only the higher 16 bits
  6307. * are used. Finally, the tsf_h is read from the tsf register.
  6308. */
  6309. static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
  6310. struct d11rxhdr *rxh)
  6311. {
  6312. u32 tsf_h, tsf_l;
  6313. u16 rx_tsf_0_15, rx_tsf_16_31;
  6314. brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
  6315. rx_tsf_16_31 = (u16)(tsf_l >> 16);
  6316. rx_tsf_0_15 = rxh->RxTSFTime;
  6317. /*
  6318. * a greater tsf time indicates the low 16 bits of
  6319. * tsf_l wrapped, so decrement the high 16 bits.
  6320. */
  6321. if ((u16)tsf_l < rx_tsf_0_15) {
  6322. rx_tsf_16_31 -= 1;
  6323. if (rx_tsf_16_31 == 0xffff)
  6324. tsf_h -= 1;
  6325. }
  6326. return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
  6327. }
  6328. static void
  6329. prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  6330. struct sk_buff *p,
  6331. struct ieee80211_rx_status *rx_status)
  6332. {
  6333. int preamble;
  6334. int channel;
  6335. u32 rspec;
  6336. unsigned char *plcp;
  6337. /* fill in TSF and flag its presence */
  6338. rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
  6339. rx_status->flag |= RX_FLAG_MACTIME_MPDU;
  6340. channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
  6341. if (channel > 14) {
  6342. rx_status->band = IEEE80211_BAND_5GHZ;
  6343. rx_status->freq = ieee80211_ofdm_chan_to_freq(
  6344. WF_CHAN_FACTOR_5_G/2, channel);
  6345. } else {
  6346. rx_status->band = IEEE80211_BAND_2GHZ;
  6347. rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
  6348. }
  6349. rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
  6350. /* noise */
  6351. /* qual */
  6352. rx_status->antenna =
  6353. (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
  6354. plcp = p->data;
  6355. rspec = brcms_c_compute_rspec(rxh, plcp);
  6356. if (is_mcs_rate(rspec)) {
  6357. rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
  6358. rx_status->flag |= RX_FLAG_HT;
  6359. if (rspec_is40mhz(rspec))
  6360. rx_status->flag |= RX_FLAG_40MHZ;
  6361. } else {
  6362. switch (rspec2rate(rspec)) {
  6363. case BRCM_RATE_1M:
  6364. rx_status->rate_idx = 0;
  6365. break;
  6366. case BRCM_RATE_2M:
  6367. rx_status->rate_idx = 1;
  6368. break;
  6369. case BRCM_RATE_5M5:
  6370. rx_status->rate_idx = 2;
  6371. break;
  6372. case BRCM_RATE_11M:
  6373. rx_status->rate_idx = 3;
  6374. break;
  6375. case BRCM_RATE_6M:
  6376. rx_status->rate_idx = 4;
  6377. break;
  6378. case BRCM_RATE_9M:
  6379. rx_status->rate_idx = 5;
  6380. break;
  6381. case BRCM_RATE_12M:
  6382. rx_status->rate_idx = 6;
  6383. break;
  6384. case BRCM_RATE_18M:
  6385. rx_status->rate_idx = 7;
  6386. break;
  6387. case BRCM_RATE_24M:
  6388. rx_status->rate_idx = 8;
  6389. break;
  6390. case BRCM_RATE_36M:
  6391. rx_status->rate_idx = 9;
  6392. break;
  6393. case BRCM_RATE_48M:
  6394. rx_status->rate_idx = 10;
  6395. break;
  6396. case BRCM_RATE_54M:
  6397. rx_status->rate_idx = 11;
  6398. break;
  6399. default:
  6400. wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
  6401. }
  6402. /*
  6403. * For 5GHz, we should decrease the index as it is
  6404. * a subset of the 2.4G rates. See bitrates field
  6405. * of brcms_band_5GHz_nphy (in mac80211_if.c).
  6406. */
  6407. if (rx_status->band == IEEE80211_BAND_5GHZ)
  6408. rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
  6409. /* Determine short preamble and rate_idx */
  6410. preamble = 0;
  6411. if (is_cck_rate(rspec)) {
  6412. if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
  6413. rx_status->flag |= RX_FLAG_SHORTPRE;
  6414. } else if (is_ofdm_rate(rspec)) {
  6415. rx_status->flag |= RX_FLAG_SHORTPRE;
  6416. } else {
  6417. wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
  6418. __func__);
  6419. }
  6420. }
  6421. if (plcp3_issgi(plcp[3]))
  6422. rx_status->flag |= RX_FLAG_SHORT_GI;
  6423. if (rxh->RxStatus1 & RXS_DECERR) {
  6424. rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
  6425. wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
  6426. __func__);
  6427. }
  6428. if (rxh->RxStatus1 & RXS_FCSERR) {
  6429. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  6430. wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
  6431. __func__);
  6432. }
  6433. }
  6434. static void
  6435. brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  6436. struct sk_buff *p)
  6437. {
  6438. int len_mpdu;
  6439. struct ieee80211_rx_status rx_status;
  6440. memset(&rx_status, 0, sizeof(rx_status));
  6441. prep_mac80211_status(wlc, rxh, p, &rx_status);
  6442. /* mac header+body length, exclude CRC and plcp header */
  6443. len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
  6444. skb_pull(p, D11_PHY_HDR_LEN);
  6445. __skb_trim(p, len_mpdu);
  6446. memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
  6447. ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
  6448. }
  6449. /* calculate frame duration for Mixed-mode L-SIG spoofing, return
  6450. * number of bytes goes in the length field
  6451. *
  6452. * Formula given by HT PHY Spec v 1.13
  6453. * len = 3(nsyms + nstream + 3) - 3
  6454. */
  6455. u16
  6456. brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
  6457. uint mac_len)
  6458. {
  6459. uint nsyms, len = 0, kNdps;
  6460. BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
  6461. wlc->pub->unit, rspec2rate(ratespec), mac_len);
  6462. if (is_mcs_rate(ratespec)) {
  6463. uint mcs = ratespec & RSPEC_RATE_MASK;
  6464. int tot_streams = (mcs_2_txstreams(mcs) + 1) +
  6465. rspec_stc(ratespec);
  6466. /*
  6467. * the payload duration calculation matches that
  6468. * of regular ofdm
  6469. */
  6470. /* 1000Ndbps = kbps * 4 */
  6471. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  6472. rspec_issgi(ratespec)) * 4;
  6473. if (rspec_stc(ratespec) == 0)
  6474. nsyms =
  6475. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6476. APHY_TAIL_NBITS) * 1000, kNdps);
  6477. else
  6478. /* STBC needs to have even number of symbols */
  6479. nsyms =
  6480. 2 *
  6481. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6482. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  6483. /* (+3) account for HT-SIG(2) and HT-STF(1) */
  6484. nsyms += (tot_streams + 3);
  6485. /*
  6486. * 3 bytes/symbol @ legacy 6Mbps rate
  6487. * (-3) excluding service bits and tail bits
  6488. */
  6489. len = (3 * nsyms) - 3;
  6490. }
  6491. return (u16) len;
  6492. }
  6493. static void
  6494. brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
  6495. {
  6496. const struct brcms_c_rateset *rs_dflt;
  6497. struct brcms_c_rateset rs;
  6498. u8 rate;
  6499. u16 entry_ptr;
  6500. u8 plcp[D11_PHY_HDR_LEN];
  6501. u16 dur, sifs;
  6502. uint i;
  6503. sifs = get_sifs(wlc->band);
  6504. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  6505. brcms_c_rateset_copy(rs_dflt, &rs);
  6506. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  6507. /*
  6508. * walk the phy rate table and update MAC core SHM
  6509. * basic rate table entries
  6510. */
  6511. for (i = 0; i < rs.count; i++) {
  6512. rate = rs.rates[i] & BRCMS_RATE_MASK;
  6513. entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
  6514. /* Calculate the Probe Response PLCP for the given rate */
  6515. brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
  6516. /*
  6517. * Calculate the duration of the Probe Response
  6518. * frame plus SIFS for the MAC
  6519. */
  6520. dur = (u16) brcms_c_calc_frame_time(wlc, rate,
  6521. BRCMS_LONG_PREAMBLE, frame_len);
  6522. dur += sifs;
  6523. /* Update the SHM Rate Table entry Probe Response values */
  6524. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
  6525. (u16) (plcp[0] + (plcp[1] << 8)));
  6526. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
  6527. (u16) (plcp[2] + (plcp[3] << 8)));
  6528. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
  6529. }
  6530. }
  6531. /* Max buffering needed for beacon template/prb resp template is 142 bytes.
  6532. *
  6533. * PLCP header is 6 bytes.
  6534. * 802.11 A3 header is 24 bytes.
  6535. * Max beacon frame body template length is 112 bytes.
  6536. * Max probe resp frame body template length is 110 bytes.
  6537. *
  6538. * *len on input contains the max length of the packet available.
  6539. *
  6540. * The *len value is set to the number of bytes in buf used, and starts
  6541. * with the PLCP and included up to, but not including, the 4 byte FCS.
  6542. */
  6543. static void
  6544. brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
  6545. u32 bcn_rspec,
  6546. struct brcms_bss_cfg *cfg, u16 *buf, int *len)
  6547. {
  6548. static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
  6549. struct cck_phy_hdr *plcp;
  6550. struct ieee80211_mgmt *h;
  6551. int hdr_len, body_len;
  6552. hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
  6553. /* calc buffer size provided for frame body */
  6554. body_len = *len - hdr_len;
  6555. /* return actual size */
  6556. *len = hdr_len + body_len;
  6557. /* format PHY and MAC headers */
  6558. memset((char *)buf, 0, hdr_len);
  6559. plcp = (struct cck_phy_hdr *) buf;
  6560. /*
  6561. * PLCP for Probe Response frames are filled in from
  6562. * core's rate table
  6563. */
  6564. if (type == IEEE80211_STYPE_BEACON)
  6565. /* fill in PLCP */
  6566. brcms_c_compute_plcp(wlc, bcn_rspec,
  6567. (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
  6568. (u8 *) plcp);
  6569. /* "Regular" and 16 MBSS but not for 4 MBSS */
  6570. /* Update the phytxctl for the beacon based on the rspec */
  6571. brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
  6572. h = (struct ieee80211_mgmt *)&plcp[1];
  6573. /* fill in 802.11 header */
  6574. h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
  6575. /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
  6576. /* A1 filled in by MAC for prb resp, broadcast for bcn */
  6577. if (type == IEEE80211_STYPE_BEACON)
  6578. memcpy(&h->da, &ether_bcast, ETH_ALEN);
  6579. memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
  6580. memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
  6581. /* SEQ filled in by MAC */
  6582. }
  6583. int brcms_c_get_header_len(void)
  6584. {
  6585. return TXOFF;
  6586. }
  6587. /*
  6588. * Update all beacons for the system.
  6589. */
  6590. void brcms_c_update_beacon(struct brcms_c_info *wlc)
  6591. {
  6592. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6593. if (bsscfg->up && !bsscfg->BSS)
  6594. /* Clear the soft intmask */
  6595. wlc->defmacintmask &= ~MI_BCNTPL;
  6596. }
  6597. /* Write ssid into shared memory */
  6598. static void
  6599. brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
  6600. {
  6601. u8 *ssidptr = cfg->SSID;
  6602. u16 base = M_SSID;
  6603. u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
  6604. /* padding the ssid with zero and copy it into shm */
  6605. memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
  6606. memcpy(ssidbuf, ssidptr, cfg->SSID_len);
  6607. brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
  6608. brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
  6609. }
  6610. static void
  6611. brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
  6612. struct brcms_bss_cfg *cfg,
  6613. bool suspend)
  6614. {
  6615. u16 prb_resp[BCN_TMPL_LEN / 2];
  6616. int len = BCN_TMPL_LEN;
  6617. /*
  6618. * write the probe response to hardware, or save in
  6619. * the config structure
  6620. */
  6621. /* create the probe response template */
  6622. brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
  6623. cfg, prb_resp, &len);
  6624. if (suspend)
  6625. brcms_c_suspend_mac_and_wait(wlc);
  6626. /* write the probe response into the template region */
  6627. brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
  6628. (len + 3) & ~3, prb_resp);
  6629. /* write the length of the probe response frame (+PLCP/-FCS) */
  6630. brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
  6631. /* write the SSID and SSID length */
  6632. brcms_c_shm_ssid_upd(wlc, cfg);
  6633. /*
  6634. * Write PLCP headers and durations for probe response frames
  6635. * at all rates. Use the actual frame length covered by the
  6636. * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
  6637. * by subtracting the PLCP len and adding the FCS.
  6638. */
  6639. len += (-D11_PHY_HDR_LEN + FCS_LEN);
  6640. brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
  6641. if (suspend)
  6642. brcms_c_enable_mac(wlc);
  6643. }
  6644. void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
  6645. {
  6646. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6647. /* update AP or IBSS probe responses */
  6648. if (bsscfg->up && !bsscfg->BSS)
  6649. brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
  6650. }
  6651. /* prepares pdu for transmission. returns BCM error codes */
  6652. int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop)
  6653. {
  6654. uint fifo;
  6655. struct d11txh *txh;
  6656. struct ieee80211_hdr *h;
  6657. struct scb *scb;
  6658. txh = (struct d11txh *) (pdu->data);
  6659. h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
  6660. /* get the pkt queue info. This was put at brcms_c_sendctl or
  6661. * brcms_c_send for PDU */
  6662. fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
  6663. scb = NULL;
  6664. *fifop = fifo;
  6665. /* return if insufficient dma resources */
  6666. if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) {
  6667. /* Mark precedences related to this FIFO, unsendable */
  6668. /* A fifo is full. Clear precedences related to that FIFO */
  6669. wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]);
  6670. return -EBUSY;
  6671. }
  6672. return 0;
  6673. }
  6674. int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
  6675. uint *blocks)
  6676. {
  6677. if (fifo >= NFIFO)
  6678. return -EINVAL;
  6679. *blocks = wlc_hw->xmtfifo_sz[fifo];
  6680. return 0;
  6681. }
  6682. void
  6683. brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
  6684. const u8 *addr)
  6685. {
  6686. brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
  6687. if (match_reg_offset == RCM_BSSID_OFFSET)
  6688. memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
  6689. }
  6690. /*
  6691. * Flag 'scan in progress' to withhold dynamic phy calibration
  6692. */
  6693. void brcms_c_scan_start(struct brcms_c_info *wlc)
  6694. {
  6695. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
  6696. }
  6697. void brcms_c_scan_stop(struct brcms_c_info *wlc)
  6698. {
  6699. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
  6700. }
  6701. void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
  6702. {
  6703. wlc->pub->associated = state;
  6704. wlc->bsscfg->associated = state;
  6705. }
  6706. /*
  6707. * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
  6708. * AMPDU traffic, packets pending in hardware have to be invalidated so that
  6709. * when later on hardware releases them, they can be handled appropriately.
  6710. */
  6711. void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
  6712. struct ieee80211_sta *sta,
  6713. void (*dma_callback_fn))
  6714. {
  6715. struct dma_pub *dmah;
  6716. int i;
  6717. for (i = 0; i < NFIFO; i++) {
  6718. dmah = hw->di[i];
  6719. if (dmah != NULL)
  6720. dma_walk_packets(dmah, dma_callback_fn, sta);
  6721. }
  6722. }
  6723. int brcms_c_get_curband(struct brcms_c_info *wlc)
  6724. {
  6725. return wlc->band->bandunit;
  6726. }
  6727. void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
  6728. {
  6729. /* flush packet queue when requested */
  6730. if (drop)
  6731. brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
  6732. /* wait for queue and DMA fifos to run dry */
  6733. while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0)
  6734. brcms_msleep(wlc->wl, 1);
  6735. }
  6736. void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
  6737. {
  6738. wlc->bcn_li_bcn = interval;
  6739. if (wlc->pub->up)
  6740. brcms_c_bcn_li_upd(wlc);
  6741. }
  6742. int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
  6743. {
  6744. uint qdbm;
  6745. /* Remove override bit and clip to max qdbm value */
  6746. qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
  6747. return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
  6748. }
  6749. int brcms_c_get_tx_power(struct brcms_c_info *wlc)
  6750. {
  6751. uint qdbm;
  6752. bool override;
  6753. wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
  6754. /* Return qdbm units */
  6755. return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
  6756. }
  6757. /* Process received frames */
  6758. /*
  6759. * Return true if more frames need to be processed. false otherwise.
  6760. * Param 'bound' indicates max. # frames to process before break out.
  6761. */
  6762. static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
  6763. {
  6764. struct d11rxhdr *rxh;
  6765. struct ieee80211_hdr *h;
  6766. uint len;
  6767. bool is_amsdu;
  6768. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  6769. /* frame starts with rxhdr */
  6770. rxh = (struct d11rxhdr *) (p->data);
  6771. /* strip off rxhdr */
  6772. skb_pull(p, BRCMS_HWRXOFF);
  6773. /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
  6774. if (rxh->RxStatus1 & RXS_PBPRES) {
  6775. if (p->len < 2) {
  6776. wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
  6777. "len %d\n", wlc->pub->unit, p->len);
  6778. goto toss;
  6779. }
  6780. skb_pull(p, 2);
  6781. }
  6782. h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
  6783. len = p->len;
  6784. if (rxh->RxStatus1 & RXS_FCSERR) {
  6785. if (!(wlc->filter_flags & FIF_FCSFAIL))
  6786. goto toss;
  6787. }
  6788. /* check received pkt has at least frame control field */
  6789. if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
  6790. goto toss;
  6791. /* not supporting A-MSDU */
  6792. is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
  6793. if (is_amsdu)
  6794. goto toss;
  6795. brcms_c_recvctl(wlc, rxh, p);
  6796. return;
  6797. toss:
  6798. brcmu_pkt_buf_free_skb(p);
  6799. }
  6800. /* Process received frames */
  6801. /*
  6802. * Return true if more frames need to be processed. false otherwise.
  6803. * Param 'bound' indicates max. # frames to process before break out.
  6804. */
  6805. static bool
  6806. brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
  6807. {
  6808. struct sk_buff *p;
  6809. struct sk_buff *next = NULL;
  6810. struct sk_buff_head recv_frames;
  6811. uint n = 0;
  6812. uint bound_limit = bound ? RXBND : -1;
  6813. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  6814. skb_queue_head_init(&recv_frames);
  6815. /* gather received frames */
  6816. while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
  6817. /* !give others some time to run! */
  6818. if (++n >= bound_limit)
  6819. break;
  6820. }
  6821. /* post more rbufs */
  6822. dma_rxfill(wlc_hw->di[fifo]);
  6823. /* process each frame */
  6824. skb_queue_walk_safe(&recv_frames, p, next) {
  6825. struct d11rxhdr_le *rxh_le;
  6826. struct d11rxhdr *rxh;
  6827. skb_unlink(p, &recv_frames);
  6828. rxh_le = (struct d11rxhdr_le *)p->data;
  6829. rxh = (struct d11rxhdr *)p->data;
  6830. /* fixup rx header endianness */
  6831. rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
  6832. rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
  6833. rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
  6834. rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
  6835. rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
  6836. rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
  6837. rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
  6838. rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
  6839. rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
  6840. rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
  6841. rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
  6842. brcms_c_recv(wlc_hw->wlc, p);
  6843. }
  6844. return n >= bound_limit;
  6845. }
  6846. /* second-level interrupt processing
  6847. * Return true if another dpc needs to be re-scheduled. false otherwise.
  6848. * Param 'bounded' indicates if applicable loops should be bounded.
  6849. */
  6850. bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
  6851. {
  6852. u32 macintstatus;
  6853. struct brcms_hardware *wlc_hw = wlc->hw;
  6854. struct bcma_device *core = wlc_hw->d11core;
  6855. struct wiphy *wiphy = wlc->wiphy;
  6856. if (brcms_deviceremoved(wlc)) {
  6857. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  6858. __func__);
  6859. brcms_down(wlc->wl);
  6860. return false;
  6861. }
  6862. /* grab and clear the saved software intstatus bits */
  6863. macintstatus = wlc->macintstatus;
  6864. wlc->macintstatus = 0;
  6865. BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
  6866. wlc_hw->unit, macintstatus);
  6867. WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
  6868. /* tx status */
  6869. if (macintstatus & MI_TFS) {
  6870. bool fatal;
  6871. if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
  6872. wlc->macintstatus |= MI_TFS;
  6873. if (fatal) {
  6874. wiphy_err(wiphy, "MI_TFS: fatal\n");
  6875. goto fatal;
  6876. }
  6877. }
  6878. if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
  6879. brcms_c_tbtt(wlc);
  6880. /* ATIM window end */
  6881. if (macintstatus & MI_ATIMWINEND) {
  6882. BCMMSG(wlc->wiphy, "end of ATIM window\n");
  6883. bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
  6884. wlc->qvalid = 0;
  6885. }
  6886. /*
  6887. * received data or control frame, MI_DMAINT is
  6888. * indication of RX_FIFO interrupt
  6889. */
  6890. if (macintstatus & MI_DMAINT)
  6891. if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
  6892. wlc->macintstatus |= MI_DMAINT;
  6893. /* noise sample collected */
  6894. if (macintstatus & MI_BG_NOISE)
  6895. wlc_phy_noise_sample_intr(wlc_hw->band->pi);
  6896. if (macintstatus & MI_GP0) {
  6897. wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
  6898. "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
  6899. printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
  6900. __func__, ai_get_chip_id(wlc_hw->sih),
  6901. ai_get_chiprev(wlc_hw->sih));
  6902. brcms_fatal_error(wlc_hw->wlc->wl);
  6903. }
  6904. /* gptimer timeout */
  6905. if (macintstatus & MI_TO)
  6906. bcma_write32(core, D11REGOFFS(gptimer), 0);
  6907. if (macintstatus & MI_RFDISABLE) {
  6908. BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
  6909. " RF Disable Input\n", wlc_hw->unit);
  6910. brcms_rfkill_set_hw_state(wlc->wl);
  6911. }
  6912. /* send any enq'd tx packets. Just makes sure to jump start tx */
  6913. if (!pktq_empty(&wlc->pkt_queue->q))
  6914. brcms_c_send_q(wlc);
  6915. /* it isn't done and needs to be resched if macintstatus is non-zero */
  6916. return wlc->macintstatus != 0;
  6917. fatal:
  6918. brcms_fatal_error(wlc_hw->wlc->wl);
  6919. return wlc->macintstatus != 0;
  6920. }
  6921. void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
  6922. {
  6923. struct bcma_device *core = wlc->hw->d11core;
  6924. u16 chanspec;
  6925. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  6926. /*
  6927. * This will happen if a big-hammer was executed. In
  6928. * that case, we want to go back to the channel that
  6929. * we were on and not new channel
  6930. */
  6931. if (wlc->pub->associated)
  6932. chanspec = wlc->home_chanspec;
  6933. else
  6934. chanspec = brcms_c_init_chanspec(wlc);
  6935. brcms_b_init(wlc->hw, chanspec);
  6936. /* update beacon listen interval */
  6937. brcms_c_bcn_li_upd(wlc);
  6938. /* write ethernet address to core */
  6939. brcms_c_set_mac(wlc->bsscfg);
  6940. brcms_c_set_bssid(wlc->bsscfg);
  6941. /* Update tsf_cfprep if associated and up */
  6942. if (wlc->pub->associated && wlc->bsscfg->up) {
  6943. u32 bi;
  6944. /* get beacon period and convert to uS */
  6945. bi = wlc->bsscfg->current_bss->beacon_period << 10;
  6946. /*
  6947. * update since init path would reset
  6948. * to default value
  6949. */
  6950. bcma_write32(core, D11REGOFFS(tsf_cfprep),
  6951. bi << CFPREP_CBI_SHIFT);
  6952. /* Update maccontrol PM related bits */
  6953. brcms_c_set_ps_ctrl(wlc);
  6954. }
  6955. brcms_c_bandinit_ordered(wlc, chanspec);
  6956. /* init probe response timeout */
  6957. brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
  6958. /* init max burst txop (framebursting) */
  6959. brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
  6960. (wlc->
  6961. _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
  6962. /* initialize maximum allowed duty cycle */
  6963. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
  6964. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
  6965. /*
  6966. * Update some shared memory locations related to
  6967. * max AMPDU size allowed to received
  6968. */
  6969. brcms_c_ampdu_shm_upd(wlc->ampdu);
  6970. /* band-specific inits */
  6971. brcms_c_bsinit(wlc);
  6972. /* Enable EDCF mode (while the MAC is suspended) */
  6973. bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
  6974. brcms_c_edcf_setparams(wlc, false);
  6975. /* Init precedence maps for empty FIFOs */
  6976. brcms_c_tx_prec_map_init(wlc);
  6977. /* read the ucode version if we have not yet done so */
  6978. if (wlc->ucode_rev == 0) {
  6979. wlc->ucode_rev =
  6980. brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
  6981. wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
  6982. }
  6983. /* ..now really unleash hell (allow the MAC out of suspend) */
  6984. brcms_c_enable_mac(wlc);
  6985. /* suspend the tx fifos and mute the phy for preism cac time */
  6986. if (mute_tx)
  6987. brcms_b_mute(wlc->hw, true);
  6988. /* clear tx flow control */
  6989. brcms_c_txflowcontrol_reset(wlc);
  6990. /* enable the RF Disable Delay timer */
  6991. bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
  6992. /*
  6993. * Initialize WME parameters; if they haven't been set by some other
  6994. * mechanism (IOVar, etc) then read them from the hardware.
  6995. */
  6996. if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
  6997. /* Uninitialized; read from HW */
  6998. int ac;
  6999. for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
  7000. wlc->wme_retries[ac] =
  7001. brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
  7002. }
  7003. }
  7004. /*
  7005. * The common driver entry routine. Error codes should be unique
  7006. */
  7007. struct brcms_c_info *
  7008. brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
  7009. bool piomode, uint *perr)
  7010. {
  7011. struct brcms_c_info *wlc;
  7012. uint err = 0;
  7013. uint i, j;
  7014. struct brcms_pub *pub;
  7015. /* allocate struct brcms_c_info state and its substructures */
  7016. wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, 0);
  7017. if (wlc == NULL)
  7018. goto fail;
  7019. wlc->wiphy = wl->wiphy;
  7020. pub = wlc->pub;
  7021. #if defined(BCMDBG)
  7022. wlc_info_dbg = wlc;
  7023. #endif
  7024. wlc->band = wlc->bandstate[0];
  7025. wlc->core = wlc->corestate;
  7026. wlc->wl = wl;
  7027. pub->unit = unit;
  7028. pub->_piomode = piomode;
  7029. wlc->bandinit_pending = false;
  7030. /* populate struct brcms_c_info with default values */
  7031. brcms_c_info_init(wlc, unit);
  7032. /* update sta/ap related parameters */
  7033. brcms_c_ap_upd(wlc);
  7034. /*
  7035. * low level attach steps(all hw accesses go
  7036. * inside, no more in rest of the attach)
  7037. */
  7038. err = brcms_b_attach(wlc, core, unit, piomode);
  7039. if (err)
  7040. goto fail;
  7041. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
  7042. pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
  7043. /* disable allowed duty cycle */
  7044. wlc->tx_duty_cycle_ofdm = 0;
  7045. wlc->tx_duty_cycle_cck = 0;
  7046. brcms_c_stf_phy_chain_calc(wlc);
  7047. /* txchain 1: txant 0, txchain 2: txant 1 */
  7048. if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
  7049. wlc->stf->txant = wlc->stf->hw_txchain - 1;
  7050. /* push to BMAC driver */
  7051. wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
  7052. wlc->stf->hw_rxchain);
  7053. /* pull up some info resulting from the low attach */
  7054. for (i = 0; i < NFIFO; i++)
  7055. wlc->core->txavail[i] = wlc->hw->txavail[i];
  7056. memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  7057. memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  7058. for (j = 0; j < wlc->pub->_nbands; j++) {
  7059. wlc->band = wlc->bandstate[j];
  7060. if (!brcms_c_attach_stf_ant_init(wlc)) {
  7061. err = 24;
  7062. goto fail;
  7063. }
  7064. /* default contention windows size limits */
  7065. wlc->band->CWmin = APHY_CWMIN;
  7066. wlc->band->CWmax = PHY_CWMAX;
  7067. /* init gmode value */
  7068. if (wlc->band->bandtype == BRCM_BAND_2G) {
  7069. wlc->band->gmode = GMODE_AUTO;
  7070. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
  7071. wlc->band->gmode);
  7072. }
  7073. /* init _n_enab supported mode */
  7074. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  7075. pub->_n_enab = SUPPORT_11N;
  7076. brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
  7077. ((pub->_n_enab ==
  7078. SUPPORT_11N) ? WL_11N_2x2 :
  7079. WL_11N_3x3));
  7080. }
  7081. /* init per-band default rateset, depend on band->gmode */
  7082. brcms_default_rateset(wlc, &wlc->band->defrateset);
  7083. /* fill in hw_rateset */
  7084. brcms_c_rateset_filter(&wlc->band->defrateset,
  7085. &wlc->band->hw_rateset, false,
  7086. BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  7087. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  7088. }
  7089. /*
  7090. * update antenna config due to
  7091. * wlc->stf->txant/txchain/ant_rx_ovr change
  7092. */
  7093. brcms_c_stf_phy_txant_upd(wlc);
  7094. /* attach each modules */
  7095. err = brcms_c_attach_module(wlc);
  7096. if (err != 0)
  7097. goto fail;
  7098. if (!brcms_c_timers_init(wlc, unit)) {
  7099. wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
  7100. __func__);
  7101. err = 32;
  7102. goto fail;
  7103. }
  7104. /* depend on rateset, gmode */
  7105. wlc->cmi = brcms_c_channel_mgr_attach(wlc);
  7106. if (!wlc->cmi) {
  7107. wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
  7108. "\n", unit, __func__);
  7109. err = 33;
  7110. goto fail;
  7111. }
  7112. /* init default when all parameters are ready, i.e. ->rateset */
  7113. brcms_c_bss_default_init(wlc);
  7114. /*
  7115. * Complete the wlc default state initializations..
  7116. */
  7117. /* allocate our initial queue */
  7118. wlc->pkt_queue = brcms_c_txq_alloc(wlc);
  7119. if (wlc->pkt_queue == NULL) {
  7120. wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
  7121. unit, __func__);
  7122. err = 100;
  7123. goto fail;
  7124. }
  7125. wlc->bsscfg->wlc = wlc;
  7126. wlc->mimoft = FT_HT;
  7127. wlc->mimo_40txbw = AUTO;
  7128. wlc->ofdm_40txbw = AUTO;
  7129. wlc->cck_40txbw = AUTO;
  7130. brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
  7131. /* Set default values of SGI */
  7132. if (BRCMS_SGI_CAP_PHY(wlc)) {
  7133. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  7134. BRCMS_N_SGI_40));
  7135. } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
  7136. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  7137. BRCMS_N_SGI_40));
  7138. } else {
  7139. brcms_c_ht_update_sgi_rx(wlc, 0);
  7140. }
  7141. brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
  7142. if (perr)
  7143. *perr = 0;
  7144. return wlc;
  7145. fail:
  7146. wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
  7147. unit, __func__, err);
  7148. if (wlc)
  7149. brcms_c_detach(wlc);
  7150. if (perr)
  7151. *perr = err;
  7152. return NULL;
  7153. }