sdio_chip.h 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990
  1. /*
  2. * Copyright (c) 2011 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _BRCMFMAC_SDIO_CHIP_H_
  17. #define _BRCMFMAC_SDIO_CHIP_H_
  18. /*
  19. * Core reg address translation.
  20. * Both macro's returns a 32 bits byte address on the backplane bus.
  21. */
  22. #define CORE_CC_REG(base, field) \
  23. (base + offsetof(struct chipcregs, field))
  24. #define CORE_BUS_REG(base, field) \
  25. (base + offsetof(struct sdpcmd_regs, field))
  26. #define CORE_SB(base, field) \
  27. (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
  28. struct chip_info {
  29. u32 chip;
  30. u32 chiprev;
  31. u32 cccorebase;
  32. u32 ccrev;
  33. u32 cccaps;
  34. u32 buscorebase; /* 32 bits backplane bus address */
  35. u32 buscorerev;
  36. u32 buscoretype;
  37. u32 ramcorebase;
  38. u32 armcorebase;
  39. u32 pmurev;
  40. u32 ramsize;
  41. };
  42. struct sbconfig {
  43. u32 PAD[2];
  44. u32 sbipsflag; /* initiator port ocp slave flag */
  45. u32 PAD[3];
  46. u32 sbtpsflag; /* target port ocp slave flag */
  47. u32 PAD[11];
  48. u32 sbtmerrloga; /* (sonics >= 2.3) */
  49. u32 PAD;
  50. u32 sbtmerrlog; /* (sonics >= 2.3) */
  51. u32 PAD[3];
  52. u32 sbadmatch3; /* address match3 */
  53. u32 PAD;
  54. u32 sbadmatch2; /* address match2 */
  55. u32 PAD;
  56. u32 sbadmatch1; /* address match1 */
  57. u32 PAD[7];
  58. u32 sbimstate; /* initiator agent state */
  59. u32 sbintvec; /* interrupt mask */
  60. u32 sbtmstatelow; /* target state */
  61. u32 sbtmstatehigh; /* target state */
  62. u32 sbbwa0; /* bandwidth allocation table0 */
  63. u32 PAD;
  64. u32 sbimconfiglow; /* initiator configuration */
  65. u32 sbimconfighigh; /* initiator configuration */
  66. u32 sbadmatch0; /* address match0 */
  67. u32 PAD;
  68. u32 sbtmconfiglow; /* target configuration */
  69. u32 sbtmconfighigh; /* target configuration */
  70. u32 sbbconfig; /* broadcast configuration */
  71. u32 PAD;
  72. u32 sbbstate; /* broadcast state */
  73. u32 PAD[3];
  74. u32 sbactcnfg; /* activate configuration */
  75. u32 PAD[3];
  76. u32 sbflagst; /* current sbflags */
  77. u32 PAD[3];
  78. u32 sbidlow; /* identification */
  79. u32 sbidhigh; /* identification */
  80. };
  81. extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
  82. struct chip_info *ci, u32 regs);
  83. #endif /* _BRCMFMAC_SDIO_CHIP_H_ */