setup.c 35 KB

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  1. /*
  2. * linux/arch/x86-64/kernel/setup.c
  3. *
  4. * Copyright (C) 1995 Linus Torvalds
  5. *
  6. * Nov 2001 Dave Jones <davej@suse.de>
  7. * Forked from i386 setup code.
  8. */
  9. /*
  10. * This file handles the architecture-dependent parts of initialization
  11. */
  12. #include <linux/errno.h>
  13. #include <linux/sched.h>
  14. #include <linux/kernel.h>
  15. #include <linux/mm.h>
  16. #include <linux/stddef.h>
  17. #include <linux/unistd.h>
  18. #include <linux/ptrace.h>
  19. #include <linux/slab.h>
  20. #include <linux/user.h>
  21. #include <linux/a.out.h>
  22. #include <linux/tty.h>
  23. #include <linux/ioport.h>
  24. #include <linux/delay.h>
  25. #include <linux/config.h>
  26. #include <linux/init.h>
  27. #include <linux/initrd.h>
  28. #include <linux/highmem.h>
  29. #include <linux/bootmem.h>
  30. #include <linux/module.h>
  31. #include <asm/processor.h>
  32. #include <linux/console.h>
  33. #include <linux/seq_file.h>
  34. #include <linux/crash_dump.h>
  35. #include <linux/root_dev.h>
  36. #include <linux/pci.h>
  37. #include <linux/acpi.h>
  38. #include <linux/kallsyms.h>
  39. #include <linux/edd.h>
  40. #include <linux/mmzone.h>
  41. #include <linux/kexec.h>
  42. #include <linux/cpufreq.h>
  43. #include <linux/dmi.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/ctype.h>
  46. #include <asm/mtrr.h>
  47. #include <asm/uaccess.h>
  48. #include <asm/system.h>
  49. #include <asm/io.h>
  50. #include <asm/smp.h>
  51. #include <asm/msr.h>
  52. #include <asm/desc.h>
  53. #include <video/edid.h>
  54. #include <asm/e820.h>
  55. #include <asm/dma.h>
  56. #include <asm/mpspec.h>
  57. #include <asm/mmu_context.h>
  58. #include <asm/bootsetup.h>
  59. #include <asm/proto.h>
  60. #include <asm/setup.h>
  61. #include <asm/mach_apic.h>
  62. #include <asm/numa.h>
  63. #include <asm/swiotlb.h>
  64. #include <asm/sections.h>
  65. #include <asm/dmi.h>
  66. /*
  67. * Machine setup..
  68. */
  69. struct cpuinfo_x86 boot_cpu_data __read_mostly;
  70. unsigned long mmu_cr4_features;
  71. int acpi_disabled;
  72. EXPORT_SYMBOL(acpi_disabled);
  73. #ifdef CONFIG_ACPI
  74. extern int __initdata acpi_ht;
  75. extern acpi_interrupt_flags acpi_sci_flags;
  76. int __initdata acpi_force = 0;
  77. #endif
  78. int acpi_numa __initdata;
  79. /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  80. int bootloader_type;
  81. unsigned long saved_video_mode;
  82. /*
  83. * Early DMI memory
  84. */
  85. int dmi_alloc_index;
  86. char dmi_alloc_data[DMI_MAX_DATA];
  87. /*
  88. * Setup options
  89. */
  90. struct screen_info screen_info;
  91. struct sys_desc_table_struct {
  92. unsigned short length;
  93. unsigned char table[0];
  94. };
  95. struct edid_info edid_info;
  96. struct e820map e820;
  97. extern int root_mountflags;
  98. char command_line[COMMAND_LINE_SIZE];
  99. struct resource standard_io_resources[] = {
  100. { .name = "dma1", .start = 0x00, .end = 0x1f,
  101. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  102. { .name = "pic1", .start = 0x20, .end = 0x21,
  103. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  104. { .name = "timer0", .start = 0x40, .end = 0x43,
  105. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  106. { .name = "timer1", .start = 0x50, .end = 0x53,
  107. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  108. { .name = "keyboard", .start = 0x60, .end = 0x6f,
  109. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  110. { .name = "dma page reg", .start = 0x80, .end = 0x8f,
  111. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  112. { .name = "pic2", .start = 0xa0, .end = 0xa1,
  113. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  114. { .name = "dma2", .start = 0xc0, .end = 0xdf,
  115. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  116. { .name = "fpu", .start = 0xf0, .end = 0xff,
  117. .flags = IORESOURCE_BUSY | IORESOURCE_IO }
  118. };
  119. #define STANDARD_IO_RESOURCES \
  120. (sizeof standard_io_resources / sizeof standard_io_resources[0])
  121. #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
  122. struct resource data_resource = {
  123. .name = "Kernel data",
  124. .start = 0,
  125. .end = 0,
  126. .flags = IORESOURCE_RAM,
  127. };
  128. struct resource code_resource = {
  129. .name = "Kernel code",
  130. .start = 0,
  131. .end = 0,
  132. .flags = IORESOURCE_RAM,
  133. };
  134. #define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
  135. static struct resource system_rom_resource = {
  136. .name = "System ROM",
  137. .start = 0xf0000,
  138. .end = 0xfffff,
  139. .flags = IORESOURCE_ROM,
  140. };
  141. static struct resource extension_rom_resource = {
  142. .name = "Extension ROM",
  143. .start = 0xe0000,
  144. .end = 0xeffff,
  145. .flags = IORESOURCE_ROM,
  146. };
  147. static struct resource adapter_rom_resources[] = {
  148. { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
  149. .flags = IORESOURCE_ROM },
  150. { .name = "Adapter ROM", .start = 0, .end = 0,
  151. .flags = IORESOURCE_ROM },
  152. { .name = "Adapter ROM", .start = 0, .end = 0,
  153. .flags = IORESOURCE_ROM },
  154. { .name = "Adapter ROM", .start = 0, .end = 0,
  155. .flags = IORESOURCE_ROM },
  156. { .name = "Adapter ROM", .start = 0, .end = 0,
  157. .flags = IORESOURCE_ROM },
  158. { .name = "Adapter ROM", .start = 0, .end = 0,
  159. .flags = IORESOURCE_ROM }
  160. };
  161. #define ADAPTER_ROM_RESOURCES \
  162. (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
  163. static struct resource video_rom_resource = {
  164. .name = "Video ROM",
  165. .start = 0xc0000,
  166. .end = 0xc7fff,
  167. .flags = IORESOURCE_ROM,
  168. };
  169. static struct resource video_ram_resource = {
  170. .name = "Video RAM area",
  171. .start = 0xa0000,
  172. .end = 0xbffff,
  173. .flags = IORESOURCE_RAM,
  174. };
  175. #define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
  176. static int __init romchecksum(unsigned char *rom, unsigned long length)
  177. {
  178. unsigned char *p, sum = 0;
  179. for (p = rom; p < rom + length; p++)
  180. sum += *p;
  181. return sum == 0;
  182. }
  183. static void __init probe_roms(void)
  184. {
  185. unsigned long start, length, upper;
  186. unsigned char *rom;
  187. int i;
  188. /* video rom */
  189. upper = adapter_rom_resources[0].start;
  190. for (start = video_rom_resource.start; start < upper; start += 2048) {
  191. rom = isa_bus_to_virt(start);
  192. if (!romsignature(rom))
  193. continue;
  194. video_rom_resource.start = start;
  195. /* 0 < length <= 0x7f * 512, historically */
  196. length = rom[2] * 512;
  197. /* if checksum okay, trust length byte */
  198. if (length && romchecksum(rom, length))
  199. video_rom_resource.end = start + length - 1;
  200. request_resource(&iomem_resource, &video_rom_resource);
  201. break;
  202. }
  203. start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
  204. if (start < upper)
  205. start = upper;
  206. /* system rom */
  207. request_resource(&iomem_resource, &system_rom_resource);
  208. upper = system_rom_resource.start;
  209. /* check for extension rom (ignore length byte!) */
  210. rom = isa_bus_to_virt(extension_rom_resource.start);
  211. if (romsignature(rom)) {
  212. length = extension_rom_resource.end - extension_rom_resource.start + 1;
  213. if (romchecksum(rom, length)) {
  214. request_resource(&iomem_resource, &extension_rom_resource);
  215. upper = extension_rom_resource.start;
  216. }
  217. }
  218. /* check for adapter roms on 2k boundaries */
  219. for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
  220. rom = isa_bus_to_virt(start);
  221. if (!romsignature(rom))
  222. continue;
  223. /* 0 < length <= 0x7f * 512, historically */
  224. length = rom[2] * 512;
  225. /* but accept any length that fits if checksum okay */
  226. if (!length || start + length > upper || !romchecksum(rom, length))
  227. continue;
  228. adapter_rom_resources[i].start = start;
  229. adapter_rom_resources[i].end = start + length - 1;
  230. request_resource(&iomem_resource, &adapter_rom_resources[i]);
  231. start = adapter_rom_resources[i++].end & ~2047UL;
  232. }
  233. }
  234. /* Check for full argument with no trailing characters */
  235. static int fullarg(char *p, char *arg)
  236. {
  237. int l = strlen(arg);
  238. return !memcmp(p, arg, l) && (p[l] == 0 || isspace(p[l]));
  239. }
  240. static __init void parse_cmdline_early (char ** cmdline_p)
  241. {
  242. char c = ' ', *to = command_line, *from = COMMAND_LINE;
  243. int len = 0;
  244. int userdef = 0;
  245. for (;;) {
  246. if (c != ' ')
  247. goto next_char;
  248. #ifdef CONFIG_SMP
  249. /*
  250. * If the BIOS enumerates physical processors before logical,
  251. * maxcpus=N at enumeration-time can be used to disable HT.
  252. */
  253. else if (!memcmp(from, "maxcpus=", 8)) {
  254. extern unsigned int maxcpus;
  255. maxcpus = simple_strtoul(from + 8, NULL, 0);
  256. }
  257. #endif
  258. #ifdef CONFIG_ACPI
  259. /* "acpi=off" disables both ACPI table parsing and interpreter init */
  260. if (fullarg(from,"acpi=off"))
  261. disable_acpi();
  262. if (fullarg(from, "acpi=force")) {
  263. /* add later when we do DMI horrors: */
  264. acpi_force = 1;
  265. acpi_disabled = 0;
  266. }
  267. /* acpi=ht just means: do ACPI MADT parsing
  268. at bootup, but don't enable the full ACPI interpreter */
  269. if (fullarg(from, "acpi=ht")) {
  270. if (!acpi_force)
  271. disable_acpi();
  272. acpi_ht = 1;
  273. }
  274. else if (fullarg(from, "pci=noacpi"))
  275. acpi_disable_pci();
  276. else if (fullarg(from, "acpi=noirq"))
  277. acpi_noirq_set();
  278. else if (fullarg(from, "acpi_sci=edge"))
  279. acpi_sci_flags.trigger = 1;
  280. else if (fullarg(from, "acpi_sci=level"))
  281. acpi_sci_flags.trigger = 3;
  282. else if (fullarg(from, "acpi_sci=high"))
  283. acpi_sci_flags.polarity = 1;
  284. else if (fullarg(from, "acpi_sci=low"))
  285. acpi_sci_flags.polarity = 3;
  286. /* acpi=strict disables out-of-spec workarounds */
  287. else if (fullarg(from, "acpi=strict")) {
  288. acpi_strict = 1;
  289. }
  290. #ifdef CONFIG_X86_IO_APIC
  291. else if (fullarg(from, "acpi_skip_timer_override"))
  292. acpi_skip_timer_override = 1;
  293. #endif
  294. #endif
  295. if (fullarg(from, "disable_timer_pin_1"))
  296. disable_timer_pin_1 = 1;
  297. if (fullarg(from, "enable_timer_pin_1"))
  298. disable_timer_pin_1 = -1;
  299. if (fullarg(from, "nolapic") || fullarg(from, "disableapic")) {
  300. clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
  301. disable_apic = 1;
  302. }
  303. if (fullarg(from, "noapic"))
  304. skip_ioapic_setup = 1;
  305. if (fullarg(from,"apic")) {
  306. skip_ioapic_setup = 0;
  307. ioapic_force = 1;
  308. }
  309. if (!memcmp(from, "mem=", 4))
  310. parse_memopt(from+4, &from);
  311. if (!memcmp(from, "memmap=", 7)) {
  312. /* exactmap option is for used defined memory */
  313. if (!memcmp(from+7, "exactmap", 8)) {
  314. #ifdef CONFIG_CRASH_DUMP
  315. /* If we are doing a crash dump, we
  316. * still need to know the real mem
  317. * size before original memory map is
  318. * reset.
  319. */
  320. saved_max_pfn = e820_end_of_ram();
  321. #endif
  322. from += 8+7;
  323. end_pfn_map = 0;
  324. e820.nr_map = 0;
  325. userdef = 1;
  326. }
  327. else {
  328. parse_memmapopt(from+7, &from);
  329. userdef = 1;
  330. }
  331. }
  332. #ifdef CONFIG_NUMA
  333. if (!memcmp(from, "numa=", 5))
  334. numa_setup(from+5);
  335. #endif
  336. if (!memcmp(from,"iommu=",6)) {
  337. iommu_setup(from+6);
  338. }
  339. if (fullarg(from,"oops=panic"))
  340. panic_on_oops = 1;
  341. if (!memcmp(from, "noexec=", 7))
  342. nonx_setup(from + 7);
  343. #ifdef CONFIG_KEXEC
  344. /* crashkernel=size@addr specifies the location to reserve for
  345. * a crash kernel. By reserving this memory we guarantee
  346. * that linux never set's it up as a DMA target.
  347. * Useful for holding code to do something appropriate
  348. * after a kernel panic.
  349. */
  350. else if (!memcmp(from, "crashkernel=", 12)) {
  351. unsigned long size, base;
  352. size = memparse(from+12, &from);
  353. if (*from == '@') {
  354. base = memparse(from+1, &from);
  355. /* FIXME: Do I want a sanity check
  356. * to validate the memory range?
  357. */
  358. crashk_res.start = base;
  359. crashk_res.end = base + size - 1;
  360. }
  361. }
  362. #endif
  363. #ifdef CONFIG_PROC_VMCORE
  364. /* elfcorehdr= specifies the location of elf core header
  365. * stored by the crashed kernel. This option will be passed
  366. * by kexec loader to the capture kernel.
  367. */
  368. else if(!memcmp(from, "elfcorehdr=", 11))
  369. elfcorehdr_addr = memparse(from+11, &from);
  370. #endif
  371. #ifdef CONFIG_HOTPLUG_CPU
  372. else if (!memcmp(from, "additional_cpus=", 16))
  373. setup_additional_cpus(from+16);
  374. #endif
  375. next_char:
  376. c = *(from++);
  377. if (!c)
  378. break;
  379. if (COMMAND_LINE_SIZE <= ++len)
  380. break;
  381. *(to++) = c;
  382. }
  383. if (userdef) {
  384. printk(KERN_INFO "user-defined physical RAM map:\n");
  385. e820_print_map("user");
  386. }
  387. *to = '\0';
  388. *cmdline_p = command_line;
  389. }
  390. #ifndef CONFIG_NUMA
  391. static void __init
  392. contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
  393. {
  394. unsigned long bootmap_size, bootmap;
  395. bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
  396. bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
  397. if (bootmap == -1L)
  398. panic("Cannot find bootmem map of size %ld\n",bootmap_size);
  399. bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
  400. e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
  401. reserve_bootmem(bootmap, bootmap_size);
  402. }
  403. #endif
  404. #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
  405. struct edd edd;
  406. #ifdef CONFIG_EDD_MODULE
  407. EXPORT_SYMBOL(edd);
  408. #endif
  409. /**
  410. * copy_edd() - Copy the BIOS EDD information
  411. * from boot_params into a safe place.
  412. *
  413. */
  414. static inline void copy_edd(void)
  415. {
  416. memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
  417. memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
  418. edd.mbr_signature_nr = EDD_MBR_SIG_NR;
  419. edd.edd_info_nr = EDD_NR;
  420. }
  421. #else
  422. static inline void copy_edd(void)
  423. {
  424. }
  425. #endif
  426. #define EBDA_ADDR_POINTER 0x40E
  427. unsigned __initdata ebda_addr;
  428. unsigned __initdata ebda_size;
  429. static void discover_ebda(void)
  430. {
  431. /*
  432. * there is a real-mode segmented pointer pointing to the
  433. * 4K EBDA area at 0x40E
  434. */
  435. ebda_addr = *(unsigned short *)EBDA_ADDR_POINTER;
  436. ebda_addr <<= 4;
  437. ebda_size = *(unsigned short *)(unsigned long)ebda_addr;
  438. /* Round EBDA up to pages */
  439. if (ebda_size == 0)
  440. ebda_size = 1;
  441. ebda_size <<= 10;
  442. ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
  443. if (ebda_size > 64*1024)
  444. ebda_size = 64*1024;
  445. }
  446. void __init setup_arch(char **cmdline_p)
  447. {
  448. unsigned long kernel_end;
  449. ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
  450. screen_info = SCREEN_INFO;
  451. edid_info = EDID_INFO;
  452. saved_video_mode = SAVED_VIDEO_MODE;
  453. bootloader_type = LOADER_TYPE;
  454. #ifdef CONFIG_BLK_DEV_RAM
  455. rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
  456. rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
  457. rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
  458. #endif
  459. setup_memory_region();
  460. copy_edd();
  461. if (!MOUNT_ROOT_RDONLY)
  462. root_mountflags &= ~MS_RDONLY;
  463. init_mm.start_code = (unsigned long) &_text;
  464. init_mm.end_code = (unsigned long) &_etext;
  465. init_mm.end_data = (unsigned long) &_edata;
  466. init_mm.brk = (unsigned long) &_end;
  467. code_resource.start = virt_to_phys(&_text);
  468. code_resource.end = virt_to_phys(&_etext)-1;
  469. data_resource.start = virt_to_phys(&_etext);
  470. data_resource.end = virt_to_phys(&_edata)-1;
  471. parse_cmdline_early(cmdline_p);
  472. early_identify_cpu(&boot_cpu_data);
  473. /*
  474. * partially used pages are not usable - thus
  475. * we are rounding upwards:
  476. */
  477. end_pfn = e820_end_of_ram();
  478. num_physpages = end_pfn; /* for pfn_valid */
  479. check_efer();
  480. discover_ebda();
  481. init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
  482. dmi_scan_machine();
  483. zap_low_mappings(0);
  484. #ifdef CONFIG_ACPI
  485. /*
  486. * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
  487. * Call this early for SRAT node setup.
  488. */
  489. acpi_boot_table_init();
  490. #endif
  491. #ifdef CONFIG_ACPI_NUMA
  492. /*
  493. * Parse SRAT to discover nodes.
  494. */
  495. acpi_numa_init();
  496. #endif
  497. #ifdef CONFIG_NUMA
  498. numa_initmem_init(0, end_pfn);
  499. #else
  500. contig_initmem_init(0, end_pfn);
  501. #endif
  502. /* Reserve direct mapping */
  503. reserve_bootmem_generic(table_start << PAGE_SHIFT,
  504. (table_end - table_start) << PAGE_SHIFT);
  505. /* reserve kernel */
  506. kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
  507. reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
  508. /*
  509. * reserve physical page 0 - it's a special BIOS page on many boxes,
  510. * enabling clean reboots, SMP operation, laptop functions.
  511. */
  512. reserve_bootmem_generic(0, PAGE_SIZE);
  513. /* reserve ebda region */
  514. if (ebda_addr)
  515. reserve_bootmem_generic(ebda_addr, ebda_size);
  516. #ifdef CONFIG_SMP
  517. /*
  518. * But first pinch a few for the stack/trampoline stuff
  519. * FIXME: Don't need the extra page at 4K, but need to fix
  520. * trampoline before removing it. (see the GDT stuff)
  521. */
  522. reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
  523. /* Reserve SMP trampoline */
  524. reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
  525. #endif
  526. #ifdef CONFIG_ACPI_SLEEP
  527. /*
  528. * Reserve low memory region for sleep support.
  529. */
  530. acpi_reserve_bootmem();
  531. #endif
  532. #ifdef CONFIG_X86_LOCAL_APIC
  533. /*
  534. * Find and reserve possible boot-time SMP configuration:
  535. */
  536. find_smp_config();
  537. #endif
  538. #ifdef CONFIG_BLK_DEV_INITRD
  539. if (LOADER_TYPE && INITRD_START) {
  540. if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
  541. reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
  542. initrd_start =
  543. INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
  544. initrd_end = initrd_start+INITRD_SIZE;
  545. }
  546. else {
  547. printk(KERN_ERR "initrd extends beyond end of memory "
  548. "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
  549. (unsigned long)(INITRD_START + INITRD_SIZE),
  550. (unsigned long)(end_pfn << PAGE_SHIFT));
  551. initrd_start = 0;
  552. }
  553. }
  554. #endif
  555. #ifdef CONFIG_KEXEC
  556. if (crashk_res.start != crashk_res.end) {
  557. reserve_bootmem_generic(crashk_res.start,
  558. crashk_res.end - crashk_res.start + 1);
  559. }
  560. #endif
  561. paging_init();
  562. check_ioapic();
  563. /*
  564. * set this early, so we dont allocate cpu0
  565. * if MADT list doesnt list BSP first
  566. * mpparse.c/MP_processor_info() allocates logical cpu numbers.
  567. */
  568. cpu_set(0, cpu_present_map);
  569. #ifdef CONFIG_ACPI
  570. /*
  571. * Read APIC and some other early information from ACPI tables.
  572. */
  573. acpi_boot_init();
  574. #endif
  575. init_cpu_to_node();
  576. #ifdef CONFIG_X86_LOCAL_APIC
  577. /*
  578. * get boot-time SMP configuration:
  579. */
  580. if (smp_found_config)
  581. get_smp_config();
  582. init_apic_mappings();
  583. #endif
  584. /*
  585. * Request address space for all standard RAM and ROM resources
  586. * and also for regions reported as reserved by the e820.
  587. */
  588. probe_roms();
  589. e820_reserve_resources();
  590. request_resource(&iomem_resource, &video_ram_resource);
  591. {
  592. unsigned i;
  593. /* request I/O space for devices used on all i[345]86 PCs */
  594. for (i = 0; i < STANDARD_IO_RESOURCES; i++)
  595. request_resource(&ioport_resource, &standard_io_resources[i]);
  596. }
  597. e820_setup_gap();
  598. #ifdef CONFIG_IOMMU
  599. iommu_hole_init();
  600. #endif
  601. #ifdef CONFIG_VT
  602. #if defined(CONFIG_VGA_CONSOLE)
  603. conswitchp = &vga_con;
  604. #elif defined(CONFIG_DUMMY_CONSOLE)
  605. conswitchp = &dummy_con;
  606. #endif
  607. #endif
  608. }
  609. static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
  610. {
  611. unsigned int *v;
  612. if (c->extended_cpuid_level < 0x80000004)
  613. return 0;
  614. v = (unsigned int *) c->x86_model_id;
  615. cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
  616. cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
  617. cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
  618. c->x86_model_id[48] = 0;
  619. return 1;
  620. }
  621. static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
  622. {
  623. unsigned int n, dummy, eax, ebx, ecx, edx;
  624. n = c->extended_cpuid_level;
  625. if (n >= 0x80000005) {
  626. cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
  627. printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
  628. edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
  629. c->x86_cache_size=(ecx>>24)+(edx>>24);
  630. /* On K8 L1 TLB is inclusive, so don't count it */
  631. c->x86_tlbsize = 0;
  632. }
  633. if (n >= 0x80000006) {
  634. cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
  635. ecx = cpuid_ecx(0x80000006);
  636. c->x86_cache_size = ecx >> 16;
  637. c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
  638. printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
  639. c->x86_cache_size, ecx & 0xFF);
  640. }
  641. if (n >= 0x80000007)
  642. cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
  643. if (n >= 0x80000008) {
  644. cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
  645. c->x86_virt_bits = (eax >> 8) & 0xff;
  646. c->x86_phys_bits = eax & 0xff;
  647. }
  648. }
  649. #ifdef CONFIG_NUMA
  650. static int nearby_node(int apicid)
  651. {
  652. int i;
  653. for (i = apicid - 1; i >= 0; i--) {
  654. int node = apicid_to_node[i];
  655. if (node != NUMA_NO_NODE && node_online(node))
  656. return node;
  657. }
  658. for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
  659. int node = apicid_to_node[i];
  660. if (node != NUMA_NO_NODE && node_online(node))
  661. return node;
  662. }
  663. return first_node(node_online_map); /* Shouldn't happen */
  664. }
  665. #endif
  666. /*
  667. * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  668. * Assumes number of cores is a power of two.
  669. */
  670. static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
  671. {
  672. #ifdef CONFIG_SMP
  673. int cpu = smp_processor_id();
  674. unsigned bits;
  675. #ifdef CONFIG_NUMA
  676. int node = 0;
  677. unsigned apicid = hard_smp_processor_id();
  678. #endif
  679. unsigned ecx = cpuid_ecx(0x80000008);
  680. c->x86_max_cores = (ecx & 0xff) + 1;
  681. /* CPU telling us the core id bits shift? */
  682. bits = (ecx >> 12) & 0xF;
  683. /* Otherwise recompute */
  684. if (bits == 0) {
  685. while ((1 << bits) < c->x86_max_cores)
  686. bits++;
  687. }
  688. /* Low order bits define the core id (index of core in socket) */
  689. cpu_core_id[cpu] = phys_proc_id[cpu] & ((1 << bits)-1);
  690. /* Convert the APIC ID into the socket ID */
  691. phys_proc_id[cpu] = phys_pkg_id(bits);
  692. #ifdef CONFIG_NUMA
  693. node = phys_proc_id[cpu];
  694. if (apicid_to_node[apicid] != NUMA_NO_NODE)
  695. node = apicid_to_node[apicid];
  696. if (!node_online(node)) {
  697. /* Two possibilities here:
  698. - The CPU is missing memory and no node was created.
  699. In that case try picking one from a nearby CPU
  700. - The APIC IDs differ from the HyperTransport node IDs
  701. which the K8 northbridge parsing fills in.
  702. Assume they are all increased by a constant offset,
  703. but in the same order as the HT nodeids.
  704. If that doesn't result in a usable node fall back to the
  705. path for the previous case. */
  706. int ht_nodeid = apicid - (phys_proc_id[0] << bits);
  707. if (ht_nodeid >= 0 &&
  708. apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
  709. node = apicid_to_node[ht_nodeid];
  710. /* Pick a nearby node */
  711. if (!node_online(node))
  712. node = nearby_node(apicid);
  713. }
  714. numa_set_node(cpu, node);
  715. printk(KERN_INFO "CPU %d/%x(%d) -> Node %d -> Core %d\n",
  716. cpu, apicid, c->x86_max_cores, node, cpu_core_id[cpu]);
  717. #endif
  718. #endif
  719. }
  720. static int __init init_amd(struct cpuinfo_x86 *c)
  721. {
  722. int r;
  723. unsigned level;
  724. #ifdef CONFIG_SMP
  725. unsigned long value;
  726. /*
  727. * Disable TLB flush filter by setting HWCR.FFDIS on K8
  728. * bit 6 of msr C001_0015
  729. *
  730. * Errata 63 for SH-B3 steppings
  731. * Errata 122 for all steppings (F+ have it disabled by default)
  732. */
  733. if (c->x86 == 15) {
  734. rdmsrl(MSR_K8_HWCR, value);
  735. value |= 1 << 6;
  736. wrmsrl(MSR_K8_HWCR, value);
  737. }
  738. #endif
  739. /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  740. 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
  741. clear_bit(0*32+31, &c->x86_capability);
  742. /* On C+ stepping K8 rep microcode works well for copy/memset */
  743. level = cpuid_eax(1);
  744. if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
  745. set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
  746. /* Enable workaround for FXSAVE leak */
  747. if (c->x86 >= 6)
  748. set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
  749. r = get_model_name(c);
  750. if (!r) {
  751. switch (c->x86) {
  752. case 15:
  753. /* Should distinguish Models here, but this is only
  754. a fallback anyways. */
  755. strcpy(c->x86_model_id, "Hammer");
  756. break;
  757. }
  758. }
  759. display_cacheinfo(c);
  760. /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
  761. if (c->x86_power & (1<<8))
  762. set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
  763. /* Multi core CPU? */
  764. if (c->extended_cpuid_level >= 0x80000008)
  765. amd_detect_cmp(c);
  766. /* Fix cpuid4 emulation for more */
  767. num_cache_leaves = 3;
  768. return r;
  769. }
  770. static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
  771. {
  772. #ifdef CONFIG_SMP
  773. u32 eax, ebx, ecx, edx;
  774. int index_msb, core_bits;
  775. int cpu = smp_processor_id();
  776. cpuid(1, &eax, &ebx, &ecx, &edx);
  777. if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
  778. return;
  779. smp_num_siblings = (ebx & 0xff0000) >> 16;
  780. if (smp_num_siblings == 1) {
  781. printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
  782. } else if (smp_num_siblings > 1 ) {
  783. if (smp_num_siblings > NR_CPUS) {
  784. printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
  785. smp_num_siblings = 1;
  786. return;
  787. }
  788. index_msb = get_count_order(smp_num_siblings);
  789. phys_proc_id[cpu] = phys_pkg_id(index_msb);
  790. printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
  791. phys_proc_id[cpu]);
  792. smp_num_siblings = smp_num_siblings / c->x86_max_cores;
  793. index_msb = get_count_order(smp_num_siblings) ;
  794. core_bits = get_count_order(c->x86_max_cores);
  795. cpu_core_id[cpu] = phys_pkg_id(index_msb) &
  796. ((1 << core_bits) - 1);
  797. if (c->x86_max_cores > 1)
  798. printk(KERN_INFO "CPU: Processor Core ID: %d\n",
  799. cpu_core_id[cpu]);
  800. }
  801. #endif
  802. }
  803. /*
  804. * find out the number of processor cores on the die
  805. */
  806. static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
  807. {
  808. unsigned int eax;
  809. if (c->cpuid_level < 4)
  810. return 1;
  811. __asm__("cpuid"
  812. : "=a" (eax)
  813. : "0" (4), "c" (0)
  814. : "bx", "dx");
  815. if (eax & 0x1f)
  816. return ((eax >> 26) + 1);
  817. else
  818. return 1;
  819. }
  820. static void srat_detect_node(void)
  821. {
  822. #ifdef CONFIG_NUMA
  823. unsigned node;
  824. int cpu = smp_processor_id();
  825. /* Don't do the funky fallback heuristics the AMD version employs
  826. for now. */
  827. node = apicid_to_node[hard_smp_processor_id()];
  828. if (node == NUMA_NO_NODE)
  829. node = first_node(node_online_map);
  830. numa_set_node(cpu, node);
  831. if (acpi_numa > 0)
  832. printk(KERN_INFO "CPU %d -> Node %d\n", cpu, node);
  833. #endif
  834. }
  835. static void __cpuinit init_intel(struct cpuinfo_x86 *c)
  836. {
  837. /* Cache sizes */
  838. unsigned n;
  839. init_intel_cacheinfo(c);
  840. n = c->extended_cpuid_level;
  841. if (n >= 0x80000008) {
  842. unsigned eax = cpuid_eax(0x80000008);
  843. c->x86_virt_bits = (eax >> 8) & 0xff;
  844. c->x86_phys_bits = eax & 0xff;
  845. /* CPUID workaround for Intel 0F34 CPU */
  846. if (c->x86_vendor == X86_VENDOR_INTEL &&
  847. c->x86 == 0xF && c->x86_model == 0x3 &&
  848. c->x86_mask == 0x4)
  849. c->x86_phys_bits = 36;
  850. }
  851. if (c->x86 == 15)
  852. c->x86_cache_alignment = c->x86_clflush_size * 2;
  853. if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  854. (c->x86 == 0x6 && c->x86_model >= 0x0e))
  855. set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
  856. set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
  857. c->x86_max_cores = intel_num_cpu_cores(c);
  858. srat_detect_node();
  859. }
  860. static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
  861. {
  862. char *v = c->x86_vendor_id;
  863. if (!strcmp(v, "AuthenticAMD"))
  864. c->x86_vendor = X86_VENDOR_AMD;
  865. else if (!strcmp(v, "GenuineIntel"))
  866. c->x86_vendor = X86_VENDOR_INTEL;
  867. else
  868. c->x86_vendor = X86_VENDOR_UNKNOWN;
  869. }
  870. struct cpu_model_info {
  871. int vendor;
  872. int family;
  873. char *model_names[16];
  874. };
  875. /* Do some early cpuid on the boot CPU to get some parameter that are
  876. needed before check_bugs. Everything advanced is in identify_cpu
  877. below. */
  878. void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
  879. {
  880. u32 tfms;
  881. c->loops_per_jiffy = loops_per_jiffy;
  882. c->x86_cache_size = -1;
  883. c->x86_vendor = X86_VENDOR_UNKNOWN;
  884. c->x86_model = c->x86_mask = 0; /* So far unknown... */
  885. c->x86_vendor_id[0] = '\0'; /* Unset */
  886. c->x86_model_id[0] = '\0'; /* Unset */
  887. c->x86_clflush_size = 64;
  888. c->x86_cache_alignment = c->x86_clflush_size;
  889. c->x86_max_cores = 1;
  890. c->extended_cpuid_level = 0;
  891. memset(&c->x86_capability, 0, sizeof c->x86_capability);
  892. /* Get vendor name */
  893. cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
  894. (unsigned int *)&c->x86_vendor_id[0],
  895. (unsigned int *)&c->x86_vendor_id[8],
  896. (unsigned int *)&c->x86_vendor_id[4]);
  897. get_cpu_vendor(c);
  898. /* Initialize the standard set of capabilities */
  899. /* Note that the vendor-specific code below might override */
  900. /* Intel-defined flags: level 0x00000001 */
  901. if (c->cpuid_level >= 0x00000001) {
  902. __u32 misc;
  903. cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
  904. &c->x86_capability[0]);
  905. c->x86 = (tfms >> 8) & 0xf;
  906. c->x86_model = (tfms >> 4) & 0xf;
  907. c->x86_mask = tfms & 0xf;
  908. if (c->x86 == 0xf)
  909. c->x86 += (tfms >> 20) & 0xff;
  910. if (c->x86 >= 0x6)
  911. c->x86_model += ((tfms >> 16) & 0xF) << 4;
  912. if (c->x86_capability[0] & (1<<19))
  913. c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
  914. } else {
  915. /* Have CPUID level 0 only - unheard of */
  916. c->x86 = 4;
  917. }
  918. #ifdef CONFIG_SMP
  919. phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
  920. #endif
  921. }
  922. /*
  923. * This does the hard work of actually picking apart the CPU stuff...
  924. */
  925. void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
  926. {
  927. int i;
  928. u32 xlvl;
  929. early_identify_cpu(c);
  930. /* AMD-defined flags: level 0x80000001 */
  931. xlvl = cpuid_eax(0x80000000);
  932. c->extended_cpuid_level = xlvl;
  933. if ((xlvl & 0xffff0000) == 0x80000000) {
  934. if (xlvl >= 0x80000001) {
  935. c->x86_capability[1] = cpuid_edx(0x80000001);
  936. c->x86_capability[6] = cpuid_ecx(0x80000001);
  937. }
  938. if (xlvl >= 0x80000004)
  939. get_model_name(c); /* Default name */
  940. }
  941. /* Transmeta-defined flags: level 0x80860001 */
  942. xlvl = cpuid_eax(0x80860000);
  943. if ((xlvl & 0xffff0000) == 0x80860000) {
  944. /* Don't set x86_cpuid_level here for now to not confuse. */
  945. if (xlvl >= 0x80860001)
  946. c->x86_capability[2] = cpuid_edx(0x80860001);
  947. }
  948. c->apicid = phys_pkg_id(0);
  949. /*
  950. * Vendor-specific initialization. In this section we
  951. * canonicalize the feature flags, meaning if there are
  952. * features a certain CPU supports which CPUID doesn't
  953. * tell us, CPUID claiming incorrect flags, or other bugs,
  954. * we handle them here.
  955. *
  956. * At the end of this section, c->x86_capability better
  957. * indicate the features this CPU genuinely supports!
  958. */
  959. switch (c->x86_vendor) {
  960. case X86_VENDOR_AMD:
  961. init_amd(c);
  962. break;
  963. case X86_VENDOR_INTEL:
  964. init_intel(c);
  965. break;
  966. case X86_VENDOR_UNKNOWN:
  967. default:
  968. display_cacheinfo(c);
  969. break;
  970. }
  971. select_idle_routine(c);
  972. detect_ht(c);
  973. /*
  974. * On SMP, boot_cpu_data holds the common feature set between
  975. * all CPUs; so make sure that we indicate which features are
  976. * common between the CPUs. The first time this routine gets
  977. * executed, c == &boot_cpu_data.
  978. */
  979. if (c != &boot_cpu_data) {
  980. /* AND the already accumulated flags with these */
  981. for (i = 0 ; i < NCAPINTS ; i++)
  982. boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
  983. }
  984. #ifdef CONFIG_X86_MCE
  985. mcheck_init(c);
  986. #endif
  987. if (c == &boot_cpu_data)
  988. mtrr_bp_init();
  989. else
  990. mtrr_ap_init();
  991. #ifdef CONFIG_NUMA
  992. numa_add_cpu(smp_processor_id());
  993. #endif
  994. }
  995. void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
  996. {
  997. if (c->x86_model_id[0])
  998. printk("%s", c->x86_model_id);
  999. if (c->x86_mask || c->cpuid_level >= 0)
  1000. printk(" stepping %02x\n", c->x86_mask);
  1001. else
  1002. printk("\n");
  1003. }
  1004. /*
  1005. * Get CPU information for use by the procfs.
  1006. */
  1007. static int show_cpuinfo(struct seq_file *m, void *v)
  1008. {
  1009. struct cpuinfo_x86 *c = v;
  1010. /*
  1011. * These flag bits must match the definitions in <asm/cpufeature.h>.
  1012. * NULL means this bit is undefined or reserved; either way it doesn't
  1013. * have meaning as far as Linux is concerned. Note that it's important
  1014. * to realize there is a difference between this table and CPUID -- if
  1015. * applications want to get the raw CPUID data, they should access
  1016. * /dev/cpu/<cpu_nr>/cpuid instead.
  1017. */
  1018. static char *x86_cap_flags[] = {
  1019. /* Intel-defined */
  1020. "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
  1021. "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
  1022. "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
  1023. "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
  1024. /* AMD-defined */
  1025. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1026. NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
  1027. NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
  1028. NULL, "fxsr_opt", "rdtscp", NULL, NULL, "lm", "3dnowext", "3dnow",
  1029. /* Transmeta-defined */
  1030. "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
  1031. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1032. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1033. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1034. /* Other (Linux-defined) */
  1035. "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
  1036. "constant_tsc", NULL, NULL,
  1037. "up", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1038. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1039. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1040. /* Intel-defined (#2) */
  1041. "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
  1042. "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
  1043. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1044. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1045. /* VIA/Cyrix/Centaur-defined */
  1046. NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
  1047. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1048. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1049. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1050. /* AMD-defined (#2) */
  1051. "lahf_lm", "cmp_legacy", "svm", NULL, "cr8_legacy", NULL, NULL, NULL,
  1052. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1053. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1054. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1055. };
  1056. static char *x86_power_flags[] = {
  1057. "ts", /* temperature sensor */
  1058. "fid", /* frequency id control */
  1059. "vid", /* voltage id control */
  1060. "ttp", /* thermal trip */
  1061. "tm",
  1062. "stc",
  1063. NULL,
  1064. /* nothing */ /* constant_tsc - moved to flags */
  1065. };
  1066. #ifdef CONFIG_SMP
  1067. if (!cpu_online(c-cpu_data))
  1068. return 0;
  1069. #endif
  1070. seq_printf(m,"processor\t: %u\n"
  1071. "vendor_id\t: %s\n"
  1072. "cpu family\t: %d\n"
  1073. "model\t\t: %d\n"
  1074. "model name\t: %s\n",
  1075. (unsigned)(c-cpu_data),
  1076. c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
  1077. c->x86,
  1078. (int)c->x86_model,
  1079. c->x86_model_id[0] ? c->x86_model_id : "unknown");
  1080. if (c->x86_mask || c->cpuid_level >= 0)
  1081. seq_printf(m, "stepping\t: %d\n", c->x86_mask);
  1082. else
  1083. seq_printf(m, "stepping\t: unknown\n");
  1084. if (cpu_has(c,X86_FEATURE_TSC)) {
  1085. unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
  1086. if (!freq)
  1087. freq = cpu_khz;
  1088. seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
  1089. freq / 1000, (freq % 1000));
  1090. }
  1091. /* Cache size */
  1092. if (c->x86_cache_size >= 0)
  1093. seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
  1094. #ifdef CONFIG_SMP
  1095. if (smp_num_siblings * c->x86_max_cores > 1) {
  1096. int cpu = c - cpu_data;
  1097. seq_printf(m, "physical id\t: %d\n", phys_proc_id[cpu]);
  1098. seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
  1099. seq_printf(m, "core id\t\t: %d\n", cpu_core_id[cpu]);
  1100. seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
  1101. }
  1102. #endif
  1103. seq_printf(m,
  1104. "fpu\t\t: yes\n"
  1105. "fpu_exception\t: yes\n"
  1106. "cpuid level\t: %d\n"
  1107. "wp\t\t: yes\n"
  1108. "flags\t\t:",
  1109. c->cpuid_level);
  1110. {
  1111. int i;
  1112. for ( i = 0 ; i < 32*NCAPINTS ; i++ )
  1113. if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
  1114. seq_printf(m, " %s", x86_cap_flags[i]);
  1115. }
  1116. seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
  1117. c->loops_per_jiffy/(500000/HZ),
  1118. (c->loops_per_jiffy/(5000/HZ)) % 100);
  1119. if (c->x86_tlbsize > 0)
  1120. seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
  1121. seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
  1122. seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
  1123. seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
  1124. c->x86_phys_bits, c->x86_virt_bits);
  1125. seq_printf(m, "power management:");
  1126. {
  1127. unsigned i;
  1128. for (i = 0; i < 32; i++)
  1129. if (c->x86_power & (1 << i)) {
  1130. if (i < ARRAY_SIZE(x86_power_flags) &&
  1131. x86_power_flags[i])
  1132. seq_printf(m, "%s%s",
  1133. x86_power_flags[i][0]?" ":"",
  1134. x86_power_flags[i]);
  1135. else
  1136. seq_printf(m, " [%d]", i);
  1137. }
  1138. }
  1139. seq_printf(m, "\n\n");
  1140. return 0;
  1141. }
  1142. static void *c_start(struct seq_file *m, loff_t *pos)
  1143. {
  1144. return *pos < NR_CPUS ? cpu_data + *pos : NULL;
  1145. }
  1146. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  1147. {
  1148. ++*pos;
  1149. return c_start(m, pos);
  1150. }
  1151. static void c_stop(struct seq_file *m, void *v)
  1152. {
  1153. }
  1154. struct seq_operations cpuinfo_op = {
  1155. .start =c_start,
  1156. .next = c_next,
  1157. .stop = c_stop,
  1158. .show = show_cpuinfo,
  1159. };
  1160. #ifdef CONFIG_INPUT_PCSPKR
  1161. #include <linux/platform_device.h>
  1162. static __init int add_pcspkr(void)
  1163. {
  1164. struct platform_device *pd;
  1165. int ret;
  1166. pd = platform_device_alloc("pcspkr", -1);
  1167. if (!pd)
  1168. return -ENOMEM;
  1169. ret = platform_device_add(pd);
  1170. if (ret)
  1171. platform_device_put(pd);
  1172. return ret;
  1173. }
  1174. device_initcall(add_pcspkr);
  1175. #endif