iwl-agn.c 110 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #define DRV_VERSION IWLWIFI_VERSION VD
  67. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  68. MODULE_VERSION(DRV_VERSION);
  69. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  70. MODULE_LICENSE("GPL");
  71. MODULE_ALIAS("iwl4965");
  72. /*************** STATION TABLE MANAGEMENT ****
  73. * mac80211 should be examined to determine if sta_info is duplicating
  74. * the functionality provided here
  75. */
  76. /**************************************************************/
  77. /**
  78. * iwl_commit_rxon - commit staging_rxon to hardware
  79. *
  80. * The RXON command in staging_rxon is committed to the hardware and
  81. * the active_rxon structure is updated with the new data. This
  82. * function correctly transitions out of the RXON_ASSOC_MSK state if
  83. * a HW tune is required based on the RXON structure changes.
  84. */
  85. int iwl_commit_rxon(struct iwl_priv *priv)
  86. {
  87. /* cast away the const for active_rxon in this function */
  88. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  89. int ret;
  90. bool new_assoc =
  91. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  92. if (!iwl_is_alive(priv))
  93. return -EBUSY;
  94. /* always get timestamp with Rx frame */
  95. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  96. ret = iwl_check_rxon_cmd(priv);
  97. if (ret) {
  98. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  99. return -EINVAL;
  100. }
  101. /*
  102. * receive commit_rxon request
  103. * abort any previous channel switch if still in process
  104. */
  105. if (priv->switch_rxon.switch_in_progress &&
  106. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  107. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  108. le16_to_cpu(priv->switch_rxon.channel));
  109. priv->switch_rxon.switch_in_progress = false;
  110. }
  111. /* If we don't need to send a full RXON, we can use
  112. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  113. * and other flags for the current radio configuration. */
  114. if (!iwl_full_rxon_required(priv)) {
  115. ret = iwl_send_rxon_assoc(priv);
  116. if (ret) {
  117. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  118. return ret;
  119. }
  120. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  121. iwl_print_rx_config_cmd(priv);
  122. return 0;
  123. }
  124. /* station table will be cleared */
  125. priv->assoc_station_added = 0;
  126. /* If we are currently associated and the new config requires
  127. * an RXON_ASSOC and the new config wants the associated mask enabled,
  128. * we must clear the associated from the active configuration
  129. * before we apply the new config */
  130. if (iwl_is_associated(priv) && new_assoc) {
  131. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  132. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  133. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  134. sizeof(struct iwl_rxon_cmd),
  135. &priv->active_rxon);
  136. /* If the mask clearing failed then we set
  137. * active_rxon back to what it was previously */
  138. if (ret) {
  139. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  140. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  141. return ret;
  142. }
  143. }
  144. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  145. "* with%s RXON_FILTER_ASSOC_MSK\n"
  146. "* channel = %d\n"
  147. "* bssid = %pM\n",
  148. (new_assoc ? "" : "out"),
  149. le16_to_cpu(priv->staging_rxon.channel),
  150. priv->staging_rxon.bssid_addr);
  151. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  152. /* Apply the new configuration
  153. * RXON unassoc clears the station table in uCode, send it before
  154. * we add the bcast station. If assoc bit is set, we will send RXON
  155. * after having added the bcast and bssid station.
  156. */
  157. if (!new_assoc) {
  158. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  159. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  160. if (ret) {
  161. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  162. return ret;
  163. }
  164. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  165. }
  166. iwl_clear_stations_table(priv);
  167. priv->start_calib = 0;
  168. /* Add the broadcast address so we can send broadcast frames */
  169. priv->cfg->ops->lib->add_bcast_station(priv);
  170. /* If we have set the ASSOC_MSK and we are in BSS mode then
  171. * add the IWL_AP_ID to the station rate table */
  172. if (new_assoc) {
  173. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  174. ret = iwl_rxon_add_station(priv,
  175. priv->active_rxon.bssid_addr, 1);
  176. if (ret == IWL_INVALID_STATION) {
  177. IWL_ERR(priv,
  178. "Error adding AP address for TX.\n");
  179. return -EIO;
  180. }
  181. priv->assoc_station_added = 1;
  182. if (priv->default_wep_key &&
  183. iwl_send_static_wepkey_cmd(priv, 0))
  184. IWL_ERR(priv,
  185. "Could not send WEP static key.\n");
  186. }
  187. /*
  188. * allow CTS-to-self if possible for new association.
  189. * this is relevant only for 5000 series and up,
  190. * but will not damage 4965
  191. */
  192. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  193. /* Apply the new configuration
  194. * RXON assoc doesn't clear the station table in uCode,
  195. */
  196. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  197. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  198. if (ret) {
  199. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  200. return ret;
  201. }
  202. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  203. }
  204. iwl_print_rx_config_cmd(priv);
  205. iwl_init_sensitivity(priv);
  206. /* If we issue a new RXON command which required a tune then we must
  207. * send a new TXPOWER command or we won't be able to Tx any frames */
  208. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  209. if (ret) {
  210. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  211. return ret;
  212. }
  213. return 0;
  214. }
  215. void iwl_update_chain_flags(struct iwl_priv *priv)
  216. {
  217. if (priv->cfg->ops->hcmd->set_rxon_chain)
  218. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  219. iwlcore_commit_rxon(priv);
  220. }
  221. static void iwl_clear_free_frames(struct iwl_priv *priv)
  222. {
  223. struct list_head *element;
  224. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  225. priv->frames_count);
  226. while (!list_empty(&priv->free_frames)) {
  227. element = priv->free_frames.next;
  228. list_del(element);
  229. kfree(list_entry(element, struct iwl_frame, list));
  230. priv->frames_count--;
  231. }
  232. if (priv->frames_count) {
  233. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  234. priv->frames_count);
  235. priv->frames_count = 0;
  236. }
  237. }
  238. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  239. {
  240. struct iwl_frame *frame;
  241. struct list_head *element;
  242. if (list_empty(&priv->free_frames)) {
  243. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  244. if (!frame) {
  245. IWL_ERR(priv, "Could not allocate frame!\n");
  246. return NULL;
  247. }
  248. priv->frames_count++;
  249. return frame;
  250. }
  251. element = priv->free_frames.next;
  252. list_del(element);
  253. return list_entry(element, struct iwl_frame, list);
  254. }
  255. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  256. {
  257. memset(frame, 0, sizeof(*frame));
  258. list_add(&frame->list, &priv->free_frames);
  259. }
  260. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  261. struct ieee80211_hdr *hdr,
  262. int left)
  263. {
  264. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  265. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  266. (priv->iw_mode != NL80211_IFTYPE_AP)))
  267. return 0;
  268. if (priv->ibss_beacon->len > left)
  269. return 0;
  270. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  271. return priv->ibss_beacon->len;
  272. }
  273. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  274. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  275. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  276. u8 *beacon, u32 frame_size)
  277. {
  278. u16 tim_idx;
  279. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  280. /*
  281. * The index is relative to frame start but we start looking at the
  282. * variable-length part of the beacon.
  283. */
  284. tim_idx = mgmt->u.beacon.variable - beacon;
  285. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  286. while ((tim_idx < (frame_size - 2)) &&
  287. (beacon[tim_idx] != WLAN_EID_TIM))
  288. tim_idx += beacon[tim_idx+1] + 2;
  289. /* If TIM field was found, set variables */
  290. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  291. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  292. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  293. } else
  294. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  295. }
  296. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  297. struct iwl_frame *frame)
  298. {
  299. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  300. u32 frame_size;
  301. u32 rate_flags;
  302. u32 rate;
  303. /*
  304. * We have to set up the TX command, the TX Beacon command, and the
  305. * beacon contents.
  306. */
  307. /* Initialize memory */
  308. tx_beacon_cmd = &frame->u.beacon;
  309. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  310. /* Set up TX beacon contents */
  311. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  312. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  313. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  314. return 0;
  315. /* Set up TX command fields */
  316. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  317. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  318. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  319. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  320. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  321. /* Set up TX beacon command fields */
  322. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  323. frame_size);
  324. /* Set up packet rate and flags */
  325. rate = iwl_rate_get_lowest_plcp(priv);
  326. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  327. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  328. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  329. rate_flags |= RATE_MCS_CCK_MSK;
  330. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  331. rate_flags);
  332. return sizeof(*tx_beacon_cmd) + frame_size;
  333. }
  334. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  335. {
  336. struct iwl_frame *frame;
  337. unsigned int frame_size;
  338. int rc;
  339. frame = iwl_get_free_frame(priv);
  340. if (!frame) {
  341. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  342. "command.\n");
  343. return -ENOMEM;
  344. }
  345. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  346. if (!frame_size) {
  347. IWL_ERR(priv, "Error configuring the beacon command\n");
  348. iwl_free_frame(priv, frame);
  349. return -EINVAL;
  350. }
  351. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  352. &frame->u.cmd[0]);
  353. iwl_free_frame(priv, frame);
  354. return rc;
  355. }
  356. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  357. {
  358. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  359. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  360. if (sizeof(dma_addr_t) > sizeof(u32))
  361. addr |=
  362. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  363. return addr;
  364. }
  365. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  366. {
  367. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  368. return le16_to_cpu(tb->hi_n_len) >> 4;
  369. }
  370. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  371. dma_addr_t addr, u16 len)
  372. {
  373. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  374. u16 hi_n_len = len << 4;
  375. put_unaligned_le32(addr, &tb->lo);
  376. if (sizeof(dma_addr_t) > sizeof(u32))
  377. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  378. tb->hi_n_len = cpu_to_le16(hi_n_len);
  379. tfd->num_tbs = idx + 1;
  380. }
  381. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  382. {
  383. return tfd->num_tbs & 0x1f;
  384. }
  385. /**
  386. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  387. * @priv - driver private data
  388. * @txq - tx queue
  389. *
  390. * Does NOT advance any TFD circular buffer read/write indexes
  391. * Does NOT free the TFD itself (which is within circular buffer)
  392. */
  393. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  394. {
  395. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  396. struct iwl_tfd *tfd;
  397. struct pci_dev *dev = priv->pci_dev;
  398. int index = txq->q.read_ptr;
  399. int i;
  400. int num_tbs;
  401. tfd = &tfd_tmp[index];
  402. /* Sanity check on number of chunks */
  403. num_tbs = iwl_tfd_get_num_tbs(tfd);
  404. if (num_tbs >= IWL_NUM_OF_TBS) {
  405. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  406. /* @todo issue fatal error, it is quite serious situation */
  407. return;
  408. }
  409. /* Unmap tx_cmd */
  410. if (num_tbs)
  411. pci_unmap_single(dev,
  412. pci_unmap_addr(&txq->meta[index], mapping),
  413. pci_unmap_len(&txq->meta[index], len),
  414. PCI_DMA_BIDIRECTIONAL);
  415. /* Unmap chunks, if any. */
  416. for (i = 1; i < num_tbs; i++) {
  417. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  418. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  419. if (txq->txb) {
  420. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  421. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  422. }
  423. }
  424. }
  425. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  426. struct iwl_tx_queue *txq,
  427. dma_addr_t addr, u16 len,
  428. u8 reset, u8 pad)
  429. {
  430. struct iwl_queue *q;
  431. struct iwl_tfd *tfd, *tfd_tmp;
  432. u32 num_tbs;
  433. q = &txq->q;
  434. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  435. tfd = &tfd_tmp[q->write_ptr];
  436. if (reset)
  437. memset(tfd, 0, sizeof(*tfd));
  438. num_tbs = iwl_tfd_get_num_tbs(tfd);
  439. /* Each TFD can point to a maximum 20 Tx buffers */
  440. if (num_tbs >= IWL_NUM_OF_TBS) {
  441. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  442. IWL_NUM_OF_TBS);
  443. return -EINVAL;
  444. }
  445. BUG_ON(addr & ~DMA_BIT_MASK(36));
  446. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  447. IWL_ERR(priv, "Unaligned address = %llx\n",
  448. (unsigned long long)addr);
  449. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  450. return 0;
  451. }
  452. /*
  453. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  454. * given Tx queue, and enable the DMA channel used for that queue.
  455. *
  456. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  457. * channels supported in hardware.
  458. */
  459. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  460. struct iwl_tx_queue *txq)
  461. {
  462. int txq_id = txq->q.id;
  463. /* Circular buffer (TFD queue in DRAM) physical base address */
  464. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  465. txq->q.dma_addr >> 8);
  466. return 0;
  467. }
  468. /******************************************************************************
  469. *
  470. * Generic RX handler implementations
  471. *
  472. ******************************************************************************/
  473. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  474. struct iwl_rx_mem_buffer *rxb)
  475. {
  476. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  477. struct iwl_alive_resp *palive;
  478. struct delayed_work *pwork;
  479. palive = &pkt->u.alive_frame;
  480. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  481. "0x%01X 0x%01X\n",
  482. palive->is_valid, palive->ver_type,
  483. palive->ver_subtype);
  484. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  485. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  486. memcpy(&priv->card_alive_init,
  487. &pkt->u.alive_frame,
  488. sizeof(struct iwl_init_alive_resp));
  489. pwork = &priv->init_alive_start;
  490. } else {
  491. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  492. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  493. sizeof(struct iwl_alive_resp));
  494. pwork = &priv->alive_start;
  495. }
  496. /* We delay the ALIVE response by 5ms to
  497. * give the HW RF Kill time to activate... */
  498. if (palive->is_valid == UCODE_VALID_OK)
  499. queue_delayed_work(priv->workqueue, pwork,
  500. msecs_to_jiffies(5));
  501. else
  502. IWL_WARN(priv, "uCode did not respond OK.\n");
  503. }
  504. static void iwl_bg_beacon_update(struct work_struct *work)
  505. {
  506. struct iwl_priv *priv =
  507. container_of(work, struct iwl_priv, beacon_update);
  508. struct sk_buff *beacon;
  509. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  510. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  511. if (!beacon) {
  512. IWL_ERR(priv, "update beacon failed\n");
  513. return;
  514. }
  515. mutex_lock(&priv->mutex);
  516. /* new beacon skb is allocated every time; dispose previous.*/
  517. if (priv->ibss_beacon)
  518. dev_kfree_skb(priv->ibss_beacon);
  519. priv->ibss_beacon = beacon;
  520. mutex_unlock(&priv->mutex);
  521. iwl_send_beacon_cmd(priv);
  522. }
  523. /**
  524. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  525. *
  526. * This callback is provided in order to send a statistics request.
  527. *
  528. * This timer function is continually reset to execute within
  529. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  530. * was received. We need to ensure we receive the statistics in order
  531. * to update the temperature used for calibrating the TXPOWER.
  532. */
  533. static void iwl_bg_statistics_periodic(unsigned long data)
  534. {
  535. struct iwl_priv *priv = (struct iwl_priv *)data;
  536. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  537. return;
  538. /* dont send host command if rf-kill is on */
  539. if (!iwl_is_ready_rf(priv))
  540. return;
  541. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  542. }
  543. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  544. u32 start_idx, u32 num_events,
  545. u32 mode)
  546. {
  547. u32 i;
  548. u32 ptr; /* SRAM byte address of log data */
  549. u32 ev, time, data; /* event log data */
  550. unsigned long reg_flags;
  551. if (mode == 0)
  552. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  553. else
  554. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  555. /* Make sure device is powered up for SRAM reads */
  556. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  557. if (iwl_grab_nic_access(priv)) {
  558. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  559. return;
  560. }
  561. /* Set starting address; reads will auto-increment */
  562. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  563. rmb();
  564. /*
  565. * "time" is actually "data" for mode 0 (no timestamp).
  566. * place event id # at far right for easier visual parsing.
  567. */
  568. for (i = 0; i < num_events; i++) {
  569. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  570. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  571. if (mode == 0) {
  572. trace_iwlwifi_dev_ucode_cont_event(priv,
  573. 0, time, ev);
  574. } else {
  575. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  576. trace_iwlwifi_dev_ucode_cont_event(priv,
  577. time, data, ev);
  578. }
  579. }
  580. /* Allow device to power down */
  581. iwl_release_nic_access(priv);
  582. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  583. }
  584. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  585. {
  586. u32 capacity; /* event log capacity in # entries */
  587. u32 base; /* SRAM byte address of event log header */
  588. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  589. u32 num_wraps; /* # times uCode wrapped to top of log */
  590. u32 next_entry; /* index of next entry to be written by uCode */
  591. if (priv->ucode_type == UCODE_INIT)
  592. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  593. else
  594. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  595. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  596. capacity = iwl_read_targ_mem(priv, base);
  597. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  598. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  599. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  600. } else
  601. return;
  602. if (num_wraps == priv->event_log.num_wraps) {
  603. iwl_print_cont_event_trace(priv,
  604. base, priv->event_log.next_entry,
  605. next_entry - priv->event_log.next_entry,
  606. mode);
  607. priv->event_log.non_wraps_count++;
  608. } else {
  609. if ((num_wraps - priv->event_log.num_wraps) > 1)
  610. priv->event_log.wraps_more_count++;
  611. else
  612. priv->event_log.wraps_once_count++;
  613. trace_iwlwifi_dev_ucode_wrap_event(priv,
  614. num_wraps - priv->event_log.num_wraps,
  615. next_entry, priv->event_log.next_entry);
  616. if (next_entry < priv->event_log.next_entry) {
  617. iwl_print_cont_event_trace(priv, base,
  618. priv->event_log.next_entry,
  619. capacity - priv->event_log.next_entry,
  620. mode);
  621. iwl_print_cont_event_trace(priv, base, 0,
  622. next_entry, mode);
  623. } else {
  624. iwl_print_cont_event_trace(priv, base,
  625. next_entry, capacity - next_entry,
  626. mode);
  627. iwl_print_cont_event_trace(priv, base, 0,
  628. next_entry, mode);
  629. }
  630. }
  631. priv->event_log.num_wraps = num_wraps;
  632. priv->event_log.next_entry = next_entry;
  633. }
  634. /**
  635. * iwl_bg_ucode_trace - Timer callback to log ucode event
  636. *
  637. * The timer is continually set to execute every
  638. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  639. * this function is to perform continuous uCode event logging operation
  640. * if enabled
  641. */
  642. static void iwl_bg_ucode_trace(unsigned long data)
  643. {
  644. struct iwl_priv *priv = (struct iwl_priv *)data;
  645. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  646. return;
  647. if (priv->event_log.ucode_trace) {
  648. iwl_continuous_event_trace(priv);
  649. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  650. mod_timer(&priv->ucode_trace,
  651. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  652. }
  653. }
  654. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  655. struct iwl_rx_mem_buffer *rxb)
  656. {
  657. #ifdef CONFIG_IWLWIFI_DEBUG
  658. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  659. struct iwl4965_beacon_notif *beacon =
  660. (struct iwl4965_beacon_notif *)pkt->u.raw;
  661. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  662. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  663. "tsf %d %d rate %d\n",
  664. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  665. beacon->beacon_notify_hdr.failure_frame,
  666. le32_to_cpu(beacon->ibss_mgr_status),
  667. le32_to_cpu(beacon->high_tsf),
  668. le32_to_cpu(beacon->low_tsf), rate);
  669. #endif
  670. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  671. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  672. queue_work(priv->workqueue, &priv->beacon_update);
  673. }
  674. /* Handle notification from uCode that card's power state is changing
  675. * due to software, hardware, or critical temperature RFKILL */
  676. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  677. struct iwl_rx_mem_buffer *rxb)
  678. {
  679. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  680. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  681. unsigned long status = priv->status;
  682. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  683. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  684. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  685. (flags & CT_CARD_DISABLED) ?
  686. "Reached" : "Not reached");
  687. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  688. CT_CARD_DISABLED)) {
  689. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  690. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  691. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  692. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  693. if (!(flags & RXON_CARD_DISABLED)) {
  694. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  695. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  696. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  697. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  698. }
  699. if (flags & CT_CARD_DISABLED)
  700. iwl_tt_enter_ct_kill(priv);
  701. }
  702. if (!(flags & CT_CARD_DISABLED))
  703. iwl_tt_exit_ct_kill(priv);
  704. if (flags & HW_CARD_DISABLED)
  705. set_bit(STATUS_RF_KILL_HW, &priv->status);
  706. else
  707. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  708. if (!(flags & RXON_CARD_DISABLED))
  709. iwl_scan_cancel(priv);
  710. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  711. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  712. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  713. test_bit(STATUS_RF_KILL_HW, &priv->status));
  714. else
  715. wake_up_interruptible(&priv->wait_command_queue);
  716. }
  717. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  718. {
  719. if (src == IWL_PWR_SRC_VAUX) {
  720. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  721. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  722. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  723. ~APMG_PS_CTRL_MSK_PWR_SRC);
  724. } else {
  725. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  726. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  727. ~APMG_PS_CTRL_MSK_PWR_SRC);
  728. }
  729. return 0;
  730. }
  731. /**
  732. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  733. *
  734. * Setup the RX handlers for each of the reply types sent from the uCode
  735. * to the host.
  736. *
  737. * This function chains into the hardware specific files for them to setup
  738. * any hardware specific handlers as well.
  739. */
  740. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  741. {
  742. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  743. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  744. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  745. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  746. iwl_rx_spectrum_measure_notif;
  747. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  748. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  749. iwl_rx_pm_debug_statistics_notif;
  750. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  751. /*
  752. * The same handler is used for both the REPLY to a discrete
  753. * statistics request from the host as well as for the periodic
  754. * statistics notifications (after received beacons) from the uCode.
  755. */
  756. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  757. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  758. iwl_setup_rx_scan_handlers(priv);
  759. /* status change handler */
  760. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  761. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  762. iwl_rx_missed_beacon_notif;
  763. /* Rx handlers */
  764. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  765. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  766. /* block ack */
  767. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  768. /* Set up hardware specific Rx handlers */
  769. priv->cfg->ops->lib->rx_handler_setup(priv);
  770. }
  771. /**
  772. * iwl_rx_handle - Main entry function for receiving responses from uCode
  773. *
  774. * Uses the priv->rx_handlers callback function array to invoke
  775. * the appropriate handlers, including command responses,
  776. * frame-received notifications, and other notifications.
  777. */
  778. void iwl_rx_handle(struct iwl_priv *priv)
  779. {
  780. struct iwl_rx_mem_buffer *rxb;
  781. struct iwl_rx_packet *pkt;
  782. struct iwl_rx_queue *rxq = &priv->rxq;
  783. u32 r, i;
  784. int reclaim;
  785. unsigned long flags;
  786. u8 fill_rx = 0;
  787. u32 count = 8;
  788. int total_empty;
  789. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  790. * buffer that the driver may process (last buffer filled by ucode). */
  791. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  792. i = rxq->read;
  793. /* Rx interrupt, but nothing sent from uCode */
  794. if (i == r)
  795. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  796. /* calculate total frames need to be restock after handling RX */
  797. total_empty = r - rxq->write_actual;
  798. if (total_empty < 0)
  799. total_empty += RX_QUEUE_SIZE;
  800. if (total_empty > (RX_QUEUE_SIZE / 2))
  801. fill_rx = 1;
  802. while (i != r) {
  803. rxb = rxq->queue[i];
  804. /* If an RXB doesn't have a Rx queue slot associated with it,
  805. * then a bug has been introduced in the queue refilling
  806. * routines -- catch it here */
  807. BUG_ON(rxb == NULL);
  808. rxq->queue[i] = NULL;
  809. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  810. PAGE_SIZE << priv->hw_params.rx_page_order,
  811. PCI_DMA_FROMDEVICE);
  812. pkt = rxb_addr(rxb);
  813. trace_iwlwifi_dev_rx(priv, pkt,
  814. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  815. /* Reclaim a command buffer only if this packet is a response
  816. * to a (driver-originated) command.
  817. * If the packet (e.g. Rx frame) originated from uCode,
  818. * there is no command buffer to reclaim.
  819. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  820. * but apparently a few don't get set; catch them here. */
  821. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  822. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  823. (pkt->hdr.cmd != REPLY_RX) &&
  824. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  825. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  826. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  827. (pkt->hdr.cmd != REPLY_TX);
  828. /* Based on type of command response or notification,
  829. * handle those that need handling via function in
  830. * rx_handlers table. See iwl_setup_rx_handlers() */
  831. if (priv->rx_handlers[pkt->hdr.cmd]) {
  832. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  833. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  834. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  835. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  836. } else {
  837. /* No handling needed */
  838. IWL_DEBUG_RX(priv,
  839. "r %d i %d No handler needed for %s, 0x%02x\n",
  840. r, i, get_cmd_string(pkt->hdr.cmd),
  841. pkt->hdr.cmd);
  842. }
  843. /*
  844. * XXX: After here, we should always check rxb->page
  845. * against NULL before touching it or its virtual
  846. * memory (pkt). Because some rx_handler might have
  847. * already taken or freed the pages.
  848. */
  849. if (reclaim) {
  850. /* Invoke any callbacks, transfer the buffer to caller,
  851. * and fire off the (possibly) blocking iwl_send_cmd()
  852. * as we reclaim the driver command queue */
  853. if (rxb->page)
  854. iwl_tx_cmd_complete(priv, rxb);
  855. else
  856. IWL_WARN(priv, "Claim null rxb?\n");
  857. }
  858. /* Reuse the page if possible. For notification packets and
  859. * SKBs that fail to Rx correctly, add them back into the
  860. * rx_free list for reuse later. */
  861. spin_lock_irqsave(&rxq->lock, flags);
  862. if (rxb->page != NULL) {
  863. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  864. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  865. PCI_DMA_FROMDEVICE);
  866. list_add_tail(&rxb->list, &rxq->rx_free);
  867. rxq->free_count++;
  868. } else
  869. list_add_tail(&rxb->list, &rxq->rx_used);
  870. spin_unlock_irqrestore(&rxq->lock, flags);
  871. i = (i + 1) & RX_QUEUE_MASK;
  872. /* If there are a lot of unused frames,
  873. * restock the Rx queue so ucode wont assert. */
  874. if (fill_rx) {
  875. count++;
  876. if (count >= 8) {
  877. rxq->read = i;
  878. iwl_rx_replenish_now(priv);
  879. count = 0;
  880. }
  881. }
  882. }
  883. /* Backtrack one entry */
  884. rxq->read = i;
  885. if (fill_rx)
  886. iwl_rx_replenish_now(priv);
  887. else
  888. iwl_rx_queue_restock(priv);
  889. }
  890. /* call this function to flush any scheduled tasklet */
  891. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  892. {
  893. /* wait to make sure we flush pending tasklet*/
  894. synchronize_irq(priv->pci_dev->irq);
  895. tasklet_kill(&priv->irq_tasklet);
  896. }
  897. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  898. {
  899. u32 inta, handled = 0;
  900. u32 inta_fh;
  901. unsigned long flags;
  902. u32 i;
  903. #ifdef CONFIG_IWLWIFI_DEBUG
  904. u32 inta_mask;
  905. #endif
  906. spin_lock_irqsave(&priv->lock, flags);
  907. /* Ack/clear/reset pending uCode interrupts.
  908. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  909. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  910. inta = iwl_read32(priv, CSR_INT);
  911. iwl_write32(priv, CSR_INT, inta);
  912. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  913. * Any new interrupts that happen after this, either while we're
  914. * in this tasklet, or later, will show up in next ISR/tasklet. */
  915. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  916. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  917. #ifdef CONFIG_IWLWIFI_DEBUG
  918. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  919. /* just for debug */
  920. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  921. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  922. inta, inta_mask, inta_fh);
  923. }
  924. #endif
  925. spin_unlock_irqrestore(&priv->lock, flags);
  926. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  927. * atomic, make sure that inta covers all the interrupts that
  928. * we've discovered, even if FH interrupt came in just after
  929. * reading CSR_INT. */
  930. if (inta_fh & CSR49_FH_INT_RX_MASK)
  931. inta |= CSR_INT_BIT_FH_RX;
  932. if (inta_fh & CSR49_FH_INT_TX_MASK)
  933. inta |= CSR_INT_BIT_FH_TX;
  934. /* Now service all interrupt bits discovered above. */
  935. if (inta & CSR_INT_BIT_HW_ERR) {
  936. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  937. /* Tell the device to stop sending interrupts */
  938. iwl_disable_interrupts(priv);
  939. priv->isr_stats.hw++;
  940. iwl_irq_handle_error(priv);
  941. handled |= CSR_INT_BIT_HW_ERR;
  942. return;
  943. }
  944. #ifdef CONFIG_IWLWIFI_DEBUG
  945. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  946. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  947. if (inta & CSR_INT_BIT_SCD) {
  948. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  949. "the frame/frames.\n");
  950. priv->isr_stats.sch++;
  951. }
  952. /* Alive notification via Rx interrupt will do the real work */
  953. if (inta & CSR_INT_BIT_ALIVE) {
  954. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  955. priv->isr_stats.alive++;
  956. }
  957. }
  958. #endif
  959. /* Safely ignore these bits for debug checks below */
  960. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  961. /* HW RF KILL switch toggled */
  962. if (inta & CSR_INT_BIT_RF_KILL) {
  963. int hw_rf_kill = 0;
  964. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  965. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  966. hw_rf_kill = 1;
  967. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  968. hw_rf_kill ? "disable radio" : "enable radio");
  969. priv->isr_stats.rfkill++;
  970. /* driver only loads ucode once setting the interface up.
  971. * the driver allows loading the ucode even if the radio
  972. * is killed. Hence update the killswitch state here. The
  973. * rfkill handler will care about restarting if needed.
  974. */
  975. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  976. if (hw_rf_kill)
  977. set_bit(STATUS_RF_KILL_HW, &priv->status);
  978. else
  979. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  980. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  981. }
  982. handled |= CSR_INT_BIT_RF_KILL;
  983. }
  984. /* Chip got too hot and stopped itself */
  985. if (inta & CSR_INT_BIT_CT_KILL) {
  986. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  987. priv->isr_stats.ctkill++;
  988. handled |= CSR_INT_BIT_CT_KILL;
  989. }
  990. /* Error detected by uCode */
  991. if (inta & CSR_INT_BIT_SW_ERR) {
  992. IWL_ERR(priv, "Microcode SW error detected. "
  993. " Restarting 0x%X.\n", inta);
  994. priv->isr_stats.sw++;
  995. priv->isr_stats.sw_err = inta;
  996. iwl_irq_handle_error(priv);
  997. handled |= CSR_INT_BIT_SW_ERR;
  998. }
  999. /*
  1000. * uCode wakes up after power-down sleep.
  1001. * Tell device about any new tx or host commands enqueued,
  1002. * and about any Rx buffers made available while asleep.
  1003. */
  1004. if (inta & CSR_INT_BIT_WAKEUP) {
  1005. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1006. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1007. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1008. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1009. priv->isr_stats.wakeup++;
  1010. handled |= CSR_INT_BIT_WAKEUP;
  1011. }
  1012. /* All uCode command responses, including Tx command responses,
  1013. * Rx "responses" (frame-received notification), and other
  1014. * notifications from uCode come through here*/
  1015. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1016. iwl_rx_handle(priv);
  1017. priv->isr_stats.rx++;
  1018. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1019. }
  1020. /* This "Tx" DMA channel is used only for loading uCode */
  1021. if (inta & CSR_INT_BIT_FH_TX) {
  1022. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1023. priv->isr_stats.tx++;
  1024. handled |= CSR_INT_BIT_FH_TX;
  1025. /* Wake up uCode load routine, now that load is complete */
  1026. priv->ucode_write_complete = 1;
  1027. wake_up_interruptible(&priv->wait_command_queue);
  1028. }
  1029. if (inta & ~handled) {
  1030. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1031. priv->isr_stats.unhandled++;
  1032. }
  1033. if (inta & ~(priv->inta_mask)) {
  1034. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1035. inta & ~priv->inta_mask);
  1036. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1037. }
  1038. /* Re-enable all interrupts */
  1039. /* only Re-enable if diabled by irq */
  1040. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1041. iwl_enable_interrupts(priv);
  1042. #ifdef CONFIG_IWLWIFI_DEBUG
  1043. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1044. inta = iwl_read32(priv, CSR_INT);
  1045. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1046. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1047. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1048. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1049. }
  1050. #endif
  1051. }
  1052. /* tasklet for iwlagn interrupt */
  1053. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1054. {
  1055. u32 inta = 0;
  1056. u32 handled = 0;
  1057. unsigned long flags;
  1058. u32 i;
  1059. #ifdef CONFIG_IWLWIFI_DEBUG
  1060. u32 inta_mask;
  1061. #endif
  1062. spin_lock_irqsave(&priv->lock, flags);
  1063. /* Ack/clear/reset pending uCode interrupts.
  1064. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1065. */
  1066. iwl_write32(priv, CSR_INT, priv->inta);
  1067. inta = priv->inta;
  1068. #ifdef CONFIG_IWLWIFI_DEBUG
  1069. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1070. /* just for debug */
  1071. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1072. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1073. inta, inta_mask);
  1074. }
  1075. #endif
  1076. spin_unlock_irqrestore(&priv->lock, flags);
  1077. /* saved interrupt in inta variable now we can reset priv->inta */
  1078. priv->inta = 0;
  1079. /* Now service all interrupt bits discovered above. */
  1080. if (inta & CSR_INT_BIT_HW_ERR) {
  1081. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1082. /* Tell the device to stop sending interrupts */
  1083. iwl_disable_interrupts(priv);
  1084. priv->isr_stats.hw++;
  1085. iwl_irq_handle_error(priv);
  1086. handled |= CSR_INT_BIT_HW_ERR;
  1087. return;
  1088. }
  1089. #ifdef CONFIG_IWLWIFI_DEBUG
  1090. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1091. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1092. if (inta & CSR_INT_BIT_SCD) {
  1093. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1094. "the frame/frames.\n");
  1095. priv->isr_stats.sch++;
  1096. }
  1097. /* Alive notification via Rx interrupt will do the real work */
  1098. if (inta & CSR_INT_BIT_ALIVE) {
  1099. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1100. priv->isr_stats.alive++;
  1101. }
  1102. }
  1103. #endif
  1104. /* Safely ignore these bits for debug checks below */
  1105. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1106. /* HW RF KILL switch toggled */
  1107. if (inta & CSR_INT_BIT_RF_KILL) {
  1108. int hw_rf_kill = 0;
  1109. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1110. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1111. hw_rf_kill = 1;
  1112. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1113. hw_rf_kill ? "disable radio" : "enable radio");
  1114. priv->isr_stats.rfkill++;
  1115. /* driver only loads ucode once setting the interface up.
  1116. * the driver allows loading the ucode even if the radio
  1117. * is killed. Hence update the killswitch state here. The
  1118. * rfkill handler will care about restarting if needed.
  1119. */
  1120. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1121. if (hw_rf_kill)
  1122. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1123. else
  1124. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1125. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1126. }
  1127. handled |= CSR_INT_BIT_RF_KILL;
  1128. }
  1129. /* Chip got too hot and stopped itself */
  1130. if (inta & CSR_INT_BIT_CT_KILL) {
  1131. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1132. priv->isr_stats.ctkill++;
  1133. handled |= CSR_INT_BIT_CT_KILL;
  1134. }
  1135. /* Error detected by uCode */
  1136. if (inta & CSR_INT_BIT_SW_ERR) {
  1137. IWL_ERR(priv, "Microcode SW error detected. "
  1138. " Restarting 0x%X.\n", inta);
  1139. priv->isr_stats.sw++;
  1140. priv->isr_stats.sw_err = inta;
  1141. iwl_irq_handle_error(priv);
  1142. handled |= CSR_INT_BIT_SW_ERR;
  1143. }
  1144. /* uCode wakes up after power-down sleep */
  1145. if (inta & CSR_INT_BIT_WAKEUP) {
  1146. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1147. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1148. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1149. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1150. priv->isr_stats.wakeup++;
  1151. handled |= CSR_INT_BIT_WAKEUP;
  1152. }
  1153. /* All uCode command responses, including Tx command responses,
  1154. * Rx "responses" (frame-received notification), and other
  1155. * notifications from uCode come through here*/
  1156. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1157. CSR_INT_BIT_RX_PERIODIC)) {
  1158. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1159. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1160. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1161. iwl_write32(priv, CSR_FH_INT_STATUS,
  1162. CSR49_FH_INT_RX_MASK);
  1163. }
  1164. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1165. handled |= CSR_INT_BIT_RX_PERIODIC;
  1166. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1167. }
  1168. /* Sending RX interrupt require many steps to be done in the
  1169. * the device:
  1170. * 1- write interrupt to current index in ICT table.
  1171. * 2- dma RX frame.
  1172. * 3- update RX shared data to indicate last write index.
  1173. * 4- send interrupt.
  1174. * This could lead to RX race, driver could receive RX interrupt
  1175. * but the shared data changes does not reflect this;
  1176. * periodic interrupt will detect any dangling Rx activity.
  1177. */
  1178. /* Disable periodic interrupt; we use it as just a one-shot. */
  1179. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1180. CSR_INT_PERIODIC_DIS);
  1181. iwl_rx_handle(priv);
  1182. /*
  1183. * Enable periodic interrupt in 8 msec only if we received
  1184. * real RX interrupt (instead of just periodic int), to catch
  1185. * any dangling Rx interrupt. If it was just the periodic
  1186. * interrupt, there was no dangling Rx activity, and no need
  1187. * to extend the periodic interrupt; one-shot is enough.
  1188. */
  1189. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1190. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1191. CSR_INT_PERIODIC_ENA);
  1192. priv->isr_stats.rx++;
  1193. }
  1194. /* This "Tx" DMA channel is used only for loading uCode */
  1195. if (inta & CSR_INT_BIT_FH_TX) {
  1196. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1197. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1198. priv->isr_stats.tx++;
  1199. handled |= CSR_INT_BIT_FH_TX;
  1200. /* Wake up uCode load routine, now that load is complete */
  1201. priv->ucode_write_complete = 1;
  1202. wake_up_interruptible(&priv->wait_command_queue);
  1203. }
  1204. if (inta & ~handled) {
  1205. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1206. priv->isr_stats.unhandled++;
  1207. }
  1208. if (inta & ~(priv->inta_mask)) {
  1209. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1210. inta & ~priv->inta_mask);
  1211. }
  1212. /* Re-enable all interrupts */
  1213. /* only Re-enable if diabled by irq */
  1214. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1215. iwl_enable_interrupts(priv);
  1216. }
  1217. /******************************************************************************
  1218. *
  1219. * uCode download functions
  1220. *
  1221. ******************************************************************************/
  1222. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1223. {
  1224. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1225. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1226. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1227. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1228. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1229. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1230. }
  1231. static void iwl_nic_start(struct iwl_priv *priv)
  1232. {
  1233. /* Remove all resets to allow NIC to operate */
  1234. iwl_write32(priv, CSR_RESET, 0);
  1235. }
  1236. /**
  1237. * iwl_read_ucode - Read uCode images from disk file.
  1238. *
  1239. * Copy into buffers for card to fetch via bus-mastering
  1240. */
  1241. static int iwl_read_ucode(struct iwl_priv *priv)
  1242. {
  1243. struct iwl_ucode_header *ucode;
  1244. int ret = -EINVAL, index;
  1245. const struct firmware *ucode_raw;
  1246. const char *name_pre = priv->cfg->fw_name_pre;
  1247. const unsigned int api_max = priv->cfg->ucode_api_max;
  1248. const unsigned int api_min = priv->cfg->ucode_api_min;
  1249. char buf[25];
  1250. u8 *src;
  1251. size_t len;
  1252. u32 api_ver, build;
  1253. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1254. u16 eeprom_ver;
  1255. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1256. * request_firmware() is synchronous, file is in memory on return. */
  1257. for (index = api_max; index >= api_min; index--) {
  1258. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1259. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1260. if (ret < 0) {
  1261. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1262. buf, ret);
  1263. if (ret == -ENOENT)
  1264. continue;
  1265. else
  1266. goto error;
  1267. } else {
  1268. if (index < api_max)
  1269. IWL_ERR(priv, "Loaded firmware %s, "
  1270. "which is deprecated. "
  1271. "Please use API v%u instead.\n",
  1272. buf, api_max);
  1273. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1274. buf, ucode_raw->size);
  1275. break;
  1276. }
  1277. }
  1278. if (ret < 0)
  1279. goto error;
  1280. /* Make sure that we got at least the v1 header! */
  1281. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1282. IWL_ERR(priv, "File size way too small!\n");
  1283. ret = -EINVAL;
  1284. goto err_release;
  1285. }
  1286. /* Data from ucode file: header followed by uCode images */
  1287. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1288. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1289. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1290. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1291. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1292. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1293. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1294. init_data_size =
  1295. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1296. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1297. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1298. /* api_ver should match the api version forming part of the
  1299. * firmware filename ... but we don't check for that and only rely
  1300. * on the API version read from firmware header from here on forward */
  1301. if (api_ver < api_min || api_ver > api_max) {
  1302. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1303. "Driver supports v%u, firmware is v%u.\n",
  1304. api_max, api_ver);
  1305. priv->ucode_ver = 0;
  1306. ret = -EINVAL;
  1307. goto err_release;
  1308. }
  1309. if (api_ver != api_max)
  1310. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1311. "got v%u. New firmware can be obtained "
  1312. "from http://www.intellinuxwireless.org.\n",
  1313. api_max, api_ver);
  1314. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1315. IWL_UCODE_MAJOR(priv->ucode_ver),
  1316. IWL_UCODE_MINOR(priv->ucode_ver),
  1317. IWL_UCODE_API(priv->ucode_ver),
  1318. IWL_UCODE_SERIAL(priv->ucode_ver));
  1319. snprintf(priv->hw->wiphy->fw_version,
  1320. sizeof(priv->hw->wiphy->fw_version),
  1321. "%u.%u.%u.%u",
  1322. IWL_UCODE_MAJOR(priv->ucode_ver),
  1323. IWL_UCODE_MINOR(priv->ucode_ver),
  1324. IWL_UCODE_API(priv->ucode_ver),
  1325. IWL_UCODE_SERIAL(priv->ucode_ver));
  1326. if (build)
  1327. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1328. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1329. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1330. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1331. ? "OTP" : "EEPROM", eeprom_ver);
  1332. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1333. priv->ucode_ver);
  1334. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1335. inst_size);
  1336. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1337. data_size);
  1338. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1339. init_size);
  1340. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1341. init_data_size);
  1342. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1343. boot_size);
  1344. /* Verify size of file vs. image size info in file's header */
  1345. if (ucode_raw->size !=
  1346. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1347. inst_size + data_size + init_size +
  1348. init_data_size + boot_size) {
  1349. IWL_DEBUG_INFO(priv,
  1350. "uCode file size %d does not match expected size\n",
  1351. (int)ucode_raw->size);
  1352. ret = -EINVAL;
  1353. goto err_release;
  1354. }
  1355. /* Verify that uCode images will fit in card's SRAM */
  1356. if (inst_size > priv->hw_params.max_inst_size) {
  1357. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1358. inst_size);
  1359. ret = -EINVAL;
  1360. goto err_release;
  1361. }
  1362. if (data_size > priv->hw_params.max_data_size) {
  1363. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1364. data_size);
  1365. ret = -EINVAL;
  1366. goto err_release;
  1367. }
  1368. if (init_size > priv->hw_params.max_inst_size) {
  1369. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1370. init_size);
  1371. ret = -EINVAL;
  1372. goto err_release;
  1373. }
  1374. if (init_data_size > priv->hw_params.max_data_size) {
  1375. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1376. init_data_size);
  1377. ret = -EINVAL;
  1378. goto err_release;
  1379. }
  1380. if (boot_size > priv->hw_params.max_bsm_size) {
  1381. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1382. boot_size);
  1383. ret = -EINVAL;
  1384. goto err_release;
  1385. }
  1386. /* Allocate ucode buffers for card's bus-master loading ... */
  1387. /* Runtime instructions and 2 copies of data:
  1388. * 1) unmodified from disk
  1389. * 2) backup cache for save/restore during power-downs */
  1390. priv->ucode_code.len = inst_size;
  1391. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1392. priv->ucode_data.len = data_size;
  1393. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1394. priv->ucode_data_backup.len = data_size;
  1395. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1396. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1397. !priv->ucode_data_backup.v_addr)
  1398. goto err_pci_alloc;
  1399. /* Initialization instructions and data */
  1400. if (init_size && init_data_size) {
  1401. priv->ucode_init.len = init_size;
  1402. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1403. priv->ucode_init_data.len = init_data_size;
  1404. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1405. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1406. goto err_pci_alloc;
  1407. }
  1408. /* Bootstrap (instructions only, no data) */
  1409. if (boot_size) {
  1410. priv->ucode_boot.len = boot_size;
  1411. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1412. if (!priv->ucode_boot.v_addr)
  1413. goto err_pci_alloc;
  1414. }
  1415. /* Copy images into buffers for card's bus-master reads ... */
  1416. /* Runtime instructions (first block of data in file) */
  1417. len = inst_size;
  1418. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1419. memcpy(priv->ucode_code.v_addr, src, len);
  1420. src += len;
  1421. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1422. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1423. /* Runtime data (2nd block)
  1424. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1425. len = data_size;
  1426. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1427. memcpy(priv->ucode_data.v_addr, src, len);
  1428. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1429. src += len;
  1430. /* Initialization instructions (3rd block) */
  1431. if (init_size) {
  1432. len = init_size;
  1433. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1434. len);
  1435. memcpy(priv->ucode_init.v_addr, src, len);
  1436. src += len;
  1437. }
  1438. /* Initialization data (4th block) */
  1439. if (init_data_size) {
  1440. len = init_data_size;
  1441. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1442. len);
  1443. memcpy(priv->ucode_init_data.v_addr, src, len);
  1444. src += len;
  1445. }
  1446. /* Bootstrap instructions (5th block) */
  1447. len = boot_size;
  1448. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1449. memcpy(priv->ucode_boot.v_addr, src, len);
  1450. /* We have our copies now, allow OS release its copies */
  1451. release_firmware(ucode_raw);
  1452. return 0;
  1453. err_pci_alloc:
  1454. IWL_ERR(priv, "failed to allocate pci memory\n");
  1455. ret = -ENOMEM;
  1456. iwl_dealloc_ucode_pci(priv);
  1457. err_release:
  1458. release_firmware(ucode_raw);
  1459. error:
  1460. return ret;
  1461. }
  1462. static const char *desc_lookup_text[] = {
  1463. "OK",
  1464. "FAIL",
  1465. "BAD_PARAM",
  1466. "BAD_CHECKSUM",
  1467. "NMI_INTERRUPT_WDG",
  1468. "SYSASSERT",
  1469. "FATAL_ERROR",
  1470. "BAD_COMMAND",
  1471. "HW_ERROR_TUNE_LOCK",
  1472. "HW_ERROR_TEMPERATURE",
  1473. "ILLEGAL_CHAN_FREQ",
  1474. "VCC_NOT_STABLE",
  1475. "FH_ERROR",
  1476. "NMI_INTERRUPT_HOST",
  1477. "NMI_INTERRUPT_ACTION_PT",
  1478. "NMI_INTERRUPT_UNKNOWN",
  1479. "UCODE_VERSION_MISMATCH",
  1480. "HW_ERROR_ABS_LOCK",
  1481. "HW_ERROR_CAL_LOCK_FAIL",
  1482. "NMI_INTERRUPT_INST_ACTION_PT",
  1483. "NMI_INTERRUPT_DATA_ACTION_PT",
  1484. "NMI_TRM_HW_ER",
  1485. "NMI_INTERRUPT_TRM",
  1486. "NMI_INTERRUPT_BREAK_POINT"
  1487. "DEBUG_0",
  1488. "DEBUG_1",
  1489. "DEBUG_2",
  1490. "DEBUG_3",
  1491. "ADVANCED SYSASSERT"
  1492. };
  1493. static const char *desc_lookup(int i)
  1494. {
  1495. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1496. if (i < 0 || i > max)
  1497. i = max;
  1498. return desc_lookup_text[i];
  1499. }
  1500. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1501. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1502. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1503. {
  1504. u32 data2, line;
  1505. u32 desc, time, count, base, data1;
  1506. u32 blink1, blink2, ilink1, ilink2;
  1507. if (priv->ucode_type == UCODE_INIT)
  1508. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1509. else
  1510. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1511. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1512. IWL_ERR(priv,
  1513. "Not valid error log pointer 0x%08X for %s uCode\n",
  1514. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1515. return;
  1516. }
  1517. count = iwl_read_targ_mem(priv, base);
  1518. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1519. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1520. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1521. priv->status, count);
  1522. }
  1523. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1524. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1525. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1526. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1527. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1528. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1529. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1530. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1531. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1532. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1533. blink1, blink2, ilink1, ilink2);
  1534. IWL_ERR(priv, "Desc Time "
  1535. "data1 data2 line\n");
  1536. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1537. desc_lookup(desc), desc, time, data1, data2, line);
  1538. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1539. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1540. ilink1, ilink2);
  1541. }
  1542. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1543. /**
  1544. * iwl_print_event_log - Dump error event log to syslog
  1545. *
  1546. */
  1547. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1548. u32 num_events, u32 mode,
  1549. int pos, char **buf, size_t bufsz)
  1550. {
  1551. u32 i;
  1552. u32 base; /* SRAM byte address of event log header */
  1553. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1554. u32 ptr; /* SRAM byte address of log data */
  1555. u32 ev, time, data; /* event log data */
  1556. unsigned long reg_flags;
  1557. if (num_events == 0)
  1558. return pos;
  1559. if (priv->ucode_type == UCODE_INIT)
  1560. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1561. else
  1562. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1563. if (mode == 0)
  1564. event_size = 2 * sizeof(u32);
  1565. else
  1566. event_size = 3 * sizeof(u32);
  1567. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1568. /* Make sure device is powered up for SRAM reads */
  1569. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1570. iwl_grab_nic_access(priv);
  1571. /* Set starting address; reads will auto-increment */
  1572. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1573. rmb();
  1574. /* "time" is actually "data" for mode 0 (no timestamp).
  1575. * place event id # at far right for easier visual parsing. */
  1576. for (i = 0; i < num_events; i++) {
  1577. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1578. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1579. if (mode == 0) {
  1580. /* data, ev */
  1581. if (bufsz) {
  1582. pos += scnprintf(*buf + pos, bufsz - pos,
  1583. "EVT_LOG:0x%08x:%04u\n",
  1584. time, ev);
  1585. } else {
  1586. trace_iwlwifi_dev_ucode_event(priv, 0,
  1587. time, ev);
  1588. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1589. time, ev);
  1590. }
  1591. } else {
  1592. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1593. if (bufsz) {
  1594. pos += scnprintf(*buf + pos, bufsz - pos,
  1595. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1596. time, data, ev);
  1597. } else {
  1598. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1599. time, data, ev);
  1600. trace_iwlwifi_dev_ucode_event(priv, time,
  1601. data, ev);
  1602. }
  1603. }
  1604. }
  1605. /* Allow device to power down */
  1606. iwl_release_nic_access(priv);
  1607. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1608. return pos;
  1609. }
  1610. /**
  1611. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1612. */
  1613. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1614. u32 num_wraps, u32 next_entry,
  1615. u32 size, u32 mode,
  1616. int pos, char **buf, size_t bufsz)
  1617. {
  1618. /*
  1619. * display the newest DEFAULT_LOG_ENTRIES entries
  1620. * i.e the entries just before the next ont that uCode would fill.
  1621. */
  1622. if (num_wraps) {
  1623. if (next_entry < size) {
  1624. pos = iwl_print_event_log(priv,
  1625. capacity - (size - next_entry),
  1626. size - next_entry, mode,
  1627. pos, buf, bufsz);
  1628. pos = iwl_print_event_log(priv, 0,
  1629. next_entry, mode,
  1630. pos, buf, bufsz);
  1631. } else
  1632. pos = iwl_print_event_log(priv, next_entry - size,
  1633. size, mode, pos, buf, bufsz);
  1634. } else {
  1635. if (next_entry < size) {
  1636. pos = iwl_print_event_log(priv, 0, next_entry,
  1637. mode, pos, buf, bufsz);
  1638. } else {
  1639. pos = iwl_print_event_log(priv, next_entry - size,
  1640. size, mode, pos, buf, bufsz);
  1641. }
  1642. }
  1643. return pos;
  1644. }
  1645. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1646. #define MAX_EVENT_LOG_SIZE (512)
  1647. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1648. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1649. char **buf, bool display)
  1650. {
  1651. u32 base; /* SRAM byte address of event log header */
  1652. u32 capacity; /* event log capacity in # entries */
  1653. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1654. u32 num_wraps; /* # times uCode wrapped to top of log */
  1655. u32 next_entry; /* index of next entry to be written by uCode */
  1656. u32 size; /* # entries that we'll print */
  1657. int pos = 0;
  1658. size_t bufsz = 0;
  1659. if (priv->ucode_type == UCODE_INIT)
  1660. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1661. else
  1662. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1663. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1664. IWL_ERR(priv,
  1665. "Invalid event log pointer 0x%08X for %s uCode\n",
  1666. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1667. return -EINVAL;
  1668. }
  1669. /* event log header */
  1670. capacity = iwl_read_targ_mem(priv, base);
  1671. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1672. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1673. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1674. if (capacity > MAX_EVENT_LOG_SIZE) {
  1675. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1676. capacity, MAX_EVENT_LOG_SIZE);
  1677. capacity = MAX_EVENT_LOG_SIZE;
  1678. }
  1679. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1680. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1681. next_entry, MAX_EVENT_LOG_SIZE);
  1682. next_entry = MAX_EVENT_LOG_SIZE;
  1683. }
  1684. size = num_wraps ? capacity : next_entry;
  1685. /* bail out if nothing in log */
  1686. if (size == 0) {
  1687. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1688. return pos;
  1689. }
  1690. #ifdef CONFIG_IWLWIFI_DEBUG
  1691. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1692. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1693. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1694. #else
  1695. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1696. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1697. #endif
  1698. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1699. size);
  1700. #ifdef CONFIG_IWLWIFI_DEBUG
  1701. if (display) {
  1702. if (full_log)
  1703. bufsz = capacity * 48;
  1704. else
  1705. bufsz = size * 48;
  1706. *buf = kmalloc(bufsz, GFP_KERNEL);
  1707. if (!*buf)
  1708. return -ENOMEM;
  1709. }
  1710. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1711. /*
  1712. * if uCode has wrapped back to top of log,
  1713. * start at the oldest entry,
  1714. * i.e the next one that uCode would fill.
  1715. */
  1716. if (num_wraps)
  1717. pos = iwl_print_event_log(priv, next_entry,
  1718. capacity - next_entry, mode,
  1719. pos, buf, bufsz);
  1720. /* (then/else) start at top of log */
  1721. pos = iwl_print_event_log(priv, 0,
  1722. next_entry, mode, pos, buf, bufsz);
  1723. } else
  1724. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1725. next_entry, size, mode,
  1726. pos, buf, bufsz);
  1727. #else
  1728. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1729. next_entry, size, mode,
  1730. pos, buf, bufsz);
  1731. #endif
  1732. return pos;
  1733. }
  1734. /**
  1735. * iwl_alive_start - called after REPLY_ALIVE notification received
  1736. * from protocol/runtime uCode (initialization uCode's
  1737. * Alive gets handled by iwl_init_alive_start()).
  1738. */
  1739. static void iwl_alive_start(struct iwl_priv *priv)
  1740. {
  1741. int ret = 0;
  1742. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1743. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1744. /* We had an error bringing up the hardware, so take it
  1745. * all the way back down so we can try again */
  1746. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1747. goto restart;
  1748. }
  1749. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1750. * This is a paranoid check, because we would not have gotten the
  1751. * "runtime" alive if code weren't properly loaded. */
  1752. if (iwl_verify_ucode(priv)) {
  1753. /* Runtime instruction load was bad;
  1754. * take it all the way back down so we can try again */
  1755. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1756. goto restart;
  1757. }
  1758. iwl_clear_stations_table(priv);
  1759. ret = priv->cfg->ops->lib->alive_notify(priv);
  1760. if (ret) {
  1761. IWL_WARN(priv,
  1762. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1763. goto restart;
  1764. }
  1765. /* After the ALIVE response, we can send host commands to the uCode */
  1766. set_bit(STATUS_ALIVE, &priv->status);
  1767. if (iwl_is_rfkill(priv))
  1768. return;
  1769. ieee80211_wake_queues(priv->hw);
  1770. priv->active_rate = priv->rates_mask;
  1771. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1772. /* Configure Tx antenna selection based on H/W config */
  1773. if (priv->cfg->ops->hcmd->set_tx_ant)
  1774. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1775. if (iwl_is_associated(priv)) {
  1776. struct iwl_rxon_cmd *active_rxon =
  1777. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1778. /* apply any changes in staging */
  1779. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1780. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1781. } else {
  1782. /* Initialize our rx_config data */
  1783. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1784. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1785. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1786. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1787. }
  1788. /* Configure Bluetooth device coexistence support */
  1789. iwl_send_bt_config(priv);
  1790. iwl_reset_run_time_calib(priv);
  1791. /* Configure the adapter for unassociated operation */
  1792. iwlcore_commit_rxon(priv);
  1793. /* At this point, the NIC is initialized and operational */
  1794. iwl_rf_kill_ct_config(priv);
  1795. iwl_leds_init(priv);
  1796. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1797. set_bit(STATUS_READY, &priv->status);
  1798. wake_up_interruptible(&priv->wait_command_queue);
  1799. iwl_power_update_mode(priv, true);
  1800. /* reassociate for ADHOC mode */
  1801. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1802. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1803. priv->vif);
  1804. if (beacon)
  1805. iwl_mac_beacon_update(priv->hw, beacon);
  1806. }
  1807. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1808. iwl_set_mode(priv, priv->iw_mode);
  1809. return;
  1810. restart:
  1811. queue_work(priv->workqueue, &priv->restart);
  1812. }
  1813. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1814. static void __iwl_down(struct iwl_priv *priv)
  1815. {
  1816. unsigned long flags;
  1817. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1818. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1819. if (!exit_pending)
  1820. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1821. iwl_clear_stations_table(priv);
  1822. /* Unblock any waiting calls */
  1823. wake_up_interruptible_all(&priv->wait_command_queue);
  1824. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1825. * exiting the module */
  1826. if (!exit_pending)
  1827. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1828. /* stop and reset the on-board processor */
  1829. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1830. /* tell the device to stop sending interrupts */
  1831. spin_lock_irqsave(&priv->lock, flags);
  1832. iwl_disable_interrupts(priv);
  1833. spin_unlock_irqrestore(&priv->lock, flags);
  1834. iwl_synchronize_irq(priv);
  1835. if (priv->mac80211_registered)
  1836. ieee80211_stop_queues(priv->hw);
  1837. /* If we have not previously called iwl_init() then
  1838. * clear all bits but the RF Kill bit and return */
  1839. if (!iwl_is_init(priv)) {
  1840. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1841. STATUS_RF_KILL_HW |
  1842. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1843. STATUS_GEO_CONFIGURED |
  1844. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1845. STATUS_EXIT_PENDING;
  1846. goto exit;
  1847. }
  1848. /* ...otherwise clear out all the status bits but the RF Kill
  1849. * bit and continue taking the NIC down. */
  1850. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1851. STATUS_RF_KILL_HW |
  1852. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1853. STATUS_GEO_CONFIGURED |
  1854. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1855. STATUS_FW_ERROR |
  1856. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1857. STATUS_EXIT_PENDING;
  1858. /* device going down, Stop using ICT table */
  1859. iwl_disable_ict(priv);
  1860. iwl_txq_ctx_stop(priv);
  1861. iwl_rxq_stop(priv);
  1862. /* Power-down device's busmaster DMA clocks */
  1863. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1864. udelay(5);
  1865. /* Make sure (redundant) we've released our request to stay awake */
  1866. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1867. /* Stop the device, and put it in low power state */
  1868. priv->cfg->ops->lib->apm_ops.stop(priv);
  1869. exit:
  1870. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1871. if (priv->ibss_beacon)
  1872. dev_kfree_skb(priv->ibss_beacon);
  1873. priv->ibss_beacon = NULL;
  1874. /* clear out any free frames */
  1875. iwl_clear_free_frames(priv);
  1876. }
  1877. static void iwl_down(struct iwl_priv *priv)
  1878. {
  1879. mutex_lock(&priv->mutex);
  1880. __iwl_down(priv);
  1881. mutex_unlock(&priv->mutex);
  1882. iwl_cancel_deferred_work(priv);
  1883. }
  1884. #define HW_READY_TIMEOUT (50)
  1885. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1886. {
  1887. int ret = 0;
  1888. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1889. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1890. /* See if we got it */
  1891. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1892. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1893. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1894. HW_READY_TIMEOUT);
  1895. if (ret != -ETIMEDOUT)
  1896. priv->hw_ready = true;
  1897. else
  1898. priv->hw_ready = false;
  1899. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1900. (priv->hw_ready == 1) ? "ready" : "not ready");
  1901. return ret;
  1902. }
  1903. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1904. {
  1905. int ret = 0;
  1906. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1907. ret = iwl_set_hw_ready(priv);
  1908. if (priv->hw_ready)
  1909. return ret;
  1910. /* If HW is not ready, prepare the conditions to check again */
  1911. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1912. CSR_HW_IF_CONFIG_REG_PREPARE);
  1913. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1914. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1915. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1916. /* HW should be ready by now, check again. */
  1917. if (ret != -ETIMEDOUT)
  1918. iwl_set_hw_ready(priv);
  1919. return ret;
  1920. }
  1921. #define MAX_HW_RESTARTS 5
  1922. static int __iwl_up(struct iwl_priv *priv)
  1923. {
  1924. int i;
  1925. int ret;
  1926. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1927. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1928. return -EIO;
  1929. }
  1930. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1931. IWL_ERR(priv, "ucode not available for device bringup\n");
  1932. return -EIO;
  1933. }
  1934. iwl_prepare_card_hw(priv);
  1935. if (!priv->hw_ready) {
  1936. IWL_WARN(priv, "Exit HW not ready\n");
  1937. return -EIO;
  1938. }
  1939. /* If platform's RF_KILL switch is NOT set to KILL */
  1940. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1941. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1942. else
  1943. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1944. if (iwl_is_rfkill(priv)) {
  1945. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1946. iwl_enable_interrupts(priv);
  1947. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1948. return 0;
  1949. }
  1950. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1951. ret = iwl_hw_nic_init(priv);
  1952. if (ret) {
  1953. IWL_ERR(priv, "Unable to init nic\n");
  1954. return ret;
  1955. }
  1956. /* make sure rfkill handshake bits are cleared */
  1957. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1958. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1959. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1960. /* clear (again), then enable host interrupts */
  1961. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1962. iwl_enable_interrupts(priv);
  1963. /* really make sure rfkill handshake bits are cleared */
  1964. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1965. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1966. /* Copy original ucode data image from disk into backup cache.
  1967. * This will be used to initialize the on-board processor's
  1968. * data SRAM for a clean start when the runtime program first loads. */
  1969. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1970. priv->ucode_data.len);
  1971. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1972. iwl_clear_stations_table(priv);
  1973. /* load bootstrap state machine,
  1974. * load bootstrap program into processor's memory,
  1975. * prepare to load the "initialize" uCode */
  1976. ret = priv->cfg->ops->lib->load_ucode(priv);
  1977. if (ret) {
  1978. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1979. ret);
  1980. continue;
  1981. }
  1982. /* start card; "initialize" will load runtime ucode */
  1983. iwl_nic_start(priv);
  1984. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1985. return 0;
  1986. }
  1987. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1988. __iwl_down(priv);
  1989. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1990. /* tried to restart and config the device for as long as our
  1991. * patience could withstand */
  1992. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1993. return -EIO;
  1994. }
  1995. /*****************************************************************************
  1996. *
  1997. * Workqueue callbacks
  1998. *
  1999. *****************************************************************************/
  2000. static void iwl_bg_init_alive_start(struct work_struct *data)
  2001. {
  2002. struct iwl_priv *priv =
  2003. container_of(data, struct iwl_priv, init_alive_start.work);
  2004. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2005. return;
  2006. mutex_lock(&priv->mutex);
  2007. priv->cfg->ops->lib->init_alive_start(priv);
  2008. mutex_unlock(&priv->mutex);
  2009. }
  2010. static void iwl_bg_alive_start(struct work_struct *data)
  2011. {
  2012. struct iwl_priv *priv =
  2013. container_of(data, struct iwl_priv, alive_start.work);
  2014. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2015. return;
  2016. /* enable dram interrupt */
  2017. iwl_reset_ict(priv);
  2018. mutex_lock(&priv->mutex);
  2019. iwl_alive_start(priv);
  2020. mutex_unlock(&priv->mutex);
  2021. }
  2022. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2023. {
  2024. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2025. run_time_calib_work);
  2026. mutex_lock(&priv->mutex);
  2027. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2028. test_bit(STATUS_SCANNING, &priv->status)) {
  2029. mutex_unlock(&priv->mutex);
  2030. return;
  2031. }
  2032. if (priv->start_calib) {
  2033. iwl_chain_noise_calibration(priv, &priv->statistics);
  2034. iwl_sensitivity_calibration(priv, &priv->statistics);
  2035. }
  2036. mutex_unlock(&priv->mutex);
  2037. return;
  2038. }
  2039. static void iwl_bg_up(struct work_struct *data)
  2040. {
  2041. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  2042. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2043. return;
  2044. mutex_lock(&priv->mutex);
  2045. __iwl_up(priv);
  2046. mutex_unlock(&priv->mutex);
  2047. }
  2048. static void iwl_bg_restart(struct work_struct *data)
  2049. {
  2050. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2051. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2052. return;
  2053. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2054. mutex_lock(&priv->mutex);
  2055. priv->vif = NULL;
  2056. priv->is_open = 0;
  2057. mutex_unlock(&priv->mutex);
  2058. iwl_down(priv);
  2059. ieee80211_restart_hw(priv->hw);
  2060. } else {
  2061. iwl_down(priv);
  2062. queue_work(priv->workqueue, &priv->up);
  2063. }
  2064. }
  2065. static void iwl_bg_rx_replenish(struct work_struct *data)
  2066. {
  2067. struct iwl_priv *priv =
  2068. container_of(data, struct iwl_priv, rx_replenish);
  2069. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2070. return;
  2071. mutex_lock(&priv->mutex);
  2072. iwl_rx_replenish(priv);
  2073. mutex_unlock(&priv->mutex);
  2074. }
  2075. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2076. void iwl_post_associate(struct iwl_priv *priv)
  2077. {
  2078. struct ieee80211_conf *conf = NULL;
  2079. int ret = 0;
  2080. unsigned long flags;
  2081. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  2082. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2083. return;
  2084. }
  2085. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2086. priv->assoc_id, priv->active_rxon.bssid_addr);
  2087. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2088. return;
  2089. if (!priv->vif || !priv->is_open)
  2090. return;
  2091. iwl_scan_cancel_timeout(priv, 200);
  2092. conf = ieee80211_get_hw_conf(priv->hw);
  2093. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2094. iwlcore_commit_rxon(priv);
  2095. iwl_setup_rxon_timing(priv);
  2096. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2097. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2098. if (ret)
  2099. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2100. "Attempting to continue.\n");
  2101. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2102. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2103. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2104. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2105. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2106. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2107. priv->assoc_id, priv->beacon_int);
  2108. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2109. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2110. else
  2111. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2112. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2113. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2114. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2115. else
  2116. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2117. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2118. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2119. }
  2120. iwlcore_commit_rxon(priv);
  2121. switch (priv->iw_mode) {
  2122. case NL80211_IFTYPE_STATION:
  2123. break;
  2124. case NL80211_IFTYPE_ADHOC:
  2125. /* assume default assoc id */
  2126. priv->assoc_id = 1;
  2127. iwl_rxon_add_station(priv, priv->bssid, 0);
  2128. iwl_send_beacon_cmd(priv);
  2129. break;
  2130. default:
  2131. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2132. __func__, priv->iw_mode);
  2133. break;
  2134. }
  2135. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2136. priv->assoc_station_added = 1;
  2137. spin_lock_irqsave(&priv->lock, flags);
  2138. iwl_activate_qos(priv, 0);
  2139. spin_unlock_irqrestore(&priv->lock, flags);
  2140. /* the chain noise calibration will enabled PM upon completion
  2141. * If chain noise has already been run, then we need to enable
  2142. * power management here */
  2143. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2144. iwl_power_update_mode(priv, false);
  2145. /* Enable Rx differential gain and sensitivity calibrations */
  2146. iwl_chain_noise_reset(priv);
  2147. priv->start_calib = 1;
  2148. }
  2149. /*****************************************************************************
  2150. *
  2151. * mac80211 entry point functions
  2152. *
  2153. *****************************************************************************/
  2154. #define UCODE_READY_TIMEOUT (4 * HZ)
  2155. /*
  2156. * Not a mac80211 entry point function, but it fits in with all the
  2157. * other mac80211 functions grouped here.
  2158. */
  2159. static int iwl_mac_setup_register(struct iwl_priv *priv)
  2160. {
  2161. int ret;
  2162. struct ieee80211_hw *hw = priv->hw;
  2163. hw->rate_control_algorithm = "iwl-agn-rs";
  2164. /* Tell mac80211 our characteristics */
  2165. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2166. IEEE80211_HW_NOISE_DBM |
  2167. IEEE80211_HW_AMPDU_AGGREGATION |
  2168. IEEE80211_HW_SPECTRUM_MGMT;
  2169. if (!priv->cfg->broken_powersave)
  2170. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2171. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2172. if (priv->cfg->sku & IWL_SKU_N)
  2173. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2174. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2175. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2176. hw->wiphy->interface_modes =
  2177. BIT(NL80211_IFTYPE_STATION) |
  2178. BIT(NL80211_IFTYPE_ADHOC);
  2179. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2180. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2181. /*
  2182. * For now, disable PS by default because it affects
  2183. * RX performance significantly.
  2184. */
  2185. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2186. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2187. /* we create the 802.11 header and a zero-length SSID element */
  2188. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2189. /* Default value; 4 EDCA QOS priorities */
  2190. hw->queues = 4;
  2191. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2192. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2193. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2194. &priv->bands[IEEE80211_BAND_2GHZ];
  2195. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2196. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2197. &priv->bands[IEEE80211_BAND_5GHZ];
  2198. ret = ieee80211_register_hw(priv->hw);
  2199. if (ret) {
  2200. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2201. return ret;
  2202. }
  2203. priv->mac80211_registered = 1;
  2204. return 0;
  2205. }
  2206. static int iwl_mac_start(struct ieee80211_hw *hw)
  2207. {
  2208. struct iwl_priv *priv = hw->priv;
  2209. int ret;
  2210. IWL_DEBUG_MAC80211(priv, "enter\n");
  2211. /* we should be verifying the device is ready to be opened */
  2212. mutex_lock(&priv->mutex);
  2213. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2214. * ucode filename and max sizes are card-specific. */
  2215. if (!priv->ucode_code.len) {
  2216. ret = iwl_read_ucode(priv);
  2217. if (ret) {
  2218. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2219. mutex_unlock(&priv->mutex);
  2220. return ret;
  2221. }
  2222. }
  2223. ret = __iwl_up(priv);
  2224. mutex_unlock(&priv->mutex);
  2225. if (ret)
  2226. return ret;
  2227. if (iwl_is_rfkill(priv))
  2228. goto out;
  2229. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2230. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2231. * mac80211 will not be run successfully. */
  2232. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2233. test_bit(STATUS_READY, &priv->status),
  2234. UCODE_READY_TIMEOUT);
  2235. if (!ret) {
  2236. if (!test_bit(STATUS_READY, &priv->status)) {
  2237. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2238. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2239. return -ETIMEDOUT;
  2240. }
  2241. }
  2242. iwl_led_start(priv);
  2243. out:
  2244. priv->is_open = 1;
  2245. IWL_DEBUG_MAC80211(priv, "leave\n");
  2246. return 0;
  2247. }
  2248. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2249. {
  2250. struct iwl_priv *priv = hw->priv;
  2251. IWL_DEBUG_MAC80211(priv, "enter\n");
  2252. if (!priv->is_open)
  2253. return;
  2254. priv->is_open = 0;
  2255. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2256. /* stop mac, cancel any scan request and clear
  2257. * RXON_FILTER_ASSOC_MSK BIT
  2258. */
  2259. mutex_lock(&priv->mutex);
  2260. iwl_scan_cancel_timeout(priv, 100);
  2261. mutex_unlock(&priv->mutex);
  2262. }
  2263. iwl_down(priv);
  2264. flush_workqueue(priv->workqueue);
  2265. /* enable interrupts again in order to receive rfkill changes */
  2266. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2267. iwl_enable_interrupts(priv);
  2268. IWL_DEBUG_MAC80211(priv, "leave\n");
  2269. }
  2270. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2271. {
  2272. struct iwl_priv *priv = hw->priv;
  2273. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2274. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2275. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2276. if (iwl_tx_skb(priv, skb))
  2277. dev_kfree_skb_any(skb);
  2278. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2279. return NETDEV_TX_OK;
  2280. }
  2281. void iwl_config_ap(struct iwl_priv *priv)
  2282. {
  2283. int ret = 0;
  2284. unsigned long flags;
  2285. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2286. return;
  2287. /* The following should be done only at AP bring up */
  2288. if (!iwl_is_associated(priv)) {
  2289. /* RXON - unassoc (to set timing command) */
  2290. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2291. iwlcore_commit_rxon(priv);
  2292. /* RXON Timing */
  2293. iwl_setup_rxon_timing(priv);
  2294. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2295. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2296. if (ret)
  2297. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2298. "Attempting to continue.\n");
  2299. /* AP has all antennas */
  2300. priv->chain_noise_data.active_chains =
  2301. priv->hw_params.valid_rx_ant;
  2302. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2303. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2304. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2305. /* FIXME: what should be the assoc_id for AP? */
  2306. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2307. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2308. priv->staging_rxon.flags |=
  2309. RXON_FLG_SHORT_PREAMBLE_MSK;
  2310. else
  2311. priv->staging_rxon.flags &=
  2312. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2313. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2314. if (priv->assoc_capability &
  2315. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2316. priv->staging_rxon.flags |=
  2317. RXON_FLG_SHORT_SLOT_MSK;
  2318. else
  2319. priv->staging_rxon.flags &=
  2320. ~RXON_FLG_SHORT_SLOT_MSK;
  2321. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2322. priv->staging_rxon.flags &=
  2323. ~RXON_FLG_SHORT_SLOT_MSK;
  2324. }
  2325. /* restore RXON assoc */
  2326. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2327. iwlcore_commit_rxon(priv);
  2328. iwl_reset_qos(priv);
  2329. spin_lock_irqsave(&priv->lock, flags);
  2330. iwl_activate_qos(priv, 1);
  2331. spin_unlock_irqrestore(&priv->lock, flags);
  2332. iwl_add_bcast_station(priv);
  2333. }
  2334. iwl_send_beacon_cmd(priv);
  2335. /* FIXME - we need to add code here to detect a totally new
  2336. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2337. * clear sta table, add BCAST sta... */
  2338. }
  2339. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2340. struct ieee80211_vif *vif,
  2341. struct ieee80211_key_conf *keyconf,
  2342. struct ieee80211_sta *sta,
  2343. u32 iv32, u16 *phase1key)
  2344. {
  2345. struct iwl_priv *priv = hw->priv;
  2346. IWL_DEBUG_MAC80211(priv, "enter\n");
  2347. iwl_update_tkip_key(priv, keyconf,
  2348. sta ? sta->addr : iwl_bcast_addr,
  2349. iv32, phase1key);
  2350. IWL_DEBUG_MAC80211(priv, "leave\n");
  2351. }
  2352. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2353. struct ieee80211_vif *vif,
  2354. struct ieee80211_sta *sta,
  2355. struct ieee80211_key_conf *key)
  2356. {
  2357. struct iwl_priv *priv = hw->priv;
  2358. const u8 *addr;
  2359. int ret;
  2360. u8 sta_id;
  2361. bool is_default_wep_key = false;
  2362. IWL_DEBUG_MAC80211(priv, "enter\n");
  2363. if (priv->cfg->mod_params->sw_crypto) {
  2364. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2365. return -EOPNOTSUPP;
  2366. }
  2367. addr = sta ? sta->addr : iwl_bcast_addr;
  2368. sta_id = iwl_find_station(priv, addr);
  2369. if (sta_id == IWL_INVALID_STATION) {
  2370. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2371. addr);
  2372. return -EINVAL;
  2373. }
  2374. mutex_lock(&priv->mutex);
  2375. iwl_scan_cancel_timeout(priv, 100);
  2376. mutex_unlock(&priv->mutex);
  2377. /* If we are getting WEP group key and we didn't receive any key mapping
  2378. * so far, we are in legacy wep mode (group key only), otherwise we are
  2379. * in 1X mode.
  2380. * In legacy wep mode, we use another host command to the uCode */
  2381. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2382. priv->iw_mode != NL80211_IFTYPE_AP) {
  2383. if (cmd == SET_KEY)
  2384. is_default_wep_key = !priv->key_mapping_key;
  2385. else
  2386. is_default_wep_key =
  2387. (key->hw_key_idx == HW_KEY_DEFAULT);
  2388. }
  2389. switch (cmd) {
  2390. case SET_KEY:
  2391. if (is_default_wep_key)
  2392. ret = iwl_set_default_wep_key(priv, key);
  2393. else
  2394. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2395. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2396. break;
  2397. case DISABLE_KEY:
  2398. if (is_default_wep_key)
  2399. ret = iwl_remove_default_wep_key(priv, key);
  2400. else
  2401. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2402. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2403. break;
  2404. default:
  2405. ret = -EINVAL;
  2406. }
  2407. IWL_DEBUG_MAC80211(priv, "leave\n");
  2408. return ret;
  2409. }
  2410. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2411. struct ieee80211_vif *vif,
  2412. enum ieee80211_ampdu_mlme_action action,
  2413. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2414. {
  2415. struct iwl_priv *priv = hw->priv;
  2416. int ret;
  2417. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2418. sta->addr, tid);
  2419. if (!(priv->cfg->sku & IWL_SKU_N))
  2420. return -EACCES;
  2421. switch (action) {
  2422. case IEEE80211_AMPDU_RX_START:
  2423. IWL_DEBUG_HT(priv, "start Rx\n");
  2424. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2425. case IEEE80211_AMPDU_RX_STOP:
  2426. IWL_DEBUG_HT(priv, "stop Rx\n");
  2427. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2428. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2429. return 0;
  2430. else
  2431. return ret;
  2432. case IEEE80211_AMPDU_TX_START:
  2433. IWL_DEBUG_HT(priv, "start Tx\n");
  2434. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2435. case IEEE80211_AMPDU_TX_STOP:
  2436. IWL_DEBUG_HT(priv, "stop Tx\n");
  2437. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2438. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2439. return 0;
  2440. else
  2441. return ret;
  2442. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2443. /* do nothing */
  2444. return -EOPNOTSUPP;
  2445. default:
  2446. IWL_DEBUG_HT(priv, "unknown\n");
  2447. return -EINVAL;
  2448. break;
  2449. }
  2450. return 0;
  2451. }
  2452. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2453. struct ieee80211_low_level_stats *stats)
  2454. {
  2455. struct iwl_priv *priv = hw->priv;
  2456. priv = hw->priv;
  2457. IWL_DEBUG_MAC80211(priv, "enter\n");
  2458. IWL_DEBUG_MAC80211(priv, "leave\n");
  2459. return 0;
  2460. }
  2461. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2462. struct ieee80211_vif *vif,
  2463. enum sta_notify_cmd cmd,
  2464. struct ieee80211_sta *sta)
  2465. {
  2466. struct iwl_priv *priv = hw->priv;
  2467. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2468. int sta_id;
  2469. /*
  2470. * TODO: We really should use this callback to
  2471. * actually maintain the station table in
  2472. * the device.
  2473. */
  2474. switch (cmd) {
  2475. case STA_NOTIFY_ADD:
  2476. atomic_set(&sta_priv->pending_frames, 0);
  2477. if (vif->type == NL80211_IFTYPE_AP)
  2478. sta_priv->client = true;
  2479. break;
  2480. case STA_NOTIFY_SLEEP:
  2481. WARN_ON(!sta_priv->client);
  2482. sta_priv->asleep = true;
  2483. if (atomic_read(&sta_priv->pending_frames) > 0)
  2484. ieee80211_sta_block_awake(hw, sta, true);
  2485. break;
  2486. case STA_NOTIFY_AWAKE:
  2487. WARN_ON(!sta_priv->client);
  2488. if (!sta_priv->asleep)
  2489. break;
  2490. sta_priv->asleep = false;
  2491. sta_id = iwl_find_station(priv, sta->addr);
  2492. if (sta_id != IWL_INVALID_STATION)
  2493. iwl_sta_modify_ps_wake(priv, sta_id);
  2494. break;
  2495. default:
  2496. break;
  2497. }
  2498. }
  2499. /*****************************************************************************
  2500. *
  2501. * sysfs attributes
  2502. *
  2503. *****************************************************************************/
  2504. #ifdef CONFIG_IWLWIFI_DEBUG
  2505. /*
  2506. * The following adds a new attribute to the sysfs representation
  2507. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2508. * used for controlling the debug level.
  2509. *
  2510. * See the level definitions in iwl for details.
  2511. *
  2512. * The debug_level being managed using sysfs below is a per device debug
  2513. * level that is used instead of the global debug level if it (the per
  2514. * device debug level) is set.
  2515. */
  2516. static ssize_t show_debug_level(struct device *d,
  2517. struct device_attribute *attr, char *buf)
  2518. {
  2519. struct iwl_priv *priv = dev_get_drvdata(d);
  2520. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2521. }
  2522. static ssize_t store_debug_level(struct device *d,
  2523. struct device_attribute *attr,
  2524. const char *buf, size_t count)
  2525. {
  2526. struct iwl_priv *priv = dev_get_drvdata(d);
  2527. unsigned long val;
  2528. int ret;
  2529. ret = strict_strtoul(buf, 0, &val);
  2530. if (ret)
  2531. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2532. else {
  2533. priv->debug_level = val;
  2534. if (iwl_alloc_traffic_mem(priv))
  2535. IWL_ERR(priv,
  2536. "Not enough memory to generate traffic log\n");
  2537. }
  2538. return strnlen(buf, count);
  2539. }
  2540. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2541. show_debug_level, store_debug_level);
  2542. #endif /* CONFIG_IWLWIFI_DEBUG */
  2543. static ssize_t show_temperature(struct device *d,
  2544. struct device_attribute *attr, char *buf)
  2545. {
  2546. struct iwl_priv *priv = dev_get_drvdata(d);
  2547. if (!iwl_is_alive(priv))
  2548. return -EAGAIN;
  2549. return sprintf(buf, "%d\n", priv->temperature);
  2550. }
  2551. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2552. static ssize_t show_tx_power(struct device *d,
  2553. struct device_attribute *attr, char *buf)
  2554. {
  2555. struct iwl_priv *priv = dev_get_drvdata(d);
  2556. if (!iwl_is_ready_rf(priv))
  2557. return sprintf(buf, "off\n");
  2558. else
  2559. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2560. }
  2561. static ssize_t store_tx_power(struct device *d,
  2562. struct device_attribute *attr,
  2563. const char *buf, size_t count)
  2564. {
  2565. struct iwl_priv *priv = dev_get_drvdata(d);
  2566. unsigned long val;
  2567. int ret;
  2568. ret = strict_strtoul(buf, 10, &val);
  2569. if (ret)
  2570. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2571. else {
  2572. ret = iwl_set_tx_power(priv, val, false);
  2573. if (ret)
  2574. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2575. ret);
  2576. else
  2577. ret = count;
  2578. }
  2579. return ret;
  2580. }
  2581. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2582. static ssize_t show_flags(struct device *d,
  2583. struct device_attribute *attr, char *buf)
  2584. {
  2585. struct iwl_priv *priv = dev_get_drvdata(d);
  2586. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2587. }
  2588. static ssize_t store_flags(struct device *d,
  2589. struct device_attribute *attr,
  2590. const char *buf, size_t count)
  2591. {
  2592. struct iwl_priv *priv = dev_get_drvdata(d);
  2593. unsigned long val;
  2594. u32 flags;
  2595. int ret = strict_strtoul(buf, 0, &val);
  2596. if (ret)
  2597. return ret;
  2598. flags = (u32)val;
  2599. mutex_lock(&priv->mutex);
  2600. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2601. /* Cancel any currently running scans... */
  2602. if (iwl_scan_cancel_timeout(priv, 100))
  2603. IWL_WARN(priv, "Could not cancel scan.\n");
  2604. else {
  2605. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2606. priv->staging_rxon.flags = cpu_to_le32(flags);
  2607. iwlcore_commit_rxon(priv);
  2608. }
  2609. }
  2610. mutex_unlock(&priv->mutex);
  2611. return count;
  2612. }
  2613. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2614. static ssize_t show_filter_flags(struct device *d,
  2615. struct device_attribute *attr, char *buf)
  2616. {
  2617. struct iwl_priv *priv = dev_get_drvdata(d);
  2618. return sprintf(buf, "0x%04X\n",
  2619. le32_to_cpu(priv->active_rxon.filter_flags));
  2620. }
  2621. static ssize_t store_filter_flags(struct device *d,
  2622. struct device_attribute *attr,
  2623. const char *buf, size_t count)
  2624. {
  2625. struct iwl_priv *priv = dev_get_drvdata(d);
  2626. unsigned long val;
  2627. u32 filter_flags;
  2628. int ret = strict_strtoul(buf, 0, &val);
  2629. if (ret)
  2630. return ret;
  2631. filter_flags = (u32)val;
  2632. mutex_lock(&priv->mutex);
  2633. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2634. /* Cancel any currently running scans... */
  2635. if (iwl_scan_cancel_timeout(priv, 100))
  2636. IWL_WARN(priv, "Could not cancel scan.\n");
  2637. else {
  2638. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2639. "0x%04X\n", filter_flags);
  2640. priv->staging_rxon.filter_flags =
  2641. cpu_to_le32(filter_flags);
  2642. iwlcore_commit_rxon(priv);
  2643. }
  2644. }
  2645. mutex_unlock(&priv->mutex);
  2646. return count;
  2647. }
  2648. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2649. store_filter_flags);
  2650. static ssize_t show_statistics(struct device *d,
  2651. struct device_attribute *attr, char *buf)
  2652. {
  2653. struct iwl_priv *priv = dev_get_drvdata(d);
  2654. u32 size = sizeof(struct iwl_notif_statistics);
  2655. u32 len = 0, ofs = 0;
  2656. u8 *data = (u8 *)&priv->statistics;
  2657. int rc = 0;
  2658. if (!iwl_is_alive(priv))
  2659. return -EAGAIN;
  2660. mutex_lock(&priv->mutex);
  2661. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2662. mutex_unlock(&priv->mutex);
  2663. if (rc) {
  2664. len = sprintf(buf,
  2665. "Error sending statistics request: 0x%08X\n", rc);
  2666. return len;
  2667. }
  2668. while (size && (PAGE_SIZE - len)) {
  2669. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2670. PAGE_SIZE - len, 1);
  2671. len = strlen(buf);
  2672. if (PAGE_SIZE - len)
  2673. buf[len++] = '\n';
  2674. ofs += 16;
  2675. size -= min(size, 16U);
  2676. }
  2677. return len;
  2678. }
  2679. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2680. static ssize_t show_rts_ht_protection(struct device *d,
  2681. struct device_attribute *attr, char *buf)
  2682. {
  2683. struct iwl_priv *priv = dev_get_drvdata(d);
  2684. return sprintf(buf, "%s\n",
  2685. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2686. }
  2687. static ssize_t store_rts_ht_protection(struct device *d,
  2688. struct device_attribute *attr,
  2689. const char *buf, size_t count)
  2690. {
  2691. struct iwl_priv *priv = dev_get_drvdata(d);
  2692. unsigned long val;
  2693. int ret;
  2694. ret = strict_strtoul(buf, 10, &val);
  2695. if (ret)
  2696. IWL_INFO(priv, "Input is not in decimal form.\n");
  2697. else {
  2698. if (!iwl_is_associated(priv))
  2699. priv->cfg->use_rts_for_ht = val ? true : false;
  2700. else
  2701. IWL_ERR(priv, "Sta associated with AP - "
  2702. "Change protection mechanism is not allowed\n");
  2703. ret = count;
  2704. }
  2705. return ret;
  2706. }
  2707. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2708. show_rts_ht_protection, store_rts_ht_protection);
  2709. /*****************************************************************************
  2710. *
  2711. * driver setup and teardown
  2712. *
  2713. *****************************************************************************/
  2714. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2715. {
  2716. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2717. init_waitqueue_head(&priv->wait_command_queue);
  2718. INIT_WORK(&priv->up, iwl_bg_up);
  2719. INIT_WORK(&priv->restart, iwl_bg_restart);
  2720. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2721. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2722. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2723. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2724. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2725. iwl_setup_scan_deferred_work(priv);
  2726. if (priv->cfg->ops->lib->setup_deferred_work)
  2727. priv->cfg->ops->lib->setup_deferred_work(priv);
  2728. init_timer(&priv->statistics_periodic);
  2729. priv->statistics_periodic.data = (unsigned long)priv;
  2730. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2731. init_timer(&priv->ucode_trace);
  2732. priv->ucode_trace.data = (unsigned long)priv;
  2733. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2734. if (!priv->cfg->use_isr_legacy)
  2735. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2736. iwl_irq_tasklet, (unsigned long)priv);
  2737. else
  2738. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2739. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2740. }
  2741. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2742. {
  2743. if (priv->cfg->ops->lib->cancel_deferred_work)
  2744. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2745. cancel_delayed_work_sync(&priv->init_alive_start);
  2746. cancel_delayed_work(&priv->scan_check);
  2747. cancel_delayed_work(&priv->alive_start);
  2748. cancel_work_sync(&priv->beacon_update);
  2749. del_timer_sync(&priv->statistics_periodic);
  2750. del_timer_sync(&priv->ucode_trace);
  2751. }
  2752. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2753. struct ieee80211_rate *rates)
  2754. {
  2755. int i;
  2756. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2757. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2758. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2759. rates[i].hw_value_short = i;
  2760. rates[i].flags = 0;
  2761. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2762. /*
  2763. * If CCK != 1M then set short preamble rate flag.
  2764. */
  2765. rates[i].flags |=
  2766. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2767. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2768. }
  2769. }
  2770. }
  2771. static int iwl_init_drv(struct iwl_priv *priv)
  2772. {
  2773. int ret;
  2774. priv->ibss_beacon = NULL;
  2775. spin_lock_init(&priv->sta_lock);
  2776. spin_lock_init(&priv->hcmd_lock);
  2777. INIT_LIST_HEAD(&priv->free_frames);
  2778. mutex_init(&priv->mutex);
  2779. /* Clear the driver's (not device's) station table */
  2780. iwl_clear_stations_table(priv);
  2781. priv->ieee_channels = NULL;
  2782. priv->ieee_rates = NULL;
  2783. priv->band = IEEE80211_BAND_2GHZ;
  2784. priv->iw_mode = NL80211_IFTYPE_STATION;
  2785. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2786. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2787. /* Choose which receivers/antennas to use */
  2788. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2789. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2790. iwl_init_scan_params(priv);
  2791. iwl_reset_qos(priv);
  2792. priv->qos_data.qos_active = 0;
  2793. priv->qos_data.qos_cap.val = 0;
  2794. priv->rates_mask = IWL_RATES_MASK;
  2795. /* Set the tx_power_user_lmt to the lowest power level
  2796. * this value will get overwritten by channel max power avg
  2797. * from eeprom */
  2798. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2799. ret = iwl_init_channel_map(priv);
  2800. if (ret) {
  2801. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2802. goto err;
  2803. }
  2804. ret = iwlcore_init_geos(priv);
  2805. if (ret) {
  2806. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2807. goto err_free_channel_map;
  2808. }
  2809. iwl_init_hw_rates(priv, priv->ieee_rates);
  2810. return 0;
  2811. err_free_channel_map:
  2812. iwl_free_channel_map(priv);
  2813. err:
  2814. return ret;
  2815. }
  2816. static void iwl_uninit_drv(struct iwl_priv *priv)
  2817. {
  2818. iwl_calib_free_results(priv);
  2819. iwlcore_free_geos(priv);
  2820. iwl_free_channel_map(priv);
  2821. kfree(priv->scan);
  2822. }
  2823. static struct attribute *iwl_sysfs_entries[] = {
  2824. &dev_attr_flags.attr,
  2825. &dev_attr_filter_flags.attr,
  2826. &dev_attr_statistics.attr,
  2827. &dev_attr_temperature.attr,
  2828. &dev_attr_tx_power.attr,
  2829. &dev_attr_rts_ht_protection.attr,
  2830. #ifdef CONFIG_IWLWIFI_DEBUG
  2831. &dev_attr_debug_level.attr,
  2832. #endif
  2833. NULL
  2834. };
  2835. static struct attribute_group iwl_attribute_group = {
  2836. .name = NULL, /* put in device directory */
  2837. .attrs = iwl_sysfs_entries,
  2838. };
  2839. static struct ieee80211_ops iwl_hw_ops = {
  2840. .tx = iwl_mac_tx,
  2841. .start = iwl_mac_start,
  2842. .stop = iwl_mac_stop,
  2843. .add_interface = iwl_mac_add_interface,
  2844. .remove_interface = iwl_mac_remove_interface,
  2845. .config = iwl_mac_config,
  2846. .configure_filter = iwl_configure_filter,
  2847. .set_key = iwl_mac_set_key,
  2848. .update_tkip_key = iwl_mac_update_tkip_key,
  2849. .get_stats = iwl_mac_get_stats,
  2850. .get_tx_stats = iwl_mac_get_tx_stats,
  2851. .conf_tx = iwl_mac_conf_tx,
  2852. .reset_tsf = iwl_mac_reset_tsf,
  2853. .bss_info_changed = iwl_bss_info_changed,
  2854. .ampdu_action = iwl_mac_ampdu_action,
  2855. .hw_scan = iwl_mac_hw_scan,
  2856. .sta_notify = iwl_mac_sta_notify,
  2857. };
  2858. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2859. {
  2860. int err = 0;
  2861. struct iwl_priv *priv;
  2862. struct ieee80211_hw *hw;
  2863. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2864. unsigned long flags;
  2865. u16 pci_cmd;
  2866. /************************
  2867. * 1. Allocating HW data
  2868. ************************/
  2869. /* Disabling hardware scan means that mac80211 will perform scans
  2870. * "the hard way", rather than using device's scan. */
  2871. if (cfg->mod_params->disable_hw_scan) {
  2872. if (iwl_debug_level & IWL_DL_INFO)
  2873. dev_printk(KERN_DEBUG, &(pdev->dev),
  2874. "Disabling hw_scan\n");
  2875. iwl_hw_ops.hw_scan = NULL;
  2876. }
  2877. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2878. if (!hw) {
  2879. err = -ENOMEM;
  2880. goto out;
  2881. }
  2882. priv = hw->priv;
  2883. /* At this point both hw and priv are allocated. */
  2884. SET_IEEE80211_DEV(hw, &pdev->dev);
  2885. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2886. priv->cfg = cfg;
  2887. priv->pci_dev = pdev;
  2888. priv->inta_mask = CSR_INI_SET_MASK;
  2889. #ifdef CONFIG_IWLWIFI_DEBUG
  2890. atomic_set(&priv->restrict_refcnt, 0);
  2891. #endif
  2892. if (iwl_alloc_traffic_mem(priv))
  2893. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2894. /**************************
  2895. * 2. Initializing PCI bus
  2896. **************************/
  2897. if (pci_enable_device(pdev)) {
  2898. err = -ENODEV;
  2899. goto out_ieee80211_free_hw;
  2900. }
  2901. pci_set_master(pdev);
  2902. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2903. if (!err)
  2904. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2905. if (err) {
  2906. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2907. if (!err)
  2908. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2909. /* both attempts failed: */
  2910. if (err) {
  2911. IWL_WARN(priv, "No suitable DMA available.\n");
  2912. goto out_pci_disable_device;
  2913. }
  2914. }
  2915. err = pci_request_regions(pdev, DRV_NAME);
  2916. if (err)
  2917. goto out_pci_disable_device;
  2918. pci_set_drvdata(pdev, priv);
  2919. /***********************
  2920. * 3. Read REV register
  2921. ***********************/
  2922. priv->hw_base = pci_iomap(pdev, 0, 0);
  2923. if (!priv->hw_base) {
  2924. err = -ENODEV;
  2925. goto out_pci_release_regions;
  2926. }
  2927. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2928. (unsigned long long) pci_resource_len(pdev, 0));
  2929. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2930. /* these spin locks will be used in apm_ops.init and EEPROM access
  2931. * we should init now
  2932. */
  2933. spin_lock_init(&priv->reg_lock);
  2934. spin_lock_init(&priv->lock);
  2935. iwl_hw_detect(priv);
  2936. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2937. priv->cfg->name, priv->hw_rev);
  2938. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2939. * PCI Tx retries from interfering with C3 CPU state */
  2940. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2941. iwl_prepare_card_hw(priv);
  2942. if (!priv->hw_ready) {
  2943. IWL_WARN(priv, "Failed, HW not ready\n");
  2944. goto out_iounmap;
  2945. }
  2946. /*****************
  2947. * 4. Read EEPROM
  2948. *****************/
  2949. /* Read the EEPROM */
  2950. err = iwl_eeprom_init(priv);
  2951. if (err) {
  2952. IWL_ERR(priv, "Unable to init EEPROM\n");
  2953. goto out_iounmap;
  2954. }
  2955. err = iwl_eeprom_check_version(priv);
  2956. if (err)
  2957. goto out_free_eeprom;
  2958. /* extract MAC Address */
  2959. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2960. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2961. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2962. /************************
  2963. * 5. Setup HW constants
  2964. ************************/
  2965. if (iwl_set_hw_params(priv)) {
  2966. IWL_ERR(priv, "failed to set hw parameters\n");
  2967. goto out_free_eeprom;
  2968. }
  2969. /*******************
  2970. * 6. Setup priv
  2971. *******************/
  2972. err = iwl_init_drv(priv);
  2973. if (err)
  2974. goto out_free_eeprom;
  2975. /* At this point both hw and priv are initialized. */
  2976. /********************
  2977. * 7. Setup services
  2978. ********************/
  2979. spin_lock_irqsave(&priv->lock, flags);
  2980. iwl_disable_interrupts(priv);
  2981. spin_unlock_irqrestore(&priv->lock, flags);
  2982. pci_enable_msi(priv->pci_dev);
  2983. iwl_alloc_isr_ict(priv);
  2984. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2985. IRQF_SHARED, DRV_NAME, priv);
  2986. if (err) {
  2987. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2988. goto out_disable_msi;
  2989. }
  2990. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2991. if (err) {
  2992. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2993. goto out_free_irq;
  2994. }
  2995. iwl_setup_deferred_work(priv);
  2996. iwl_setup_rx_handlers(priv);
  2997. /*********************************************
  2998. * 8. Enable interrupts and read RFKILL state
  2999. *********************************************/
  3000. /* enable interrupts if needed: hw bug w/a */
  3001. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3002. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3003. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3004. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3005. }
  3006. iwl_enable_interrupts(priv);
  3007. /* If platform's RF_KILL switch is NOT set to KILL */
  3008. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3009. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3010. else
  3011. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3012. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3013. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3014. iwl_power_initialize(priv);
  3015. iwl_tt_initialize(priv);
  3016. /**************************************************
  3017. * 9. Setup and register with mac80211 and debugfs
  3018. **************************************************/
  3019. err = iwl_mac_setup_register(priv);
  3020. if (err)
  3021. goto out_remove_sysfs;
  3022. err = iwl_dbgfs_register(priv, DRV_NAME);
  3023. if (err)
  3024. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  3025. return 0;
  3026. out_remove_sysfs:
  3027. destroy_workqueue(priv->workqueue);
  3028. priv->workqueue = NULL;
  3029. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3030. out_free_irq:
  3031. free_irq(priv->pci_dev->irq, priv);
  3032. iwl_free_isr_ict(priv);
  3033. out_disable_msi:
  3034. pci_disable_msi(priv->pci_dev);
  3035. iwl_uninit_drv(priv);
  3036. out_free_eeprom:
  3037. iwl_eeprom_free(priv);
  3038. out_iounmap:
  3039. pci_iounmap(pdev, priv->hw_base);
  3040. out_pci_release_regions:
  3041. pci_set_drvdata(pdev, NULL);
  3042. pci_release_regions(pdev);
  3043. out_pci_disable_device:
  3044. pci_disable_device(pdev);
  3045. out_ieee80211_free_hw:
  3046. iwl_free_traffic_mem(priv);
  3047. ieee80211_free_hw(priv->hw);
  3048. out:
  3049. return err;
  3050. }
  3051. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3052. {
  3053. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3054. unsigned long flags;
  3055. if (!priv)
  3056. return;
  3057. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3058. iwl_dbgfs_unregister(priv);
  3059. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3060. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3061. * to be called and iwl_down since we are removing the device
  3062. * we need to set STATUS_EXIT_PENDING bit.
  3063. */
  3064. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3065. if (priv->mac80211_registered) {
  3066. ieee80211_unregister_hw(priv->hw);
  3067. priv->mac80211_registered = 0;
  3068. } else {
  3069. iwl_down(priv);
  3070. }
  3071. /*
  3072. * Make sure device is reset to low power before unloading driver.
  3073. * This may be redundant with iwl_down(), but there are paths to
  3074. * run iwl_down() without calling apm_ops.stop(), and there are
  3075. * paths to avoid running iwl_down() at all before leaving driver.
  3076. * This (inexpensive) call *makes sure* device is reset.
  3077. */
  3078. priv->cfg->ops->lib->apm_ops.stop(priv);
  3079. iwl_tt_exit(priv);
  3080. /* make sure we flush any pending irq or
  3081. * tasklet for the driver
  3082. */
  3083. spin_lock_irqsave(&priv->lock, flags);
  3084. iwl_disable_interrupts(priv);
  3085. spin_unlock_irqrestore(&priv->lock, flags);
  3086. iwl_synchronize_irq(priv);
  3087. iwl_dealloc_ucode_pci(priv);
  3088. if (priv->rxq.bd)
  3089. iwl_rx_queue_free(priv, &priv->rxq);
  3090. iwl_hw_txq_ctx_free(priv);
  3091. iwl_clear_stations_table(priv);
  3092. iwl_eeprom_free(priv);
  3093. /*netif_stop_queue(dev); */
  3094. flush_workqueue(priv->workqueue);
  3095. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3096. * priv->workqueue... so we can't take down the workqueue
  3097. * until now... */
  3098. destroy_workqueue(priv->workqueue);
  3099. priv->workqueue = NULL;
  3100. iwl_free_traffic_mem(priv);
  3101. free_irq(priv->pci_dev->irq, priv);
  3102. pci_disable_msi(priv->pci_dev);
  3103. pci_iounmap(pdev, priv->hw_base);
  3104. pci_release_regions(pdev);
  3105. pci_disable_device(pdev);
  3106. pci_set_drvdata(pdev, NULL);
  3107. iwl_uninit_drv(priv);
  3108. iwl_free_isr_ict(priv);
  3109. if (priv->ibss_beacon)
  3110. dev_kfree_skb(priv->ibss_beacon);
  3111. ieee80211_free_hw(priv->hw);
  3112. }
  3113. /*****************************************************************************
  3114. *
  3115. * driver and module entry point
  3116. *
  3117. *****************************************************************************/
  3118. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3119. static struct pci_device_id iwl_hw_card_ids[] = {
  3120. #ifdef CONFIG_IWL4965
  3121. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3122. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3123. #endif /* CONFIG_IWL4965 */
  3124. #ifdef CONFIG_IWL5000
  3125. /* 5100 Series WiFi */
  3126. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3127. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3128. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3129. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3130. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3131. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3132. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3133. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3134. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3135. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3136. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3137. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3138. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3139. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3140. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3141. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3142. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3143. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3144. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3145. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3146. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3147. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3148. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3149. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3150. /* 5300 Series WiFi */
  3151. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3152. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3153. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3154. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3155. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3156. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3157. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3158. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3159. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3160. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3161. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3162. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3163. /* 5350 Series WiFi/WiMax */
  3164. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3165. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3166. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3167. /* 5150 Series Wifi/WiMax */
  3168. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3169. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3170. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3171. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3172. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3173. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3174. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3175. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3176. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3177. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3178. /* 6x00 Series */
  3179. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3180. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3181. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3182. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3183. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3184. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3185. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3186. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3187. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3188. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3189. /* 6x50 WiFi/WiMax Series */
  3190. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3191. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3192. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3193. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3194. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3195. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3196. /* 1000 Series WiFi */
  3197. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3198. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3199. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3200. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3201. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3202. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3203. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3204. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3205. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3206. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3207. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3208. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3209. #endif /* CONFIG_IWL5000 */
  3210. {0}
  3211. };
  3212. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3213. static struct pci_driver iwl_driver = {
  3214. .name = DRV_NAME,
  3215. .id_table = iwl_hw_card_ids,
  3216. .probe = iwl_pci_probe,
  3217. .remove = __devexit_p(iwl_pci_remove),
  3218. #ifdef CONFIG_PM
  3219. .suspend = iwl_pci_suspend,
  3220. .resume = iwl_pci_resume,
  3221. #endif
  3222. };
  3223. static int __init iwl_init(void)
  3224. {
  3225. int ret;
  3226. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3227. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3228. ret = iwlagn_rate_control_register();
  3229. if (ret) {
  3230. printk(KERN_ERR DRV_NAME
  3231. "Unable to register rate control algorithm: %d\n", ret);
  3232. return ret;
  3233. }
  3234. ret = pci_register_driver(&iwl_driver);
  3235. if (ret) {
  3236. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3237. goto error_register;
  3238. }
  3239. return ret;
  3240. error_register:
  3241. iwlagn_rate_control_unregister();
  3242. return ret;
  3243. }
  3244. static void __exit iwl_exit(void)
  3245. {
  3246. pci_unregister_driver(&iwl_driver);
  3247. iwlagn_rate_control_unregister();
  3248. }
  3249. module_exit(iwl_exit);
  3250. module_init(iwl_init);
  3251. #ifdef CONFIG_IWLWIFI_DEBUG
  3252. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3253. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3254. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3255. MODULE_PARM_DESC(debug, "debug output mask");
  3256. #endif