soc-cache.c 35 KB

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  1. /*
  2. * soc-cache.c -- ASoC register cache helpers
  3. *
  4. * Copyright 2009 Wolfson Microelectronics PLC.
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/i2c.h>
  14. #include <linux/spi/spi.h>
  15. #include <sound/soc.h>
  16. #include <linux/lzo.h>
  17. #include <linux/bitmap.h>
  18. #include <linux/rbtree.h>
  19. static unsigned int snd_soc_4_12_read(struct snd_soc_codec *codec,
  20. unsigned int reg)
  21. {
  22. int ret;
  23. unsigned int val;
  24. if (reg >= codec->driver->reg_cache_size ||
  25. snd_soc_codec_volatile_register(codec, reg)) {
  26. if (codec->cache_only)
  27. return -1;
  28. BUG_ON(!codec->hw_read);
  29. return codec->hw_read(codec, reg);
  30. }
  31. ret = snd_soc_cache_read(codec, reg, &val);
  32. if (ret < 0)
  33. return -1;
  34. return val;
  35. }
  36. static int snd_soc_4_12_write(struct snd_soc_codec *codec, unsigned int reg,
  37. unsigned int value)
  38. {
  39. u8 data[2];
  40. int ret;
  41. data[0] = (reg << 4) | ((value >> 8) & 0x000f);
  42. data[1] = value & 0x00ff;
  43. if (!snd_soc_codec_volatile_register(codec, reg) &&
  44. reg < codec->driver->reg_cache_size) {
  45. ret = snd_soc_cache_write(codec, reg, value);
  46. if (ret < 0)
  47. return -1;
  48. }
  49. if (codec->cache_only) {
  50. codec->cache_sync = 1;
  51. return 0;
  52. }
  53. ret = codec->hw_write(codec->control_data, data, 2);
  54. if (ret == 2)
  55. return 0;
  56. if (ret < 0)
  57. return ret;
  58. else
  59. return -EIO;
  60. }
  61. #if defined(CONFIG_SPI_MASTER)
  62. static int snd_soc_4_12_spi_write(void *control_data, const char *data,
  63. int len)
  64. {
  65. struct spi_device *spi = control_data;
  66. struct spi_transfer t;
  67. struct spi_message m;
  68. u8 msg[2];
  69. if (len <= 0)
  70. return 0;
  71. msg[0] = data[1];
  72. msg[1] = data[0];
  73. spi_message_init(&m);
  74. memset(&t, 0, (sizeof t));
  75. t.tx_buf = &msg[0];
  76. t.len = len;
  77. spi_message_add_tail(&t, &m);
  78. spi_sync(spi, &m);
  79. return len;
  80. }
  81. #else
  82. #define snd_soc_4_12_spi_write NULL
  83. #endif
  84. static unsigned int snd_soc_7_9_read(struct snd_soc_codec *codec,
  85. unsigned int reg)
  86. {
  87. int ret;
  88. unsigned int val;
  89. if (reg >= codec->driver->reg_cache_size ||
  90. snd_soc_codec_volatile_register(codec, reg)) {
  91. if (codec->cache_only)
  92. return -1;
  93. BUG_ON(!codec->hw_read);
  94. return codec->hw_read(codec, reg);
  95. }
  96. ret = snd_soc_cache_read(codec, reg, &val);
  97. if (ret < 0)
  98. return -1;
  99. return val;
  100. }
  101. static int snd_soc_7_9_write(struct snd_soc_codec *codec, unsigned int reg,
  102. unsigned int value)
  103. {
  104. u8 data[2];
  105. int ret;
  106. data[0] = (reg << 1) | ((value >> 8) & 0x0001);
  107. data[1] = value & 0x00ff;
  108. if (!snd_soc_codec_volatile_register(codec, reg) &&
  109. reg < codec->driver->reg_cache_size) {
  110. ret = snd_soc_cache_write(codec, reg, value);
  111. if (ret < 0)
  112. return -1;
  113. }
  114. if (codec->cache_only) {
  115. codec->cache_sync = 1;
  116. return 0;
  117. }
  118. ret = codec->hw_write(codec->control_data, data, 2);
  119. if (ret == 2)
  120. return 0;
  121. if (ret < 0)
  122. return ret;
  123. else
  124. return -EIO;
  125. }
  126. #if defined(CONFIG_SPI_MASTER)
  127. static int snd_soc_7_9_spi_write(void *control_data, const char *data,
  128. int len)
  129. {
  130. struct spi_device *spi = control_data;
  131. struct spi_transfer t;
  132. struct spi_message m;
  133. u8 msg[2];
  134. if (len <= 0)
  135. return 0;
  136. msg[0] = data[0];
  137. msg[1] = data[1];
  138. spi_message_init(&m);
  139. memset(&t, 0, (sizeof t));
  140. t.tx_buf = &msg[0];
  141. t.len = len;
  142. spi_message_add_tail(&t, &m);
  143. spi_sync(spi, &m);
  144. return len;
  145. }
  146. #else
  147. #define snd_soc_7_9_spi_write NULL
  148. #endif
  149. static int snd_soc_8_8_write(struct snd_soc_codec *codec, unsigned int reg,
  150. unsigned int value)
  151. {
  152. u8 data[2];
  153. int ret;
  154. reg &= 0xff;
  155. data[0] = reg;
  156. data[1] = value & 0xff;
  157. if (!snd_soc_codec_volatile_register(codec, reg) &&
  158. reg < codec->driver->reg_cache_size) {
  159. ret = snd_soc_cache_write(codec, reg, value);
  160. if (ret < 0)
  161. return -1;
  162. }
  163. if (codec->cache_only) {
  164. codec->cache_sync = 1;
  165. return 0;
  166. }
  167. if (codec->hw_write(codec->control_data, data, 2) == 2)
  168. return 0;
  169. else
  170. return -EIO;
  171. }
  172. static unsigned int snd_soc_8_8_read(struct snd_soc_codec *codec,
  173. unsigned int reg)
  174. {
  175. int ret;
  176. unsigned int val;
  177. reg &= 0xff;
  178. if (reg >= codec->driver->reg_cache_size ||
  179. snd_soc_codec_volatile_register(codec, reg)) {
  180. if (codec->cache_only)
  181. return -1;
  182. BUG_ON(!codec->hw_read);
  183. return codec->hw_read(codec, reg);
  184. }
  185. ret = snd_soc_cache_read(codec, reg, &val);
  186. if (ret < 0)
  187. return -1;
  188. return val;
  189. }
  190. #if defined(CONFIG_SPI_MASTER)
  191. static int snd_soc_8_8_spi_write(void *control_data, const char *data,
  192. int len)
  193. {
  194. struct spi_device *spi = control_data;
  195. struct spi_transfer t;
  196. struct spi_message m;
  197. u8 msg[2];
  198. if (len <= 0)
  199. return 0;
  200. msg[0] = data[0];
  201. msg[1] = data[1];
  202. spi_message_init(&m);
  203. memset(&t, 0, (sizeof t));
  204. t.tx_buf = &msg[0];
  205. t.len = len;
  206. spi_message_add_tail(&t, &m);
  207. spi_sync(spi, &m);
  208. return len;
  209. }
  210. #else
  211. #define snd_soc_8_8_spi_write NULL
  212. #endif
  213. static int snd_soc_8_16_write(struct snd_soc_codec *codec, unsigned int reg,
  214. unsigned int value)
  215. {
  216. u8 data[3];
  217. int ret;
  218. data[0] = reg;
  219. data[1] = (value >> 8) & 0xff;
  220. data[2] = value & 0xff;
  221. if (!snd_soc_codec_volatile_register(codec, reg) &&
  222. reg < codec->driver->reg_cache_size) {
  223. ret = snd_soc_cache_write(codec, reg, value);
  224. if (ret < 0)
  225. return -1;
  226. }
  227. if (codec->cache_only) {
  228. codec->cache_sync = 1;
  229. return 0;
  230. }
  231. if (codec->hw_write(codec->control_data, data, 3) == 3)
  232. return 0;
  233. else
  234. return -EIO;
  235. }
  236. static unsigned int snd_soc_8_16_read(struct snd_soc_codec *codec,
  237. unsigned int reg)
  238. {
  239. int ret;
  240. unsigned int val;
  241. if (reg >= codec->driver->reg_cache_size ||
  242. snd_soc_codec_volatile_register(codec, reg)) {
  243. if (codec->cache_only)
  244. return -1;
  245. BUG_ON(!codec->hw_read);
  246. return codec->hw_read(codec, reg);
  247. }
  248. ret = snd_soc_cache_read(codec, reg, &val);
  249. if (ret < 0)
  250. return -1;
  251. return val;
  252. }
  253. #if defined(CONFIG_SPI_MASTER)
  254. static int snd_soc_8_16_spi_write(void *control_data, const char *data,
  255. int len)
  256. {
  257. struct spi_device *spi = control_data;
  258. struct spi_transfer t;
  259. struct spi_message m;
  260. u8 msg[3];
  261. if (len <= 0)
  262. return 0;
  263. msg[0] = data[0];
  264. msg[1] = data[1];
  265. msg[2] = data[2];
  266. spi_message_init(&m);
  267. memset(&t, 0, (sizeof t));
  268. t.tx_buf = &msg[0];
  269. t.len = len;
  270. spi_message_add_tail(&t, &m);
  271. spi_sync(spi, &m);
  272. return len;
  273. }
  274. #else
  275. #define snd_soc_8_16_spi_write NULL
  276. #endif
  277. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  278. static unsigned int snd_soc_8_8_read_i2c(struct snd_soc_codec *codec,
  279. unsigned int r)
  280. {
  281. struct i2c_msg xfer[2];
  282. u8 reg = r;
  283. u8 data;
  284. int ret;
  285. struct i2c_client *client = codec->control_data;
  286. /* Write register */
  287. xfer[0].addr = client->addr;
  288. xfer[0].flags = 0;
  289. xfer[0].len = 1;
  290. xfer[0].buf = &reg;
  291. /* Read data */
  292. xfer[1].addr = client->addr;
  293. xfer[1].flags = I2C_M_RD;
  294. xfer[1].len = 1;
  295. xfer[1].buf = &data;
  296. ret = i2c_transfer(client->adapter, xfer, 2);
  297. if (ret != 2) {
  298. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  299. return 0;
  300. }
  301. return data;
  302. }
  303. #else
  304. #define snd_soc_8_8_read_i2c NULL
  305. #endif
  306. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  307. static unsigned int snd_soc_8_16_read_i2c(struct snd_soc_codec *codec,
  308. unsigned int r)
  309. {
  310. struct i2c_msg xfer[2];
  311. u8 reg = r;
  312. u16 data;
  313. int ret;
  314. struct i2c_client *client = codec->control_data;
  315. /* Write register */
  316. xfer[0].addr = client->addr;
  317. xfer[0].flags = 0;
  318. xfer[0].len = 1;
  319. xfer[0].buf = &reg;
  320. /* Read data */
  321. xfer[1].addr = client->addr;
  322. xfer[1].flags = I2C_M_RD;
  323. xfer[1].len = 2;
  324. xfer[1].buf = (u8 *)&data;
  325. ret = i2c_transfer(client->adapter, xfer, 2);
  326. if (ret != 2) {
  327. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  328. return 0;
  329. }
  330. return (data >> 8) | ((data & 0xff) << 8);
  331. }
  332. #else
  333. #define snd_soc_8_16_read_i2c NULL
  334. #endif
  335. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  336. static unsigned int snd_soc_16_8_read_i2c(struct snd_soc_codec *codec,
  337. unsigned int r)
  338. {
  339. struct i2c_msg xfer[2];
  340. u16 reg = r;
  341. u8 data;
  342. int ret;
  343. struct i2c_client *client = codec->control_data;
  344. /* Write register */
  345. xfer[0].addr = client->addr;
  346. xfer[0].flags = 0;
  347. xfer[0].len = 2;
  348. xfer[0].buf = (u8 *)&reg;
  349. /* Read data */
  350. xfer[1].addr = client->addr;
  351. xfer[1].flags = I2C_M_RD;
  352. xfer[1].len = 1;
  353. xfer[1].buf = &data;
  354. ret = i2c_transfer(client->adapter, xfer, 2);
  355. if (ret != 2) {
  356. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  357. return 0;
  358. }
  359. return data;
  360. }
  361. #else
  362. #define snd_soc_16_8_read_i2c NULL
  363. #endif
  364. static unsigned int snd_soc_16_8_read(struct snd_soc_codec *codec,
  365. unsigned int reg)
  366. {
  367. int ret;
  368. unsigned int val;
  369. reg &= 0xff;
  370. if (reg >= codec->driver->reg_cache_size ||
  371. snd_soc_codec_volatile_register(codec, reg)) {
  372. if (codec->cache_only)
  373. return -1;
  374. BUG_ON(!codec->hw_read);
  375. return codec->hw_read(codec, reg);
  376. }
  377. ret = snd_soc_cache_read(codec, reg, &val);
  378. if (ret < 0)
  379. return -1;
  380. return val;
  381. }
  382. static int snd_soc_16_8_write(struct snd_soc_codec *codec, unsigned int reg,
  383. unsigned int value)
  384. {
  385. u8 data[3];
  386. int ret;
  387. data[0] = (reg >> 8) & 0xff;
  388. data[1] = reg & 0xff;
  389. data[2] = value;
  390. reg &= 0xff;
  391. if (!snd_soc_codec_volatile_register(codec, reg) &&
  392. reg < codec->driver->reg_cache_size) {
  393. ret = snd_soc_cache_write(codec, reg, value);
  394. if (ret < 0)
  395. return -1;
  396. }
  397. if (codec->cache_only) {
  398. codec->cache_sync = 1;
  399. return 0;
  400. }
  401. ret = codec->hw_write(codec->control_data, data, 3);
  402. if (ret == 3)
  403. return 0;
  404. if (ret < 0)
  405. return ret;
  406. else
  407. return -EIO;
  408. }
  409. #if defined(CONFIG_SPI_MASTER)
  410. static int snd_soc_16_8_spi_write(void *control_data, const char *data,
  411. int len)
  412. {
  413. struct spi_device *spi = control_data;
  414. struct spi_transfer t;
  415. struct spi_message m;
  416. u8 msg[3];
  417. if (len <= 0)
  418. return 0;
  419. msg[0] = data[0];
  420. msg[1] = data[1];
  421. msg[2] = data[2];
  422. spi_message_init(&m);
  423. memset(&t, 0, (sizeof t));
  424. t.tx_buf = &msg[0];
  425. t.len = len;
  426. spi_message_add_tail(&t, &m);
  427. spi_sync(spi, &m);
  428. return len;
  429. }
  430. #else
  431. #define snd_soc_16_8_spi_write NULL
  432. #endif
  433. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  434. static unsigned int snd_soc_16_16_read_i2c(struct snd_soc_codec *codec,
  435. unsigned int r)
  436. {
  437. struct i2c_msg xfer[2];
  438. u16 reg = cpu_to_be16(r);
  439. u16 data;
  440. int ret;
  441. struct i2c_client *client = codec->control_data;
  442. /* Write register */
  443. xfer[0].addr = client->addr;
  444. xfer[0].flags = 0;
  445. xfer[0].len = 2;
  446. xfer[0].buf = (u8 *)&reg;
  447. /* Read data */
  448. xfer[1].addr = client->addr;
  449. xfer[1].flags = I2C_M_RD;
  450. xfer[1].len = 2;
  451. xfer[1].buf = (u8 *)&data;
  452. ret = i2c_transfer(client->adapter, xfer, 2);
  453. if (ret != 2) {
  454. dev_err(&client->dev, "i2c_transfer() returned %d\n", ret);
  455. return 0;
  456. }
  457. return be16_to_cpu(data);
  458. }
  459. #else
  460. #define snd_soc_16_16_read_i2c NULL
  461. #endif
  462. static unsigned int snd_soc_16_16_read(struct snd_soc_codec *codec,
  463. unsigned int reg)
  464. {
  465. int ret;
  466. unsigned int val;
  467. if (reg >= codec->driver->reg_cache_size ||
  468. snd_soc_codec_volatile_register(codec, reg)) {
  469. if (codec->cache_only)
  470. return -1;
  471. BUG_ON(!codec->hw_read);
  472. return codec->hw_read(codec, reg);
  473. }
  474. ret = snd_soc_cache_read(codec, reg, &val);
  475. if (ret < 0)
  476. return -1;
  477. return val;
  478. }
  479. static int snd_soc_16_16_write(struct snd_soc_codec *codec, unsigned int reg,
  480. unsigned int value)
  481. {
  482. u8 data[4];
  483. int ret;
  484. data[0] = (reg >> 8) & 0xff;
  485. data[1] = reg & 0xff;
  486. data[2] = (value >> 8) & 0xff;
  487. data[3] = value & 0xff;
  488. if (!snd_soc_codec_volatile_register(codec, reg) &&
  489. reg < codec->driver->reg_cache_size) {
  490. ret = snd_soc_cache_write(codec, reg, value);
  491. if (ret < 0)
  492. return -1;
  493. }
  494. if (codec->cache_only) {
  495. codec->cache_sync = 1;
  496. return 0;
  497. }
  498. ret = codec->hw_write(codec->control_data, data, 4);
  499. if (ret == 4)
  500. return 0;
  501. if (ret < 0)
  502. return ret;
  503. else
  504. return -EIO;
  505. }
  506. #if defined(CONFIG_SPI_MASTER)
  507. static int snd_soc_16_16_spi_write(void *control_data, const char *data,
  508. int len)
  509. {
  510. struct spi_device *spi = control_data;
  511. struct spi_transfer t;
  512. struct spi_message m;
  513. u8 msg[4];
  514. if (len <= 0)
  515. return 0;
  516. msg[0] = data[0];
  517. msg[1] = data[1];
  518. msg[2] = data[2];
  519. msg[3] = data[3];
  520. spi_message_init(&m);
  521. memset(&t, 0, (sizeof t));
  522. t.tx_buf = &msg[0];
  523. t.len = len;
  524. spi_message_add_tail(&t, &m);
  525. spi_sync(spi, &m);
  526. return len;
  527. }
  528. #else
  529. #define snd_soc_16_16_spi_write NULL
  530. #endif
  531. static struct {
  532. int addr_bits;
  533. int data_bits;
  534. int (*write)(struct snd_soc_codec *codec, unsigned int, unsigned int);
  535. int (*spi_write)(void *, const char *, int);
  536. unsigned int (*read)(struct snd_soc_codec *, unsigned int);
  537. unsigned int (*i2c_read)(struct snd_soc_codec *, unsigned int);
  538. } io_types[] = {
  539. {
  540. .addr_bits = 4, .data_bits = 12,
  541. .write = snd_soc_4_12_write, .read = snd_soc_4_12_read,
  542. .spi_write = snd_soc_4_12_spi_write,
  543. },
  544. {
  545. .addr_bits = 7, .data_bits = 9,
  546. .write = snd_soc_7_9_write, .read = snd_soc_7_9_read,
  547. .spi_write = snd_soc_7_9_spi_write,
  548. },
  549. {
  550. .addr_bits = 8, .data_bits = 8,
  551. .write = snd_soc_8_8_write, .read = snd_soc_8_8_read,
  552. .i2c_read = snd_soc_8_8_read_i2c,
  553. .spi_write = snd_soc_8_8_spi_write,
  554. },
  555. {
  556. .addr_bits = 8, .data_bits = 16,
  557. .write = snd_soc_8_16_write, .read = snd_soc_8_16_read,
  558. .i2c_read = snd_soc_8_16_read_i2c,
  559. .spi_write = snd_soc_8_16_spi_write,
  560. },
  561. {
  562. .addr_bits = 16, .data_bits = 8,
  563. .write = snd_soc_16_8_write, .read = snd_soc_16_8_read,
  564. .i2c_read = snd_soc_16_8_read_i2c,
  565. .spi_write = snd_soc_16_8_spi_write,
  566. },
  567. {
  568. .addr_bits = 16, .data_bits = 16,
  569. .write = snd_soc_16_16_write, .read = snd_soc_16_16_read,
  570. .i2c_read = snd_soc_16_16_read_i2c,
  571. .spi_write = snd_soc_16_16_spi_write,
  572. },
  573. };
  574. /**
  575. * snd_soc_codec_set_cache_io: Set up standard I/O functions.
  576. *
  577. * @codec: CODEC to configure.
  578. * @type: Type of cache.
  579. * @addr_bits: Number of bits of register address data.
  580. * @data_bits: Number of bits of data per register.
  581. * @control: Control bus used.
  582. *
  583. * Register formats are frequently shared between many I2C and SPI
  584. * devices. In order to promote code reuse the ASoC core provides
  585. * some standard implementations of CODEC read and write operations
  586. * which can be set up using this function.
  587. *
  588. * The caller is responsible for allocating and initialising the
  589. * actual cache.
  590. *
  591. * Note that at present this code cannot be used by CODECs with
  592. * volatile registers.
  593. */
  594. int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
  595. int addr_bits, int data_bits,
  596. enum snd_soc_control_type control)
  597. {
  598. int i;
  599. for (i = 0; i < ARRAY_SIZE(io_types); i++)
  600. if (io_types[i].addr_bits == addr_bits &&
  601. io_types[i].data_bits == data_bits)
  602. break;
  603. if (i == ARRAY_SIZE(io_types)) {
  604. printk(KERN_ERR
  605. "No I/O functions for %d bit address %d bit data\n",
  606. addr_bits, data_bits);
  607. return -EINVAL;
  608. }
  609. codec->driver->write = io_types[i].write;
  610. codec->driver->read = io_types[i].read;
  611. switch (control) {
  612. case SND_SOC_CUSTOM:
  613. break;
  614. case SND_SOC_I2C:
  615. #if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
  616. codec->hw_write = (hw_write_t)i2c_master_send;
  617. #endif
  618. if (io_types[i].i2c_read)
  619. codec->hw_read = io_types[i].i2c_read;
  620. codec->control_data = container_of(codec->dev,
  621. struct i2c_client,
  622. dev);
  623. break;
  624. case SND_SOC_SPI:
  625. if (io_types[i].spi_write)
  626. codec->hw_write = io_types[i].spi_write;
  627. codec->control_data = container_of(codec->dev,
  628. struct spi_device,
  629. dev);
  630. break;
  631. }
  632. return 0;
  633. }
  634. EXPORT_SYMBOL_GPL(snd_soc_codec_set_cache_io);
  635. struct snd_soc_rbtree_node {
  636. struct rb_node node;
  637. unsigned int reg;
  638. unsigned int value;
  639. unsigned int defval;
  640. } __attribute__ ((packed));
  641. struct snd_soc_rbtree_ctx {
  642. struct rb_root root;
  643. };
  644. static struct snd_soc_rbtree_node *snd_soc_rbtree_lookup(
  645. struct rb_root *root, unsigned int reg)
  646. {
  647. struct rb_node *node;
  648. struct snd_soc_rbtree_node *rbnode;
  649. node = root->rb_node;
  650. while (node) {
  651. rbnode = container_of(node, struct snd_soc_rbtree_node, node);
  652. if (rbnode->reg < reg)
  653. node = node->rb_left;
  654. else if (rbnode->reg > reg)
  655. node = node->rb_right;
  656. else
  657. return rbnode;
  658. }
  659. return NULL;
  660. }
  661. static int snd_soc_rbtree_insert(struct rb_root *root,
  662. struct snd_soc_rbtree_node *rbnode)
  663. {
  664. struct rb_node **new, *parent;
  665. struct snd_soc_rbtree_node *rbnode_tmp;
  666. parent = NULL;
  667. new = &root->rb_node;
  668. while (*new) {
  669. rbnode_tmp = container_of(*new, struct snd_soc_rbtree_node,
  670. node);
  671. parent = *new;
  672. if (rbnode_tmp->reg < rbnode->reg)
  673. new = &((*new)->rb_left);
  674. else if (rbnode_tmp->reg > rbnode->reg)
  675. new = &((*new)->rb_right);
  676. else
  677. return 0;
  678. }
  679. /* insert the node into the rbtree */
  680. rb_link_node(&rbnode->node, parent, new);
  681. rb_insert_color(&rbnode->node, root);
  682. return 1;
  683. }
  684. static int snd_soc_rbtree_cache_sync(struct snd_soc_codec *codec)
  685. {
  686. struct snd_soc_rbtree_ctx *rbtree_ctx;
  687. struct rb_node *node;
  688. struct snd_soc_rbtree_node *rbnode;
  689. unsigned int val;
  690. rbtree_ctx = codec->reg_cache;
  691. for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
  692. rbnode = rb_entry(node, struct snd_soc_rbtree_node, node);
  693. if (rbnode->value == rbnode->defval)
  694. continue;
  695. snd_soc_cache_read(codec, rbnode->reg, &val);
  696. snd_soc_write(codec, rbnode->reg, val);
  697. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  698. rbnode->reg, val);
  699. }
  700. return 0;
  701. }
  702. static int snd_soc_rbtree_cache_write(struct snd_soc_codec *codec,
  703. unsigned int reg, unsigned int value)
  704. {
  705. struct snd_soc_rbtree_ctx *rbtree_ctx;
  706. struct snd_soc_rbtree_node *rbnode;
  707. rbtree_ctx = codec->reg_cache;
  708. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  709. if (rbnode) {
  710. if (rbnode->value == value)
  711. return 0;
  712. rbnode->value = value;
  713. } else {
  714. /* bail out early, no need to create the rbnode yet */
  715. if (!value)
  716. return 0;
  717. /*
  718. * for uninitialized registers whose value is changed
  719. * from the default zero, create an rbnode and insert
  720. * it into the tree.
  721. */
  722. rbnode = kzalloc(sizeof *rbnode, GFP_KERNEL);
  723. if (!rbnode)
  724. return -ENOMEM;
  725. rbnode->reg = reg;
  726. rbnode->value = value;
  727. snd_soc_rbtree_insert(&rbtree_ctx->root, rbnode);
  728. }
  729. return 0;
  730. }
  731. static int snd_soc_rbtree_cache_read(struct snd_soc_codec *codec,
  732. unsigned int reg, unsigned int *value)
  733. {
  734. struct snd_soc_rbtree_ctx *rbtree_ctx;
  735. struct snd_soc_rbtree_node *rbnode;
  736. rbtree_ctx = codec->reg_cache;
  737. rbnode = snd_soc_rbtree_lookup(&rbtree_ctx->root, reg);
  738. if (rbnode) {
  739. *value = rbnode->value;
  740. } else {
  741. /* uninitialized registers default to 0 */
  742. *value = 0;
  743. }
  744. return 0;
  745. }
  746. static int snd_soc_rbtree_cache_exit(struct snd_soc_codec *codec)
  747. {
  748. struct rb_node *next;
  749. struct snd_soc_rbtree_ctx *rbtree_ctx;
  750. struct snd_soc_rbtree_node *rbtree_node;
  751. /* if we've already been called then just return */
  752. rbtree_ctx = codec->reg_cache;
  753. if (!rbtree_ctx)
  754. return 0;
  755. /* free up the rbtree */
  756. next = rb_first(&rbtree_ctx->root);
  757. while (next) {
  758. rbtree_node = rb_entry(next, struct snd_soc_rbtree_node, node);
  759. next = rb_next(&rbtree_node->node);
  760. rb_erase(&rbtree_node->node, &rbtree_ctx->root);
  761. kfree(rbtree_node);
  762. }
  763. /* release the resources */
  764. kfree(codec->reg_cache);
  765. codec->reg_cache = NULL;
  766. return 0;
  767. }
  768. static int snd_soc_rbtree_cache_init(struct snd_soc_codec *codec)
  769. {
  770. struct snd_soc_rbtree_ctx *rbtree_ctx;
  771. codec->reg_cache = kmalloc(sizeof *rbtree_ctx, GFP_KERNEL);
  772. if (!codec->reg_cache)
  773. return -ENOMEM;
  774. rbtree_ctx = codec->reg_cache;
  775. rbtree_ctx->root = RB_ROOT;
  776. if (!codec->driver->reg_cache_default)
  777. return 0;
  778. /*
  779. * populate the rbtree with the initialized registers. All other
  780. * registers will be inserted into the tree when they are first written.
  781. *
  782. * The reasoning behind this, is that we need to step through and
  783. * dereference the cache in u8/u16 increments without sacrificing
  784. * portability. This could also be done using memcpy() but that would
  785. * be slightly more cryptic.
  786. */
  787. #define snd_soc_rbtree_populate(cache) \
  788. ({ \
  789. int ret, i; \
  790. struct snd_soc_rbtree_node *rbtree_node; \
  791. \
  792. ret = 0; \
  793. cache = codec->driver->reg_cache_default; \
  794. for (i = 0; i < codec->driver->reg_cache_size; ++i) { \
  795. if (!cache[i]) \
  796. continue; \
  797. rbtree_node = kzalloc(sizeof *rbtree_node, GFP_KERNEL); \
  798. if (!rbtree_node) { \
  799. ret = -ENOMEM; \
  800. snd_soc_cache_exit(codec); \
  801. break; \
  802. } \
  803. rbtree_node->reg = i; \
  804. rbtree_node->value = cache[i]; \
  805. rbtree_node->defval = cache[i]; \
  806. snd_soc_rbtree_insert(&rbtree_ctx->root, \
  807. rbtree_node); \
  808. } \
  809. ret; \
  810. })
  811. switch (codec->driver->reg_word_size) {
  812. case 1: {
  813. const u8 *cache;
  814. return snd_soc_rbtree_populate(cache);
  815. }
  816. case 2: {
  817. const u16 *cache;
  818. return snd_soc_rbtree_populate(cache);
  819. }
  820. default:
  821. BUG();
  822. }
  823. return 0;
  824. }
  825. struct snd_soc_lzo_ctx {
  826. void *wmem;
  827. void *dst;
  828. const void *src;
  829. size_t src_len;
  830. size_t dst_len;
  831. size_t decompressed_size;
  832. unsigned long *sync_bmp;
  833. int sync_bmp_nbits;
  834. };
  835. #define LZO_BLOCK_NUM 8
  836. static int snd_soc_lzo_block_count(void)
  837. {
  838. return LZO_BLOCK_NUM;
  839. }
  840. static int snd_soc_lzo_prepare(struct snd_soc_lzo_ctx *lzo_ctx)
  841. {
  842. lzo_ctx->wmem = kmalloc(LZO1X_MEM_COMPRESS, GFP_KERNEL);
  843. if (!lzo_ctx->wmem)
  844. return -ENOMEM;
  845. return 0;
  846. }
  847. static int snd_soc_lzo_compress(struct snd_soc_lzo_ctx *lzo_ctx)
  848. {
  849. size_t compress_size;
  850. int ret;
  851. ret = lzo1x_1_compress(lzo_ctx->src, lzo_ctx->src_len,
  852. lzo_ctx->dst, &compress_size, lzo_ctx->wmem);
  853. if (ret != LZO_E_OK || compress_size > lzo_ctx->dst_len)
  854. return -EINVAL;
  855. lzo_ctx->dst_len = compress_size;
  856. return 0;
  857. }
  858. static int snd_soc_lzo_decompress(struct snd_soc_lzo_ctx *lzo_ctx)
  859. {
  860. size_t dst_len;
  861. int ret;
  862. dst_len = lzo_ctx->dst_len;
  863. ret = lzo1x_decompress_safe(lzo_ctx->src, lzo_ctx->src_len,
  864. lzo_ctx->dst, &dst_len);
  865. if (ret != LZO_E_OK || dst_len != lzo_ctx->dst_len)
  866. return -EINVAL;
  867. return 0;
  868. }
  869. static int snd_soc_lzo_compress_cache_block(struct snd_soc_codec *codec,
  870. struct snd_soc_lzo_ctx *lzo_ctx)
  871. {
  872. int ret;
  873. lzo_ctx->dst_len = lzo1x_worst_compress(PAGE_SIZE);
  874. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  875. if (!lzo_ctx->dst) {
  876. lzo_ctx->dst_len = 0;
  877. return -ENOMEM;
  878. }
  879. ret = snd_soc_lzo_compress(lzo_ctx);
  880. if (ret < 0)
  881. return ret;
  882. return 0;
  883. }
  884. static int snd_soc_lzo_decompress_cache_block(struct snd_soc_codec *codec,
  885. struct snd_soc_lzo_ctx *lzo_ctx)
  886. {
  887. int ret;
  888. lzo_ctx->dst_len = lzo_ctx->decompressed_size;
  889. lzo_ctx->dst = kmalloc(lzo_ctx->dst_len, GFP_KERNEL);
  890. if (!lzo_ctx->dst) {
  891. lzo_ctx->dst_len = 0;
  892. return -ENOMEM;
  893. }
  894. ret = snd_soc_lzo_decompress(lzo_ctx);
  895. if (ret < 0)
  896. return ret;
  897. return 0;
  898. }
  899. static inline int snd_soc_lzo_get_blkindex(struct snd_soc_codec *codec,
  900. unsigned int reg)
  901. {
  902. struct snd_soc_codec_driver *codec_drv;
  903. size_t reg_size;
  904. codec_drv = codec->driver;
  905. reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
  906. return (reg * codec_drv->reg_word_size) /
  907. DIV_ROUND_UP(reg_size, snd_soc_lzo_block_count());
  908. }
  909. static inline int snd_soc_lzo_get_blkpos(struct snd_soc_codec *codec,
  910. unsigned int reg)
  911. {
  912. struct snd_soc_codec_driver *codec_drv;
  913. size_t reg_size;
  914. codec_drv = codec->driver;
  915. reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
  916. return reg % (DIV_ROUND_UP(reg_size, snd_soc_lzo_block_count()) /
  917. codec_drv->reg_word_size);
  918. }
  919. static inline int snd_soc_lzo_get_blksize(struct snd_soc_codec *codec)
  920. {
  921. struct snd_soc_codec_driver *codec_drv;
  922. size_t reg_size;
  923. codec_drv = codec->driver;
  924. reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
  925. return DIV_ROUND_UP(reg_size, snd_soc_lzo_block_count());
  926. }
  927. static int snd_soc_lzo_cache_sync(struct snd_soc_codec *codec)
  928. {
  929. struct snd_soc_lzo_ctx **lzo_blocks;
  930. unsigned int val;
  931. int i;
  932. lzo_blocks = codec->reg_cache;
  933. for_each_set_bit(i, lzo_blocks[0]->sync_bmp, lzo_blocks[0]->sync_bmp_nbits) {
  934. snd_soc_cache_read(codec, i, &val);
  935. snd_soc_write(codec, i, val);
  936. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  937. i, val);
  938. }
  939. return 0;
  940. }
  941. static int snd_soc_lzo_cache_write(struct snd_soc_codec *codec,
  942. unsigned int reg, unsigned int value)
  943. {
  944. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  945. int ret, blkindex, blkpos;
  946. size_t blksize, tmp_dst_len;
  947. void *tmp_dst;
  948. /* index of the compressed lzo block */
  949. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  950. /* register index within the decompressed block */
  951. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  952. /* size of the compressed block */
  953. blksize = snd_soc_lzo_get_blksize(codec);
  954. lzo_blocks = codec->reg_cache;
  955. lzo_block = lzo_blocks[blkindex];
  956. /* save the pointer and length of the compressed block */
  957. tmp_dst = lzo_block->dst;
  958. tmp_dst_len = lzo_block->dst_len;
  959. /* prepare the source to be the compressed block */
  960. lzo_block->src = lzo_block->dst;
  961. lzo_block->src_len = lzo_block->dst_len;
  962. /* decompress the block */
  963. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  964. if (ret < 0) {
  965. kfree(lzo_block->dst);
  966. goto out;
  967. }
  968. /* write the new value to the cache */
  969. switch (codec->driver->reg_word_size) {
  970. case 1: {
  971. u8 *cache;
  972. cache = lzo_block->dst;
  973. if (cache[blkpos] == value) {
  974. kfree(lzo_block->dst);
  975. goto out;
  976. }
  977. cache[blkpos] = value;
  978. }
  979. break;
  980. case 2: {
  981. u16 *cache;
  982. cache = lzo_block->dst;
  983. if (cache[blkpos] == value) {
  984. kfree(lzo_block->dst);
  985. goto out;
  986. }
  987. cache[blkpos] = value;
  988. }
  989. break;
  990. default:
  991. BUG();
  992. }
  993. /* prepare the source to be the decompressed block */
  994. lzo_block->src = lzo_block->dst;
  995. lzo_block->src_len = lzo_block->dst_len;
  996. /* compress the block */
  997. ret = snd_soc_lzo_compress_cache_block(codec, lzo_block);
  998. if (ret < 0) {
  999. kfree(lzo_block->dst);
  1000. kfree(lzo_block->src);
  1001. goto out;
  1002. }
  1003. /* set the bit so we know we have to sync this register */
  1004. set_bit(reg, lzo_block->sync_bmp);
  1005. kfree(tmp_dst);
  1006. kfree(lzo_block->src);
  1007. return 0;
  1008. out:
  1009. lzo_block->dst = tmp_dst;
  1010. lzo_block->dst_len = tmp_dst_len;
  1011. return ret;
  1012. }
  1013. static int snd_soc_lzo_cache_read(struct snd_soc_codec *codec,
  1014. unsigned int reg, unsigned int *value)
  1015. {
  1016. struct snd_soc_lzo_ctx *lzo_block, **lzo_blocks;
  1017. int ret, blkindex, blkpos;
  1018. size_t blksize, tmp_dst_len;
  1019. void *tmp_dst;
  1020. *value = 0;
  1021. /* index of the compressed lzo block */
  1022. blkindex = snd_soc_lzo_get_blkindex(codec, reg);
  1023. /* register index within the decompressed block */
  1024. blkpos = snd_soc_lzo_get_blkpos(codec, reg);
  1025. /* size of the compressed block */
  1026. blksize = snd_soc_lzo_get_blksize(codec);
  1027. lzo_blocks = codec->reg_cache;
  1028. lzo_block = lzo_blocks[blkindex];
  1029. /* save the pointer and length of the compressed block */
  1030. tmp_dst = lzo_block->dst;
  1031. tmp_dst_len = lzo_block->dst_len;
  1032. /* prepare the source to be the compressed block */
  1033. lzo_block->src = lzo_block->dst;
  1034. lzo_block->src_len = lzo_block->dst_len;
  1035. /* decompress the block */
  1036. ret = snd_soc_lzo_decompress_cache_block(codec, lzo_block);
  1037. if (ret >= 0) {
  1038. /* fetch the value from the cache */
  1039. switch (codec->driver->reg_word_size) {
  1040. case 1: {
  1041. u8 *cache;
  1042. cache = lzo_block->dst;
  1043. *value = cache[blkpos];
  1044. }
  1045. break;
  1046. case 2: {
  1047. u16 *cache;
  1048. cache = lzo_block->dst;
  1049. *value = cache[blkpos];
  1050. }
  1051. break;
  1052. default:
  1053. BUG();
  1054. }
  1055. }
  1056. kfree(lzo_block->dst);
  1057. /* restore the pointer and length of the compressed block */
  1058. lzo_block->dst = tmp_dst;
  1059. lzo_block->dst_len = tmp_dst_len;
  1060. return 0;
  1061. }
  1062. static int snd_soc_lzo_cache_exit(struct snd_soc_codec *codec)
  1063. {
  1064. struct snd_soc_lzo_ctx **lzo_blocks;
  1065. int i, blkcount;
  1066. lzo_blocks = codec->reg_cache;
  1067. if (!lzo_blocks)
  1068. return 0;
  1069. blkcount = snd_soc_lzo_block_count();
  1070. /*
  1071. * the pointer to the bitmap used for syncing the cache
  1072. * is shared amongst all lzo_blocks. Ensure it is freed
  1073. * only once.
  1074. */
  1075. if (lzo_blocks[0])
  1076. kfree(lzo_blocks[0]->sync_bmp);
  1077. for (i = 0; i < blkcount; ++i) {
  1078. if (lzo_blocks[i]) {
  1079. kfree(lzo_blocks[i]->wmem);
  1080. kfree(lzo_blocks[i]->dst);
  1081. }
  1082. /* each lzo_block is a pointer returned by kmalloc or NULL */
  1083. kfree(lzo_blocks[i]);
  1084. }
  1085. kfree(lzo_blocks);
  1086. codec->reg_cache = NULL;
  1087. return 0;
  1088. }
  1089. static int snd_soc_lzo_cache_init(struct snd_soc_codec *codec)
  1090. {
  1091. struct snd_soc_lzo_ctx **lzo_blocks;
  1092. size_t reg_size, bmp_size;
  1093. struct snd_soc_codec_driver *codec_drv;
  1094. int ret, tofree, i, blksize, blkcount;
  1095. const char *p, *end;
  1096. unsigned long *sync_bmp;
  1097. ret = 0;
  1098. codec_drv = codec->driver;
  1099. reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
  1100. /*
  1101. * If we have not been given a default register cache
  1102. * then allocate a dummy zero-ed out region, compress it
  1103. * and remember to free it afterwards.
  1104. */
  1105. tofree = 0;
  1106. if (!codec_drv->reg_cache_default)
  1107. tofree = 1;
  1108. if (!codec_drv->reg_cache_default) {
  1109. codec_drv->reg_cache_default = kzalloc(reg_size,
  1110. GFP_KERNEL);
  1111. if (!codec_drv->reg_cache_default)
  1112. return -ENOMEM;
  1113. }
  1114. blkcount = snd_soc_lzo_block_count();
  1115. codec->reg_cache = kzalloc(blkcount * sizeof *lzo_blocks,
  1116. GFP_KERNEL);
  1117. if (!codec->reg_cache) {
  1118. ret = -ENOMEM;
  1119. goto err_tofree;
  1120. }
  1121. lzo_blocks = codec->reg_cache;
  1122. /*
  1123. * allocate a bitmap to be used when syncing the cache with
  1124. * the hardware. Each time a register is modified, the corresponding
  1125. * bit is set in the bitmap, so we know that we have to sync
  1126. * that register.
  1127. */
  1128. bmp_size = codec_drv->reg_cache_size;
  1129. sync_bmp = kmalloc(BITS_TO_LONGS(bmp_size) * sizeof (long),
  1130. GFP_KERNEL);
  1131. if (!sync_bmp) {
  1132. ret = -ENOMEM;
  1133. goto err;
  1134. }
  1135. bitmap_zero(sync_bmp, reg_size);
  1136. /* allocate the lzo blocks and initialize them */
  1137. for (i = 0; i < blkcount; ++i) {
  1138. lzo_blocks[i] = kzalloc(sizeof **lzo_blocks,
  1139. GFP_KERNEL);
  1140. if (!lzo_blocks[i]) {
  1141. kfree(sync_bmp);
  1142. ret = -ENOMEM;
  1143. goto err;
  1144. }
  1145. lzo_blocks[i]->sync_bmp = sync_bmp;
  1146. lzo_blocks[i]->sync_bmp_nbits = reg_size;
  1147. /* alloc the working space for the compressed block */
  1148. ret = snd_soc_lzo_prepare(lzo_blocks[i]);
  1149. if (ret < 0)
  1150. goto err;
  1151. }
  1152. blksize = snd_soc_lzo_get_blksize(codec);
  1153. p = codec_drv->reg_cache_default;
  1154. end = codec_drv->reg_cache_default + reg_size;
  1155. /* compress the register map and fill the lzo blocks */
  1156. for (i = 0; i < blkcount; ++i, p += blksize) {
  1157. lzo_blocks[i]->src = p;
  1158. if (p + blksize > end)
  1159. lzo_blocks[i]->src_len = end - p;
  1160. else
  1161. lzo_blocks[i]->src_len = blksize;
  1162. ret = snd_soc_lzo_compress_cache_block(codec,
  1163. lzo_blocks[i]);
  1164. if (ret < 0)
  1165. goto err;
  1166. lzo_blocks[i]->decompressed_size =
  1167. lzo_blocks[i]->src_len;
  1168. }
  1169. if (tofree)
  1170. kfree(codec_drv->reg_cache_default);
  1171. return 0;
  1172. err:
  1173. snd_soc_cache_exit(codec);
  1174. err_tofree:
  1175. if (tofree)
  1176. kfree(codec_drv->reg_cache_default);
  1177. return ret;
  1178. }
  1179. static int snd_soc_flat_cache_sync(struct snd_soc_codec *codec)
  1180. {
  1181. int i;
  1182. struct snd_soc_codec_driver *codec_drv;
  1183. unsigned int val;
  1184. codec_drv = codec->driver;
  1185. for (i = 0; i < codec_drv->reg_cache_size; ++i) {
  1186. snd_soc_cache_read(codec, i, &val);
  1187. if (codec_drv->reg_cache_default) {
  1188. switch (codec_drv->reg_word_size) {
  1189. case 1: {
  1190. const u8 *cache;
  1191. cache = codec_drv->reg_cache_default;
  1192. if (cache[i] == val)
  1193. continue;
  1194. }
  1195. break;
  1196. case 2: {
  1197. const u16 *cache;
  1198. cache = codec_drv->reg_cache_default;
  1199. if (cache[i] == val)
  1200. continue;
  1201. }
  1202. break;
  1203. default:
  1204. BUG();
  1205. }
  1206. }
  1207. snd_soc_write(codec, i, val);
  1208. dev_dbg(codec->dev, "Synced register %#x, value = %#x\n",
  1209. i, val);
  1210. }
  1211. return 0;
  1212. }
  1213. static int snd_soc_flat_cache_write(struct snd_soc_codec *codec,
  1214. unsigned int reg, unsigned int value)
  1215. {
  1216. switch (codec->driver->reg_word_size) {
  1217. case 1: {
  1218. u8 *cache;
  1219. cache = codec->reg_cache;
  1220. cache[reg] = value;
  1221. }
  1222. break;
  1223. case 2: {
  1224. u16 *cache;
  1225. cache = codec->reg_cache;
  1226. cache[reg] = value;
  1227. }
  1228. break;
  1229. default:
  1230. BUG();
  1231. }
  1232. return 0;
  1233. }
  1234. static int snd_soc_flat_cache_read(struct snd_soc_codec *codec,
  1235. unsigned int reg, unsigned int *value)
  1236. {
  1237. switch (codec->driver->reg_word_size) {
  1238. case 1: {
  1239. u8 *cache;
  1240. cache = codec->reg_cache;
  1241. *value = cache[reg];
  1242. }
  1243. break;
  1244. case 2: {
  1245. u16 *cache;
  1246. cache = codec->reg_cache;
  1247. *value = cache[reg];
  1248. }
  1249. break;
  1250. default:
  1251. BUG();
  1252. }
  1253. return 0;
  1254. }
  1255. static int snd_soc_flat_cache_exit(struct snd_soc_codec *codec)
  1256. {
  1257. if (!codec->reg_cache)
  1258. return 0;
  1259. kfree(codec->reg_cache);
  1260. codec->reg_cache = NULL;
  1261. return 0;
  1262. }
  1263. static int snd_soc_flat_cache_init(struct snd_soc_codec *codec)
  1264. {
  1265. struct snd_soc_codec_driver *codec_drv;
  1266. size_t reg_size;
  1267. codec_drv = codec->driver;
  1268. reg_size = codec_drv->reg_cache_size * codec_drv->reg_word_size;
  1269. if (codec_drv->reg_cache_default)
  1270. codec->reg_cache = kmemdup(codec_drv->reg_cache_default,
  1271. reg_size, GFP_KERNEL);
  1272. else
  1273. codec->reg_cache = kzalloc(reg_size, GFP_KERNEL);
  1274. if (!codec->reg_cache)
  1275. return -ENOMEM;
  1276. return 0;
  1277. }
  1278. /* an array of all supported compression types */
  1279. static const struct snd_soc_cache_ops cache_types[] = {
  1280. {
  1281. .id = SND_SOC_NO_COMPRESSION,
  1282. .init = snd_soc_flat_cache_init,
  1283. .exit = snd_soc_flat_cache_exit,
  1284. .read = snd_soc_flat_cache_read,
  1285. .write = snd_soc_flat_cache_write,
  1286. .sync = snd_soc_flat_cache_sync
  1287. },
  1288. {
  1289. .id = SND_SOC_LZO_COMPRESSION,
  1290. .init = snd_soc_lzo_cache_init,
  1291. .exit = snd_soc_lzo_cache_exit,
  1292. .read = snd_soc_lzo_cache_read,
  1293. .write = snd_soc_lzo_cache_write,
  1294. .sync = snd_soc_lzo_cache_sync
  1295. },
  1296. {
  1297. .id = SND_SOC_RBTREE_COMPRESSION,
  1298. .init = snd_soc_rbtree_cache_init,
  1299. .exit = snd_soc_rbtree_cache_exit,
  1300. .read = snd_soc_rbtree_cache_read,
  1301. .write = snd_soc_rbtree_cache_write,
  1302. .sync = snd_soc_rbtree_cache_sync
  1303. }
  1304. };
  1305. int snd_soc_cache_init(struct snd_soc_codec *codec)
  1306. {
  1307. int i;
  1308. for (i = 0; i < ARRAY_SIZE(cache_types); ++i)
  1309. if (cache_types[i].id == codec->driver->compress_type)
  1310. break;
  1311. if (i == ARRAY_SIZE(cache_types)) {
  1312. dev_err(codec->dev, "Could not match compress type: %d\n",
  1313. codec->driver->compress_type);
  1314. return -EINVAL;
  1315. }
  1316. mutex_init(&codec->cache_rw_mutex);
  1317. codec->cache_ops = &cache_types[i];
  1318. if (codec->cache_ops->init)
  1319. return codec->cache_ops->init(codec);
  1320. return -EINVAL;
  1321. }
  1322. /*
  1323. * NOTE: keep in mind that this function might be called
  1324. * multiple times.
  1325. */
  1326. int snd_soc_cache_exit(struct snd_soc_codec *codec)
  1327. {
  1328. if (codec->cache_ops && codec->cache_ops->exit)
  1329. return codec->cache_ops->exit(codec);
  1330. return -EINVAL;
  1331. }
  1332. /**
  1333. * snd_soc_cache_read: Fetch the value of a given register from the cache.
  1334. *
  1335. * @codec: CODEC to configure.
  1336. * @reg: The register index.
  1337. * @value: The value to be returned.
  1338. */
  1339. int snd_soc_cache_read(struct snd_soc_codec *codec,
  1340. unsigned int reg, unsigned int *value)
  1341. {
  1342. int ret;
  1343. mutex_lock(&codec->cache_rw_mutex);
  1344. if (value && codec->cache_ops && codec->cache_ops->read) {
  1345. ret = codec->cache_ops->read(codec, reg, value);
  1346. mutex_unlock(&codec->cache_rw_mutex);
  1347. return ret;
  1348. }
  1349. mutex_unlock(&codec->cache_rw_mutex);
  1350. return -EINVAL;
  1351. }
  1352. EXPORT_SYMBOL_GPL(snd_soc_cache_read);
  1353. /**
  1354. * snd_soc_cache_write: Set the value of a given register in the cache.
  1355. *
  1356. * @codec: CODEC to configure.
  1357. * @reg: The register index.
  1358. * @value: The new register value.
  1359. */
  1360. int snd_soc_cache_write(struct snd_soc_codec *codec,
  1361. unsigned int reg, unsigned int value)
  1362. {
  1363. int ret;
  1364. mutex_lock(&codec->cache_rw_mutex);
  1365. if (codec->cache_ops && codec->cache_ops->write) {
  1366. ret = codec->cache_ops->write(codec, reg, value);
  1367. mutex_unlock(&codec->cache_rw_mutex);
  1368. return ret;
  1369. }
  1370. mutex_unlock(&codec->cache_rw_mutex);
  1371. return -EINVAL;
  1372. }
  1373. EXPORT_SYMBOL_GPL(snd_soc_cache_write);
  1374. /**
  1375. * snd_soc_cache_sync: Sync the register cache with the hardware.
  1376. *
  1377. * @codec: CODEC to configure.
  1378. *
  1379. * Any registers that should not be synced should be marked as
  1380. * volatile. In general drivers can choose not to use the provided
  1381. * syncing functionality if they so require.
  1382. */
  1383. int snd_soc_cache_sync(struct snd_soc_codec *codec)
  1384. {
  1385. int ret;
  1386. if (!codec->cache_sync) {
  1387. return 0;
  1388. }
  1389. if (codec->cache_ops && codec->cache_ops->sync) {
  1390. ret = codec->cache_ops->sync(codec);
  1391. if (!ret)
  1392. codec->cache_sync = 0;
  1393. return ret;
  1394. }
  1395. return -EINVAL;
  1396. }
  1397. EXPORT_SYMBOL_GPL(snd_soc_cache_sync);