tx.c 31 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "tx.h"
  18. #include "efx.h"
  19. #include "falcon.h"
  20. #include "workarounds.h"
  21. /*
  22. * TX descriptor ring full threshold
  23. *
  24. * The tx_queue descriptor ring fill-level must fall below this value
  25. * before we restart the netif queue
  26. */
  27. #define EFX_NETDEV_TX_THRESHOLD(_tx_queue) \
  28. (_tx_queue->efx->type->txd_ring_mask / 2u)
  29. /* We want to be able to nest calls to netif_stop_queue(), since each
  30. * channel can have an individual stop on the queue.
  31. */
  32. void efx_stop_queue(struct efx_nic *efx)
  33. {
  34. spin_lock_bh(&efx->netif_stop_lock);
  35. EFX_TRACE(efx, "stop TX queue\n");
  36. atomic_inc(&efx->netif_stop_count);
  37. netif_stop_queue(efx->net_dev);
  38. spin_unlock_bh(&efx->netif_stop_lock);
  39. }
  40. /* Wake netif's TX queue
  41. * We want to be able to nest calls to netif_stop_queue(), since each
  42. * channel can have an individual stop on the queue.
  43. */
  44. void efx_wake_queue(struct efx_nic *efx)
  45. {
  46. local_bh_disable();
  47. if (atomic_dec_and_lock(&efx->netif_stop_count,
  48. &efx->netif_stop_lock)) {
  49. EFX_TRACE(efx, "waking TX queue\n");
  50. netif_wake_queue(efx->net_dev);
  51. spin_unlock(&efx->netif_stop_lock);
  52. }
  53. local_bh_enable();
  54. }
  55. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  56. struct efx_tx_buffer *buffer)
  57. {
  58. if (buffer->unmap_len) {
  59. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  60. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  61. buffer->unmap_len);
  62. if (buffer->unmap_single)
  63. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  64. PCI_DMA_TODEVICE);
  65. else
  66. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  67. PCI_DMA_TODEVICE);
  68. buffer->unmap_len = 0;
  69. buffer->unmap_single = false;
  70. }
  71. if (buffer->skb) {
  72. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  73. buffer->skb = NULL;
  74. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  75. "complete\n", tx_queue->queue, read_ptr);
  76. }
  77. }
  78. /**
  79. * struct efx_tso_header - a DMA mapped buffer for packet headers
  80. * @next: Linked list of free ones.
  81. * The list is protected by the TX queue lock.
  82. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  83. * @dma_addr: The DMA address of the header below.
  84. *
  85. * This controls the memory used for a TSO header. Use TSOH_DATA()
  86. * to find the packet header data. Use TSOH_SIZE() to calculate the
  87. * total size required for a given packet header length. TSO headers
  88. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  89. */
  90. struct efx_tso_header {
  91. union {
  92. struct efx_tso_header *next;
  93. size_t unmap_len;
  94. };
  95. dma_addr_t dma_addr;
  96. };
  97. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  98. struct sk_buff *skb);
  99. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  100. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  101. struct efx_tso_header *tsoh);
  102. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  103. struct efx_tx_buffer *buffer)
  104. {
  105. if (buffer->tsoh) {
  106. if (likely(!buffer->tsoh->unmap_len)) {
  107. buffer->tsoh->next = tx_queue->tso_headers_free;
  108. tx_queue->tso_headers_free = buffer->tsoh;
  109. } else {
  110. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  111. }
  112. buffer->tsoh = NULL;
  113. }
  114. }
  115. /*
  116. * Add a socket buffer to a TX queue
  117. *
  118. * This maps all fragments of a socket buffer for DMA and adds them to
  119. * the TX queue. The queue's insert pointer will be incremented by
  120. * the number of fragments in the socket buffer.
  121. *
  122. * If any DMA mapping fails, any mapped fragments will be unmapped,
  123. * the queue's insert pointer will be restored to its original value.
  124. *
  125. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  126. * You must hold netif_tx_lock() to call this function.
  127. */
  128. static int efx_enqueue_skb(struct efx_tx_queue *tx_queue,
  129. struct sk_buff *skb)
  130. {
  131. struct efx_nic *efx = tx_queue->efx;
  132. struct pci_dev *pci_dev = efx->pci_dev;
  133. struct efx_tx_buffer *buffer;
  134. skb_frag_t *fragment;
  135. struct page *page;
  136. int page_offset;
  137. unsigned int len, unmap_len = 0, fill_level, insert_ptr, misalign;
  138. dma_addr_t dma_addr, unmap_addr = 0;
  139. unsigned int dma_len;
  140. bool unmap_single;
  141. int q_space, i = 0;
  142. int rc = NETDEV_TX_OK;
  143. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  144. if (skb_shinfo((struct sk_buff *)skb)->gso_size)
  145. return efx_enqueue_skb_tso(tx_queue, skb);
  146. /* Get size of the initial fragment */
  147. len = skb_headlen(skb);
  148. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  149. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  150. /* Map for DMA. Use pci_map_single rather than pci_map_page
  151. * since this is more efficient on machines with sparse
  152. * memory.
  153. */
  154. unmap_single = true;
  155. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  156. /* Process all fragments */
  157. while (1) {
  158. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  159. goto pci_err;
  160. /* Store fields for marking in the per-fragment final
  161. * descriptor */
  162. unmap_len = len;
  163. unmap_addr = dma_addr;
  164. /* Add to TX queue, splitting across DMA boundaries */
  165. do {
  166. if (unlikely(q_space-- <= 0)) {
  167. /* It might be that completions have
  168. * happened since the xmit path last
  169. * checked. Update the xmit path's
  170. * copy of read_count.
  171. */
  172. ++tx_queue->stopped;
  173. /* This memory barrier protects the
  174. * change of stopped from the access
  175. * of read_count. */
  176. smp_mb();
  177. tx_queue->old_read_count =
  178. *(volatile unsigned *)
  179. &tx_queue->read_count;
  180. fill_level = (tx_queue->insert_count
  181. - tx_queue->old_read_count);
  182. q_space = (efx->type->txd_ring_mask - 1 -
  183. fill_level);
  184. if (unlikely(q_space-- <= 0))
  185. goto stop;
  186. smp_mb();
  187. --tx_queue->stopped;
  188. }
  189. insert_ptr = (tx_queue->insert_count &
  190. efx->type->txd_ring_mask);
  191. buffer = &tx_queue->buffer[insert_ptr];
  192. efx_tsoh_free(tx_queue, buffer);
  193. EFX_BUG_ON_PARANOID(buffer->tsoh);
  194. EFX_BUG_ON_PARANOID(buffer->skb);
  195. EFX_BUG_ON_PARANOID(buffer->len);
  196. EFX_BUG_ON_PARANOID(!buffer->continuation);
  197. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  198. dma_len = (((~dma_addr) & efx->type->tx_dma_mask) + 1);
  199. if (likely(dma_len > len))
  200. dma_len = len;
  201. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  202. if (misalign && dma_len + misalign > 512)
  203. dma_len = 512 - misalign;
  204. /* Fill out per descriptor fields */
  205. buffer->len = dma_len;
  206. buffer->dma_addr = dma_addr;
  207. len -= dma_len;
  208. dma_addr += dma_len;
  209. ++tx_queue->insert_count;
  210. } while (len);
  211. /* Transfer ownership of the unmapping to the final buffer */
  212. buffer->unmap_single = unmap_single;
  213. buffer->unmap_len = unmap_len;
  214. unmap_len = 0;
  215. /* Get address and size of next fragment */
  216. if (i >= skb_shinfo(skb)->nr_frags)
  217. break;
  218. fragment = &skb_shinfo(skb)->frags[i];
  219. len = fragment->size;
  220. page = fragment->page;
  221. page_offset = fragment->page_offset;
  222. i++;
  223. /* Map for DMA */
  224. unmap_single = false;
  225. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  226. PCI_DMA_TODEVICE);
  227. }
  228. /* Transfer ownership of the skb to the final buffer */
  229. buffer->skb = skb;
  230. buffer->continuation = false;
  231. /* Pass off to hardware */
  232. falcon_push_buffers(tx_queue);
  233. return NETDEV_TX_OK;
  234. pci_err:
  235. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  236. "fragments for DMA\n", tx_queue->queue, skb->len,
  237. skb_shinfo(skb)->nr_frags + 1);
  238. /* Mark the packet as transmitted, and free the SKB ourselves */
  239. dev_kfree_skb_any((struct sk_buff *)skb);
  240. goto unwind;
  241. stop:
  242. rc = NETDEV_TX_BUSY;
  243. if (tx_queue->stopped == 1)
  244. efx_stop_queue(efx);
  245. unwind:
  246. /* Work backwards until we hit the original insert pointer value */
  247. while (tx_queue->insert_count != tx_queue->write_count) {
  248. --tx_queue->insert_count;
  249. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  250. buffer = &tx_queue->buffer[insert_ptr];
  251. efx_dequeue_buffer(tx_queue, buffer);
  252. buffer->len = 0;
  253. }
  254. /* Free the fragment we were mid-way through pushing */
  255. if (unmap_len) {
  256. if (unmap_single)
  257. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  258. PCI_DMA_TODEVICE);
  259. else
  260. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  261. PCI_DMA_TODEVICE);
  262. }
  263. return rc;
  264. }
  265. /* Remove packets from the TX queue
  266. *
  267. * This removes packets from the TX queue, up to and including the
  268. * specified index.
  269. */
  270. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  271. unsigned int index)
  272. {
  273. struct efx_nic *efx = tx_queue->efx;
  274. unsigned int stop_index, read_ptr;
  275. unsigned int mask = tx_queue->efx->type->txd_ring_mask;
  276. stop_index = (index + 1) & mask;
  277. read_ptr = tx_queue->read_count & mask;
  278. while (read_ptr != stop_index) {
  279. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  280. if (unlikely(buffer->len == 0)) {
  281. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  282. "completion id %x\n", tx_queue->queue,
  283. read_ptr);
  284. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  285. return;
  286. }
  287. efx_dequeue_buffer(tx_queue, buffer);
  288. buffer->continuation = true;
  289. buffer->len = 0;
  290. ++tx_queue->read_count;
  291. read_ptr = tx_queue->read_count & mask;
  292. }
  293. }
  294. /* Initiate a packet transmission on the specified TX queue.
  295. * Note that returning anything other than NETDEV_TX_OK will cause the
  296. * OS to free the skb.
  297. *
  298. * This function is split out from efx_hard_start_xmit to allow the
  299. * loopback test to direct packets via specific TX queues. It is
  300. * therefore a non-static inline, so as not to penalise performance
  301. * for non-loopback transmissions.
  302. *
  303. * Context: netif_tx_lock held
  304. */
  305. inline int efx_xmit(struct efx_nic *efx,
  306. struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  307. {
  308. int rc;
  309. /* Map fragments for DMA and add to TX queue */
  310. rc = efx_enqueue_skb(tx_queue, skb);
  311. if (unlikely(rc != NETDEV_TX_OK))
  312. goto out;
  313. /* Update last TX timer */
  314. efx->net_dev->trans_start = jiffies;
  315. out:
  316. return rc;
  317. }
  318. /* Initiate a packet transmission. We use one channel per CPU
  319. * (sharing when we have more CPUs than channels). On Falcon, the TX
  320. * completion events will be directed back to the CPU that transmitted
  321. * the packet, which should be cache-efficient.
  322. *
  323. * Context: non-blocking.
  324. * Note that returning anything other than NETDEV_TX_OK will cause the
  325. * OS to free the skb.
  326. */
  327. int efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
  328. {
  329. struct efx_nic *efx = netdev_priv(net_dev);
  330. struct efx_tx_queue *tx_queue;
  331. if (unlikely(efx->port_inhibited))
  332. return NETDEV_TX_BUSY;
  333. if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
  334. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM];
  335. else
  336. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM];
  337. return efx_xmit(efx, tx_queue, skb);
  338. }
  339. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  340. {
  341. unsigned fill_level;
  342. struct efx_nic *efx = tx_queue->efx;
  343. EFX_BUG_ON_PARANOID(index > efx->type->txd_ring_mask);
  344. efx_dequeue_buffers(tx_queue, index);
  345. /* See if we need to restart the netif queue. This barrier
  346. * separates the update of read_count from the test of
  347. * stopped. */
  348. smp_mb();
  349. if (unlikely(tx_queue->stopped)) {
  350. fill_level = tx_queue->insert_count - tx_queue->read_count;
  351. if (fill_level < EFX_NETDEV_TX_THRESHOLD(tx_queue)) {
  352. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  353. /* Do this under netif_tx_lock(), to avoid racing
  354. * with efx_xmit(). */
  355. netif_tx_lock(efx->net_dev);
  356. if (tx_queue->stopped) {
  357. tx_queue->stopped = 0;
  358. efx_wake_queue(efx);
  359. }
  360. netif_tx_unlock(efx->net_dev);
  361. }
  362. }
  363. }
  364. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  365. {
  366. struct efx_nic *efx = tx_queue->efx;
  367. unsigned int txq_size;
  368. int i, rc;
  369. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  370. /* Allocate software ring */
  371. txq_size = (efx->type->txd_ring_mask + 1) * sizeof(*tx_queue->buffer);
  372. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  373. if (!tx_queue->buffer)
  374. return -ENOMEM;
  375. for (i = 0; i <= efx->type->txd_ring_mask; ++i)
  376. tx_queue->buffer[i].continuation = true;
  377. /* Allocate hardware ring */
  378. rc = falcon_probe_tx(tx_queue);
  379. if (rc)
  380. goto fail;
  381. return 0;
  382. fail:
  383. kfree(tx_queue->buffer);
  384. tx_queue->buffer = NULL;
  385. return rc;
  386. }
  387. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  388. {
  389. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  390. tx_queue->insert_count = 0;
  391. tx_queue->write_count = 0;
  392. tx_queue->read_count = 0;
  393. tx_queue->old_read_count = 0;
  394. BUG_ON(tx_queue->stopped);
  395. /* Set up TX descriptor ring */
  396. falcon_init_tx(tx_queue);
  397. }
  398. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  399. {
  400. struct efx_tx_buffer *buffer;
  401. if (!tx_queue->buffer)
  402. return;
  403. /* Free any buffers left in the ring */
  404. while (tx_queue->read_count != tx_queue->write_count) {
  405. buffer = &tx_queue->buffer[tx_queue->read_count &
  406. tx_queue->efx->type->txd_ring_mask];
  407. efx_dequeue_buffer(tx_queue, buffer);
  408. buffer->continuation = true;
  409. buffer->len = 0;
  410. ++tx_queue->read_count;
  411. }
  412. }
  413. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  414. {
  415. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  416. /* Flush TX queue, remove descriptor ring */
  417. falcon_fini_tx(tx_queue);
  418. efx_release_tx_buffers(tx_queue);
  419. /* Free up TSO header cache */
  420. efx_fini_tso(tx_queue);
  421. /* Release queue's stop on port, if any */
  422. if (tx_queue->stopped) {
  423. tx_queue->stopped = 0;
  424. efx_wake_queue(tx_queue->efx);
  425. }
  426. }
  427. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  428. {
  429. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  430. falcon_remove_tx(tx_queue);
  431. kfree(tx_queue->buffer);
  432. tx_queue->buffer = NULL;
  433. }
  434. /* Efx TCP segmentation acceleration.
  435. *
  436. * Why? Because by doing it here in the driver we can go significantly
  437. * faster than the GSO.
  438. *
  439. * Requires TX checksum offload support.
  440. */
  441. /* Number of bytes inserted at the start of a TSO header buffer,
  442. * similar to NET_IP_ALIGN.
  443. */
  444. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  445. #define TSOH_OFFSET 0
  446. #else
  447. #define TSOH_OFFSET NET_IP_ALIGN
  448. #endif
  449. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  450. /* Total size of struct efx_tso_header, buffer and padding */
  451. #define TSOH_SIZE(hdr_len) \
  452. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  453. /* Size of blocks on free list. Larger blocks must be allocated from
  454. * the heap.
  455. */
  456. #define TSOH_STD_SIZE 128
  457. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  458. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  459. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  460. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  461. /**
  462. * struct tso_state - TSO state for an SKB
  463. * @out_len: Remaining length in current segment
  464. * @seqnum: Current sequence number
  465. * @ipv4_id: Current IPv4 ID, host endian
  466. * @packet_space: Remaining space in current packet
  467. * @dma_addr: DMA address of current position
  468. * @in_len: Remaining length in current SKB fragment
  469. * @unmap_len: Length of SKB fragment
  470. * @unmap_addr: DMA address of SKB fragment
  471. * @unmap_single: DMA single vs page mapping flag
  472. * @header_len: Number of bytes of header
  473. * @full_packet_size: Number of bytes to put in each outgoing segment
  474. *
  475. * The state used during segmentation. It is put into this data structure
  476. * just to make it easy to pass into inline functions.
  477. */
  478. struct tso_state {
  479. /* Output position */
  480. unsigned out_len;
  481. unsigned seqnum;
  482. unsigned ipv4_id;
  483. unsigned packet_space;
  484. /* Input position */
  485. dma_addr_t dma_addr;
  486. unsigned in_len;
  487. unsigned unmap_len;
  488. dma_addr_t unmap_addr;
  489. bool unmap_single;
  490. unsigned header_len;
  491. int full_packet_size;
  492. };
  493. /*
  494. * Verify that our various assumptions about sk_buffs and the conditions
  495. * under which TSO will be attempted hold true.
  496. */
  497. static void efx_tso_check_safe(struct sk_buff *skb)
  498. {
  499. __be16 protocol = skb->protocol;
  500. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  501. protocol);
  502. if (protocol == htons(ETH_P_8021Q)) {
  503. /* Find the encapsulated protocol; reset network header
  504. * and transport header based on that. */
  505. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  506. protocol = veh->h_vlan_encapsulated_proto;
  507. skb_set_network_header(skb, sizeof(*veh));
  508. if (protocol == htons(ETH_P_IP))
  509. skb_set_transport_header(skb, sizeof(*veh) +
  510. 4 * ip_hdr(skb)->ihl);
  511. }
  512. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP));
  513. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  514. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  515. + (tcp_hdr(skb)->doff << 2u)) >
  516. skb_headlen(skb));
  517. }
  518. /*
  519. * Allocate a page worth of efx_tso_header structures, and string them
  520. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  521. */
  522. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  523. {
  524. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  525. struct efx_tso_header *tsoh;
  526. dma_addr_t dma_addr;
  527. u8 *base_kva, *kva;
  528. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  529. if (base_kva == NULL) {
  530. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  531. " headers\n");
  532. return -ENOMEM;
  533. }
  534. /* pci_alloc_consistent() allocates pages. */
  535. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  536. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  537. tsoh = (struct efx_tso_header *)kva;
  538. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  539. tsoh->next = tx_queue->tso_headers_free;
  540. tx_queue->tso_headers_free = tsoh;
  541. }
  542. return 0;
  543. }
  544. /* Free up a TSO header, and all others in the same page. */
  545. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  546. struct efx_tso_header *tsoh,
  547. struct pci_dev *pci_dev)
  548. {
  549. struct efx_tso_header **p;
  550. unsigned long base_kva;
  551. dma_addr_t base_dma;
  552. base_kva = (unsigned long)tsoh & PAGE_MASK;
  553. base_dma = tsoh->dma_addr & PAGE_MASK;
  554. p = &tx_queue->tso_headers_free;
  555. while (*p != NULL) {
  556. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  557. *p = (*p)->next;
  558. else
  559. p = &(*p)->next;
  560. }
  561. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  562. }
  563. static struct efx_tso_header *
  564. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  565. {
  566. struct efx_tso_header *tsoh;
  567. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  568. if (unlikely(!tsoh))
  569. return NULL;
  570. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  571. TSOH_BUFFER(tsoh), header_len,
  572. PCI_DMA_TODEVICE);
  573. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  574. tsoh->dma_addr))) {
  575. kfree(tsoh);
  576. return NULL;
  577. }
  578. tsoh->unmap_len = header_len;
  579. return tsoh;
  580. }
  581. static void
  582. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  583. {
  584. pci_unmap_single(tx_queue->efx->pci_dev,
  585. tsoh->dma_addr, tsoh->unmap_len,
  586. PCI_DMA_TODEVICE);
  587. kfree(tsoh);
  588. }
  589. /**
  590. * efx_tx_queue_insert - push descriptors onto the TX queue
  591. * @tx_queue: Efx TX queue
  592. * @dma_addr: DMA address of fragment
  593. * @len: Length of fragment
  594. * @final_buffer: The final buffer inserted into the queue
  595. *
  596. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  597. * @tx_queue full.
  598. */
  599. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  600. dma_addr_t dma_addr, unsigned len,
  601. struct efx_tx_buffer **final_buffer)
  602. {
  603. struct efx_tx_buffer *buffer;
  604. struct efx_nic *efx = tx_queue->efx;
  605. unsigned dma_len, fill_level, insert_ptr, misalign;
  606. int q_space;
  607. EFX_BUG_ON_PARANOID(len <= 0);
  608. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  609. /* -1 as there is no way to represent all descriptors used */
  610. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  611. while (1) {
  612. if (unlikely(q_space-- <= 0)) {
  613. /* It might be that completions have happened
  614. * since the xmit path last checked. Update
  615. * the xmit path's copy of read_count.
  616. */
  617. ++tx_queue->stopped;
  618. /* This memory barrier protects the change of
  619. * stopped from the access of read_count. */
  620. smp_mb();
  621. tx_queue->old_read_count =
  622. *(volatile unsigned *)&tx_queue->read_count;
  623. fill_level = (tx_queue->insert_count
  624. - tx_queue->old_read_count);
  625. q_space = efx->type->txd_ring_mask - 1 - fill_level;
  626. if (unlikely(q_space-- <= 0)) {
  627. *final_buffer = NULL;
  628. return 1;
  629. }
  630. smp_mb();
  631. --tx_queue->stopped;
  632. }
  633. insert_ptr = tx_queue->insert_count & efx->type->txd_ring_mask;
  634. buffer = &tx_queue->buffer[insert_ptr];
  635. ++tx_queue->insert_count;
  636. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  637. tx_queue->read_count >
  638. efx->type->txd_ring_mask);
  639. efx_tsoh_free(tx_queue, buffer);
  640. EFX_BUG_ON_PARANOID(buffer->len);
  641. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  642. EFX_BUG_ON_PARANOID(buffer->skb);
  643. EFX_BUG_ON_PARANOID(!buffer->continuation);
  644. EFX_BUG_ON_PARANOID(buffer->tsoh);
  645. buffer->dma_addr = dma_addr;
  646. /* Ensure we do not cross a boundary unsupported by H/W */
  647. dma_len = (~dma_addr & efx->type->tx_dma_mask) + 1;
  648. misalign = (unsigned)dma_addr & efx->type->bug5391_mask;
  649. if (misalign && dma_len + misalign > 512)
  650. dma_len = 512 - misalign;
  651. /* If there is enough space to send then do so */
  652. if (dma_len >= len)
  653. break;
  654. buffer->len = dma_len; /* Don't set the other members */
  655. dma_addr += dma_len;
  656. len -= dma_len;
  657. }
  658. EFX_BUG_ON_PARANOID(!len);
  659. buffer->len = len;
  660. *final_buffer = buffer;
  661. return 0;
  662. }
  663. /*
  664. * Put a TSO header into the TX queue.
  665. *
  666. * This is special-cased because we know that it is small enough to fit in
  667. * a single fragment, and we know it doesn't cross a page boundary. It
  668. * also allows us to not worry about end-of-packet etc.
  669. */
  670. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  671. struct efx_tso_header *tsoh, unsigned len)
  672. {
  673. struct efx_tx_buffer *buffer;
  674. buffer = &tx_queue->buffer[tx_queue->insert_count &
  675. tx_queue->efx->type->txd_ring_mask];
  676. efx_tsoh_free(tx_queue, buffer);
  677. EFX_BUG_ON_PARANOID(buffer->len);
  678. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  679. EFX_BUG_ON_PARANOID(buffer->skb);
  680. EFX_BUG_ON_PARANOID(!buffer->continuation);
  681. EFX_BUG_ON_PARANOID(buffer->tsoh);
  682. buffer->len = len;
  683. buffer->dma_addr = tsoh->dma_addr;
  684. buffer->tsoh = tsoh;
  685. ++tx_queue->insert_count;
  686. }
  687. /* Remove descriptors put into a tx_queue. */
  688. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  689. {
  690. struct efx_tx_buffer *buffer;
  691. dma_addr_t unmap_addr;
  692. /* Work backwards until we hit the original insert pointer value */
  693. while (tx_queue->insert_count != tx_queue->write_count) {
  694. --tx_queue->insert_count;
  695. buffer = &tx_queue->buffer[tx_queue->insert_count &
  696. tx_queue->efx->type->txd_ring_mask];
  697. efx_tsoh_free(tx_queue, buffer);
  698. EFX_BUG_ON_PARANOID(buffer->skb);
  699. buffer->len = 0;
  700. buffer->continuation = true;
  701. if (buffer->unmap_len) {
  702. unmap_addr = (buffer->dma_addr + buffer->len -
  703. buffer->unmap_len);
  704. if (buffer->unmap_single)
  705. pci_unmap_single(tx_queue->efx->pci_dev,
  706. unmap_addr, buffer->unmap_len,
  707. PCI_DMA_TODEVICE);
  708. else
  709. pci_unmap_page(tx_queue->efx->pci_dev,
  710. unmap_addr, buffer->unmap_len,
  711. PCI_DMA_TODEVICE);
  712. buffer->unmap_len = 0;
  713. }
  714. }
  715. }
  716. /* Parse the SKB header and initialise state. */
  717. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  718. {
  719. /* All ethernet/IP/TCP headers combined size is TCP header size
  720. * plus offset of TCP header relative to start of packet.
  721. */
  722. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  723. + PTR_DIFF(tcp_hdr(skb), skb->data));
  724. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  725. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  726. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  727. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  728. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  729. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  730. st->packet_space = st->full_packet_size;
  731. st->out_len = skb->len - st->header_len;
  732. st->unmap_len = 0;
  733. st->unmap_single = false;
  734. }
  735. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  736. skb_frag_t *frag)
  737. {
  738. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  739. frag->page_offset, frag->size,
  740. PCI_DMA_TODEVICE);
  741. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  742. st->unmap_single = false;
  743. st->unmap_len = frag->size;
  744. st->in_len = frag->size;
  745. st->dma_addr = st->unmap_addr;
  746. return 0;
  747. }
  748. return -ENOMEM;
  749. }
  750. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  751. const struct sk_buff *skb)
  752. {
  753. int hl = st->header_len;
  754. int len = skb_headlen(skb) - hl;
  755. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  756. len, PCI_DMA_TODEVICE);
  757. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  758. st->unmap_single = true;
  759. st->unmap_len = len;
  760. st->in_len = len;
  761. st->dma_addr = st->unmap_addr;
  762. return 0;
  763. }
  764. return -ENOMEM;
  765. }
  766. /**
  767. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  768. * @tx_queue: Efx TX queue
  769. * @skb: Socket buffer
  770. * @st: TSO state
  771. *
  772. * Form descriptors for the current fragment, until we reach the end
  773. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  774. * space in @tx_queue.
  775. */
  776. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  777. const struct sk_buff *skb,
  778. struct tso_state *st)
  779. {
  780. struct efx_tx_buffer *buffer;
  781. int n, end_of_packet, rc;
  782. if (st->in_len == 0)
  783. return 0;
  784. if (st->packet_space == 0)
  785. return 0;
  786. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  787. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  788. n = min(st->in_len, st->packet_space);
  789. st->packet_space -= n;
  790. st->out_len -= n;
  791. st->in_len -= n;
  792. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  793. if (likely(rc == 0)) {
  794. if (st->out_len == 0)
  795. /* Transfer ownership of the skb */
  796. buffer->skb = skb;
  797. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  798. buffer->continuation = !end_of_packet;
  799. if (st->in_len == 0) {
  800. /* Transfer ownership of the pci mapping */
  801. buffer->unmap_len = st->unmap_len;
  802. buffer->unmap_single = st->unmap_single;
  803. st->unmap_len = 0;
  804. }
  805. }
  806. st->dma_addr += n;
  807. return rc;
  808. }
  809. /**
  810. * tso_start_new_packet - generate a new header and prepare for the new packet
  811. * @tx_queue: Efx TX queue
  812. * @skb: Socket buffer
  813. * @st: TSO state
  814. *
  815. * Generate a new header and prepare for the new packet. Return 0 on
  816. * success, or -1 if failed to alloc header.
  817. */
  818. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  819. const struct sk_buff *skb,
  820. struct tso_state *st)
  821. {
  822. struct efx_tso_header *tsoh;
  823. struct iphdr *tsoh_iph;
  824. struct tcphdr *tsoh_th;
  825. unsigned ip_length;
  826. u8 *header;
  827. /* Allocate a DMA-mapped header buffer. */
  828. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  829. if (tx_queue->tso_headers_free == NULL) {
  830. if (efx_tsoh_block_alloc(tx_queue))
  831. return -1;
  832. }
  833. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  834. tsoh = tx_queue->tso_headers_free;
  835. tx_queue->tso_headers_free = tsoh->next;
  836. tsoh->unmap_len = 0;
  837. } else {
  838. tx_queue->tso_long_headers++;
  839. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  840. if (unlikely(!tsoh))
  841. return -1;
  842. }
  843. header = TSOH_BUFFER(tsoh);
  844. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  845. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  846. /* Copy and update the headers. */
  847. memcpy(header, skb->data, st->header_len);
  848. tsoh_th->seq = htonl(st->seqnum);
  849. st->seqnum += skb_shinfo(skb)->gso_size;
  850. if (st->out_len > skb_shinfo(skb)->gso_size) {
  851. /* This packet will not finish the TSO burst. */
  852. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  853. tsoh_th->fin = 0;
  854. tsoh_th->psh = 0;
  855. } else {
  856. /* This packet will be the last in the TSO burst. */
  857. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  858. tsoh_th->fin = tcp_hdr(skb)->fin;
  859. tsoh_th->psh = tcp_hdr(skb)->psh;
  860. }
  861. tsoh_iph->tot_len = htons(ip_length);
  862. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  863. tsoh_iph->id = htons(st->ipv4_id);
  864. st->ipv4_id++;
  865. st->packet_space = skb_shinfo(skb)->gso_size;
  866. ++tx_queue->tso_packets;
  867. /* Form a descriptor for this header. */
  868. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  869. return 0;
  870. }
  871. /**
  872. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  873. * @tx_queue: Efx TX queue
  874. * @skb: Socket buffer
  875. *
  876. * Context: You must hold netif_tx_lock() to call this function.
  877. *
  878. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  879. * @skb was not enqueued. In all cases @skb is consumed. Return
  880. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  881. */
  882. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  883. struct sk_buff *skb)
  884. {
  885. struct efx_nic *efx = tx_queue->efx;
  886. int frag_i, rc, rc2 = NETDEV_TX_OK;
  887. struct tso_state state;
  888. /* Verify TSO is safe - these checks should never fail. */
  889. efx_tso_check_safe(skb);
  890. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  891. tso_start(&state, skb);
  892. /* Assume that skb header area contains exactly the headers, and
  893. * all payload is in the frag list.
  894. */
  895. if (skb_headlen(skb) == state.header_len) {
  896. /* Grab the first payload fragment. */
  897. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  898. frag_i = 0;
  899. rc = tso_get_fragment(&state, efx,
  900. skb_shinfo(skb)->frags + frag_i);
  901. if (rc)
  902. goto mem_err;
  903. } else {
  904. rc = tso_get_head_fragment(&state, efx, skb);
  905. if (rc)
  906. goto mem_err;
  907. frag_i = -1;
  908. }
  909. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  910. goto mem_err;
  911. while (1) {
  912. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  913. if (unlikely(rc))
  914. goto stop;
  915. /* Move onto the next fragment? */
  916. if (state.in_len == 0) {
  917. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  918. /* End of payload reached. */
  919. break;
  920. rc = tso_get_fragment(&state, efx,
  921. skb_shinfo(skb)->frags + frag_i);
  922. if (rc)
  923. goto mem_err;
  924. }
  925. /* Start at new packet? */
  926. if (state.packet_space == 0 &&
  927. tso_start_new_packet(tx_queue, skb, &state) < 0)
  928. goto mem_err;
  929. }
  930. /* Pass off to hardware */
  931. falcon_push_buffers(tx_queue);
  932. tx_queue->tso_bursts++;
  933. return NETDEV_TX_OK;
  934. mem_err:
  935. EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n");
  936. dev_kfree_skb_any((struct sk_buff *)skb);
  937. goto unwind;
  938. stop:
  939. rc2 = NETDEV_TX_BUSY;
  940. /* Stop the queue if it wasn't stopped before. */
  941. if (tx_queue->stopped == 1)
  942. efx_stop_queue(efx);
  943. unwind:
  944. /* Free the DMA mapping we were in the process of writing out */
  945. if (state.unmap_len) {
  946. if (state.unmap_single)
  947. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  948. state.unmap_len, PCI_DMA_TODEVICE);
  949. else
  950. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  951. state.unmap_len, PCI_DMA_TODEVICE);
  952. }
  953. efx_enqueue_unwind(tx_queue);
  954. return rc2;
  955. }
  956. /*
  957. * Free up all TSO datastructures associated with tx_queue. This
  958. * routine should be called only once the tx_queue is both empty and
  959. * will no longer be used.
  960. */
  961. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  962. {
  963. unsigned i;
  964. if (tx_queue->buffer) {
  965. for (i = 0; i <= tx_queue->efx->type->txd_ring_mask; ++i)
  966. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  967. }
  968. while (tx_queue->tso_headers_free != NULL)
  969. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  970. tx_queue->efx->pci_dev);
  971. }