rgb.c 6.0 KB

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  1. /*
  2. * Copyright (C) 2012 Avionic Design GmbH
  3. * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <linux/clk.h>
  10. #include "drm.h"
  11. #include "dc.h"
  12. struct tegra_rgb {
  13. struct tegra_output output;
  14. struct tegra_dc *dc;
  15. struct clk *clk_parent;
  16. struct clk *clk;
  17. };
  18. static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
  19. {
  20. return container_of(output, struct tegra_rgb, output);
  21. }
  22. struct reg_entry {
  23. unsigned long offset;
  24. unsigned long value;
  25. };
  26. static const struct reg_entry rgb_enable[] = {
  27. { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
  28. { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
  29. { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
  30. { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
  31. { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
  32. { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
  33. { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
  34. { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
  35. { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
  36. { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
  37. { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
  38. { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
  39. { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
  40. { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
  41. { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
  42. { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
  43. { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
  44. { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
  45. { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
  46. };
  47. static const struct reg_entry rgb_disable[] = {
  48. { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
  49. { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
  50. { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
  51. { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
  52. { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
  53. { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
  54. { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
  55. { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
  56. { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
  57. { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
  58. { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
  59. { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
  60. { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
  61. { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
  62. { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
  63. { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
  64. { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
  65. { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
  66. { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
  67. };
  68. static void tegra_dc_write_regs(struct tegra_dc *dc,
  69. const struct reg_entry *table,
  70. unsigned int num)
  71. {
  72. unsigned int i;
  73. for (i = 0; i < num; i++)
  74. tegra_dc_writel(dc, table[i].value, table[i].offset);
  75. }
  76. static int tegra_output_rgb_enable(struct tegra_output *output)
  77. {
  78. struct tegra_rgb *rgb = to_rgb(output);
  79. tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
  80. return 0;
  81. }
  82. static int tegra_output_rgb_disable(struct tegra_output *output)
  83. {
  84. struct tegra_rgb *rgb = to_rgb(output);
  85. tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
  86. return 0;
  87. }
  88. static int tegra_output_rgb_setup_clock(struct tegra_output *output,
  89. struct clk *clk, unsigned long pclk)
  90. {
  91. struct tegra_rgb *rgb = to_rgb(output);
  92. return clk_set_parent(clk, rgb->clk_parent);
  93. }
  94. static int tegra_output_rgb_check_mode(struct tegra_output *output,
  95. struct drm_display_mode *mode,
  96. enum drm_mode_status *status)
  97. {
  98. /*
  99. * FIXME: For now, always assume that the mode is okay. There are
  100. * unresolved issues with clk_round_rate(), which doesn't always
  101. * reliably report whether a frequency can be set or not.
  102. */
  103. *status = MODE_OK;
  104. return 0;
  105. }
  106. static const struct tegra_output_ops rgb_ops = {
  107. .enable = tegra_output_rgb_enable,
  108. .disable = tegra_output_rgb_disable,
  109. .setup_clock = tegra_output_rgb_setup_clock,
  110. .check_mode = tegra_output_rgb_check_mode,
  111. };
  112. int tegra_dc_rgb_probe(struct tegra_dc *dc)
  113. {
  114. struct device_node *np;
  115. struct tegra_rgb *rgb;
  116. int err;
  117. np = of_get_child_by_name(dc->dev->of_node, "rgb");
  118. if (!np || !of_device_is_available(np))
  119. return -ENODEV;
  120. rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
  121. if (!rgb)
  122. return -ENOMEM;
  123. rgb->output.dev = dc->dev;
  124. rgb->output.of_node = np;
  125. rgb->dc = dc;
  126. err = tegra_output_probe(&rgb->output);
  127. if (err < 0)
  128. return err;
  129. rgb->clk = devm_clk_get(dc->dev, NULL);
  130. if (IS_ERR(rgb->clk)) {
  131. dev_err(dc->dev, "failed to get clock\n");
  132. return PTR_ERR(rgb->clk);
  133. }
  134. rgb->clk_parent = devm_clk_get(dc->dev, "parent");
  135. if (IS_ERR(rgb->clk_parent)) {
  136. dev_err(dc->dev, "failed to get parent clock\n");
  137. return PTR_ERR(rgb->clk_parent);
  138. }
  139. err = clk_set_parent(rgb->clk, rgb->clk_parent);
  140. if (err < 0) {
  141. dev_err(dc->dev, "failed to set parent clock: %d\n", err);
  142. return err;
  143. }
  144. dc->rgb = &rgb->output;
  145. return 0;
  146. }
  147. int tegra_dc_rgb_remove(struct tegra_dc *dc)
  148. {
  149. int err;
  150. if (!dc->rgb)
  151. return 0;
  152. err = tegra_output_remove(dc->rgb);
  153. if (err < 0)
  154. return err;
  155. return 0;
  156. }
  157. int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
  158. {
  159. struct tegra_rgb *rgb = to_rgb(dc->rgb);
  160. int err;
  161. if (!dc->rgb)
  162. return -ENODEV;
  163. rgb->output.type = TEGRA_OUTPUT_RGB;
  164. rgb->output.ops = &rgb_ops;
  165. err = tegra_output_init(dc->base.dev, &rgb->output);
  166. if (err < 0) {
  167. dev_err(dc->dev, "output setup failed: %d\n", err);
  168. return err;
  169. }
  170. /*
  171. * By default, outputs can be associated with each display controller.
  172. * RGB outputs are an exception, so we make sure they can be attached
  173. * to only their parent display controller.
  174. */
  175. rgb->output.encoder.possible_crtcs = 1 << dc->pipe;
  176. return 0;
  177. }
  178. int tegra_dc_rgb_exit(struct tegra_dc *dc)
  179. {
  180. if (dc->rgb) {
  181. int err;
  182. err = tegra_output_disable(dc->rgb);
  183. if (err < 0) {
  184. dev_err(dc->dev, "output failed to disable: %d\n", err);
  185. return err;
  186. }
  187. err = tegra_output_exit(dc->rgb);
  188. if (err < 0) {
  189. dev_err(dc->dev, "output cleanup failed: %d\n", err);
  190. return err;
  191. }
  192. dc->rgb = NULL;
  193. }
  194. return 0;
  195. }