Home Verkennen Help
Registreren Inloggen
phyus
/
linux-vybrid_public
8
0
Vork 0
Bestanden Issues 0 Pull-aanvragen 0 Wiki
Boom: a7ed099ffc
Aftakkingen Labels
linux-vybrid_pu...
/
arch
/
arm
/
mach-spear
/
include
/
mach
/
spear.h

spear.h 3.5 KB
Geschiedenis Ruwe

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101 
  1. /*
    2. 

  2.  * SPEAr3xx/6xx Machine family specific definition
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2009,2012 ST Microelectronics
    5. 

  5.  * Rajeev Kumar<rajeev-dlh.kumar@st.com>
    6. 

  6.  * Viresh Kumar <viresh.linux@gmail.com>
    7. 

  7.  *
    8. 

  8.  * This file is licensed under the terms of the GNU General Public
    9. 

  9.  * License version 2. This program is licensed "as is" without any
    10. 

  10.  * warranty of any kind, whether express or implied.
    11. 

  11.  */
    12. 

  12. 

  13. #ifndef __MACH_SPEAR_H
    14. 

  14. #define __MACH_SPEAR_H
    15. 

  15. 

  16. #include <asm/memory.h>
    17. 

  17. 

  18. #if defined(CONFIG_ARCH_SPEAR3XX) || defined (CONFIG_ARCH_SPEAR6XX)
    19. 

  19. 

  20. /* ICM1 - Low speed connection */
    21. 

  21. #define SPEAR_ICM1_2_BASE		UL(0xD0000000)
    22. 

  22. #define VA_SPEAR_ICM1_2_BASE		UL(0xFD000000)
    23. 

  23. #define SPEAR_ICM1_UART_BASE		UL(0xD0000000)
    24. 

  24. #define VA_SPEAR_ICM1_UART_BASE		(VA_SPEAR_ICM1_2_BASE | SPEAR_ICM1_UART_BASE)
    25. 

  25. #define SPEAR3XX_ICM1_SSP_BASE		UL(0xD0100000)
    26. 

  26. 

  27. /* ML-1, 2 - Multi Layer CPU Subsystem */
    28. 

  28. #define SPEAR_ICM3_ML1_2_BASE		UL(0xF0000000)
    29. 

  29. #define VA_SPEAR6XX_ML_CPU_BASE		UL(0xF0000000)
    30. 

  30. 

  31. /* ICM3 - Basic Subsystem */
    32. 

  32. #define SPEAR_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
    33. 

  33. #define VA_SPEAR_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
    34. 

  34. #define SPEAR_ICM3_DMA_BASE		UL(0xFC400000)
    35. 

  35. #define SPEAR_ICM3_SYS_CTRL_BASE	UL(0xFCA00000)
    36. 

  36. #define VA_SPEAR_ICM3_SYS_CTRL_BASE	(VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_SYS_CTRL_BASE)
    37. 

  37. #define SPEAR_ICM3_MISC_REG_BASE	UL(0xFCA80000)
    38. 

  38. #define VA_SPEAR_ICM3_MISC_REG_BASE	(VA_SPEAR_ICM3_SMI_CTRL_BASE | SPEAR_ICM3_MISC_REG_BASE)
    39. 

  39. 

  40. /* Debug uart for linux, will be used for debug and uncompress messages */
    41. 

  41. #define SPEAR_DBG_UART_BASE		SPEAR_ICM1_UART_BASE
    42. 

  42. #define VA_SPEAR_DBG_UART_BASE		VA_SPEAR_ICM1_UART_BASE
    43. 

  43. 

  44. /* Sysctl base for spear platform */
    45. 

  45. #define SPEAR_SYS_CTRL_BASE		SPEAR_ICM3_SYS_CTRL_BASE
    46. 

  46. #define VA_SPEAR_SYS_CTRL_BASE		VA_SPEAR_ICM3_SYS_CTRL_BASE
    47. 

  47. 

  48. /* SPEAr320 Macros */
    49. 

  49. #define SPEAR320_SOC_CONFIG_BASE	UL(0xB3000000)
    50. 

  50. #define VA_SPEAR320_SOC_CONFIG_BASE	UL(0xFE000000)
    51. 

  51. #define SPEAR320_CONTROL_REG		IOMEM(VA_SPEAR320_SOC_CONFIG_BASE)
    52. 

  52. #define SPEAR320_EXT_CTRL_REG		IOMEM(VA_SPEAR320_SOC_CONFIG_BASE + 0x0018)
    53. 

  53. 	#define SPEAR320_UARTX_PCLK_MASK		0x1
    54. 

  54. 	#define SPEAR320_UART2_PCLK_SHIFT		8
    55. 

  55. 	#define SPEAR320_UART3_PCLK_SHIFT		9
    56. 

  56. 	#define SPEAR320_UART4_PCLK_SHIFT		10
    57. 

  57. 	#define SPEAR320_UART5_PCLK_SHIFT		11
    58. 

  58. 	#define SPEAR320_UART6_PCLK_SHIFT		12
    59. 

  59. 	#define SPEAR320_RS485_PCLK_SHIFT		13
    60. 

  60. #endif /* SPEAR3xx || SPEAR6XX */
    61. 

  61. 

  62. #ifdef CONFIG_ARCH_SPEAR13XX
    63. 

  63. 

  64. #define PERIP_GRP2_BASE				UL(0xB3000000)
    65. 

  65. #define VA_PERIP_GRP2_BASE			IOMEM(0xFE000000)
    66. 

  66. #define MCIF_SDHCI_BASE				UL(0xB3000000)
    67. 

  67. #define SYSRAM0_BASE				UL(0xB3800000)
    68. 

  68. #define VA_SYSRAM0_BASE				IOMEM(0xFE800000)
    69. 

  69. #define SYS_LOCATION				(VA_SYSRAM0_BASE + 0x600)
    70. 

  70. 

  71. #define PERIP_GRP1_BASE				UL(0xE0000000)
    72. 

  72. #define VA_PERIP_GRP1_BASE			IOMEM(0xFD000000)
    73. 

  73. #define UART_BASE				UL(0xE0000000)
    74. 

  74. #define VA_UART_BASE				IOMEM(0xFD000000)
    75. 

  75. #define SSP_BASE				UL(0xE0100000)
    76. 

  76. #define MISC_BASE				UL(0xE0700000)
    77. 

  77. #define VA_MISC_BASE				IOMEM(0xFD700000)
    78. 

  78. 

  79. #define A9SM_AND_MPMC_BASE			UL(0xEC000000)
    80. 

  80. #define VA_A9SM_AND_MPMC_BASE			IOMEM(0xFC000000)
    81. 

  81. 

  82. /* A9SM peripheral offsets */
    83. 

  83. #define A9SM_PERIP_BASE				UL(0xEC800000)
    84. 

  84. #define VA_A9SM_PERIP_BASE			IOMEM(0xFC800000)
    85. 

  85. #define VA_SCU_BASE				(VA_A9SM_PERIP_BASE + 0x00)
    86. 

  86. 

  87. #define L2CC_BASE				UL(0xED000000)
    88. 

  88. #define VA_L2CC_BASE				IOMEM(UL(0xFB000000))
    89. 

  89. 

  90. /* others */
    91. 

  91. #define DMAC0_BASE				UL(0xEA800000)
    92. 

  92. #define DMAC1_BASE				UL(0xEB000000)
    93. 

  93. #define MCIF_CF_BASE				UL(0xB2800000)
    94. 

  94. 

  95. /* Debug uart for linux, will be used for debug and uncompress messages */
    96. 

  96. #define SPEAR_DBG_UART_BASE			UART_BASE
    97. 

  97. #define VA_SPEAR_DBG_UART_BASE			VA_UART_BASE
    98. 

  98. 

  99. #endif /* SPEAR13XX */
    100. 

  100. 

  101. #endif /* __MACH_SPEAR_H */
    102.