intel_dp.c 39 KB

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  1. /*
  2. * Copyright © 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Keith Packard <keithp@keithp.com>
  25. *
  26. */
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "drm_crtc.h"
  32. #include "drm_crtc_helper.h"
  33. #include "intel_drv.h"
  34. #include "i915_drm.h"
  35. #include "i915_drv.h"
  36. #include "drm_dp_helper.h"
  37. #define DP_LINK_STATUS_SIZE 6
  38. #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
  39. #define DP_LINK_CONFIGURATION_SIZE 9
  40. #define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
  41. struct intel_dp_priv {
  42. uint32_t output_reg;
  43. uint32_t DP;
  44. uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
  45. bool has_audio;
  46. int dpms_mode;
  47. uint8_t link_bw;
  48. uint8_t lane_count;
  49. uint8_t dpcd[4];
  50. struct intel_encoder *intel_encoder;
  51. struct i2c_adapter adapter;
  52. struct i2c_algo_dp_aux_data algo;
  53. };
  54. static void
  55. intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  56. uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
  57. static void
  58. intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
  59. void
  60. intel_edp_link_config (struct intel_encoder *intel_encoder,
  61. int *lane_num, int *link_bw)
  62. {
  63. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  64. *lane_num = dp_priv->lane_count;
  65. if (dp_priv->link_bw == DP_LINK_BW_1_62)
  66. *link_bw = 162000;
  67. else if (dp_priv->link_bw == DP_LINK_BW_2_7)
  68. *link_bw = 270000;
  69. }
  70. static int
  71. intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
  72. {
  73. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  74. int max_lane_count = 4;
  75. if (dp_priv->dpcd[0] >= 0x11) {
  76. max_lane_count = dp_priv->dpcd[2] & 0x1f;
  77. switch (max_lane_count) {
  78. case 1: case 2: case 4:
  79. break;
  80. default:
  81. max_lane_count = 4;
  82. }
  83. }
  84. return max_lane_count;
  85. }
  86. static int
  87. intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
  88. {
  89. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  90. int max_link_bw = dp_priv->dpcd[1];
  91. switch (max_link_bw) {
  92. case DP_LINK_BW_1_62:
  93. case DP_LINK_BW_2_7:
  94. break;
  95. default:
  96. max_link_bw = DP_LINK_BW_1_62;
  97. break;
  98. }
  99. return max_link_bw;
  100. }
  101. static int
  102. intel_dp_link_clock(uint8_t link_bw)
  103. {
  104. if (link_bw == DP_LINK_BW_2_7)
  105. return 270000;
  106. else
  107. return 162000;
  108. }
  109. /* I think this is a fiction */
  110. static int
  111. intel_dp_link_required(struct drm_device *dev,
  112. struct intel_encoder *intel_encoder, int pixel_clock)
  113. {
  114. struct drm_i915_private *dev_priv = dev->dev_private;
  115. if (IS_eDP(intel_encoder))
  116. return (pixel_clock * dev_priv->edp_bpp) / 8;
  117. else
  118. return pixel_clock * 3;
  119. }
  120. static int
  121. intel_dp_mode_valid(struct drm_connector *connector,
  122. struct drm_display_mode *mode)
  123. {
  124. struct drm_encoder *encoder = intel_attached_encoder(connector);
  125. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  126. int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
  127. int max_lanes = intel_dp_max_lane_count(intel_encoder);
  128. if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
  129. > max_link_clock * max_lanes)
  130. return MODE_CLOCK_HIGH;
  131. if (mode->clock < 10000)
  132. return MODE_CLOCK_LOW;
  133. return MODE_OK;
  134. }
  135. static uint32_t
  136. pack_aux(uint8_t *src, int src_bytes)
  137. {
  138. int i;
  139. uint32_t v = 0;
  140. if (src_bytes > 4)
  141. src_bytes = 4;
  142. for (i = 0; i < src_bytes; i++)
  143. v |= ((uint32_t) src[i]) << ((3-i) * 8);
  144. return v;
  145. }
  146. static void
  147. unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
  148. {
  149. int i;
  150. if (dst_bytes > 4)
  151. dst_bytes = 4;
  152. for (i = 0; i < dst_bytes; i++)
  153. dst[i] = src >> ((3-i) * 8);
  154. }
  155. /* hrawclock is 1/4 the FSB frequency */
  156. static int
  157. intel_hrawclk(struct drm_device *dev)
  158. {
  159. struct drm_i915_private *dev_priv = dev->dev_private;
  160. uint32_t clkcfg;
  161. clkcfg = I915_READ(CLKCFG);
  162. switch (clkcfg & CLKCFG_FSB_MASK) {
  163. case CLKCFG_FSB_400:
  164. return 100;
  165. case CLKCFG_FSB_533:
  166. return 133;
  167. case CLKCFG_FSB_667:
  168. return 166;
  169. case CLKCFG_FSB_800:
  170. return 200;
  171. case CLKCFG_FSB_1067:
  172. return 266;
  173. case CLKCFG_FSB_1333:
  174. return 333;
  175. /* these two are just a guess; one of them might be right */
  176. case CLKCFG_FSB_1600:
  177. case CLKCFG_FSB_1600_ALT:
  178. return 400;
  179. default:
  180. return 133;
  181. }
  182. }
  183. static int
  184. intel_dp_aux_ch(struct intel_encoder *intel_encoder,
  185. uint8_t *send, int send_bytes,
  186. uint8_t *recv, int recv_size)
  187. {
  188. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  189. uint32_t output_reg = dp_priv->output_reg;
  190. struct drm_device *dev = intel_encoder->enc.dev;
  191. struct drm_i915_private *dev_priv = dev->dev_private;
  192. uint32_t ch_ctl = output_reg + 0x10;
  193. uint32_t ch_data = ch_ctl + 4;
  194. int i;
  195. int recv_bytes;
  196. uint32_t ctl;
  197. uint32_t status;
  198. uint32_t aux_clock_divider;
  199. int try, precharge;
  200. /* The clock divider is based off the hrawclk,
  201. * and would like to run at 2MHz. So, take the
  202. * hrawclk value and divide by 2 and use that
  203. */
  204. if (IS_eDP(intel_encoder)) {
  205. if (IS_GEN6(dev))
  206. aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
  207. else
  208. aux_clock_divider = 225; /* eDP input clock at 450Mhz */
  209. } else if (HAS_PCH_SPLIT(dev))
  210. aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
  211. else
  212. aux_clock_divider = intel_hrawclk(dev) / 2;
  213. if (IS_GEN6(dev))
  214. precharge = 3;
  215. else
  216. precharge = 5;
  217. /* Must try at least 3 times according to DP spec */
  218. for (try = 0; try < 5; try++) {
  219. /* Load the send data into the aux channel data registers */
  220. for (i = 0; i < send_bytes; i += 4) {
  221. uint32_t d = pack_aux(send + i, send_bytes - i);
  222. I915_WRITE(ch_data + i, d);
  223. }
  224. ctl = (DP_AUX_CH_CTL_SEND_BUSY |
  225. DP_AUX_CH_CTL_TIME_OUT_400us |
  226. (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
  227. (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
  228. (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
  229. DP_AUX_CH_CTL_DONE |
  230. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  231. DP_AUX_CH_CTL_RECEIVE_ERROR);
  232. /* Send the command and wait for it to complete */
  233. I915_WRITE(ch_ctl, ctl);
  234. (void) I915_READ(ch_ctl);
  235. for (;;) {
  236. udelay(100);
  237. status = I915_READ(ch_ctl);
  238. if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
  239. break;
  240. }
  241. /* Clear done status and any errors */
  242. I915_WRITE(ch_ctl, (status |
  243. DP_AUX_CH_CTL_DONE |
  244. DP_AUX_CH_CTL_TIME_OUT_ERROR |
  245. DP_AUX_CH_CTL_RECEIVE_ERROR));
  246. (void) I915_READ(ch_ctl);
  247. if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
  248. break;
  249. }
  250. if ((status & DP_AUX_CH_CTL_DONE) == 0) {
  251. DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
  252. return -EBUSY;
  253. }
  254. /* Check for timeout or receive error.
  255. * Timeouts occur when the sink is not connected
  256. */
  257. if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
  258. DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
  259. return -EIO;
  260. }
  261. /* Timeouts occur when the device isn't connected, so they're
  262. * "normal" -- don't fill the kernel log with these */
  263. if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
  264. DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
  265. return -ETIMEDOUT;
  266. }
  267. /* Unload any bytes sent back from the other side */
  268. recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
  269. DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
  270. if (recv_bytes > recv_size)
  271. recv_bytes = recv_size;
  272. for (i = 0; i < recv_bytes; i += 4) {
  273. uint32_t d = I915_READ(ch_data + i);
  274. unpack_aux(d, recv + i, recv_bytes - i);
  275. }
  276. return recv_bytes;
  277. }
  278. /* Write data to the aux channel in native mode */
  279. static int
  280. intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
  281. uint16_t address, uint8_t *send, int send_bytes)
  282. {
  283. int ret;
  284. uint8_t msg[20];
  285. int msg_bytes;
  286. uint8_t ack;
  287. if (send_bytes > 16)
  288. return -1;
  289. msg[0] = AUX_NATIVE_WRITE << 4;
  290. msg[1] = address >> 8;
  291. msg[2] = address & 0xff;
  292. msg[3] = send_bytes - 1;
  293. memcpy(&msg[4], send, send_bytes);
  294. msg_bytes = send_bytes + 4;
  295. for (;;) {
  296. ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
  297. if (ret < 0)
  298. return ret;
  299. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
  300. break;
  301. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  302. udelay(100);
  303. else
  304. return -EIO;
  305. }
  306. return send_bytes;
  307. }
  308. /* Write a single byte to the aux channel in native mode */
  309. static int
  310. intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
  311. uint16_t address, uint8_t byte)
  312. {
  313. return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
  314. }
  315. /* read bytes from a native aux channel */
  316. static int
  317. intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
  318. uint16_t address, uint8_t *recv, int recv_bytes)
  319. {
  320. uint8_t msg[4];
  321. int msg_bytes;
  322. uint8_t reply[20];
  323. int reply_bytes;
  324. uint8_t ack;
  325. int ret;
  326. msg[0] = AUX_NATIVE_READ << 4;
  327. msg[1] = address >> 8;
  328. msg[2] = address & 0xff;
  329. msg[3] = recv_bytes - 1;
  330. msg_bytes = 4;
  331. reply_bytes = recv_bytes + 1;
  332. for (;;) {
  333. ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
  334. reply, reply_bytes);
  335. if (ret == 0)
  336. return -EPROTO;
  337. if (ret < 0)
  338. return ret;
  339. ack = reply[0];
  340. if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
  341. memcpy(recv, reply + 1, ret - 1);
  342. return ret - 1;
  343. }
  344. else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
  345. udelay(100);
  346. else
  347. return -EIO;
  348. }
  349. }
  350. static int
  351. intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
  352. uint8_t write_byte, uint8_t *read_byte)
  353. {
  354. struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
  355. struct intel_dp_priv *dp_priv = container_of(adapter,
  356. struct intel_dp_priv,
  357. adapter);
  358. struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
  359. uint16_t address = algo_data->address;
  360. uint8_t msg[5];
  361. uint8_t reply[2];
  362. int msg_bytes;
  363. int reply_bytes;
  364. int ret;
  365. /* Set up the command byte */
  366. if (mode & MODE_I2C_READ)
  367. msg[0] = AUX_I2C_READ << 4;
  368. else
  369. msg[0] = AUX_I2C_WRITE << 4;
  370. if (!(mode & MODE_I2C_STOP))
  371. msg[0] |= AUX_I2C_MOT << 4;
  372. msg[1] = address >> 8;
  373. msg[2] = address;
  374. switch (mode) {
  375. case MODE_I2C_WRITE:
  376. msg[3] = 0;
  377. msg[4] = write_byte;
  378. msg_bytes = 5;
  379. reply_bytes = 1;
  380. break;
  381. case MODE_I2C_READ:
  382. msg[3] = 0;
  383. msg_bytes = 4;
  384. reply_bytes = 2;
  385. break;
  386. default:
  387. msg_bytes = 3;
  388. reply_bytes = 1;
  389. break;
  390. }
  391. for (;;) {
  392. ret = intel_dp_aux_ch(intel_encoder,
  393. msg, msg_bytes,
  394. reply, reply_bytes);
  395. if (ret < 0) {
  396. DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
  397. return ret;
  398. }
  399. switch (reply[0] & AUX_I2C_REPLY_MASK) {
  400. case AUX_I2C_REPLY_ACK:
  401. if (mode == MODE_I2C_READ) {
  402. *read_byte = reply[1];
  403. }
  404. return reply_bytes - 1;
  405. case AUX_I2C_REPLY_NACK:
  406. DRM_DEBUG_KMS("aux_ch nack\n");
  407. return -EREMOTEIO;
  408. case AUX_I2C_REPLY_DEFER:
  409. DRM_DEBUG_KMS("aux_ch defer\n");
  410. udelay(100);
  411. break;
  412. default:
  413. DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
  414. return -EREMOTEIO;
  415. }
  416. }
  417. }
  418. static int
  419. intel_dp_i2c_init(struct intel_encoder *intel_encoder,
  420. struct intel_connector *intel_connector, const char *name)
  421. {
  422. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  423. DRM_DEBUG_KMS("i2c_init %s\n", name);
  424. dp_priv->algo.running = false;
  425. dp_priv->algo.address = 0;
  426. dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
  427. memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
  428. dp_priv->adapter.owner = THIS_MODULE;
  429. dp_priv->adapter.class = I2C_CLASS_DDC;
  430. strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
  431. dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
  432. dp_priv->adapter.algo_data = &dp_priv->algo;
  433. dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
  434. return i2c_dp_aux_add_bus(&dp_priv->adapter);
  435. }
  436. static bool
  437. intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
  438. struct drm_display_mode *adjusted_mode)
  439. {
  440. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  441. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  442. int lane_count, clock;
  443. int max_lane_count = intel_dp_max_lane_count(intel_encoder);
  444. int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
  445. static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
  446. for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
  447. for (clock = 0; clock <= max_clock; clock++) {
  448. int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
  449. if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
  450. <= link_avail) {
  451. dp_priv->link_bw = bws[clock];
  452. dp_priv->lane_count = lane_count;
  453. adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
  454. DRM_DEBUG_KMS("Display port link bw %02x lane "
  455. "count %d clock %d\n",
  456. dp_priv->link_bw, dp_priv->lane_count,
  457. adjusted_mode->clock);
  458. return true;
  459. }
  460. }
  461. }
  462. return false;
  463. }
  464. struct intel_dp_m_n {
  465. uint32_t tu;
  466. uint32_t gmch_m;
  467. uint32_t gmch_n;
  468. uint32_t link_m;
  469. uint32_t link_n;
  470. };
  471. static void
  472. intel_reduce_ratio(uint32_t *num, uint32_t *den)
  473. {
  474. while (*num > 0xffffff || *den > 0xffffff) {
  475. *num >>= 1;
  476. *den >>= 1;
  477. }
  478. }
  479. static void
  480. intel_dp_compute_m_n(int bytes_per_pixel,
  481. int nlanes,
  482. int pixel_clock,
  483. int link_clock,
  484. struct intel_dp_m_n *m_n)
  485. {
  486. m_n->tu = 64;
  487. m_n->gmch_m = pixel_clock * bytes_per_pixel;
  488. m_n->gmch_n = link_clock * nlanes;
  489. intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  490. m_n->link_m = pixel_clock;
  491. m_n->link_n = link_clock;
  492. intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
  493. }
  494. void
  495. intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
  496. struct drm_display_mode *adjusted_mode)
  497. {
  498. struct drm_device *dev = crtc->dev;
  499. struct drm_mode_config *mode_config = &dev->mode_config;
  500. struct drm_encoder *encoder;
  501. struct drm_i915_private *dev_priv = dev->dev_private;
  502. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  503. int lane_count = 4;
  504. struct intel_dp_m_n m_n;
  505. /*
  506. * Find the lane count in the intel_encoder private
  507. */
  508. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  509. struct intel_encoder *intel_encoder;
  510. struct intel_dp_priv *dp_priv;
  511. if (!encoder || encoder->crtc != crtc)
  512. continue;
  513. intel_encoder = enc_to_intel_encoder(encoder);
  514. dp_priv = intel_encoder->dev_priv;
  515. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
  516. lane_count = dp_priv->lane_count;
  517. break;
  518. }
  519. }
  520. /*
  521. * Compute the GMCH and Link ratios. The '3' here is
  522. * the number of bytes_per_pixel post-LUT, which we always
  523. * set up for 8-bits of R/G/B, or 3 bytes total.
  524. */
  525. intel_dp_compute_m_n(3, lane_count,
  526. mode->clock, adjusted_mode->clock, &m_n);
  527. if (HAS_PCH_SPLIT(dev)) {
  528. if (intel_crtc->pipe == 0) {
  529. I915_WRITE(TRANSA_DATA_M1,
  530. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  531. m_n.gmch_m);
  532. I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
  533. I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
  534. I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
  535. } else {
  536. I915_WRITE(TRANSB_DATA_M1,
  537. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  538. m_n.gmch_m);
  539. I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
  540. I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
  541. I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
  542. }
  543. } else {
  544. if (intel_crtc->pipe == 0) {
  545. I915_WRITE(PIPEA_GMCH_DATA_M,
  546. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  547. m_n.gmch_m);
  548. I915_WRITE(PIPEA_GMCH_DATA_N,
  549. m_n.gmch_n);
  550. I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
  551. I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
  552. } else {
  553. I915_WRITE(PIPEB_GMCH_DATA_M,
  554. ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
  555. m_n.gmch_m);
  556. I915_WRITE(PIPEB_GMCH_DATA_N,
  557. m_n.gmch_n);
  558. I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
  559. I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
  560. }
  561. }
  562. }
  563. static void
  564. intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
  565. struct drm_display_mode *adjusted_mode)
  566. {
  567. struct drm_device *dev = encoder->dev;
  568. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  569. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  570. struct drm_crtc *crtc = intel_encoder->enc.crtc;
  571. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  572. dp_priv->DP = (DP_VOLTAGE_0_4 |
  573. DP_PRE_EMPHASIS_0);
  574. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  575. dp_priv->DP |= DP_SYNC_HS_HIGH;
  576. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  577. dp_priv->DP |= DP_SYNC_VS_HIGH;
  578. if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
  579. dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
  580. else
  581. dp_priv->DP |= DP_LINK_TRAIN_OFF;
  582. switch (dp_priv->lane_count) {
  583. case 1:
  584. dp_priv->DP |= DP_PORT_WIDTH_1;
  585. break;
  586. case 2:
  587. dp_priv->DP |= DP_PORT_WIDTH_2;
  588. break;
  589. case 4:
  590. dp_priv->DP |= DP_PORT_WIDTH_4;
  591. break;
  592. }
  593. if (dp_priv->has_audio)
  594. dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
  595. memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
  596. dp_priv->link_configuration[0] = dp_priv->link_bw;
  597. dp_priv->link_configuration[1] = dp_priv->lane_count;
  598. /*
  599. * Check for DPCD version > 1.1 and enhanced framing support
  600. */
  601. if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
  602. dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  603. dp_priv->DP |= DP_ENHANCED_FRAMING;
  604. }
  605. /* CPT DP's pipe select is decided in TRANS_DP_CTL */
  606. if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
  607. dp_priv->DP |= DP_PIPEB_SELECT;
  608. if (IS_eDP(intel_encoder)) {
  609. /* don't miss out required setting for eDP */
  610. dp_priv->DP |= DP_PLL_ENABLE;
  611. if (adjusted_mode->clock < 200000)
  612. dp_priv->DP |= DP_PLL_FREQ_160MHZ;
  613. else
  614. dp_priv->DP |= DP_PLL_FREQ_270MHZ;
  615. }
  616. }
  617. static void ironlake_edp_backlight_on (struct drm_device *dev)
  618. {
  619. struct drm_i915_private *dev_priv = dev->dev_private;
  620. u32 pp;
  621. DRM_DEBUG_KMS("\n");
  622. pp = I915_READ(PCH_PP_CONTROL);
  623. pp |= EDP_BLC_ENABLE;
  624. I915_WRITE(PCH_PP_CONTROL, pp);
  625. }
  626. static void ironlake_edp_backlight_off (struct drm_device *dev)
  627. {
  628. struct drm_i915_private *dev_priv = dev->dev_private;
  629. u32 pp;
  630. DRM_DEBUG_KMS("\n");
  631. pp = I915_READ(PCH_PP_CONTROL);
  632. pp &= ~EDP_BLC_ENABLE;
  633. I915_WRITE(PCH_PP_CONTROL, pp);
  634. }
  635. static void
  636. intel_dp_dpms(struct drm_encoder *encoder, int mode)
  637. {
  638. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  639. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  640. struct drm_device *dev = encoder->dev;
  641. struct drm_i915_private *dev_priv = dev->dev_private;
  642. uint32_t dp_reg = I915_READ(dp_priv->output_reg);
  643. if (mode != DRM_MODE_DPMS_ON) {
  644. if (dp_reg & DP_PORT_EN) {
  645. intel_dp_link_down(intel_encoder, dp_priv->DP);
  646. if (IS_eDP(intel_encoder))
  647. ironlake_edp_backlight_off(dev);
  648. }
  649. } else {
  650. if (!(dp_reg & DP_PORT_EN)) {
  651. intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
  652. if (IS_eDP(intel_encoder))
  653. ironlake_edp_backlight_on(dev);
  654. }
  655. }
  656. dp_priv->dpms_mode = mode;
  657. }
  658. /*
  659. * Fetch AUX CH registers 0x202 - 0x207 which contain
  660. * link status information
  661. */
  662. static bool
  663. intel_dp_get_link_status(struct intel_encoder *intel_encoder,
  664. uint8_t link_status[DP_LINK_STATUS_SIZE])
  665. {
  666. int ret;
  667. ret = intel_dp_aux_native_read(intel_encoder,
  668. DP_LANE0_1_STATUS,
  669. link_status, DP_LINK_STATUS_SIZE);
  670. if (ret != DP_LINK_STATUS_SIZE)
  671. return false;
  672. return true;
  673. }
  674. static uint8_t
  675. intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  676. int r)
  677. {
  678. return link_status[r - DP_LANE0_1_STATUS];
  679. }
  680. static uint8_t
  681. intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
  682. int lane)
  683. {
  684. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  685. int s = ((lane & 1) ?
  686. DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  687. DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
  688. uint8_t l = intel_dp_link_status(link_status, i);
  689. return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
  690. }
  691. static uint8_t
  692. intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
  693. int lane)
  694. {
  695. int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  696. int s = ((lane & 1) ?
  697. DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
  698. DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
  699. uint8_t l = intel_dp_link_status(link_status, i);
  700. return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
  701. }
  702. #if 0
  703. static char *voltage_names[] = {
  704. "0.4V", "0.6V", "0.8V", "1.2V"
  705. };
  706. static char *pre_emph_names[] = {
  707. "0dB", "3.5dB", "6dB", "9.5dB"
  708. };
  709. static char *link_train_names[] = {
  710. "pattern 1", "pattern 2", "idle", "off"
  711. };
  712. #endif
  713. /*
  714. * These are source-specific values; current Intel hardware supports
  715. * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
  716. */
  717. #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
  718. static uint8_t
  719. intel_dp_pre_emphasis_max(uint8_t voltage_swing)
  720. {
  721. switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
  722. case DP_TRAIN_VOLTAGE_SWING_400:
  723. return DP_TRAIN_PRE_EMPHASIS_6;
  724. case DP_TRAIN_VOLTAGE_SWING_600:
  725. return DP_TRAIN_PRE_EMPHASIS_6;
  726. case DP_TRAIN_VOLTAGE_SWING_800:
  727. return DP_TRAIN_PRE_EMPHASIS_3_5;
  728. case DP_TRAIN_VOLTAGE_SWING_1200:
  729. default:
  730. return DP_TRAIN_PRE_EMPHASIS_0;
  731. }
  732. }
  733. static void
  734. intel_get_adjust_train(struct intel_encoder *intel_encoder,
  735. uint8_t link_status[DP_LINK_STATUS_SIZE],
  736. int lane_count,
  737. uint8_t train_set[4])
  738. {
  739. uint8_t v = 0;
  740. uint8_t p = 0;
  741. int lane;
  742. for (lane = 0; lane < lane_count; lane++) {
  743. uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
  744. uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
  745. if (this_v > v)
  746. v = this_v;
  747. if (this_p > p)
  748. p = this_p;
  749. }
  750. if (v >= I830_DP_VOLTAGE_MAX)
  751. v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
  752. if (p >= intel_dp_pre_emphasis_max(v))
  753. p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  754. for (lane = 0; lane < 4; lane++)
  755. train_set[lane] = v | p;
  756. }
  757. static uint32_t
  758. intel_dp_signal_levels(uint8_t train_set, int lane_count)
  759. {
  760. uint32_t signal_levels = 0;
  761. switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
  762. case DP_TRAIN_VOLTAGE_SWING_400:
  763. default:
  764. signal_levels |= DP_VOLTAGE_0_4;
  765. break;
  766. case DP_TRAIN_VOLTAGE_SWING_600:
  767. signal_levels |= DP_VOLTAGE_0_6;
  768. break;
  769. case DP_TRAIN_VOLTAGE_SWING_800:
  770. signal_levels |= DP_VOLTAGE_0_8;
  771. break;
  772. case DP_TRAIN_VOLTAGE_SWING_1200:
  773. signal_levels |= DP_VOLTAGE_1_2;
  774. break;
  775. }
  776. switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
  777. case DP_TRAIN_PRE_EMPHASIS_0:
  778. default:
  779. signal_levels |= DP_PRE_EMPHASIS_0;
  780. break;
  781. case DP_TRAIN_PRE_EMPHASIS_3_5:
  782. signal_levels |= DP_PRE_EMPHASIS_3_5;
  783. break;
  784. case DP_TRAIN_PRE_EMPHASIS_6:
  785. signal_levels |= DP_PRE_EMPHASIS_6;
  786. break;
  787. case DP_TRAIN_PRE_EMPHASIS_9_5:
  788. signal_levels |= DP_PRE_EMPHASIS_9_5;
  789. break;
  790. }
  791. return signal_levels;
  792. }
  793. /* Gen6's DP voltage swing and pre-emphasis control */
  794. static uint32_t
  795. intel_gen6_edp_signal_levels(uint8_t train_set)
  796. {
  797. switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
  798. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
  799. return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
  800. case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
  801. return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
  802. case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
  803. return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
  804. case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
  805. return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
  806. default:
  807. DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
  808. return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
  809. }
  810. }
  811. static uint8_t
  812. intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
  813. int lane)
  814. {
  815. int i = DP_LANE0_1_STATUS + (lane >> 1);
  816. int s = (lane & 1) * 4;
  817. uint8_t l = intel_dp_link_status(link_status, i);
  818. return (l >> s) & 0xf;
  819. }
  820. /* Check for clock recovery is done on all channels */
  821. static bool
  822. intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
  823. {
  824. int lane;
  825. uint8_t lane_status;
  826. for (lane = 0; lane < lane_count; lane++) {
  827. lane_status = intel_get_lane_status(link_status, lane);
  828. if ((lane_status & DP_LANE_CR_DONE) == 0)
  829. return false;
  830. }
  831. return true;
  832. }
  833. /* Check to see if channel eq is done on all channels */
  834. #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
  835. DP_LANE_CHANNEL_EQ_DONE|\
  836. DP_LANE_SYMBOL_LOCKED)
  837. static bool
  838. intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
  839. {
  840. uint8_t lane_align;
  841. uint8_t lane_status;
  842. int lane;
  843. lane_align = intel_dp_link_status(link_status,
  844. DP_LANE_ALIGN_STATUS_UPDATED);
  845. if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  846. return false;
  847. for (lane = 0; lane < lane_count; lane++) {
  848. lane_status = intel_get_lane_status(link_status, lane);
  849. if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
  850. return false;
  851. }
  852. return true;
  853. }
  854. static bool
  855. intel_dp_set_link_train(struct intel_encoder *intel_encoder,
  856. uint32_t dp_reg_value,
  857. uint8_t dp_train_pat,
  858. uint8_t train_set[4],
  859. bool first)
  860. {
  861. struct drm_device *dev = intel_encoder->enc.dev;
  862. struct drm_i915_private *dev_priv = dev->dev_private;
  863. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  864. int ret;
  865. I915_WRITE(dp_priv->output_reg, dp_reg_value);
  866. POSTING_READ(dp_priv->output_reg);
  867. if (first)
  868. intel_wait_for_vblank(dev);
  869. intel_dp_aux_native_write_1(intel_encoder,
  870. DP_TRAINING_PATTERN_SET,
  871. dp_train_pat);
  872. ret = intel_dp_aux_native_write(intel_encoder,
  873. DP_TRAINING_LANE0_SET, train_set, 4);
  874. if (ret != 4)
  875. return false;
  876. return true;
  877. }
  878. static void
  879. intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
  880. uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
  881. {
  882. struct drm_device *dev = intel_encoder->enc.dev;
  883. struct drm_i915_private *dev_priv = dev->dev_private;
  884. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  885. uint8_t train_set[4];
  886. uint8_t link_status[DP_LINK_STATUS_SIZE];
  887. int i;
  888. uint8_t voltage;
  889. bool clock_recovery = false;
  890. bool channel_eq = false;
  891. bool first = true;
  892. int tries;
  893. u32 reg;
  894. /* Write the link configuration data */
  895. intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
  896. link_configuration, DP_LINK_CONFIGURATION_SIZE);
  897. DP |= DP_PORT_EN;
  898. if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
  899. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  900. else
  901. DP &= ~DP_LINK_TRAIN_MASK;
  902. memset(train_set, 0, 4);
  903. voltage = 0xff;
  904. tries = 0;
  905. clock_recovery = false;
  906. for (;;) {
  907. /* Use train_set[0] to set the voltage and pre emphasis values */
  908. uint32_t signal_levels;
  909. if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
  910. signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
  911. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  912. } else {
  913. signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
  914. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  915. }
  916. if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
  917. reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
  918. else
  919. reg = DP | DP_LINK_TRAIN_PAT_1;
  920. if (!intel_dp_set_link_train(intel_encoder, reg,
  921. DP_TRAINING_PATTERN_1, train_set, first))
  922. break;
  923. first = false;
  924. /* Set training pattern 1 */
  925. udelay(100);
  926. if (!intel_dp_get_link_status(intel_encoder, link_status))
  927. break;
  928. if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
  929. clock_recovery = true;
  930. break;
  931. }
  932. /* Check to see if we've tried the max voltage */
  933. for (i = 0; i < dp_priv->lane_count; i++)
  934. if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  935. break;
  936. if (i == dp_priv->lane_count)
  937. break;
  938. /* Check to see if we've tried the same voltage 5 times */
  939. if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  940. ++tries;
  941. if (tries == 5)
  942. break;
  943. } else
  944. tries = 0;
  945. voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  946. /* Compute new train_set as requested by target */
  947. intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
  948. }
  949. /* channel equalization */
  950. tries = 0;
  951. channel_eq = false;
  952. for (;;) {
  953. /* Use train_set[0] to set the voltage and pre emphasis values */
  954. uint32_t signal_levels;
  955. if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
  956. signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
  957. DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
  958. } else {
  959. signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
  960. DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
  961. }
  962. if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
  963. reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
  964. else
  965. reg = DP | DP_LINK_TRAIN_PAT_2;
  966. /* channel eq pattern */
  967. if (!intel_dp_set_link_train(intel_encoder, reg,
  968. DP_TRAINING_PATTERN_2, train_set,
  969. false))
  970. break;
  971. udelay(400);
  972. if (!intel_dp_get_link_status(intel_encoder, link_status))
  973. break;
  974. if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
  975. channel_eq = true;
  976. break;
  977. }
  978. /* Try 5 times */
  979. if (tries > 5)
  980. break;
  981. /* Compute new train_set as requested by target */
  982. intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
  983. ++tries;
  984. }
  985. if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
  986. reg = DP | DP_LINK_TRAIN_OFF_CPT;
  987. else
  988. reg = DP | DP_LINK_TRAIN_OFF;
  989. I915_WRITE(dp_priv->output_reg, reg);
  990. POSTING_READ(dp_priv->output_reg);
  991. intel_dp_aux_native_write_1(intel_encoder,
  992. DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
  993. }
  994. static void
  995. intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
  996. {
  997. struct drm_device *dev = intel_encoder->enc.dev;
  998. struct drm_i915_private *dev_priv = dev->dev_private;
  999. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  1000. DRM_DEBUG_KMS("\n");
  1001. if (IS_eDP(intel_encoder)) {
  1002. DP &= ~DP_PLL_ENABLE;
  1003. I915_WRITE(dp_priv->output_reg, DP);
  1004. POSTING_READ(dp_priv->output_reg);
  1005. udelay(100);
  1006. }
  1007. if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
  1008. DP &= ~DP_LINK_TRAIN_MASK_CPT;
  1009. I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
  1010. POSTING_READ(dp_priv->output_reg);
  1011. } else {
  1012. DP &= ~DP_LINK_TRAIN_MASK;
  1013. I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
  1014. POSTING_READ(dp_priv->output_reg);
  1015. }
  1016. udelay(17000);
  1017. if (IS_eDP(intel_encoder))
  1018. DP |= DP_LINK_TRAIN_OFF;
  1019. I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
  1020. POSTING_READ(dp_priv->output_reg);
  1021. }
  1022. /*
  1023. * According to DP spec
  1024. * 5.1.2:
  1025. * 1. Read DPCD
  1026. * 2. Configure link according to Receiver Capabilities
  1027. * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
  1028. * 4. Check link status on receipt of hot-plug interrupt
  1029. */
  1030. static void
  1031. intel_dp_check_link_status(struct intel_encoder *intel_encoder)
  1032. {
  1033. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  1034. uint8_t link_status[DP_LINK_STATUS_SIZE];
  1035. if (!intel_encoder->enc.crtc)
  1036. return;
  1037. if (!intel_dp_get_link_status(intel_encoder, link_status)) {
  1038. intel_dp_link_down(intel_encoder, dp_priv->DP);
  1039. return;
  1040. }
  1041. if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
  1042. intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
  1043. }
  1044. static enum drm_connector_status
  1045. ironlake_dp_detect(struct drm_connector *connector)
  1046. {
  1047. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1048. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1049. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  1050. enum drm_connector_status status;
  1051. status = connector_status_disconnected;
  1052. if (intel_dp_aux_native_read(intel_encoder,
  1053. 0x000, dp_priv->dpcd,
  1054. sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
  1055. {
  1056. if (dp_priv->dpcd[0] != 0)
  1057. status = connector_status_connected;
  1058. }
  1059. DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
  1060. dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
  1061. return status;
  1062. }
  1063. /**
  1064. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
  1065. *
  1066. * \return true if DP port is connected.
  1067. * \return false if DP port is disconnected.
  1068. */
  1069. static enum drm_connector_status
  1070. intel_dp_detect(struct drm_connector *connector)
  1071. {
  1072. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1073. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1074. struct drm_device *dev = intel_encoder->enc.dev;
  1075. struct drm_i915_private *dev_priv = dev->dev_private;
  1076. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  1077. uint32_t temp, bit;
  1078. enum drm_connector_status status;
  1079. dp_priv->has_audio = false;
  1080. if (HAS_PCH_SPLIT(dev))
  1081. return ironlake_dp_detect(connector);
  1082. switch (dp_priv->output_reg) {
  1083. case DP_B:
  1084. bit = DPB_HOTPLUG_INT_STATUS;
  1085. break;
  1086. case DP_C:
  1087. bit = DPC_HOTPLUG_INT_STATUS;
  1088. break;
  1089. case DP_D:
  1090. bit = DPD_HOTPLUG_INT_STATUS;
  1091. break;
  1092. default:
  1093. return connector_status_unknown;
  1094. }
  1095. temp = I915_READ(PORT_HOTPLUG_STAT);
  1096. if ((temp & bit) == 0)
  1097. return connector_status_disconnected;
  1098. status = connector_status_disconnected;
  1099. if (intel_dp_aux_native_read(intel_encoder,
  1100. 0x000, dp_priv->dpcd,
  1101. sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
  1102. {
  1103. if (dp_priv->dpcd[0] != 0)
  1104. status = connector_status_connected;
  1105. }
  1106. return status;
  1107. }
  1108. static int intel_dp_get_modes(struct drm_connector *connector)
  1109. {
  1110. struct drm_encoder *encoder = intel_attached_encoder(connector);
  1111. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1112. struct drm_device *dev = intel_encoder->enc.dev;
  1113. struct drm_i915_private *dev_priv = dev->dev_private;
  1114. int ret;
  1115. /* We should parse the EDID data and find out if it has an audio sink
  1116. */
  1117. ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
  1118. if (ret)
  1119. return ret;
  1120. /* if eDP has no EDID, try to use fixed panel mode from VBT */
  1121. if (IS_eDP(intel_encoder)) {
  1122. if (dev_priv->panel_fixed_mode != NULL) {
  1123. struct drm_display_mode *mode;
  1124. mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
  1125. drm_mode_probed_add(connector, mode);
  1126. return 1;
  1127. }
  1128. }
  1129. return 0;
  1130. }
  1131. static void
  1132. intel_dp_destroy (struct drm_connector *connector)
  1133. {
  1134. drm_sysfs_connector_remove(connector);
  1135. drm_connector_cleanup(connector);
  1136. kfree(connector);
  1137. }
  1138. static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
  1139. .dpms = intel_dp_dpms,
  1140. .mode_fixup = intel_dp_mode_fixup,
  1141. .prepare = intel_encoder_prepare,
  1142. .mode_set = intel_dp_mode_set,
  1143. .commit = intel_encoder_commit,
  1144. };
  1145. static const struct drm_connector_funcs intel_dp_connector_funcs = {
  1146. .dpms = drm_helper_connector_dpms,
  1147. .detect = intel_dp_detect,
  1148. .fill_modes = drm_helper_probe_single_connector_modes,
  1149. .destroy = intel_dp_destroy,
  1150. };
  1151. static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
  1152. .get_modes = intel_dp_get_modes,
  1153. .mode_valid = intel_dp_mode_valid,
  1154. .best_encoder = intel_attached_encoder,
  1155. };
  1156. static void intel_dp_enc_destroy(struct drm_encoder *encoder)
  1157. {
  1158. struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
  1159. if (intel_encoder->i2c_bus)
  1160. intel_i2c_destroy(intel_encoder->i2c_bus);
  1161. drm_encoder_cleanup(encoder);
  1162. kfree(intel_encoder);
  1163. }
  1164. static const struct drm_encoder_funcs intel_dp_enc_funcs = {
  1165. .destroy = intel_dp_enc_destroy,
  1166. };
  1167. void
  1168. intel_dp_hot_plug(struct intel_encoder *intel_encoder)
  1169. {
  1170. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  1171. if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
  1172. intel_dp_check_link_status(intel_encoder);
  1173. }
  1174. /* Return which DP Port should be selected for Transcoder DP control */
  1175. int
  1176. intel_trans_dp_port_sel (struct drm_crtc *crtc)
  1177. {
  1178. struct drm_device *dev = crtc->dev;
  1179. struct drm_mode_config *mode_config = &dev->mode_config;
  1180. struct drm_encoder *encoder;
  1181. struct intel_encoder *intel_encoder = NULL;
  1182. list_for_each_entry(encoder, &mode_config->encoder_list, head) {
  1183. if (!encoder || encoder->crtc != crtc)
  1184. continue;
  1185. intel_encoder = enc_to_intel_encoder(encoder);
  1186. if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
  1187. struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
  1188. return dp_priv->output_reg;
  1189. }
  1190. }
  1191. return -1;
  1192. }
  1193. void
  1194. intel_dp_init(struct drm_device *dev, int output_reg)
  1195. {
  1196. struct drm_i915_private *dev_priv = dev->dev_private;
  1197. struct drm_connector *connector;
  1198. struct intel_encoder *intel_encoder;
  1199. struct intel_connector *intel_connector;
  1200. struct intel_dp_priv *dp_priv;
  1201. const char *name = NULL;
  1202. intel_encoder = kcalloc(sizeof(struct intel_encoder) +
  1203. sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
  1204. if (!intel_encoder)
  1205. return;
  1206. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  1207. if (!intel_connector) {
  1208. kfree(intel_encoder);
  1209. return;
  1210. }
  1211. dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
  1212. connector = &intel_connector->base;
  1213. drm_connector_init(dev, connector, &intel_dp_connector_funcs,
  1214. DRM_MODE_CONNECTOR_DisplayPort);
  1215. drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
  1216. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1217. if (output_reg == DP_A)
  1218. intel_encoder->type = INTEL_OUTPUT_EDP;
  1219. else
  1220. intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
  1221. if (output_reg == DP_B || output_reg == PCH_DP_B)
  1222. intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
  1223. else if (output_reg == DP_C || output_reg == PCH_DP_C)
  1224. intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
  1225. else if (output_reg == DP_D || output_reg == PCH_DP_D)
  1226. intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
  1227. if (IS_eDP(intel_encoder))
  1228. intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
  1229. intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  1230. connector->interlace_allowed = true;
  1231. connector->doublescan_allowed = 0;
  1232. dp_priv->intel_encoder = intel_encoder;
  1233. dp_priv->output_reg = output_reg;
  1234. dp_priv->has_audio = false;
  1235. dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
  1236. intel_encoder->dev_priv = dp_priv;
  1237. drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
  1238. DRM_MODE_ENCODER_TMDS);
  1239. drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
  1240. drm_mode_connector_attach_encoder(&intel_connector->base,
  1241. &intel_encoder->enc);
  1242. drm_sysfs_connector_add(connector);
  1243. /* Set up the DDC bus. */
  1244. switch (output_reg) {
  1245. case DP_A:
  1246. name = "DPDDC-A";
  1247. break;
  1248. case DP_B:
  1249. case PCH_DP_B:
  1250. dev_priv->hotplug_supported_mask |=
  1251. HDMIB_HOTPLUG_INT_STATUS;
  1252. name = "DPDDC-B";
  1253. break;
  1254. case DP_C:
  1255. case PCH_DP_C:
  1256. dev_priv->hotplug_supported_mask |=
  1257. HDMIC_HOTPLUG_INT_STATUS;
  1258. name = "DPDDC-C";
  1259. break;
  1260. case DP_D:
  1261. case PCH_DP_D:
  1262. dev_priv->hotplug_supported_mask |=
  1263. HDMID_HOTPLUG_INT_STATUS;
  1264. name = "DPDDC-D";
  1265. break;
  1266. }
  1267. intel_dp_i2c_init(intel_encoder, intel_connector, name);
  1268. intel_encoder->ddc_bus = &dp_priv->adapter;
  1269. intel_encoder->hot_plug = intel_dp_hot_plug;
  1270. if (output_reg == DP_A) {
  1271. /* initialize panel mode from VBT if available for eDP */
  1272. if (dev_priv->lfp_lvds_vbt_mode) {
  1273. dev_priv->panel_fixed_mode =
  1274. drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
  1275. if (dev_priv->panel_fixed_mode) {
  1276. dev_priv->panel_fixed_mode->type |=
  1277. DRM_MODE_TYPE_PREFERRED;
  1278. }
  1279. }
  1280. }
  1281. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  1282. * 0xd. Failure to do so will result in spurious interrupts being
  1283. * generated on the port when a cable is not attached.
  1284. */
  1285. if (IS_G4X(dev) && !IS_GM45(dev)) {
  1286. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  1287. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  1288. }
  1289. }