cx23885-dvb.c 34 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc4000.h"
  38. #include "xc5000.h"
  39. #include "max2165.h"
  40. #include "tda10048.h"
  41. #include "tuner-xc2028.h"
  42. #include "tuner-simple.h"
  43. #include "dib7000p.h"
  44. #include "dibx000_common.h"
  45. #include "zl10353.h"
  46. #include "stv0900.h"
  47. #include "stv0900_reg.h"
  48. #include "stv6110.h"
  49. #include "lnbh24.h"
  50. #include "cx24116.h"
  51. #include "cimax2.h"
  52. #include "lgs8gxx.h"
  53. #include "netup-eeprom.h"
  54. #include "netup-init.h"
  55. #include "lgdt3305.h"
  56. #include "atbm8830.h"
  57. #include "ds3000.h"
  58. #include "cx23885-f300.h"
  59. #include "altera-ci.h"
  60. #include "stv0367.h"
  61. static unsigned int debug;
  62. #define dprintk(level, fmt, arg...)\
  63. do { if (debug >= level)\
  64. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  65. } while (0)
  66. /* ------------------------------------------------------------------ */
  67. static unsigned int alt_tuner;
  68. module_param(alt_tuner, int, 0644);
  69. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  70. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  71. /* ------------------------------------------------------------------ */
  72. static int dvb_buf_setup(struct videobuf_queue *q,
  73. unsigned int *count, unsigned int *size)
  74. {
  75. struct cx23885_tsport *port = q->priv_data;
  76. port->ts_packet_size = 188 * 4;
  77. port->ts_packet_count = 32;
  78. *size = port->ts_packet_size * port->ts_packet_count;
  79. *count = 32;
  80. return 0;
  81. }
  82. static int dvb_buf_prepare(struct videobuf_queue *q,
  83. struct videobuf_buffer *vb, enum v4l2_field field)
  84. {
  85. struct cx23885_tsport *port = q->priv_data;
  86. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  87. }
  88. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  89. {
  90. struct cx23885_tsport *port = q->priv_data;
  91. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  92. }
  93. static void dvb_buf_release(struct videobuf_queue *q,
  94. struct videobuf_buffer *vb)
  95. {
  96. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  97. }
  98. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
  99. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  100. {
  101. struct videobuf_dvb_frontends *f;
  102. struct videobuf_dvb_frontend *fe;
  103. f = &port->frontends;
  104. if (f->gate <= 1) /* undefined or fe0 */
  105. fe = videobuf_dvb_get_frontend(f, 1);
  106. else
  107. fe = videobuf_dvb_get_frontend(f, f->gate);
  108. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  109. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  110. /*
  111. * FIXME: Improve this path to avoid calling the
  112. * cx23885_dvb_set_frontend() every time it passes here.
  113. */
  114. cx23885_dvb_set_frontend(fe->dvb.frontend);
  115. }
  116. static struct videobuf_queue_ops dvb_qops = {
  117. .buf_setup = dvb_buf_setup,
  118. .buf_prepare = dvb_buf_prepare,
  119. .buf_queue = dvb_buf_queue,
  120. .buf_release = dvb_buf_release,
  121. };
  122. static struct s5h1409_config hauppauge_generic_config = {
  123. .demod_address = 0x32 >> 1,
  124. .output_mode = S5H1409_SERIAL_OUTPUT,
  125. .gpio = S5H1409_GPIO_ON,
  126. .qam_if = 44000,
  127. .inversion = S5H1409_INVERSION_OFF,
  128. .status_mode = S5H1409_DEMODLOCKING,
  129. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  130. };
  131. static struct tda10048_config hauppauge_hvr1200_config = {
  132. .demod_address = 0x10 >> 1,
  133. .output_mode = TDA10048_SERIAL_OUTPUT,
  134. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  135. .inversion = TDA10048_INVERSION_ON,
  136. .dtv6_if_freq_khz = TDA10048_IF_3300,
  137. .dtv7_if_freq_khz = TDA10048_IF_3800,
  138. .dtv8_if_freq_khz = TDA10048_IF_4300,
  139. .clk_freq_khz = TDA10048_CLK_16000,
  140. };
  141. static struct tda10048_config hauppauge_hvr1210_config = {
  142. .demod_address = 0x10 >> 1,
  143. .output_mode = TDA10048_SERIAL_OUTPUT,
  144. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  145. .inversion = TDA10048_INVERSION_ON,
  146. .dtv6_if_freq_khz = TDA10048_IF_3300,
  147. .dtv7_if_freq_khz = TDA10048_IF_3500,
  148. .dtv8_if_freq_khz = TDA10048_IF_4000,
  149. .clk_freq_khz = TDA10048_CLK_16000,
  150. };
  151. static struct s5h1409_config hauppauge_ezqam_config = {
  152. .demod_address = 0x32 >> 1,
  153. .output_mode = S5H1409_SERIAL_OUTPUT,
  154. .gpio = S5H1409_GPIO_OFF,
  155. .qam_if = 4000,
  156. .inversion = S5H1409_INVERSION_ON,
  157. .status_mode = S5H1409_DEMODLOCKING,
  158. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  159. };
  160. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  161. .demod_address = 0x32 >> 1,
  162. .output_mode = S5H1409_SERIAL_OUTPUT,
  163. .gpio = S5H1409_GPIO_OFF,
  164. .qam_if = 44000,
  165. .inversion = S5H1409_INVERSION_OFF,
  166. .status_mode = S5H1409_DEMODLOCKING,
  167. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  168. };
  169. static struct s5h1409_config hauppauge_hvr1500_config = {
  170. .demod_address = 0x32 >> 1,
  171. .output_mode = S5H1409_SERIAL_OUTPUT,
  172. .gpio = S5H1409_GPIO_OFF,
  173. .inversion = S5H1409_INVERSION_OFF,
  174. .status_mode = S5H1409_DEMODLOCKING,
  175. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  176. };
  177. static struct mt2131_config hauppauge_generic_tunerconfig = {
  178. 0x61
  179. };
  180. static struct lgdt330x_config fusionhdtv_5_express = {
  181. .demod_address = 0x0e,
  182. .demod_chip = LGDT3303,
  183. .serial_mpeg = 0x40,
  184. };
  185. static struct s5h1409_config hauppauge_hvr1500q_config = {
  186. .demod_address = 0x32 >> 1,
  187. .output_mode = S5H1409_SERIAL_OUTPUT,
  188. .gpio = S5H1409_GPIO_ON,
  189. .qam_if = 44000,
  190. .inversion = S5H1409_INVERSION_OFF,
  191. .status_mode = S5H1409_DEMODLOCKING,
  192. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  193. };
  194. static struct s5h1409_config dvico_s5h1409_config = {
  195. .demod_address = 0x32 >> 1,
  196. .output_mode = S5H1409_SERIAL_OUTPUT,
  197. .gpio = S5H1409_GPIO_ON,
  198. .qam_if = 44000,
  199. .inversion = S5H1409_INVERSION_OFF,
  200. .status_mode = S5H1409_DEMODLOCKING,
  201. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  202. };
  203. static struct s5h1411_config dvico_s5h1411_config = {
  204. .output_mode = S5H1411_SERIAL_OUTPUT,
  205. .gpio = S5H1411_GPIO_ON,
  206. .qam_if = S5H1411_IF_44000,
  207. .vsb_if = S5H1411_IF_44000,
  208. .inversion = S5H1411_INVERSION_OFF,
  209. .status_mode = S5H1411_DEMODLOCKING,
  210. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  211. };
  212. static struct s5h1411_config hcw_s5h1411_config = {
  213. .output_mode = S5H1411_SERIAL_OUTPUT,
  214. .gpio = S5H1411_GPIO_OFF,
  215. .vsb_if = S5H1411_IF_44000,
  216. .qam_if = S5H1411_IF_4000,
  217. .inversion = S5H1411_INVERSION_ON,
  218. .status_mode = S5H1411_DEMODLOCKING,
  219. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  220. };
  221. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  222. .i2c_address = 0x61,
  223. .if_khz = 5380,
  224. };
  225. static struct xc5000_config dvico_xc5000_tunerconfig = {
  226. .i2c_address = 0x64,
  227. .if_khz = 5380,
  228. };
  229. static struct tda829x_config tda829x_no_probe = {
  230. .probe_tuner = TDA829X_DONT_PROBE,
  231. };
  232. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  233. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  234. .if_lvl = 6, .rfagc_top = 0x37 },
  235. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  236. .if_lvl = 6, .rfagc_top = 0x37 },
  237. };
  238. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  239. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  240. .if_lvl = 1, .rfagc_top = 0x37, },
  241. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  242. .if_lvl = 1, .rfagc_top = 0x37, },
  243. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  244. .if_lvl = 1, .rfagc_top = 0x37, },
  245. };
  246. static struct tda18271_config hauppauge_tda18271_config = {
  247. .std_map = &hauppauge_tda18271_std_map,
  248. .gate = TDA18271_GATE_ANALOG,
  249. .output_opt = TDA18271_OUTPUT_LT_OFF,
  250. };
  251. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  252. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  253. .gate = TDA18271_GATE_ANALOG,
  254. .output_opt = TDA18271_OUTPUT_LT_OFF,
  255. };
  256. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  257. .gate = TDA18271_GATE_DIGITAL,
  258. .output_opt = TDA18271_OUTPUT_LT_OFF,
  259. };
  260. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  261. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  262. .if_lvl = 1, .rfagc_top = 0x58 },
  263. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  264. .if_lvl = 1, .rfagc_top = 0x58 },
  265. };
  266. static struct tda18271_config hauppauge_hvr127x_config = {
  267. .std_map = &hauppauge_hvr127x_std_map,
  268. .output_opt = TDA18271_OUTPUT_LT_OFF,
  269. };
  270. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  271. .i2c_addr = 0x0e,
  272. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  273. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  274. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  275. .deny_i2c_rptr = 1,
  276. .spectral_inversion = 1,
  277. .qam_if_khz = 4000,
  278. .vsb_if_khz = 3250,
  279. };
  280. static struct dibx000_agc_config xc3028_agc_config = {
  281. BAND_VHF | BAND_UHF, /* band_caps */
  282. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  283. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  284. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  285. * P_agc_nb_est=2, P_agc_write=0
  286. */
  287. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  288. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  289. 712, /* inv_gain */
  290. 21, /* time_stabiliz */
  291. 0, /* alpha_level */
  292. 118, /* thlock */
  293. 0, /* wbd_inv */
  294. 2867, /* wbd_ref */
  295. 0, /* wbd_sel */
  296. 2, /* wbd_alpha */
  297. 0, /* agc1_max */
  298. 0, /* agc1_min */
  299. 39718, /* agc2_max */
  300. 9930, /* agc2_min */
  301. 0, /* agc1_pt1 */
  302. 0, /* agc1_pt2 */
  303. 0, /* agc1_pt3 */
  304. 0, /* agc1_slope1 */
  305. 0, /* agc1_slope2 */
  306. 0, /* agc2_pt1 */
  307. 128, /* agc2_pt2 */
  308. 29, /* agc2_slope1 */
  309. 29, /* agc2_slope2 */
  310. 17, /* alpha_mant */
  311. 27, /* alpha_exp */
  312. 23, /* beta_mant */
  313. 51, /* beta_exp */
  314. 1, /* perform_agc_softsplit */
  315. };
  316. /* PLL Configuration for COFDM BW_MHz = 8.000000
  317. * With external clock = 30.000000 */
  318. static struct dibx000_bandwidth_config xc3028_bw_config = {
  319. 60000, /* internal */
  320. 30000, /* sampling */
  321. 1, /* pll_cfg: prediv */
  322. 8, /* pll_cfg: ratio */
  323. 3, /* pll_cfg: range */
  324. 1, /* pll_cfg: reset */
  325. 0, /* pll_cfg: bypass */
  326. 0, /* misc: refdiv */
  327. 0, /* misc: bypclk_div */
  328. 1, /* misc: IO_CLK_en_core */
  329. 1, /* misc: ADClkSrc */
  330. 0, /* misc: modulo */
  331. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  332. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  333. 20452225, /* timf */
  334. 30000000 /* xtal_hz */
  335. };
  336. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  337. .output_mpeg2_in_188_bytes = 1,
  338. .hostbus_diversity = 1,
  339. .tuner_is_baseband = 0,
  340. .update_lna = NULL,
  341. .agc_config_count = 1,
  342. .agc = &xc3028_agc_config,
  343. .bw = &xc3028_bw_config,
  344. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  345. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  346. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  347. .pwm_freq_div = 0,
  348. .agc_control = NULL,
  349. .spur_protect = 0,
  350. .output_mode = OUTMODE_MPEG2_SERIAL,
  351. };
  352. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  353. .demod_address = 0x0f,
  354. .if2 = 45600,
  355. .no_tuner = 1,
  356. .disable_i2c_gate_ctrl = 1,
  357. };
  358. static struct stv0900_reg stv0900_ts_regs[] = {
  359. { R0900_TSGENERAL, 0x00 },
  360. { R0900_P1_TSSPEED, 0x40 },
  361. { R0900_P2_TSSPEED, 0x40 },
  362. { R0900_P1_TSCFGM, 0xc0 },
  363. { R0900_P2_TSCFGM, 0xc0 },
  364. { R0900_P1_TSCFGH, 0xe0 },
  365. { R0900_P2_TSCFGH, 0xe0 },
  366. { R0900_P1_TSCFGL, 0x20 },
  367. { R0900_P2_TSCFGL, 0x20 },
  368. { 0xffff, 0xff }, /* terminate */
  369. };
  370. static struct stv0900_config netup_stv0900_config = {
  371. .demod_address = 0x68,
  372. .demod_mode = 1, /* dual */
  373. .xtal = 8000000,
  374. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  375. .diseqc_mode = 2,/* 2/3 PWM */
  376. .ts_config_regs = stv0900_ts_regs,
  377. .tun1_maddress = 0,/* 0x60 */
  378. .tun2_maddress = 3,/* 0x63 */
  379. .tun1_adc = 1,/* 1 Vpp */
  380. .tun2_adc = 1,/* 1 Vpp */
  381. };
  382. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  383. .i2c_address = 0x60,
  384. .mclk = 16000000,
  385. .clk_div = 1,
  386. .gain = 8, /* +16 dB - maximum gain */
  387. };
  388. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  389. .i2c_address = 0x63,
  390. .mclk = 16000000,
  391. .clk_div = 1,
  392. .gain = 8, /* +16 dB - maximum gain */
  393. };
  394. static struct cx24116_config tbs_cx24116_config = {
  395. .demod_address = 0x55,
  396. };
  397. static struct ds3000_config tevii_ds3000_config = {
  398. .demod_address = 0x68,
  399. };
  400. static struct cx24116_config dvbworld_cx24116_config = {
  401. .demod_address = 0x05,
  402. };
  403. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  404. .prod = LGS8GXX_PROD_LGS8GL5,
  405. .demod_address = 0x19,
  406. .serial_ts = 0,
  407. .ts_clk_pol = 1,
  408. .ts_clk_gated = 1,
  409. .if_clk_freq = 30400, /* 30.4 MHz */
  410. .if_freq = 5380, /* 5.38 MHz */
  411. .if_neg_center = 1,
  412. .ext_adc = 0,
  413. .adc_signed = 0,
  414. .if_neg_edge = 0,
  415. };
  416. static struct xc5000_config mygica_x8506_xc5000_config = {
  417. .i2c_address = 0x61,
  418. .if_khz = 5380,
  419. };
  420. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  421. {
  422. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  423. struct cx23885_tsport *port = fe->dvb->priv;
  424. struct cx23885_dev *dev = port->dev;
  425. switch (dev->board) {
  426. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  427. switch (p->modulation) {
  428. case VSB_8:
  429. cx23885_gpio_clear(dev, GPIO_5);
  430. break;
  431. case QAM_64:
  432. case QAM_256:
  433. default:
  434. cx23885_gpio_set(dev, GPIO_5);
  435. break;
  436. }
  437. break;
  438. case CX23885_BOARD_MYGICA_X8506:
  439. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  440. /* Select Digital TV */
  441. cx23885_gpio_set(dev, GPIO_0);
  442. break;
  443. }
  444. return 0;
  445. }
  446. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  447. .prod = LGS8GXX_PROD_LGS8G75,
  448. .demod_address = 0x19,
  449. .serial_ts = 0,
  450. .ts_clk_pol = 1,
  451. .ts_clk_gated = 1,
  452. .if_clk_freq = 30400, /* 30.4 MHz */
  453. .if_freq = 6500, /* 6.50 MHz */
  454. .if_neg_center = 1,
  455. .ext_adc = 0,
  456. .adc_signed = 1,
  457. .adc_vpp = 2, /* 1.6 Vpp */
  458. .if_neg_edge = 1,
  459. };
  460. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  461. .i2c_address = 0x61,
  462. .if_khz = 6500,
  463. };
  464. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  465. .prod = ATBM8830_PROD_8830,
  466. .demod_address = 0x44,
  467. .serial_ts = 0,
  468. .ts_sampling_edge = 1,
  469. .ts_clk_gated = 0,
  470. .osc_clk_freq = 30400, /* in kHz */
  471. .if_freq = 0, /* zero IF */
  472. .zif_swap_iq = 1,
  473. .agc_min = 0x2E,
  474. .agc_max = 0xFF,
  475. .agc_hold_loop = 0,
  476. };
  477. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  478. .i2c_address = 0x60,
  479. .osc_clk = 20
  480. };
  481. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  482. .prod = ATBM8830_PROD_8830,
  483. .demod_address = 0x44,
  484. .serial_ts = 1,
  485. .ts_sampling_edge = 1,
  486. .ts_clk_gated = 0,
  487. .osc_clk_freq = 30400, /* in kHz */
  488. .if_freq = 0, /* zero IF */
  489. .zif_swap_iq = 1,
  490. .agc_min = 0x2E,
  491. .agc_max = 0xFF,
  492. .agc_hold_loop = 0,
  493. };
  494. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  495. .i2c_address = 0x60,
  496. .osc_clk = 20
  497. };
  498. static struct stv0367_config netup_stv0367_config[] = {
  499. {
  500. .demod_address = 0x1c,
  501. .xtal = 27000000,
  502. .if_khz = 4500,
  503. .if_iq_mode = 0,
  504. .ts_mode = 1,
  505. .clk_pol = 0,
  506. }, {
  507. .demod_address = 0x1d,
  508. .xtal = 27000000,
  509. .if_khz = 4500,
  510. .if_iq_mode = 0,
  511. .ts_mode = 1,
  512. .clk_pol = 0,
  513. },
  514. };
  515. static struct xc5000_config netup_xc5000_config[] = {
  516. {
  517. .i2c_address = 0x61,
  518. .if_khz = 4500,
  519. }, {
  520. .i2c_address = 0x64,
  521. .if_khz = 4500,
  522. },
  523. };
  524. int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  525. {
  526. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  527. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  528. uint32_t mem = 0;
  529. mem = cx_read(MC417_RWD);
  530. if (read)
  531. cx_set(MC417_OEN, ALT_DATA);
  532. else {
  533. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  534. mem &= ~ALT_DATA;
  535. mem |= (data & ALT_DATA);
  536. }
  537. if (flag)
  538. mem |= ALT_AD_RG;
  539. else
  540. mem &= ~ALT_AD_RG;
  541. mem &= ~ALT_CS;
  542. if (read)
  543. mem = (mem & ~ALT_RD) | ALT_WR;
  544. else
  545. mem = (mem & ~ALT_WR) | ALT_RD;
  546. cx_write(MC417_RWD, mem); /* start RW cycle */
  547. for (;;) {
  548. mem = cx_read(MC417_RWD);
  549. if ((mem & ALT_RDY) == 0)
  550. break;
  551. if (time_after(jiffies, timeout))
  552. break;
  553. udelay(1);
  554. }
  555. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  556. if (read)
  557. return mem & ALT_DATA;
  558. return 0;
  559. };
  560. static int dvb_register(struct cx23885_tsport *port)
  561. {
  562. struct cx23885_dev *dev = port->dev;
  563. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  564. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  565. int mfe_shared = 0; /* bus not shared by default */
  566. int ret;
  567. /* Get the first frontend */
  568. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  569. if (!fe0)
  570. return -EINVAL;
  571. /* init struct videobuf_dvb */
  572. fe0->dvb.name = dev->name;
  573. /* multi-frontend gate control is undefined or defaults to fe0 */
  574. port->frontends.gate = 0;
  575. /* Sets the gate control callback to be used by i2c command calls */
  576. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  577. /* init frontend */
  578. switch (dev->board) {
  579. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  580. i2c_bus = &dev->i2c_bus[0];
  581. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  582. &hauppauge_generic_config,
  583. &i2c_bus->i2c_adap);
  584. if (fe0->dvb.frontend != NULL) {
  585. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  586. &i2c_bus->i2c_adap,
  587. &hauppauge_generic_tunerconfig, 0);
  588. }
  589. break;
  590. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  591. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  592. i2c_bus = &dev->i2c_bus[0];
  593. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  594. &hauppauge_lgdt3305_config,
  595. &i2c_bus->i2c_adap);
  596. if (fe0->dvb.frontend != NULL) {
  597. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  598. 0x60, &dev->i2c_bus[1].i2c_adap,
  599. &hauppauge_hvr127x_config);
  600. }
  601. break;
  602. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  603. i2c_bus = &dev->i2c_bus[0];
  604. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  605. &hcw_s5h1411_config,
  606. &i2c_bus->i2c_adap);
  607. if (fe0->dvb.frontend != NULL) {
  608. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  609. 0x60, &dev->i2c_bus[1].i2c_adap,
  610. &hauppauge_tda18271_config);
  611. }
  612. break;
  613. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  614. i2c_bus = &dev->i2c_bus[0];
  615. switch (alt_tuner) {
  616. case 1:
  617. fe0->dvb.frontend =
  618. dvb_attach(s5h1409_attach,
  619. &hauppauge_ezqam_config,
  620. &i2c_bus->i2c_adap);
  621. if (fe0->dvb.frontend != NULL) {
  622. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  623. &dev->i2c_bus[1].i2c_adap, 0x42,
  624. &tda829x_no_probe);
  625. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  626. 0x60, &dev->i2c_bus[1].i2c_adap,
  627. &hauppauge_tda18271_config);
  628. }
  629. break;
  630. case 0:
  631. default:
  632. fe0->dvb.frontend =
  633. dvb_attach(s5h1409_attach,
  634. &hauppauge_generic_config,
  635. &i2c_bus->i2c_adap);
  636. if (fe0->dvb.frontend != NULL)
  637. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  638. &i2c_bus->i2c_adap,
  639. &hauppauge_generic_tunerconfig, 0);
  640. break;
  641. }
  642. break;
  643. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  644. i2c_bus = &dev->i2c_bus[0];
  645. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  646. &hauppauge_hvr1800lp_config,
  647. &i2c_bus->i2c_adap);
  648. if (fe0->dvb.frontend != NULL) {
  649. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  650. &i2c_bus->i2c_adap,
  651. &hauppauge_generic_tunerconfig, 0);
  652. }
  653. break;
  654. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  655. i2c_bus = &dev->i2c_bus[0];
  656. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  657. &fusionhdtv_5_express,
  658. &i2c_bus->i2c_adap);
  659. if (fe0->dvb.frontend != NULL) {
  660. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  661. &i2c_bus->i2c_adap, 0x61,
  662. TUNER_LG_TDVS_H06XF);
  663. }
  664. break;
  665. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  666. i2c_bus = &dev->i2c_bus[1];
  667. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  668. &hauppauge_hvr1500q_config,
  669. &dev->i2c_bus[0].i2c_adap);
  670. if (fe0->dvb.frontend != NULL)
  671. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  672. &i2c_bus->i2c_adap,
  673. &hauppauge_hvr1500q_tunerconfig);
  674. break;
  675. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  676. i2c_bus = &dev->i2c_bus[1];
  677. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  678. &hauppauge_hvr1500_config,
  679. &dev->i2c_bus[0].i2c_adap);
  680. if (fe0->dvb.frontend != NULL) {
  681. struct dvb_frontend *fe;
  682. struct xc2028_config cfg = {
  683. .i2c_adap = &i2c_bus->i2c_adap,
  684. .i2c_addr = 0x61,
  685. };
  686. static struct xc2028_ctrl ctl = {
  687. .fname = XC2028_DEFAULT_FIRMWARE,
  688. .max_len = 64,
  689. .demod = XC3028_FE_OREN538,
  690. };
  691. fe = dvb_attach(xc2028_attach,
  692. fe0->dvb.frontend, &cfg);
  693. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  694. fe->ops.tuner_ops.set_config(fe, &ctl);
  695. }
  696. break;
  697. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  698. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  699. i2c_bus = &dev->i2c_bus[0];
  700. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  701. &hauppauge_hvr1200_config,
  702. &i2c_bus->i2c_adap);
  703. if (fe0->dvb.frontend != NULL) {
  704. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  705. &dev->i2c_bus[1].i2c_adap, 0x42,
  706. &tda829x_no_probe);
  707. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  708. 0x60, &dev->i2c_bus[1].i2c_adap,
  709. &hauppauge_hvr1200_tuner_config);
  710. }
  711. break;
  712. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  713. i2c_bus = &dev->i2c_bus[0];
  714. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  715. &hauppauge_hvr1210_config,
  716. &i2c_bus->i2c_adap);
  717. if (fe0->dvb.frontend != NULL) {
  718. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  719. 0x60, &dev->i2c_bus[1].i2c_adap,
  720. &hauppauge_hvr1210_tuner_config);
  721. }
  722. break;
  723. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  724. i2c_bus = &dev->i2c_bus[0];
  725. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  726. &i2c_bus->i2c_adap,
  727. 0x12, &hauppauge_hvr1400_dib7000_config);
  728. if (fe0->dvb.frontend != NULL) {
  729. struct dvb_frontend *fe;
  730. struct xc2028_config cfg = {
  731. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  732. .i2c_addr = 0x64,
  733. };
  734. static struct xc2028_ctrl ctl = {
  735. .fname = XC3028L_DEFAULT_FIRMWARE,
  736. .max_len = 64,
  737. .demod = XC3028_FE_DIBCOM52,
  738. /* This is true for all demods with
  739. v36 firmware? */
  740. .type = XC2028_D2633,
  741. };
  742. fe = dvb_attach(xc2028_attach,
  743. fe0->dvb.frontend, &cfg);
  744. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  745. fe->ops.tuner_ops.set_config(fe, &ctl);
  746. }
  747. break;
  748. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  749. i2c_bus = &dev->i2c_bus[port->nr - 1];
  750. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  751. &dvico_s5h1409_config,
  752. &i2c_bus->i2c_adap);
  753. if (fe0->dvb.frontend == NULL)
  754. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  755. &dvico_s5h1411_config,
  756. &i2c_bus->i2c_adap);
  757. if (fe0->dvb.frontend != NULL)
  758. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  759. &i2c_bus->i2c_adap,
  760. &dvico_xc5000_tunerconfig);
  761. break;
  762. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  763. i2c_bus = &dev->i2c_bus[port->nr - 1];
  764. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  765. &dvico_fusionhdtv_xc3028,
  766. &i2c_bus->i2c_adap);
  767. if (fe0->dvb.frontend != NULL) {
  768. struct dvb_frontend *fe;
  769. struct xc2028_config cfg = {
  770. .i2c_adap = &i2c_bus->i2c_adap,
  771. .i2c_addr = 0x61,
  772. };
  773. static struct xc2028_ctrl ctl = {
  774. .fname = XC2028_DEFAULT_FIRMWARE,
  775. .max_len = 64,
  776. .demod = XC3028_FE_ZARLINK456,
  777. };
  778. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  779. &cfg);
  780. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  781. fe->ops.tuner_ops.set_config(fe, &ctl);
  782. }
  783. break;
  784. }
  785. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  786. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  787. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  788. i2c_bus = &dev->i2c_bus[0];
  789. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  790. &dvico_fusionhdtv_xc3028,
  791. &i2c_bus->i2c_adap);
  792. if (fe0->dvb.frontend != NULL) {
  793. struct dvb_frontend *fe;
  794. struct xc2028_config cfg = {
  795. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  796. .i2c_addr = 0x61,
  797. };
  798. static struct xc2028_ctrl ctl = {
  799. .fname = XC2028_DEFAULT_FIRMWARE,
  800. .max_len = 64,
  801. .demod = XC3028_FE_ZARLINK456,
  802. };
  803. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  804. &cfg);
  805. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  806. fe->ops.tuner_ops.set_config(fe, &ctl);
  807. }
  808. break;
  809. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  810. i2c_bus = &dev->i2c_bus[0];
  811. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  812. &dvico_fusionhdtv_xc3028,
  813. &i2c_bus->i2c_adap);
  814. if (fe0->dvb.frontend != NULL) {
  815. struct dvb_frontend *fe;
  816. struct xc4000_config cfg = {
  817. .i2c_address = 0x61,
  818. .default_pm = 0,
  819. .dvb_amplitude = 134,
  820. .set_smoothedcvbs = 1,
  821. .if_khz = 4560
  822. };
  823. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  824. &dev->i2c_bus[1].i2c_adap, &cfg);
  825. }
  826. break;
  827. case CX23885_BOARD_TBS_6920:
  828. i2c_bus = &dev->i2c_bus[1];
  829. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  830. &tbs_cx24116_config,
  831. &i2c_bus->i2c_adap);
  832. if (fe0->dvb.frontend != NULL)
  833. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  834. break;
  835. case CX23885_BOARD_TEVII_S470:
  836. i2c_bus = &dev->i2c_bus[1];
  837. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  838. &tevii_ds3000_config,
  839. &i2c_bus->i2c_adap);
  840. if (fe0->dvb.frontend != NULL)
  841. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  842. break;
  843. case CX23885_BOARD_DVBWORLD_2005:
  844. i2c_bus = &dev->i2c_bus[1];
  845. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  846. &dvbworld_cx24116_config,
  847. &i2c_bus->i2c_adap);
  848. break;
  849. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  850. i2c_bus = &dev->i2c_bus[0];
  851. switch (port->nr) {
  852. /* port B */
  853. case 1:
  854. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  855. &netup_stv0900_config,
  856. &i2c_bus->i2c_adap, 0);
  857. if (fe0->dvb.frontend != NULL) {
  858. if (dvb_attach(stv6110_attach,
  859. fe0->dvb.frontend,
  860. &netup_stv6110_tunerconfig_a,
  861. &i2c_bus->i2c_adap)) {
  862. if (!dvb_attach(lnbh24_attach,
  863. fe0->dvb.frontend,
  864. &i2c_bus->i2c_adap,
  865. LNBH24_PCL | LNBH24_TTX,
  866. LNBH24_TEN, 0x09))
  867. printk(KERN_ERR
  868. "No LNBH24 found!\n");
  869. }
  870. }
  871. break;
  872. /* port C */
  873. case 2:
  874. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  875. &netup_stv0900_config,
  876. &i2c_bus->i2c_adap, 1);
  877. if (fe0->dvb.frontend != NULL) {
  878. if (dvb_attach(stv6110_attach,
  879. fe0->dvb.frontend,
  880. &netup_stv6110_tunerconfig_b,
  881. &i2c_bus->i2c_adap)) {
  882. if (!dvb_attach(lnbh24_attach,
  883. fe0->dvb.frontend,
  884. &i2c_bus->i2c_adap,
  885. LNBH24_PCL | LNBH24_TTX,
  886. LNBH24_TEN, 0x0a))
  887. printk(KERN_ERR
  888. "No LNBH24 found!\n");
  889. }
  890. }
  891. break;
  892. }
  893. break;
  894. case CX23885_BOARD_MYGICA_X8506:
  895. i2c_bus = &dev->i2c_bus[0];
  896. i2c_bus2 = &dev->i2c_bus[1];
  897. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  898. &mygica_x8506_lgs8gl5_config,
  899. &i2c_bus->i2c_adap);
  900. if (fe0->dvb.frontend != NULL) {
  901. dvb_attach(xc5000_attach,
  902. fe0->dvb.frontend,
  903. &i2c_bus2->i2c_adap,
  904. &mygica_x8506_xc5000_config);
  905. }
  906. break;
  907. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  908. i2c_bus = &dev->i2c_bus[0];
  909. i2c_bus2 = &dev->i2c_bus[1];
  910. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  911. &magicpro_prohdtve2_lgs8g75_config,
  912. &i2c_bus->i2c_adap);
  913. if (fe0->dvb.frontend != NULL) {
  914. dvb_attach(xc5000_attach,
  915. fe0->dvb.frontend,
  916. &i2c_bus2->i2c_adap,
  917. &magicpro_prohdtve2_xc5000_config);
  918. }
  919. break;
  920. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  921. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  922. i2c_bus = &dev->i2c_bus[0];
  923. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  924. &hcw_s5h1411_config,
  925. &i2c_bus->i2c_adap);
  926. if (fe0->dvb.frontend != NULL)
  927. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  928. 0x60, &dev->i2c_bus[0].i2c_adap,
  929. &hauppauge_tda18271_config);
  930. break;
  931. case CX23885_BOARD_MYGICA_X8558PRO:
  932. switch (port->nr) {
  933. /* port B */
  934. case 1:
  935. i2c_bus = &dev->i2c_bus[0];
  936. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  937. &mygica_x8558pro_atbm8830_cfg1,
  938. &i2c_bus->i2c_adap);
  939. if (fe0->dvb.frontend != NULL) {
  940. dvb_attach(max2165_attach,
  941. fe0->dvb.frontend,
  942. &i2c_bus->i2c_adap,
  943. &mygic_x8558pro_max2165_cfg1);
  944. }
  945. break;
  946. /* port C */
  947. case 2:
  948. i2c_bus = &dev->i2c_bus[1];
  949. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  950. &mygica_x8558pro_atbm8830_cfg2,
  951. &i2c_bus->i2c_adap);
  952. if (fe0->dvb.frontend != NULL) {
  953. dvb_attach(max2165_attach,
  954. fe0->dvb.frontend,
  955. &i2c_bus->i2c_adap,
  956. &mygic_x8558pro_max2165_cfg2);
  957. }
  958. break;
  959. }
  960. break;
  961. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  962. i2c_bus = &dev->i2c_bus[0];
  963. mfe_shared = 1;/* MFE */
  964. port->frontends.gate = 0;/* not clear for me yet */
  965. /* ports B, C */
  966. /* MFE frontend 1 DVB-T */
  967. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  968. &netup_stv0367_config[port->nr - 1],
  969. &i2c_bus->i2c_adap);
  970. if (fe0->dvb.frontend != NULL) {
  971. if (NULL == dvb_attach(xc5000_attach,
  972. fe0->dvb.frontend,
  973. &i2c_bus->i2c_adap,
  974. &netup_xc5000_config[port->nr - 1]))
  975. goto frontend_detach;
  976. /* load xc5000 firmware */
  977. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  978. }
  979. /* MFE frontend 2 */
  980. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  981. if (fe1 == NULL)
  982. goto frontend_detach;
  983. /* DVB-C init */
  984. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  985. &netup_stv0367_config[port->nr - 1],
  986. &i2c_bus->i2c_adap);
  987. if (fe1->dvb.frontend != NULL) {
  988. fe1->dvb.frontend->id = 1;
  989. if (NULL == dvb_attach(xc5000_attach,
  990. fe1->dvb.frontend,
  991. &i2c_bus->i2c_adap,
  992. &netup_xc5000_config[port->nr - 1]))
  993. goto frontend_detach;
  994. }
  995. break;
  996. default:
  997. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  998. " isn't supported yet\n",
  999. dev->name);
  1000. break;
  1001. }
  1002. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1003. printk(KERN_ERR "%s: frontend initialization failed\n",
  1004. dev->name);
  1005. goto frontend_detach;
  1006. }
  1007. /* define general-purpose callback pointer */
  1008. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1009. if (fe1)
  1010. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1011. #if 0
  1012. /* Ensure all frontends negotiate bus access */
  1013. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1014. if (fe1)
  1015. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1016. #endif
  1017. /* Put the analog decoder in standby to keep it quiet */
  1018. call_all(dev, core, s_power, 0);
  1019. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1020. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1021. /* register everything */
  1022. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1023. &dev->pci->dev, adapter_nr, mfe_shared,
  1024. NULL);
  1025. if (ret)
  1026. goto frontend_detach;
  1027. /* init CI & MAC */
  1028. switch (dev->board) {
  1029. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1030. static struct netup_card_info cinfo;
  1031. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1032. memcpy(port->frontends.adapter.proposed_mac,
  1033. cinfo.port[port->nr - 1].mac, 6);
  1034. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1035. port->nr, port->frontends.adapter.proposed_mac);
  1036. netup_ci_init(port);
  1037. break;
  1038. }
  1039. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1040. struct altera_ci_config netup_ci_cfg = {
  1041. .dev = dev,/* magic number to identify*/
  1042. .adapter = &port->frontends.adapter,/* for CI */
  1043. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1044. .fpga_rw = netup_altera_fpga_rw,
  1045. };
  1046. altera_ci_init(&netup_ci_cfg, port->nr);
  1047. break;
  1048. }
  1049. case CX23885_BOARD_TEVII_S470: {
  1050. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1051. if (port->nr != 1)
  1052. break;
  1053. /* Read entire EEPROM */
  1054. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1055. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1056. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1057. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1058. break;
  1059. }
  1060. }
  1061. return ret;
  1062. frontend_detach:
  1063. port->gate_ctrl = NULL;
  1064. videobuf_dvb_dealloc_frontends(&port->frontends);
  1065. return -EINVAL;
  1066. }
  1067. int cx23885_dvb_register(struct cx23885_tsport *port)
  1068. {
  1069. struct videobuf_dvb_frontend *fe0;
  1070. struct cx23885_dev *dev = port->dev;
  1071. int err, i;
  1072. /* Here we need to allocate the correct number of frontends,
  1073. * as reflected in the cards struct. The reality is that currently
  1074. * no cx23885 boards support this - yet. But, if we don't modify this
  1075. * code then the second frontend would never be allocated (later)
  1076. * and fail with error before the attach in dvb_register().
  1077. * Without these changes we risk an OOPS later. The changes here
  1078. * are for safety, and should provide a good foundation for the
  1079. * future addition of any multi-frontend cx23885 based boards.
  1080. */
  1081. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1082. port->num_frontends);
  1083. for (i = 1; i <= port->num_frontends; i++) {
  1084. if (videobuf_dvb_alloc_frontend(
  1085. &port->frontends, i) == NULL) {
  1086. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1087. return -ENOMEM;
  1088. }
  1089. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1090. if (!fe0)
  1091. err = -EINVAL;
  1092. dprintk(1, "%s\n", __func__);
  1093. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1094. dev->board,
  1095. dev->name,
  1096. dev->pci_bus,
  1097. dev->pci_slot);
  1098. err = -ENODEV;
  1099. /* dvb stuff */
  1100. /* We have to init the queue for each frontend on a port. */
  1101. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1102. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1103. &dev->pci->dev, &port->slock,
  1104. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1105. sizeof(struct cx23885_buffer), port, NULL);
  1106. }
  1107. err = dvb_register(port);
  1108. if (err != 0)
  1109. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1110. __func__, err);
  1111. return err;
  1112. }
  1113. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1114. {
  1115. struct videobuf_dvb_frontend *fe0;
  1116. /* FIXME: in an error condition where the we have
  1117. * an expected number of frontends (attach problem)
  1118. * then this might not clean up correctly, if 1
  1119. * is invalid.
  1120. * This comment only applies to future boards IF they
  1121. * implement MFE support.
  1122. */
  1123. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1124. if (fe0 && fe0->dvb.frontend)
  1125. videobuf_dvb_unregister_bus(&port->frontends);
  1126. switch (port->dev->board) {
  1127. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1128. netup_ci_exit(port);
  1129. break;
  1130. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1131. altera_ci_release(port->dev, port->nr);
  1132. break;
  1133. }
  1134. port->gate_ctrl = NULL;
  1135. return 0;
  1136. }