therm_throt.c 14 KB

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  1. /*
  2. * Thermal throttle event support code (such as syslog messaging and rate
  3. * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
  4. *
  5. * This allows consistent reporting of CPU thermal throttle events.
  6. *
  7. * Maintains a counter in /sys that keeps track of the number of thermal
  8. * events, such that the user knows how bad the thermal problem might be
  9. * (since the logging to syslog and mcelog is rate limited).
  10. *
  11. * Author: Dmitriy Zavin (dmitriyz@google.com)
  12. *
  13. * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
  14. * Inspired by Ross Biro's and Al Borchers' counter code.
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/kernel.h>
  20. #include <linux/percpu.h>
  21. #include <linux/sysdev.h>
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/smp.h>
  25. #include <linux/cpu.h>
  26. #include <asm/processor.h>
  27. #include <asm/system.h>
  28. #include <asm/apic.h>
  29. #include <asm/idle.h>
  30. #include <asm/mce.h>
  31. #include <asm/msr.h>
  32. /* How long to wait between reporting thermal events */
  33. #define CHECK_INTERVAL (300 * HZ)
  34. #define THERMAL_THROTTLING_EVENT 0
  35. #define POWER_LIMIT_EVENT 1
  36. /*
  37. * Current thermal event state:
  38. */
  39. struct _thermal_state {
  40. bool new_event;
  41. int event;
  42. u64 next_check;
  43. unsigned long count;
  44. unsigned long last_count;
  45. };
  46. struct thermal_state {
  47. struct _thermal_state core_throttle;
  48. struct _thermal_state core_power_limit;
  49. struct _thermal_state package_throttle;
  50. struct _thermal_state package_power_limit;
  51. struct _thermal_state core_thresh0;
  52. struct _thermal_state core_thresh1;
  53. };
  54. /* Callback to handle core threshold interrupts */
  55. int (*platform_thermal_notify)(__u64 msr_val);
  56. static DEFINE_PER_CPU(struct thermal_state, thermal_state);
  57. static atomic_t therm_throt_en = ATOMIC_INIT(0);
  58. static u32 lvtthmr_init __read_mostly;
  59. #ifdef CONFIG_SYSFS
  60. #define define_therm_throt_sysdev_one_ro(_name) \
  61. static SYSDEV_ATTR(_name, 0444, \
  62. therm_throt_sysdev_show_##_name, \
  63. NULL) \
  64. #define define_therm_throt_sysdev_show_func(event, name) \
  65. \
  66. static ssize_t therm_throt_sysdev_show_##event##_##name( \
  67. struct sys_device *dev, \
  68. struct sysdev_attribute *attr, \
  69. char *buf) \
  70. { \
  71. unsigned int cpu = dev->id; \
  72. ssize_t ret; \
  73. \
  74. preempt_disable(); /* CPU hotplug */ \
  75. if (cpu_online(cpu)) { \
  76. ret = sprintf(buf, "%lu\n", \
  77. per_cpu(thermal_state, cpu).event.name); \
  78. } else \
  79. ret = 0; \
  80. preempt_enable(); \
  81. \
  82. return ret; \
  83. }
  84. define_therm_throt_sysdev_show_func(core_throttle, count);
  85. define_therm_throt_sysdev_one_ro(core_throttle_count);
  86. define_therm_throt_sysdev_show_func(core_power_limit, count);
  87. define_therm_throt_sysdev_one_ro(core_power_limit_count);
  88. define_therm_throt_sysdev_show_func(package_throttle, count);
  89. define_therm_throt_sysdev_one_ro(package_throttle_count);
  90. define_therm_throt_sysdev_show_func(package_power_limit, count);
  91. define_therm_throt_sysdev_one_ro(package_power_limit_count);
  92. static struct attribute *thermal_throttle_attrs[] = {
  93. &attr_core_throttle_count.attr,
  94. NULL
  95. };
  96. static struct attribute_group thermal_attr_group = {
  97. .attrs = thermal_throttle_attrs,
  98. .name = "thermal_throttle"
  99. };
  100. #endif /* CONFIG_SYSFS */
  101. #define CORE_LEVEL 0
  102. #define PACKAGE_LEVEL 1
  103. /***
  104. * therm_throt_process - Process thermal throttling event from interrupt
  105. * @curr: Whether the condition is current or not (boolean), since the
  106. * thermal interrupt normally gets called both when the thermal
  107. * event begins and once the event has ended.
  108. *
  109. * This function is called by the thermal interrupt after the
  110. * IRQ has been acknowledged.
  111. *
  112. * It will take care of rate limiting and printing messages to the syslog.
  113. *
  114. * Returns: 0 : Event should NOT be further logged, i.e. still in
  115. * "timeout" from previous log message.
  116. * 1 : Event should be logged further, and a message has been
  117. * printed to the syslog.
  118. */
  119. static int therm_throt_process(bool new_event, int event, int level)
  120. {
  121. struct _thermal_state *state;
  122. unsigned int this_cpu = smp_processor_id();
  123. bool old_event;
  124. u64 now;
  125. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  126. now = get_jiffies_64();
  127. if (level == CORE_LEVEL) {
  128. if (event == THERMAL_THROTTLING_EVENT)
  129. state = &pstate->core_throttle;
  130. else if (event == POWER_LIMIT_EVENT)
  131. state = &pstate->core_power_limit;
  132. else
  133. return 0;
  134. } else if (level == PACKAGE_LEVEL) {
  135. if (event == THERMAL_THROTTLING_EVENT)
  136. state = &pstate->package_throttle;
  137. else if (event == POWER_LIMIT_EVENT)
  138. state = &pstate->package_power_limit;
  139. else
  140. return 0;
  141. } else
  142. return 0;
  143. old_event = state->new_event;
  144. state->new_event = new_event;
  145. if (new_event)
  146. state->count++;
  147. if (time_before64(now, state->next_check) &&
  148. state->count != state->last_count)
  149. return 0;
  150. state->next_check = now + CHECK_INTERVAL;
  151. state->last_count = state->count;
  152. /* if we just entered the thermal event */
  153. if (new_event) {
  154. if (event == THERMAL_THROTTLING_EVENT)
  155. printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
  156. this_cpu,
  157. level == CORE_LEVEL ? "Core" : "Package",
  158. state->count);
  159. else
  160. printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n",
  161. this_cpu,
  162. level == CORE_LEVEL ? "Core" : "Package",
  163. state->count);
  164. add_taint(TAINT_MACHINE_CHECK);
  165. return 1;
  166. }
  167. if (old_event) {
  168. if (event == THERMAL_THROTTLING_EVENT)
  169. printk(KERN_INFO "CPU%d: %s temperature/speed normal\n",
  170. this_cpu,
  171. level == CORE_LEVEL ? "Core" : "Package");
  172. else
  173. printk(KERN_INFO "CPU%d: %s power limit normal\n",
  174. this_cpu,
  175. level == CORE_LEVEL ? "Core" : "Package");
  176. return 1;
  177. }
  178. return 0;
  179. }
  180. static int thresh_event_valid(int event)
  181. {
  182. struct _thermal_state *state;
  183. unsigned int this_cpu = smp_processor_id();
  184. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  185. u64 now = get_jiffies_64();
  186. state = (event == 0) ? &pstate->core_thresh0 : &pstate->core_thresh1;
  187. if (time_before64(now, state->next_check))
  188. return 0;
  189. state->next_check = now + CHECK_INTERVAL;
  190. return 1;
  191. }
  192. #ifdef CONFIG_SYSFS
  193. /* Add/Remove thermal_throttle interface for CPU device: */
  194. static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
  195. unsigned int cpu)
  196. {
  197. int err;
  198. struct cpuinfo_x86 *c = &cpu_data(cpu);
  199. err = sysfs_create_group(&sys_dev->kobj, &thermal_attr_group);
  200. if (err)
  201. return err;
  202. if (cpu_has(c, X86_FEATURE_PLN))
  203. err = sysfs_add_file_to_group(&sys_dev->kobj,
  204. &attr_core_power_limit_count.attr,
  205. thermal_attr_group.name);
  206. if (cpu_has(c, X86_FEATURE_PTS)) {
  207. err = sysfs_add_file_to_group(&sys_dev->kobj,
  208. &attr_package_throttle_count.attr,
  209. thermal_attr_group.name);
  210. if (cpu_has(c, X86_FEATURE_PLN))
  211. err = sysfs_add_file_to_group(&sys_dev->kobj,
  212. &attr_package_power_limit_count.attr,
  213. thermal_attr_group.name);
  214. }
  215. return err;
  216. }
  217. static __cpuinit void thermal_throttle_remove_dev(struct sys_device *sys_dev)
  218. {
  219. sysfs_remove_group(&sys_dev->kobj, &thermal_attr_group);
  220. }
  221. /* Mutex protecting device creation against CPU hotplug: */
  222. static DEFINE_MUTEX(therm_cpu_lock);
  223. /* Get notified when a cpu comes on/off. Be hotplug friendly. */
  224. static __cpuinit int
  225. thermal_throttle_cpu_callback(struct notifier_block *nfb,
  226. unsigned long action,
  227. void *hcpu)
  228. {
  229. unsigned int cpu = (unsigned long)hcpu;
  230. struct sys_device *sys_dev;
  231. int err = 0;
  232. sys_dev = get_cpu_sysdev(cpu);
  233. switch (action) {
  234. case CPU_UP_PREPARE:
  235. case CPU_UP_PREPARE_FROZEN:
  236. mutex_lock(&therm_cpu_lock);
  237. err = thermal_throttle_add_dev(sys_dev, cpu);
  238. mutex_unlock(&therm_cpu_lock);
  239. WARN_ON(err);
  240. break;
  241. case CPU_UP_CANCELED:
  242. case CPU_UP_CANCELED_FROZEN:
  243. case CPU_DEAD:
  244. case CPU_DEAD_FROZEN:
  245. mutex_lock(&therm_cpu_lock);
  246. thermal_throttle_remove_dev(sys_dev);
  247. mutex_unlock(&therm_cpu_lock);
  248. break;
  249. }
  250. return notifier_from_errno(err);
  251. }
  252. static struct notifier_block thermal_throttle_cpu_notifier __cpuinitdata =
  253. {
  254. .notifier_call = thermal_throttle_cpu_callback,
  255. };
  256. static __init int thermal_throttle_init_device(void)
  257. {
  258. unsigned int cpu = 0;
  259. int err;
  260. if (!atomic_read(&therm_throt_en))
  261. return 0;
  262. register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
  263. #ifdef CONFIG_HOTPLUG_CPU
  264. mutex_lock(&therm_cpu_lock);
  265. #endif
  266. /* connect live CPUs to sysfs */
  267. for_each_online_cpu(cpu) {
  268. err = thermal_throttle_add_dev(get_cpu_sysdev(cpu), cpu);
  269. WARN_ON(err);
  270. }
  271. #ifdef CONFIG_HOTPLUG_CPU
  272. mutex_unlock(&therm_cpu_lock);
  273. #endif
  274. return 0;
  275. }
  276. device_initcall(thermal_throttle_init_device);
  277. #endif /* CONFIG_SYSFS */
  278. /*
  279. * Set up the most two significant bit to notify mce log that this thermal
  280. * event type.
  281. * This is a temp solution. May be changed in the future with mce log
  282. * infrasture.
  283. */
  284. #define CORE_THROTTLED (0)
  285. #define CORE_POWER_LIMIT ((__u64)1 << 62)
  286. #define PACKAGE_THROTTLED ((__u64)2 << 62)
  287. #define PACKAGE_POWER_LIMIT ((__u64)3 << 62)
  288. static void notify_thresholds(__u64 msr_val)
  289. {
  290. /* check whether the interrupt handler is defined;
  291. * otherwise simply return
  292. */
  293. if (!platform_thermal_notify)
  294. return;
  295. /* lower threshold reached */
  296. if ((msr_val & THERM_LOG_THRESHOLD0) && thresh_event_valid(0))
  297. platform_thermal_notify(msr_val);
  298. /* higher threshold reached */
  299. if ((msr_val & THERM_LOG_THRESHOLD1) && thresh_event_valid(1))
  300. platform_thermal_notify(msr_val);
  301. }
  302. /* Thermal transition interrupt handler */
  303. static void intel_thermal_interrupt(void)
  304. {
  305. __u64 msr_val;
  306. struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
  307. rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  308. /* Check for violation of core thermal thresholds*/
  309. notify_thresholds(msr_val);
  310. if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
  311. THERMAL_THROTTLING_EVENT,
  312. CORE_LEVEL) != 0)
  313. mce_log_therm_throt_event(CORE_THROTTLED | msr_val);
  314. if (cpu_has(c, X86_FEATURE_PLN))
  315. if (therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
  316. POWER_LIMIT_EVENT,
  317. CORE_LEVEL) != 0)
  318. mce_log_therm_throt_event(CORE_POWER_LIMIT | msr_val);
  319. if (cpu_has(c, X86_FEATURE_PTS)) {
  320. rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
  321. if (therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
  322. THERMAL_THROTTLING_EVENT,
  323. PACKAGE_LEVEL) != 0)
  324. mce_log_therm_throt_event(PACKAGE_THROTTLED | msr_val);
  325. if (cpu_has(c, X86_FEATURE_PLN))
  326. if (therm_throt_process(msr_val &
  327. PACKAGE_THERM_STATUS_POWER_LIMIT,
  328. POWER_LIMIT_EVENT,
  329. PACKAGE_LEVEL) != 0)
  330. mce_log_therm_throt_event(PACKAGE_POWER_LIMIT
  331. | msr_val);
  332. }
  333. }
  334. static void unexpected_thermal_interrupt(void)
  335. {
  336. printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n",
  337. smp_processor_id());
  338. add_taint(TAINT_MACHINE_CHECK);
  339. }
  340. static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
  341. asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
  342. {
  343. exit_idle();
  344. irq_enter();
  345. inc_irq_stat(irq_thermal_count);
  346. smp_thermal_vector();
  347. irq_exit();
  348. /* Ack only at the end to avoid potential reentry */
  349. ack_APIC_irq();
  350. }
  351. /* Thermal monitoring depends on APIC, ACPI and clock modulation */
  352. static int intel_thermal_supported(struct cpuinfo_x86 *c)
  353. {
  354. if (!cpu_has_apic)
  355. return 0;
  356. if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
  357. return 0;
  358. return 1;
  359. }
  360. void __init mcheck_intel_therm_init(void)
  361. {
  362. /*
  363. * This function is only called on boot CPU. Save the init thermal
  364. * LVT value on BSP and use that value to restore APs' thermal LVT
  365. * entry BIOS programmed later
  366. */
  367. if (intel_thermal_supported(&boot_cpu_data))
  368. lvtthmr_init = apic_read(APIC_LVTTHMR);
  369. }
  370. void intel_init_thermal(struct cpuinfo_x86 *c)
  371. {
  372. unsigned int cpu = smp_processor_id();
  373. int tm2 = 0;
  374. u32 l, h;
  375. if (!intel_thermal_supported(c))
  376. return;
  377. /*
  378. * First check if its enabled already, in which case there might
  379. * be some SMM goo which handles it, so we can't even put a handler
  380. * since it might be delivered via SMI already:
  381. */
  382. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  383. /*
  384. * The initial value of thermal LVT entries on all APs always reads
  385. * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
  386. * sequence to them and LVT registers are reset to 0s except for
  387. * the mask bits which are set to 1s when APs receive INIT IPI.
  388. * Always restore the value that BIOS has programmed on AP based on
  389. * BSP's info we saved since BIOS is always setting the same value
  390. * for all threads/cores
  391. */
  392. apic_write(APIC_LVTTHMR, lvtthmr_init);
  393. h = lvtthmr_init;
  394. if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
  395. printk(KERN_DEBUG
  396. "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  397. return;
  398. }
  399. /* Check whether a vector already exists */
  400. if (h & APIC_VECTOR_MASK) {
  401. printk(KERN_DEBUG
  402. "CPU%d: Thermal LVT vector (%#x) already installed\n",
  403. cpu, (h & APIC_VECTOR_MASK));
  404. return;
  405. }
  406. /* early Pentium M models use different method for enabling TM2 */
  407. if (cpu_has(c, X86_FEATURE_TM2)) {
  408. if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
  409. rdmsr(MSR_THERM2_CTL, l, h);
  410. if (l & MSR_THERM2_CTL_TM_SELECT)
  411. tm2 = 1;
  412. } else if (l & MSR_IA32_MISC_ENABLE_TM2)
  413. tm2 = 1;
  414. }
  415. /* We'll mask the thermal vector in the lapic till we're ready: */
  416. h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
  417. apic_write(APIC_LVTTHMR, h);
  418. rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  419. if (cpu_has(c, X86_FEATURE_PLN))
  420. wrmsr(MSR_IA32_THERM_INTERRUPT,
  421. l | (THERM_INT_LOW_ENABLE
  422. | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
  423. else
  424. wrmsr(MSR_IA32_THERM_INTERRUPT,
  425. l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
  426. if (cpu_has(c, X86_FEATURE_PTS)) {
  427. rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
  428. if (cpu_has(c, X86_FEATURE_PLN))
  429. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  430. l | (PACKAGE_THERM_INT_LOW_ENABLE
  431. | PACKAGE_THERM_INT_HIGH_ENABLE
  432. | PACKAGE_THERM_INT_PLN_ENABLE), h);
  433. else
  434. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  435. l | (PACKAGE_THERM_INT_LOW_ENABLE
  436. | PACKAGE_THERM_INT_HIGH_ENABLE), h);
  437. }
  438. smp_thermal_vector = intel_thermal_interrupt;
  439. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  440. wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
  441. /* Unmask the thermal vector: */
  442. l = apic_read(APIC_LVTTHMR);
  443. apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  444. printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n",
  445. tm2 ? "TM2" : "TM1");
  446. /* enable thermal throttle processing */
  447. atomic_set(&therm_throt_en, 1);
  448. }