at91sam9x5.dtsi 5.1 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. memory@20000000 {
  34. reg = <0x20000000 0x10000000>;
  35. };
  36. ahb {
  37. compatible = "simple-bus";
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. ranges;
  41. apb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. aic: interrupt-controller@fffff000 {
  47. #interrupt-cells = <2>;
  48. compatible = "atmel,at91rm9200-aic";
  49. interrupt-controller;
  50. interrupt-parent;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. ramc0: ramc@ffffe800 {
  54. compatible = "atmel,at91sam9g45-ddramc";
  55. reg = <0xffffe800 0x200>;
  56. };
  57. pmc: pmc@fffffc00 {
  58. compatible = "atmel,at91rm9200-pmc";
  59. reg = <0xfffffc00 0x100>;
  60. };
  61. rstc@fffffe00 {
  62. compatible = "atmel,at91sam9g45-rstc";
  63. reg = <0xfffffe00 0x10>;
  64. };
  65. pit: timer@fffffe30 {
  66. compatible = "atmel,at91sam9260-pit";
  67. reg = <0xfffffe30 0xf>;
  68. interrupts = <1 4>;
  69. };
  70. tcb0: timer@f8008000 {
  71. compatible = "atmel,at91sam9x5-tcb";
  72. reg = <0xf8008000 0x100>;
  73. interrupts = <17 4>;
  74. };
  75. tcb1: timer@f800c000 {
  76. compatible = "atmel,at91sam9x5-tcb";
  77. reg = <0xf800c000 0x100>;
  78. interrupts = <17 4>;
  79. };
  80. dma0: dma-controller@ffffec00 {
  81. compatible = "atmel,at91sam9g45-dma";
  82. reg = <0xffffec00 0x200>;
  83. interrupts = <20 4>;
  84. };
  85. dma1: dma-controller@ffffee00 {
  86. compatible = "atmel,at91sam9g45-dma";
  87. reg = <0xffffee00 0x200>;
  88. interrupts = <21 4>;
  89. };
  90. pioA: gpio@fffff400 {
  91. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  92. reg = <0xfffff400 0x100>;
  93. interrupts = <2 4>;
  94. #gpio-cells = <2>;
  95. gpio-controller;
  96. interrupt-controller;
  97. };
  98. pioB: gpio@fffff600 {
  99. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  100. reg = <0xfffff600 0x100>;
  101. interrupts = <2 4>;
  102. #gpio-cells = <2>;
  103. gpio-controller;
  104. interrupt-controller;
  105. };
  106. pioC: gpio@fffff800 {
  107. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  108. reg = <0xfffff800 0x100>;
  109. interrupts = <3 4>;
  110. #gpio-cells = <2>;
  111. gpio-controller;
  112. interrupt-controller;
  113. };
  114. pioD: gpio@fffffa00 {
  115. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  116. reg = <0xfffffa00 0x100>;
  117. interrupts = <3 4>;
  118. #gpio-cells = <2>;
  119. gpio-controller;
  120. interrupt-controller;
  121. };
  122. dbgu: serial@fffff200 {
  123. compatible = "atmel,at91sam9260-usart";
  124. reg = <0xfffff200 0x200>;
  125. interrupts = <1 4>;
  126. status = "disabled";
  127. };
  128. usart0: serial@f801c000 {
  129. compatible = "atmel,at91sam9260-usart";
  130. reg = <0xf801c000 0x200>;
  131. interrupts = <5 4>;
  132. atmel,use-dma-rx;
  133. atmel,use-dma-tx;
  134. status = "disabled";
  135. };
  136. usart1: serial@f8020000 {
  137. compatible = "atmel,at91sam9260-usart";
  138. reg = <0xf8020000 0x200>;
  139. interrupts = <6 4>;
  140. atmel,use-dma-rx;
  141. atmel,use-dma-tx;
  142. status = "disabled";
  143. };
  144. usart2: serial@f8024000 {
  145. compatible = "atmel,at91sam9260-usart";
  146. reg = <0xf8024000 0x200>;
  147. interrupts = <7 4>;
  148. atmel,use-dma-rx;
  149. atmel,use-dma-tx;
  150. status = "disabled";
  151. };
  152. macb0: ethernet@f802c000 {
  153. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  154. reg = <0xf802c000 0x100>;
  155. interrupts = <24 4>;
  156. status = "disabled";
  157. };
  158. macb1: ethernet@f8030000 {
  159. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  160. reg = <0xf8030000 0x100>;
  161. interrupts = <27 4>;
  162. status = "disabled";
  163. };
  164. };
  165. nand0: nand@40000000 {
  166. compatible = "atmel,at91rm9200-nand";
  167. #address-cells = <1>;
  168. #size-cells = <1>;
  169. reg = <0x40000000 0x10000000
  170. >;
  171. atmel,nand-addr-offset = <21>;
  172. atmel,nand-cmd-offset = <22>;
  173. gpios = <&pioC 8 0
  174. &pioC 14 0
  175. 0
  176. >;
  177. status = "disabled";
  178. };
  179. };
  180. i2c@0 {
  181. compatible = "i2c-gpio";
  182. gpios = <&pioA 30 0 /* sda */
  183. &pioA 31 0 /* scl */
  184. >;
  185. i2c-gpio,sda-open-drain;
  186. i2c-gpio,scl-open-drain;
  187. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. status = "disabled";
  191. };
  192. i2c@1 {
  193. compatible = "i2c-gpio";
  194. gpios = <&pioC 0 0 /* sda */
  195. &pioC 1 0 /* scl */
  196. >;
  197. i2c-gpio,sda-open-drain;
  198. i2c-gpio,scl-open-drain;
  199. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  200. #address-cells = <1>;
  201. #size-cells = <0>;
  202. status = "disabled";
  203. };
  204. i2c@2 {
  205. compatible = "i2c-gpio";
  206. gpios = <&pioB 4 0 /* sda */
  207. &pioB 5 0 /* scl */
  208. >;
  209. i2c-gpio,sda-open-drain;
  210. i2c-gpio,scl-open-drain;
  211. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. status = "disabled";
  215. };
  216. };