at91sam9g45.dtsi 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229
  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. };
  30. cpus {
  31. cpu@0 {
  32. compatible = "arm,arm926ejs";
  33. };
  34. };
  35. memory@70000000 {
  36. reg = <0x70000000 0x10000000>;
  37. };
  38. ahb {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. apb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. aic: interrupt-controller@fffff000 {
  49. #interrupt-cells = <2>;
  50. compatible = "atmel,at91rm9200-aic";
  51. interrupt-controller;
  52. interrupt-parent;
  53. reg = <0xfffff000 0x200>;
  54. };
  55. ramc0: ramc@ffffe400 {
  56. compatible = "atmel,at91sam9g45-ddramc";
  57. reg = <0xffffe400 0x200
  58. 0xffffe600 0x200>;
  59. };
  60. pmc: pmc@fffffc00 {
  61. compatible = "atmel,at91rm9200-pmc";
  62. reg = <0xfffffc00 0x100>;
  63. };
  64. rstc@fffffd00 {
  65. compatible = "atmel,at91sam9g45-rstc";
  66. reg = <0xfffffd00 0x10>;
  67. };
  68. pit: timer@fffffd30 {
  69. compatible = "atmel,at91sam9260-pit";
  70. reg = <0xfffffd30 0xf>;
  71. interrupts = <1 4>;
  72. };
  73. tcb0: timer@fff7c000 {
  74. compatible = "atmel,at91rm9200-tcb";
  75. reg = <0xfff7c000 0x100>;
  76. interrupts = <18 4>;
  77. };
  78. tcb1: timer@fffd4000 {
  79. compatible = "atmel,at91rm9200-tcb";
  80. reg = <0xfffd4000 0x100>;
  81. interrupts = <18 4>;
  82. };
  83. dma: dma-controller@ffffec00 {
  84. compatible = "atmel,at91sam9g45-dma";
  85. reg = <0xffffec00 0x200>;
  86. interrupts = <21 4>;
  87. };
  88. pioA: gpio@fffff200 {
  89. compatible = "atmel,at91rm9200-gpio";
  90. reg = <0xfffff200 0x100>;
  91. interrupts = <2 4>;
  92. #gpio-cells = <2>;
  93. gpio-controller;
  94. interrupt-controller;
  95. };
  96. pioB: gpio@fffff400 {
  97. compatible = "atmel,at91rm9200-gpio";
  98. reg = <0xfffff400 0x100>;
  99. interrupts = <3 4>;
  100. #gpio-cells = <2>;
  101. gpio-controller;
  102. interrupt-controller;
  103. };
  104. pioC: gpio@fffff600 {
  105. compatible = "atmel,at91rm9200-gpio";
  106. reg = <0xfffff600 0x100>;
  107. interrupts = <4 4>;
  108. #gpio-cells = <2>;
  109. gpio-controller;
  110. interrupt-controller;
  111. };
  112. pioD: gpio@fffff800 {
  113. compatible = "atmel,at91rm9200-gpio";
  114. reg = <0xfffff800 0x100>;
  115. interrupts = <5 4>;
  116. #gpio-cells = <2>;
  117. gpio-controller;
  118. interrupt-controller;
  119. };
  120. pioE: gpio@fffffa00 {
  121. compatible = "atmel,at91rm9200-gpio";
  122. reg = <0xfffffa00 0x100>;
  123. interrupts = <5 4>;
  124. #gpio-cells = <2>;
  125. gpio-controller;
  126. interrupt-controller;
  127. };
  128. dbgu: serial@ffffee00 {
  129. compatible = "atmel,at91sam9260-usart";
  130. reg = <0xffffee00 0x200>;
  131. interrupts = <1 4>;
  132. status = "disabled";
  133. };
  134. usart0: serial@fff8c000 {
  135. compatible = "atmel,at91sam9260-usart";
  136. reg = <0xfff8c000 0x200>;
  137. interrupts = <7 4>;
  138. atmel,use-dma-rx;
  139. atmel,use-dma-tx;
  140. status = "disabled";
  141. };
  142. usart1: serial@fff90000 {
  143. compatible = "atmel,at91sam9260-usart";
  144. reg = <0xfff90000 0x200>;
  145. interrupts = <8 4>;
  146. atmel,use-dma-rx;
  147. atmel,use-dma-tx;
  148. status = "disabled";
  149. };
  150. usart2: serial@fff94000 {
  151. compatible = "atmel,at91sam9260-usart";
  152. reg = <0xfff94000 0x200>;
  153. interrupts = <9 4>;
  154. atmel,use-dma-rx;
  155. atmel,use-dma-tx;
  156. status = "disabled";
  157. };
  158. usart3: serial@fff98000 {
  159. compatible = "atmel,at91sam9260-usart";
  160. reg = <0xfff98000 0x200>;
  161. interrupts = <10 4>;
  162. atmel,use-dma-rx;
  163. atmel,use-dma-tx;
  164. status = "disabled";
  165. };
  166. macb0: ethernet@fffbc000 {
  167. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  168. reg = <0xfffbc000 0x100>;
  169. interrupts = <25 4>;
  170. status = "disabled";
  171. };
  172. };
  173. nand0: nand@40000000 {
  174. compatible = "atmel,at91rm9200-nand";
  175. #address-cells = <1>;
  176. #size-cells = <1>;
  177. reg = <0x40000000 0x10000000
  178. 0xffffe200 0x200
  179. >;
  180. atmel,nand-addr-offset = <21>;
  181. atmel,nand-cmd-offset = <22>;
  182. gpios = <&pioC 8 0
  183. &pioC 14 0
  184. 0
  185. >;
  186. status = "disabled";
  187. };
  188. };
  189. i2c@0 {
  190. compatible = "i2c-gpio";
  191. gpios = <&pioA 20 0 /* sda */
  192. &pioA 21 0 /* scl */
  193. >;
  194. i2c-gpio,sda-open-drain;
  195. i2c-gpio,scl-open-drain;
  196. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. status = "disabled";
  200. };
  201. };