omap-dmic.c 13 KB

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  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/of_device.h>
  35. #include <plat/dma.h>
  36. #include <sound/core.h>
  37. #include <sound/pcm.h>
  38. #include <sound/pcm_params.h>
  39. #include <sound/initval.h>
  40. #include <sound/soc.h>
  41. #include "omap-pcm.h"
  42. #include "omap-dmic.h"
  43. struct omap_dmic {
  44. struct device *dev;
  45. void __iomem *io_base;
  46. struct clk *fclk;
  47. int fclk_freq;
  48. int out_freq;
  49. int clk_div;
  50. int sysclk;
  51. int threshold;
  52. u32 ch_enabled;
  53. bool active;
  54. struct mutex mutex;
  55. };
  56. /*
  57. * Stream DMA parameters
  58. */
  59. static struct omap_pcm_dma_data omap_dmic_dai_dma_params = {
  60. .name = "DMIC capture",
  61. .data_type = OMAP_DMA_DATA_TYPE_S32,
  62. .sync_mode = OMAP_DMA_SYNC_PACKET,
  63. };
  64. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  65. {
  66. __raw_writel(val, dmic->io_base + reg);
  67. }
  68. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  69. {
  70. return __raw_readl(dmic->io_base + reg);
  71. }
  72. static inline void omap_dmic_start(struct omap_dmic *dmic)
  73. {
  74. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  75. /* Configure DMA controller */
  76. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  77. OMAP_DMIC_DMA_ENABLE);
  78. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  79. }
  80. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  81. {
  82. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  83. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  84. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  85. /* Disable DMA request generation */
  86. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  87. OMAP_DMIC_DMA_ENABLE);
  88. }
  89. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  90. {
  91. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  92. OMAP_DMIC_UP_ENABLE_MASK;
  93. }
  94. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  95. struct snd_soc_dai *dai)
  96. {
  97. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  98. int ret = 0;
  99. mutex_lock(&dmic->mutex);
  100. if (!dai->active)
  101. dmic->active = 1;
  102. else
  103. ret = -EBUSY;
  104. mutex_unlock(&dmic->mutex);
  105. return ret;
  106. }
  107. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  108. struct snd_soc_dai *dai)
  109. {
  110. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  111. mutex_lock(&dmic->mutex);
  112. if (!dai->active)
  113. dmic->active = 0;
  114. mutex_unlock(&dmic->mutex);
  115. }
  116. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  117. {
  118. int divider = -EINVAL;
  119. /*
  120. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  121. * configuration.
  122. */
  123. if (sample_rate == 192000) {
  124. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  125. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  126. else
  127. dev_err(dmic->dev,
  128. "invalid clock configuration for 192KHz\n");
  129. return divider;
  130. }
  131. switch (dmic->out_freq) {
  132. case 1536000:
  133. if (dmic->fclk_freq != 24576000)
  134. goto div_err;
  135. divider = 0x4; /* Divider: 16 */
  136. break;
  137. case 2400000:
  138. switch (dmic->fclk_freq) {
  139. case 12000000:
  140. divider = 0x5; /* Divider: 5 */
  141. break;
  142. case 19200000:
  143. divider = 0x0; /* Divider: 8 */
  144. break;
  145. case 24000000:
  146. divider = 0x2; /* Divider: 10 */
  147. break;
  148. default:
  149. goto div_err;
  150. }
  151. break;
  152. case 3072000:
  153. if (dmic->fclk_freq != 24576000)
  154. goto div_err;
  155. divider = 0x3; /* Divider: 8 */
  156. break;
  157. case 3840000:
  158. if (dmic->fclk_freq != 19200000)
  159. goto div_err;
  160. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  161. break;
  162. default:
  163. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  164. dmic->out_freq);
  165. break;
  166. }
  167. return divider;
  168. div_err:
  169. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  170. dmic->out_freq, dmic->fclk_freq);
  171. return -EINVAL;
  172. }
  173. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  174. struct snd_pcm_hw_params *params,
  175. struct snd_soc_dai *dai)
  176. {
  177. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  178. int channels;
  179. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  180. if (dmic->clk_div < 0) {
  181. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  182. dmic->out_freq, dmic->fclk_freq);
  183. return -EINVAL;
  184. }
  185. dmic->ch_enabled = 0;
  186. channels = params_channels(params);
  187. switch (channels) {
  188. case 6:
  189. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  190. case 4:
  191. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  192. case 2:
  193. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  194. break;
  195. default:
  196. dev_err(dmic->dev, "invalid number of legacy channels\n");
  197. return -EINVAL;
  198. }
  199. /* packet size is threshold * channels */
  200. omap_dmic_dai_dma_params.packet_size = dmic->threshold * channels;
  201. snd_soc_dai_set_dma_data(dai, substream, &omap_dmic_dai_dma_params);
  202. return 0;
  203. }
  204. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  205. struct snd_soc_dai *dai)
  206. {
  207. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  208. u32 ctrl;
  209. /* Configure uplink threshold */
  210. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  211. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  212. /* Set dmic out format */
  213. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  214. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  215. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  216. /* Configure dmic clock divider */
  217. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  218. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  219. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  220. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  221. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  222. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  223. return 0;
  224. }
  225. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  226. int cmd, struct snd_soc_dai *dai)
  227. {
  228. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  229. switch (cmd) {
  230. case SNDRV_PCM_TRIGGER_START:
  231. omap_dmic_start(dmic);
  232. break;
  233. case SNDRV_PCM_TRIGGER_STOP:
  234. omap_dmic_stop(dmic);
  235. break;
  236. default:
  237. break;
  238. }
  239. return 0;
  240. }
  241. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  242. unsigned int freq)
  243. {
  244. struct clk *parent_clk;
  245. char *parent_clk_name;
  246. int ret = 0;
  247. switch (freq) {
  248. case 12000000:
  249. case 19200000:
  250. case 24000000:
  251. case 24576000:
  252. break;
  253. default:
  254. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  255. dmic->fclk_freq = 0;
  256. return -EINVAL;
  257. }
  258. if (dmic->sysclk == clk_id) {
  259. dmic->fclk_freq = freq;
  260. return 0;
  261. }
  262. /* re-parent not allowed if a stream is ongoing */
  263. if (dmic->active && dmic_is_enabled(dmic)) {
  264. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  265. return -EBUSY;
  266. }
  267. switch (clk_id) {
  268. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  269. parent_clk_name = "pad_clks_ck";
  270. break;
  271. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  272. parent_clk_name = "slimbus_clk";
  273. break;
  274. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  275. parent_clk_name = "dmic_sync_mux_ck";
  276. break;
  277. default:
  278. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  279. return -EINVAL;
  280. }
  281. parent_clk = clk_get(dmic->dev, parent_clk_name);
  282. if (IS_ERR(parent_clk)) {
  283. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  284. return -ENODEV;
  285. }
  286. mutex_lock(&dmic->mutex);
  287. if (dmic->active) {
  288. /* disable clock while reparenting */
  289. pm_runtime_put_sync(dmic->dev);
  290. ret = clk_set_parent(dmic->fclk, parent_clk);
  291. pm_runtime_get_sync(dmic->dev);
  292. } else {
  293. ret = clk_set_parent(dmic->fclk, parent_clk);
  294. }
  295. mutex_unlock(&dmic->mutex);
  296. if (ret < 0) {
  297. dev_err(dmic->dev, "re-parent failed\n");
  298. goto err_busy;
  299. }
  300. dmic->sysclk = clk_id;
  301. dmic->fclk_freq = freq;
  302. err_busy:
  303. clk_put(parent_clk);
  304. return ret;
  305. }
  306. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  307. unsigned int freq)
  308. {
  309. int ret = 0;
  310. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  311. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  312. clk_id);
  313. return -EINVAL;
  314. }
  315. switch (freq) {
  316. case 1536000:
  317. case 2400000:
  318. case 3072000:
  319. case 3840000:
  320. dmic->out_freq = freq;
  321. break;
  322. default:
  323. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  324. dmic->out_freq = 0;
  325. ret = -EINVAL;
  326. }
  327. return ret;
  328. }
  329. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  330. unsigned int freq, int dir)
  331. {
  332. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  333. if (dir == SND_SOC_CLOCK_IN)
  334. return omap_dmic_select_fclk(dmic, clk_id, freq);
  335. else if (dir == SND_SOC_CLOCK_OUT)
  336. return omap_dmic_select_outclk(dmic, clk_id, freq);
  337. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  338. return -EINVAL;
  339. }
  340. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  341. .startup = omap_dmic_dai_startup,
  342. .shutdown = omap_dmic_dai_shutdown,
  343. .hw_params = omap_dmic_dai_hw_params,
  344. .prepare = omap_dmic_dai_prepare,
  345. .trigger = omap_dmic_dai_trigger,
  346. .set_sysclk = omap_dmic_set_dai_sysclk,
  347. };
  348. static int omap_dmic_probe(struct snd_soc_dai *dai)
  349. {
  350. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  351. pm_runtime_enable(dmic->dev);
  352. /* Disable lines while request is ongoing */
  353. pm_runtime_get_sync(dmic->dev);
  354. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  355. pm_runtime_put_sync(dmic->dev);
  356. /* Configure DMIC threshold value */
  357. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  358. return 0;
  359. }
  360. static int omap_dmic_remove(struct snd_soc_dai *dai)
  361. {
  362. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  363. pm_runtime_disable(dmic->dev);
  364. return 0;
  365. }
  366. static struct snd_soc_dai_driver omap_dmic_dai = {
  367. .name = "omap-dmic",
  368. .probe = omap_dmic_probe,
  369. .remove = omap_dmic_remove,
  370. .capture = {
  371. .channels_min = 2,
  372. .channels_max = 6,
  373. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  374. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  375. .sig_bits = 24,
  376. },
  377. .ops = &omap_dmic_dai_ops,
  378. };
  379. static __devinit int asoc_dmic_probe(struct platform_device *pdev)
  380. {
  381. struct omap_dmic *dmic;
  382. struct resource *res;
  383. int ret;
  384. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  385. if (!dmic)
  386. return -ENOMEM;
  387. platform_set_drvdata(pdev, dmic);
  388. dmic->dev = &pdev->dev;
  389. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  390. mutex_init(&dmic->mutex);
  391. dmic->fclk = clk_get(dmic->dev, "dmic_fck");
  392. if (IS_ERR(dmic->fclk)) {
  393. dev_err(dmic->dev, "cant get dmic_fck\n");
  394. return -ENODEV;
  395. }
  396. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  397. if (!res) {
  398. dev_err(dmic->dev, "invalid dma memory resource\n");
  399. ret = -ENODEV;
  400. goto err_put_clk;
  401. }
  402. omap_dmic_dai_dma_params.port_addr = res->start + OMAP_DMIC_DATA_REG;
  403. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  404. if (!res) {
  405. dev_err(dmic->dev, "invalid dma resource\n");
  406. ret = -ENODEV;
  407. goto err_put_clk;
  408. }
  409. omap_dmic_dai_dma_params.dma_req = res->start;
  410. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  411. if (!res) {
  412. dev_err(dmic->dev, "invalid memory resource\n");
  413. ret = -ENODEV;
  414. goto err_put_clk;
  415. }
  416. if (!devm_request_mem_region(&pdev->dev, res->start,
  417. resource_size(res), pdev->name)) {
  418. dev_err(dmic->dev, "memory region already claimed\n");
  419. ret = -ENODEV;
  420. goto err_put_clk;
  421. }
  422. dmic->io_base = devm_ioremap(&pdev->dev, res->start,
  423. resource_size(res));
  424. if (!dmic->io_base) {
  425. ret = -ENOMEM;
  426. goto err_put_clk;
  427. }
  428. ret = snd_soc_register_dai(&pdev->dev, &omap_dmic_dai);
  429. if (ret)
  430. goto err_put_clk;
  431. return 0;
  432. err_put_clk:
  433. clk_put(dmic->fclk);
  434. return ret;
  435. }
  436. static int __devexit asoc_dmic_remove(struct platform_device *pdev)
  437. {
  438. struct omap_dmic *dmic = platform_get_drvdata(pdev);
  439. snd_soc_unregister_dai(&pdev->dev);
  440. clk_put(dmic->fclk);
  441. return 0;
  442. }
  443. static const struct of_device_id omap_dmic_of_match[] = {
  444. { .compatible = "ti,omap4-dmic", },
  445. { }
  446. };
  447. MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
  448. static struct platform_driver asoc_dmic_driver = {
  449. .driver = {
  450. .name = "omap-dmic",
  451. .owner = THIS_MODULE,
  452. .of_match_table = omap_dmic_of_match,
  453. },
  454. .probe = asoc_dmic_probe,
  455. .remove = __devexit_p(asoc_dmic_remove),
  456. };
  457. module_platform_driver(asoc_dmic_driver);
  458. MODULE_ALIAS("platform:omap-dmic");
  459. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  460. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  461. MODULE_LICENSE("GPL");