wm8961.c 30 KB

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  1. /*
  2. * wm8961.c -- WM8961 ALSA SoC Audio driver
  3. *
  4. * Copyright 2009-10 Wolfson Microelectronics, plc
  5. *
  6. * Author: Mark Brown
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Currently unimplemented features:
  13. * - ALC
  14. */
  15. #include <linux/module.h>
  16. #include <linux/moduleparam.h>
  17. #include <linux/init.h>
  18. #include <linux/delay.h>
  19. #include <linux/pm.h>
  20. #include <linux/i2c.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include "wm8961.h"
  29. #define WM8961_MAX_REGISTER 0xFC
  30. static u16 wm8961_reg_defaults[] = {
  31. 0x009F, /* R0 - Left Input volume */
  32. 0x009F, /* R1 - Right Input volume */
  33. 0x0000, /* R2 - LOUT1 volume */
  34. 0x0000, /* R3 - ROUT1 volume */
  35. 0x0020, /* R4 - Clocking1 */
  36. 0x0008, /* R5 - ADC & DAC Control 1 */
  37. 0x0000, /* R6 - ADC & DAC Control 2 */
  38. 0x000A, /* R7 - Audio Interface 0 */
  39. 0x01F4, /* R8 - Clocking2 */
  40. 0x0000, /* R9 - Audio Interface 1 */
  41. 0x00FF, /* R10 - Left DAC volume */
  42. 0x00FF, /* R11 - Right DAC volume */
  43. 0x0000, /* R12 */
  44. 0x0000, /* R13 */
  45. 0x0040, /* R14 - Audio Interface 2 */
  46. 0x0000, /* R15 - Software Reset */
  47. 0x0000, /* R16 */
  48. 0x007B, /* R17 - ALC1 */
  49. 0x0000, /* R18 - ALC2 */
  50. 0x0032, /* R19 - ALC3 */
  51. 0x0000, /* R20 - Noise Gate */
  52. 0x00C0, /* R21 - Left ADC volume */
  53. 0x00C0, /* R22 - Right ADC volume */
  54. 0x0120, /* R23 - Additional control(1) */
  55. 0x0000, /* R24 - Additional control(2) */
  56. 0x0000, /* R25 - Pwr Mgmt (1) */
  57. 0x0000, /* R26 - Pwr Mgmt (2) */
  58. 0x0000, /* R27 - Additional Control (3) */
  59. 0x0000, /* R28 - Anti-pop */
  60. 0x0000, /* R29 */
  61. 0x005F, /* R30 - Clocking 3 */
  62. 0x0000, /* R31 */
  63. 0x0000, /* R32 - ADCL signal path */
  64. 0x0000, /* R33 - ADCR signal path */
  65. 0x0000, /* R34 */
  66. 0x0000, /* R35 */
  67. 0x0000, /* R36 */
  68. 0x0000, /* R37 */
  69. 0x0000, /* R38 */
  70. 0x0000, /* R39 */
  71. 0x0000, /* R40 - LOUT2 volume */
  72. 0x0000, /* R41 - ROUT2 volume */
  73. 0x0000, /* R42 */
  74. 0x0000, /* R43 */
  75. 0x0000, /* R44 */
  76. 0x0000, /* R45 */
  77. 0x0000, /* R46 */
  78. 0x0000, /* R47 - Pwr Mgmt (3) */
  79. 0x0023, /* R48 - Additional Control (4) */
  80. 0x0000, /* R49 - Class D Control 1 */
  81. 0x0000, /* R50 */
  82. 0x0003, /* R51 - Class D Control 2 */
  83. 0x0000, /* R52 */
  84. 0x0000, /* R53 */
  85. 0x0000, /* R54 */
  86. 0x0000, /* R55 */
  87. 0x0106, /* R56 - Clocking 4 */
  88. 0x0000, /* R57 - DSP Sidetone 0 */
  89. 0x0000, /* R58 - DSP Sidetone 1 */
  90. 0x0000, /* R59 */
  91. 0x0000, /* R60 - DC Servo 0 */
  92. 0x0000, /* R61 - DC Servo 1 */
  93. 0x0000, /* R62 */
  94. 0x015E, /* R63 - DC Servo 3 */
  95. 0x0010, /* R64 */
  96. 0x0010, /* R65 - DC Servo 5 */
  97. 0x0000, /* R66 */
  98. 0x0001, /* R67 */
  99. 0x0003, /* R68 - Analogue PGA Bias */
  100. 0x0000, /* R69 - Analogue HP 0 */
  101. 0x0060, /* R70 */
  102. 0x01FB, /* R71 - Analogue HP 2 */
  103. 0x0000, /* R72 - Charge Pump 1 */
  104. 0x0065, /* R73 */
  105. 0x005F, /* R74 */
  106. 0x0059, /* R75 */
  107. 0x006B, /* R76 */
  108. 0x0038, /* R77 */
  109. 0x000C, /* R78 */
  110. 0x000A, /* R79 */
  111. 0x006B, /* R80 */
  112. 0x0000, /* R81 */
  113. 0x0000, /* R82 - Charge Pump B */
  114. 0x0087, /* R83 */
  115. 0x0000, /* R84 */
  116. 0x005C, /* R85 */
  117. 0x0000, /* R86 */
  118. 0x0000, /* R87 - Write Sequencer 1 */
  119. 0x0000, /* R88 - Write Sequencer 2 */
  120. 0x0000, /* R89 - Write Sequencer 3 */
  121. 0x0000, /* R90 - Write Sequencer 4 */
  122. 0x0000, /* R91 - Write Sequencer 5 */
  123. 0x0000, /* R92 - Write Sequencer 6 */
  124. 0x0000, /* R93 - Write Sequencer 7 */
  125. 0x0000, /* R94 */
  126. 0x0000, /* R95 */
  127. 0x0000, /* R96 */
  128. 0x0000, /* R97 */
  129. 0x0000, /* R98 */
  130. 0x0000, /* R99 */
  131. 0x0000, /* R100 */
  132. 0x0000, /* R101 */
  133. 0x0000, /* R102 */
  134. 0x0000, /* R103 */
  135. 0x0000, /* R104 */
  136. 0x0000, /* R105 */
  137. 0x0000, /* R106 */
  138. 0x0000, /* R107 */
  139. 0x0000, /* R108 */
  140. 0x0000, /* R109 */
  141. 0x0000, /* R110 */
  142. 0x0000, /* R111 */
  143. 0x0000, /* R112 */
  144. 0x0000, /* R113 */
  145. 0x0000, /* R114 */
  146. 0x0000, /* R115 */
  147. 0x0000, /* R116 */
  148. 0x0000, /* R117 */
  149. 0x0000, /* R118 */
  150. 0x0000, /* R119 */
  151. 0x0000, /* R120 */
  152. 0x0000, /* R121 */
  153. 0x0000, /* R122 */
  154. 0x0000, /* R123 */
  155. 0x0000, /* R124 */
  156. 0x0000, /* R125 */
  157. 0x0000, /* R126 */
  158. 0x0000, /* R127 */
  159. 0x0000, /* R128 */
  160. 0x0000, /* R129 */
  161. 0x0000, /* R130 */
  162. 0x0000, /* R131 */
  163. 0x0000, /* R132 */
  164. 0x0000, /* R133 */
  165. 0x0000, /* R134 */
  166. 0x0000, /* R135 */
  167. 0x0000, /* R136 */
  168. 0x0000, /* R137 */
  169. 0x0000, /* R138 */
  170. 0x0000, /* R139 */
  171. 0x0000, /* R140 */
  172. 0x0000, /* R141 */
  173. 0x0000, /* R142 */
  174. 0x0000, /* R143 */
  175. 0x0000, /* R144 */
  176. 0x0000, /* R145 */
  177. 0x0000, /* R146 */
  178. 0x0000, /* R147 */
  179. 0x0000, /* R148 */
  180. 0x0000, /* R149 */
  181. 0x0000, /* R150 */
  182. 0x0000, /* R151 */
  183. 0x0000, /* R152 */
  184. 0x0000, /* R153 */
  185. 0x0000, /* R154 */
  186. 0x0000, /* R155 */
  187. 0x0000, /* R156 */
  188. 0x0000, /* R157 */
  189. 0x0000, /* R158 */
  190. 0x0000, /* R159 */
  191. 0x0000, /* R160 */
  192. 0x0000, /* R161 */
  193. 0x0000, /* R162 */
  194. 0x0000, /* R163 */
  195. 0x0000, /* R164 */
  196. 0x0000, /* R165 */
  197. 0x0000, /* R166 */
  198. 0x0000, /* R167 */
  199. 0x0000, /* R168 */
  200. 0x0000, /* R169 */
  201. 0x0000, /* R170 */
  202. 0x0000, /* R171 */
  203. 0x0000, /* R172 */
  204. 0x0000, /* R173 */
  205. 0x0000, /* R174 */
  206. 0x0000, /* R175 */
  207. 0x0000, /* R176 */
  208. 0x0000, /* R177 */
  209. 0x0000, /* R178 */
  210. 0x0000, /* R179 */
  211. 0x0000, /* R180 */
  212. 0x0000, /* R181 */
  213. 0x0000, /* R182 */
  214. 0x0000, /* R183 */
  215. 0x0000, /* R184 */
  216. 0x0000, /* R185 */
  217. 0x0000, /* R186 */
  218. 0x0000, /* R187 */
  219. 0x0000, /* R188 */
  220. 0x0000, /* R189 */
  221. 0x0000, /* R190 */
  222. 0x0000, /* R191 */
  223. 0x0000, /* R192 */
  224. 0x0000, /* R193 */
  225. 0x0000, /* R194 */
  226. 0x0000, /* R195 */
  227. 0x0030, /* R196 */
  228. 0x0006, /* R197 */
  229. 0x0000, /* R198 */
  230. 0x0060, /* R199 */
  231. 0x0000, /* R200 */
  232. 0x003F, /* R201 */
  233. 0x0000, /* R202 */
  234. 0x0000, /* R203 */
  235. 0x0000, /* R204 */
  236. 0x0001, /* R205 */
  237. 0x0000, /* R206 */
  238. 0x0181, /* R207 */
  239. 0x0005, /* R208 */
  240. 0x0008, /* R209 */
  241. 0x0008, /* R210 */
  242. 0x0000, /* R211 */
  243. 0x013B, /* R212 */
  244. 0x0000, /* R213 */
  245. 0x0000, /* R214 */
  246. 0x0000, /* R215 */
  247. 0x0000, /* R216 */
  248. 0x0070, /* R217 */
  249. 0x0000, /* R218 */
  250. 0x0000, /* R219 */
  251. 0x0000, /* R220 */
  252. 0x0000, /* R221 */
  253. 0x0000, /* R222 */
  254. 0x0003, /* R223 */
  255. 0x0000, /* R224 */
  256. 0x0000, /* R225 */
  257. 0x0001, /* R226 */
  258. 0x0008, /* R227 */
  259. 0x0000, /* R228 */
  260. 0x0000, /* R229 */
  261. 0x0000, /* R230 */
  262. 0x0000, /* R231 */
  263. 0x0004, /* R232 */
  264. 0x0000, /* R233 */
  265. 0x0000, /* R234 */
  266. 0x0000, /* R235 */
  267. 0x0000, /* R236 */
  268. 0x0000, /* R237 */
  269. 0x0080, /* R238 */
  270. 0x0000, /* R239 */
  271. 0x0000, /* R240 */
  272. 0x0000, /* R241 */
  273. 0x0000, /* R242 */
  274. 0x0000, /* R243 */
  275. 0x0000, /* R244 */
  276. 0x0052, /* R245 */
  277. 0x0110, /* R246 */
  278. 0x0040, /* R247 */
  279. 0x0000, /* R248 */
  280. 0x0030, /* R249 */
  281. 0x0000, /* R250 */
  282. 0x0000, /* R251 */
  283. 0x0001, /* R252 - General test 1 */
  284. };
  285. struct wm8961_priv {
  286. enum snd_soc_control_type control_type;
  287. int sysclk;
  288. };
  289. static int wm8961_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
  290. {
  291. switch (reg) {
  292. case WM8961_SOFTWARE_RESET:
  293. case WM8961_WRITE_SEQUENCER_7:
  294. case WM8961_DC_SERVO_1:
  295. return 1;
  296. default:
  297. return 0;
  298. }
  299. }
  300. static int wm8961_reset(struct snd_soc_codec *codec)
  301. {
  302. return snd_soc_write(codec, WM8961_SOFTWARE_RESET, 0);
  303. }
  304. /*
  305. * The headphone output supports special anti-pop sequences giving
  306. * silent power up and power down.
  307. */
  308. static int wm8961_hp_event(struct snd_soc_dapm_widget *w,
  309. struct snd_kcontrol *kcontrol, int event)
  310. {
  311. struct snd_soc_codec *codec = w->codec;
  312. u16 hp_reg = snd_soc_read(codec, WM8961_ANALOGUE_HP_0);
  313. u16 cp_reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_1);
  314. u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
  315. u16 dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
  316. int timeout = 500;
  317. if (event & SND_SOC_DAPM_POST_PMU) {
  318. /* Make sure the output is shorted */
  319. hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
  320. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  321. /* Enable the charge pump */
  322. cp_reg |= WM8961_CP_ENA;
  323. snd_soc_write(codec, WM8961_CHARGE_PUMP_1, cp_reg);
  324. mdelay(5);
  325. /* Enable the PGA */
  326. pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA;
  327. snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
  328. /* Enable the amplifier */
  329. hp_reg |= WM8961_HPR_ENA | WM8961_HPL_ENA;
  330. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  331. /* Second stage enable */
  332. hp_reg |= WM8961_HPR_ENA_DLY | WM8961_HPL_ENA_DLY;
  333. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  334. /* Enable the DC servo & trigger startup */
  335. dcs_reg |=
  336. WM8961_DCS_ENA_CHAN_HPR | WM8961_DCS_TRIG_STARTUP_HPR |
  337. WM8961_DCS_ENA_CHAN_HPL | WM8961_DCS_TRIG_STARTUP_HPL;
  338. dev_dbg(codec->dev, "Enabling DC servo\n");
  339. snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
  340. do {
  341. msleep(1);
  342. dcs_reg = snd_soc_read(codec, WM8961_DC_SERVO_1);
  343. } while (--timeout &&
  344. dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
  345. WM8961_DCS_TRIG_STARTUP_HPL));
  346. if (dcs_reg & (WM8961_DCS_TRIG_STARTUP_HPR |
  347. WM8961_DCS_TRIG_STARTUP_HPL))
  348. dev_err(codec->dev, "DC servo timed out\n");
  349. else
  350. dev_dbg(codec->dev, "DC servo startup complete\n");
  351. /* Enable the output stage */
  352. hp_reg |= WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP;
  353. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  354. /* Remove the short on the output stage */
  355. hp_reg |= WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT;
  356. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  357. }
  358. if (event & SND_SOC_DAPM_PRE_PMD) {
  359. /* Short the output */
  360. hp_reg &= ~(WM8961_HPR_RMV_SHORT | WM8961_HPL_RMV_SHORT);
  361. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  362. /* Disable the output stage */
  363. hp_reg &= ~(WM8961_HPR_ENA_OUTP | WM8961_HPL_ENA_OUTP);
  364. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  365. /* Disable DC offset cancellation */
  366. dcs_reg &= ~(WM8961_DCS_ENA_CHAN_HPR |
  367. WM8961_DCS_ENA_CHAN_HPL);
  368. snd_soc_write(codec, WM8961_DC_SERVO_1, dcs_reg);
  369. /* Finish up */
  370. hp_reg &= ~(WM8961_HPR_ENA_DLY | WM8961_HPR_ENA |
  371. WM8961_HPL_ENA_DLY | WM8961_HPL_ENA);
  372. snd_soc_write(codec, WM8961_ANALOGUE_HP_0, hp_reg);
  373. /* Disable the PGA */
  374. pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA);
  375. snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
  376. /* Disable the charge pump */
  377. dev_dbg(codec->dev, "Disabling charge pump\n");
  378. snd_soc_write(codec, WM8961_CHARGE_PUMP_1,
  379. cp_reg & ~WM8961_CP_ENA);
  380. }
  381. return 0;
  382. }
  383. static int wm8961_spk_event(struct snd_soc_dapm_widget *w,
  384. struct snd_kcontrol *kcontrol, int event)
  385. {
  386. struct snd_soc_codec *codec = w->codec;
  387. u16 pwr_reg = snd_soc_read(codec, WM8961_PWR_MGMT_2);
  388. u16 spk_reg = snd_soc_read(codec, WM8961_CLASS_D_CONTROL_1);
  389. if (event & SND_SOC_DAPM_POST_PMU) {
  390. /* Enable the PGA */
  391. pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA;
  392. snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
  393. /* Enable the amplifier */
  394. spk_reg |= WM8961_SPKL_ENA | WM8961_SPKR_ENA;
  395. snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
  396. }
  397. if (event & SND_SOC_DAPM_PRE_PMD) {
  398. /* Disable the amplifier */
  399. spk_reg &= ~(WM8961_SPKL_ENA | WM8961_SPKR_ENA);
  400. snd_soc_write(codec, WM8961_CLASS_D_CONTROL_1, spk_reg);
  401. /* Disable the PGA */
  402. pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA);
  403. snd_soc_write(codec, WM8961_PWR_MGMT_2, pwr_reg);
  404. }
  405. return 0;
  406. }
  407. static const char *adc_hpf_text[] = {
  408. "Hi-fi", "Voice 1", "Voice 2", "Voice 3",
  409. };
  410. static const struct soc_enum adc_hpf =
  411. SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_2, 7, 4, adc_hpf_text);
  412. static const char *dac_deemph_text[] = {
  413. "None", "32kHz", "44.1kHz", "48kHz",
  414. };
  415. static const struct soc_enum dac_deemph =
  416. SOC_ENUM_SINGLE(WM8961_ADC_DAC_CONTROL_1, 1, 4, dac_deemph_text);
  417. static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
  418. static const DECLARE_TLV_DB_SCALE(hp_sec_tlv, -700, 100, 0);
  419. static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
  420. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  421. static unsigned int boost_tlv[] = {
  422. TLV_DB_RANGE_HEAD(4),
  423. 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
  424. 1, 1, TLV_DB_SCALE_ITEM(13, 0, 0),
  425. 2, 2, TLV_DB_SCALE_ITEM(20, 0, 0),
  426. 3, 3, TLV_DB_SCALE_ITEM(29, 0, 0),
  427. };
  428. static const DECLARE_TLV_DB_SCALE(pga_tlv, -2325, 75, 0);
  429. static const struct snd_kcontrol_new wm8961_snd_controls[] = {
  430. SOC_DOUBLE_R_TLV("Headphone Volume", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
  431. 0, 127, 0, out_tlv),
  432. SOC_DOUBLE_TLV("Headphone Secondary Volume", WM8961_ANALOGUE_HP_2,
  433. 6, 3, 7, 0, hp_sec_tlv),
  434. SOC_DOUBLE_R("Headphone ZC Switch", WM8961_LOUT1_VOLUME, WM8961_ROUT1_VOLUME,
  435. 7, 1, 0),
  436. SOC_DOUBLE_R_TLV("Speaker Volume", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
  437. 0, 127, 0, out_tlv),
  438. SOC_DOUBLE_R("Speaker ZC Switch", WM8961_LOUT2_VOLUME, WM8961_ROUT2_VOLUME,
  439. 7, 1, 0),
  440. SOC_SINGLE("Speaker AC Gain", WM8961_CLASS_D_CONTROL_2, 0, 7, 0),
  441. SOC_SINGLE("DAC x128 OSR Switch", WM8961_ADC_DAC_CONTROL_2, 0, 1, 0),
  442. SOC_ENUM("DAC Deemphasis", dac_deemph),
  443. SOC_SINGLE("DAC Soft Mute Switch", WM8961_ADC_DAC_CONTROL_2, 3, 1, 0),
  444. SOC_DOUBLE_R_TLV("Sidetone Volume", WM8961_DSP_SIDETONE_0,
  445. WM8961_DSP_SIDETONE_1, 4, 12, 0, sidetone_tlv),
  446. SOC_SINGLE("ADC High Pass Filter Switch", WM8961_ADC_DAC_CONTROL_1, 0, 1, 0),
  447. SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
  448. SOC_DOUBLE_R_TLV("Capture Volume",
  449. WM8961_LEFT_ADC_VOLUME, WM8961_RIGHT_ADC_VOLUME,
  450. 1, 119, 0, adc_tlv),
  451. SOC_DOUBLE_R_TLV("Capture Boost Volume",
  452. WM8961_ADCL_SIGNAL_PATH, WM8961_ADCR_SIGNAL_PATH,
  453. 4, 3, 0, boost_tlv),
  454. SOC_DOUBLE_R_TLV("Capture PGA Volume",
  455. WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
  456. 0, 62, 0, pga_tlv),
  457. SOC_DOUBLE_R("Capture PGA ZC Switch",
  458. WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
  459. 6, 1, 1),
  460. SOC_DOUBLE_R("Capture PGA Switch",
  461. WM8961_LEFT_INPUT_VOLUME, WM8961_RIGHT_INPUT_VOLUME,
  462. 7, 1, 1),
  463. };
  464. static const char *sidetone_text[] = {
  465. "None", "Left", "Right"
  466. };
  467. static const struct soc_enum dacl_sidetone =
  468. SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_0, 2, 3, sidetone_text);
  469. static const struct soc_enum dacr_sidetone =
  470. SOC_ENUM_SINGLE(WM8961_DSP_SIDETONE_1, 2, 3, sidetone_text);
  471. static const struct snd_kcontrol_new dacl_mux =
  472. SOC_DAPM_ENUM("DACL Sidetone", dacl_sidetone);
  473. static const struct snd_kcontrol_new dacr_mux =
  474. SOC_DAPM_ENUM("DACR Sidetone", dacr_sidetone);
  475. static const struct snd_soc_dapm_widget wm8961_dapm_widgets[] = {
  476. SND_SOC_DAPM_INPUT("LINPUT"),
  477. SND_SOC_DAPM_INPUT("RINPUT"),
  478. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8961_CLOCKING2, 4, 0, NULL, 0),
  479. SND_SOC_DAPM_PGA("Left Input", WM8961_PWR_MGMT_1, 5, 0, NULL, 0),
  480. SND_SOC_DAPM_PGA("Right Input", WM8961_PWR_MGMT_1, 4, 0, NULL, 0),
  481. SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", WM8961_PWR_MGMT_1, 3, 0),
  482. SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
  483. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8961_PWR_MGMT_1, 1, 0, NULL, 0),
  484. SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &dacl_mux),
  485. SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &dacr_mux),
  486. SND_SOC_DAPM_DAC("DACL", "HiFi Playback", WM8961_PWR_MGMT_2, 8, 0),
  487. SND_SOC_DAPM_DAC("DACR", "HiFi Playback", WM8961_PWR_MGMT_2, 7, 0),
  488. /* Handle as a mono path for DCS */
  489. SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM,
  490. 4, 0, NULL, 0, wm8961_hp_event,
  491. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  492. SND_SOC_DAPM_PGA_E("Speaker Output", SND_SOC_NOPM,
  493. 4, 0, NULL, 0, wm8961_spk_event,
  494. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  495. SND_SOC_DAPM_OUTPUT("HP_L"),
  496. SND_SOC_DAPM_OUTPUT("HP_R"),
  497. SND_SOC_DAPM_OUTPUT("SPK_LN"),
  498. SND_SOC_DAPM_OUTPUT("SPK_LP"),
  499. SND_SOC_DAPM_OUTPUT("SPK_RN"),
  500. SND_SOC_DAPM_OUTPUT("SPK_RP"),
  501. };
  502. static const struct snd_soc_dapm_route audio_paths[] = {
  503. { "DACL", NULL, "CLK_DSP" },
  504. { "DACL", NULL, "DACL Sidetone" },
  505. { "DACR", NULL, "CLK_DSP" },
  506. { "DACR", NULL, "DACR Sidetone" },
  507. { "DACL Sidetone", "Left", "ADCL" },
  508. { "DACL Sidetone", "Right", "ADCR" },
  509. { "DACR Sidetone", "Left", "ADCL" },
  510. { "DACR Sidetone", "Right", "ADCR" },
  511. { "HP_L", NULL, "Headphone Output" },
  512. { "HP_R", NULL, "Headphone Output" },
  513. { "Headphone Output", NULL, "DACL" },
  514. { "Headphone Output", NULL, "DACR" },
  515. { "SPK_LN", NULL, "Speaker Output" },
  516. { "SPK_LP", NULL, "Speaker Output" },
  517. { "SPK_RN", NULL, "Speaker Output" },
  518. { "SPK_RP", NULL, "Speaker Output" },
  519. { "Speaker Output", NULL, "DACL" },
  520. { "Speaker Output", NULL, "DACR" },
  521. { "ADCL", NULL, "Left Input" },
  522. { "ADCL", NULL, "CLK_DSP" },
  523. { "ADCR", NULL, "Right Input" },
  524. { "ADCR", NULL, "CLK_DSP" },
  525. { "Left Input", NULL, "LINPUT" },
  526. { "Right Input", NULL, "RINPUT" },
  527. };
  528. /* Values for CLK_SYS_RATE */
  529. static struct {
  530. int ratio;
  531. u16 val;
  532. } wm8961_clk_sys_ratio[] = {
  533. { 64, 0 },
  534. { 128, 1 },
  535. { 192, 2 },
  536. { 256, 3 },
  537. { 384, 4 },
  538. { 512, 5 },
  539. { 768, 6 },
  540. { 1024, 7 },
  541. { 1408, 8 },
  542. { 1536, 9 },
  543. };
  544. /* Values for SAMPLE_RATE */
  545. static struct {
  546. int rate;
  547. u16 val;
  548. } wm8961_srate[] = {
  549. { 48000, 0 },
  550. { 44100, 0 },
  551. { 32000, 1 },
  552. { 22050, 2 },
  553. { 24000, 2 },
  554. { 16000, 3 },
  555. { 11250, 4 },
  556. { 12000, 4 },
  557. { 8000, 5 },
  558. };
  559. static int wm8961_hw_params(struct snd_pcm_substream *substream,
  560. struct snd_pcm_hw_params *params,
  561. struct snd_soc_dai *dai)
  562. {
  563. struct snd_soc_codec *codec = dai->codec;
  564. struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
  565. int i, best, target, fs;
  566. u16 reg;
  567. fs = params_rate(params);
  568. if (!wm8961->sysclk) {
  569. dev_err(codec->dev, "MCLK has not been specified\n");
  570. return -EINVAL;
  571. }
  572. /* Find the closest sample rate for the filters */
  573. best = 0;
  574. for (i = 0; i < ARRAY_SIZE(wm8961_srate); i++) {
  575. if (abs(wm8961_srate[i].rate - fs) <
  576. abs(wm8961_srate[best].rate - fs))
  577. best = i;
  578. }
  579. reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_3);
  580. reg &= ~WM8961_SAMPLE_RATE_MASK;
  581. reg |= wm8961_srate[best].val;
  582. snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_3, reg);
  583. dev_dbg(codec->dev, "Selected SRATE %dHz for %dHz\n",
  584. wm8961_srate[best].rate, fs);
  585. /* Select a CLK_SYS/fs ratio equal to or higher than required */
  586. target = wm8961->sysclk / fs;
  587. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && target < 64) {
  588. dev_err(codec->dev,
  589. "SYSCLK must be at least 64*fs for DAC\n");
  590. return -EINVAL;
  591. }
  592. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && target < 256) {
  593. dev_err(codec->dev,
  594. "SYSCLK must be at least 256*fs for ADC\n");
  595. return -EINVAL;
  596. }
  597. for (i = 0; i < ARRAY_SIZE(wm8961_clk_sys_ratio); i++) {
  598. if (wm8961_clk_sys_ratio[i].ratio >= target)
  599. break;
  600. }
  601. if (i == ARRAY_SIZE(wm8961_clk_sys_ratio)) {
  602. dev_err(codec->dev, "Unable to generate CLK_SYS_RATE\n");
  603. return -EINVAL;
  604. }
  605. dev_dbg(codec->dev, "Selected CLK_SYS_RATE of %d for %d/%d=%d\n",
  606. wm8961_clk_sys_ratio[i].ratio, wm8961->sysclk, fs,
  607. wm8961->sysclk / fs);
  608. reg = snd_soc_read(codec, WM8961_CLOCKING_4);
  609. reg &= ~WM8961_CLK_SYS_RATE_MASK;
  610. reg |= wm8961_clk_sys_ratio[i].val << WM8961_CLK_SYS_RATE_SHIFT;
  611. snd_soc_write(codec, WM8961_CLOCKING_4, reg);
  612. reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
  613. reg &= ~WM8961_WL_MASK;
  614. switch (params_format(params)) {
  615. case SNDRV_PCM_FORMAT_S16_LE:
  616. break;
  617. case SNDRV_PCM_FORMAT_S20_3LE:
  618. reg |= 1 << WM8961_WL_SHIFT;
  619. break;
  620. case SNDRV_PCM_FORMAT_S24_LE:
  621. reg |= 2 << WM8961_WL_SHIFT;
  622. break;
  623. case SNDRV_PCM_FORMAT_S32_LE:
  624. reg |= 3 << WM8961_WL_SHIFT;
  625. break;
  626. default:
  627. return -EINVAL;
  628. }
  629. snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, reg);
  630. /* Sloping stop-band filter is recommended for <= 24kHz */
  631. reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
  632. if (fs <= 24000)
  633. reg |= WM8961_DACSLOPE;
  634. else
  635. reg &= ~WM8961_DACSLOPE;
  636. snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
  637. return 0;
  638. }
  639. static int wm8961_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  640. unsigned int freq,
  641. int dir)
  642. {
  643. struct snd_soc_codec *codec = dai->codec;
  644. struct wm8961_priv *wm8961 = snd_soc_codec_get_drvdata(codec);
  645. u16 reg = snd_soc_read(codec, WM8961_CLOCKING1);
  646. if (freq > 33000000) {
  647. dev_err(codec->dev, "MCLK must be <33MHz\n");
  648. return -EINVAL;
  649. }
  650. if (freq > 16500000) {
  651. dev_dbg(codec->dev, "Using MCLK/2 for %dHz MCLK\n", freq);
  652. reg |= WM8961_MCLKDIV;
  653. freq /= 2;
  654. } else {
  655. dev_dbg(codec->dev, "Using MCLK/1 for %dHz MCLK\n", freq);
  656. reg &= ~WM8961_MCLKDIV;
  657. }
  658. snd_soc_write(codec, WM8961_CLOCKING1, reg);
  659. wm8961->sysclk = freq;
  660. return 0;
  661. }
  662. static int wm8961_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  663. {
  664. struct snd_soc_codec *codec = dai->codec;
  665. u16 aif = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_0);
  666. aif &= ~(WM8961_BCLKINV | WM8961_LRP |
  667. WM8961_MS | WM8961_FORMAT_MASK);
  668. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  669. case SND_SOC_DAIFMT_CBM_CFM:
  670. aif |= WM8961_MS;
  671. break;
  672. case SND_SOC_DAIFMT_CBS_CFS:
  673. break;
  674. default:
  675. return -EINVAL;
  676. }
  677. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  678. case SND_SOC_DAIFMT_RIGHT_J:
  679. break;
  680. case SND_SOC_DAIFMT_LEFT_J:
  681. aif |= 1;
  682. break;
  683. case SND_SOC_DAIFMT_I2S:
  684. aif |= 2;
  685. break;
  686. case SND_SOC_DAIFMT_DSP_B:
  687. aif |= WM8961_LRP;
  688. case SND_SOC_DAIFMT_DSP_A:
  689. aif |= 3;
  690. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  691. case SND_SOC_DAIFMT_NB_NF:
  692. case SND_SOC_DAIFMT_IB_NF:
  693. break;
  694. default:
  695. return -EINVAL;
  696. }
  697. break;
  698. default:
  699. return -EINVAL;
  700. }
  701. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  702. case SND_SOC_DAIFMT_NB_NF:
  703. break;
  704. case SND_SOC_DAIFMT_NB_IF:
  705. aif |= WM8961_LRP;
  706. break;
  707. case SND_SOC_DAIFMT_IB_NF:
  708. aif |= WM8961_BCLKINV;
  709. break;
  710. case SND_SOC_DAIFMT_IB_IF:
  711. aif |= WM8961_BCLKINV | WM8961_LRP;
  712. break;
  713. default:
  714. return -EINVAL;
  715. }
  716. return snd_soc_write(codec, WM8961_AUDIO_INTERFACE_0, aif);
  717. }
  718. static int wm8961_set_tristate(struct snd_soc_dai *dai, int tristate)
  719. {
  720. struct snd_soc_codec *codec = dai->codec;
  721. u16 reg = snd_soc_read(codec, WM8961_ADDITIONAL_CONTROL_2);
  722. if (tristate)
  723. reg |= WM8961_TRIS;
  724. else
  725. reg &= ~WM8961_TRIS;
  726. return snd_soc_write(codec, WM8961_ADDITIONAL_CONTROL_2, reg);
  727. }
  728. static int wm8961_digital_mute(struct snd_soc_dai *dai, int mute)
  729. {
  730. struct snd_soc_codec *codec = dai->codec;
  731. u16 reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_1);
  732. if (mute)
  733. reg |= WM8961_DACMU;
  734. else
  735. reg &= ~WM8961_DACMU;
  736. msleep(17);
  737. return snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_1, reg);
  738. }
  739. static int wm8961_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
  740. {
  741. struct snd_soc_codec *codec = dai->codec;
  742. u16 reg;
  743. switch (div_id) {
  744. case WM8961_BCLK:
  745. reg = snd_soc_read(codec, WM8961_CLOCKING2);
  746. reg &= ~WM8961_BCLKDIV_MASK;
  747. reg |= div;
  748. snd_soc_write(codec, WM8961_CLOCKING2, reg);
  749. break;
  750. case WM8961_LRCLK:
  751. reg = snd_soc_read(codec, WM8961_AUDIO_INTERFACE_2);
  752. reg &= ~WM8961_LRCLK_RATE_MASK;
  753. reg |= div;
  754. snd_soc_write(codec, WM8961_AUDIO_INTERFACE_2, reg);
  755. break;
  756. default:
  757. return -EINVAL;
  758. }
  759. return 0;
  760. }
  761. static int wm8961_set_bias_level(struct snd_soc_codec *codec,
  762. enum snd_soc_bias_level level)
  763. {
  764. u16 reg;
  765. /* This is all slightly unusual since we have no bypass paths
  766. * and the output amplifier structure means we can just slam
  767. * the biases straight up rather than having to ramp them
  768. * slowly.
  769. */
  770. switch (level) {
  771. case SND_SOC_BIAS_ON:
  772. break;
  773. case SND_SOC_BIAS_PREPARE:
  774. if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
  775. /* Enable bias generation */
  776. reg = snd_soc_read(codec, WM8961_ANTI_POP);
  777. reg |= WM8961_BUFIOEN | WM8961_BUFDCOPEN;
  778. snd_soc_write(codec, WM8961_ANTI_POP, reg);
  779. /* VMID=2*50k, VREF */
  780. reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
  781. reg &= ~WM8961_VMIDSEL_MASK;
  782. reg |= (1 << WM8961_VMIDSEL_SHIFT) | WM8961_VREF;
  783. snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
  784. }
  785. break;
  786. case SND_SOC_BIAS_STANDBY:
  787. if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
  788. /* VREF off */
  789. reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
  790. reg &= ~WM8961_VREF;
  791. snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
  792. /* Bias generation off */
  793. reg = snd_soc_read(codec, WM8961_ANTI_POP);
  794. reg &= ~(WM8961_BUFIOEN | WM8961_BUFDCOPEN);
  795. snd_soc_write(codec, WM8961_ANTI_POP, reg);
  796. /* VMID off */
  797. reg = snd_soc_read(codec, WM8961_PWR_MGMT_1);
  798. reg &= ~WM8961_VMIDSEL_MASK;
  799. snd_soc_write(codec, WM8961_PWR_MGMT_1, reg);
  800. }
  801. break;
  802. case SND_SOC_BIAS_OFF:
  803. break;
  804. }
  805. codec->dapm.bias_level = level;
  806. return 0;
  807. }
  808. #define WM8961_RATES SNDRV_PCM_RATE_8000_48000
  809. #define WM8961_FORMATS \
  810. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  811. SNDRV_PCM_FMTBIT_S24_LE)
  812. static const struct snd_soc_dai_ops wm8961_dai_ops = {
  813. .hw_params = wm8961_hw_params,
  814. .set_sysclk = wm8961_set_sysclk,
  815. .set_fmt = wm8961_set_fmt,
  816. .digital_mute = wm8961_digital_mute,
  817. .set_tristate = wm8961_set_tristate,
  818. .set_clkdiv = wm8961_set_clkdiv,
  819. };
  820. static struct snd_soc_dai_driver wm8961_dai = {
  821. .name = "wm8961-hifi",
  822. .playback = {
  823. .stream_name = "HiFi Playback",
  824. .channels_min = 1,
  825. .channels_max = 2,
  826. .rates = WM8961_RATES,
  827. .formats = WM8961_FORMATS,},
  828. .capture = {
  829. .stream_name = "HiFi Capture",
  830. .channels_min = 1,
  831. .channels_max = 2,
  832. .rates = WM8961_RATES,
  833. .formats = WM8961_FORMATS,},
  834. .ops = &wm8961_dai_ops,
  835. };
  836. static int wm8961_probe(struct snd_soc_codec *codec)
  837. {
  838. struct snd_soc_dapm_context *dapm = &codec->dapm;
  839. int ret = 0;
  840. u16 reg;
  841. ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
  842. if (ret != 0) {
  843. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  844. return ret;
  845. }
  846. reg = snd_soc_read(codec, WM8961_SOFTWARE_RESET);
  847. if (reg != 0x1801) {
  848. dev_err(codec->dev, "Device is not a WM8961: ID=0x%x\n", reg);
  849. return -EINVAL;
  850. }
  851. /* This isn't volatile - readback doesn't correspond to write */
  852. codec->cache_bypass = 1;
  853. reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
  854. codec->cache_bypass = 0;
  855. dev_info(codec->dev, "WM8961 family %d revision %c\n",
  856. (reg & WM8961_DEVICE_ID_MASK) >> WM8961_DEVICE_ID_SHIFT,
  857. ((reg & WM8961_CHIP_REV_MASK) >> WM8961_CHIP_REV_SHIFT)
  858. + 'A');
  859. ret = wm8961_reset(codec);
  860. if (ret < 0) {
  861. dev_err(codec->dev, "Failed to issue reset\n");
  862. return ret;
  863. }
  864. /* Enable class W */
  865. reg = snd_soc_read(codec, WM8961_CHARGE_PUMP_B);
  866. reg |= WM8961_CP_DYN_PWR_MASK;
  867. snd_soc_write(codec, WM8961_CHARGE_PUMP_B, reg);
  868. /* Latch volume update bits (right channel only, we always
  869. * write both out) and default ZC on. */
  870. reg = snd_soc_read(codec, WM8961_ROUT1_VOLUME);
  871. snd_soc_write(codec, WM8961_ROUT1_VOLUME,
  872. reg | WM8961_LO1ZC | WM8961_OUT1VU);
  873. snd_soc_write(codec, WM8961_LOUT1_VOLUME, reg | WM8961_LO1ZC);
  874. reg = snd_soc_read(codec, WM8961_ROUT2_VOLUME);
  875. snd_soc_write(codec, WM8961_ROUT2_VOLUME,
  876. reg | WM8961_SPKRZC | WM8961_SPKVU);
  877. snd_soc_write(codec, WM8961_LOUT2_VOLUME, reg | WM8961_SPKLZC);
  878. reg = snd_soc_read(codec, WM8961_RIGHT_ADC_VOLUME);
  879. snd_soc_write(codec, WM8961_RIGHT_ADC_VOLUME, reg | WM8961_ADCVU);
  880. reg = snd_soc_read(codec, WM8961_RIGHT_INPUT_VOLUME);
  881. snd_soc_write(codec, WM8961_RIGHT_INPUT_VOLUME, reg | WM8961_IPVU);
  882. /* Use soft mute by default */
  883. reg = snd_soc_read(codec, WM8961_ADC_DAC_CONTROL_2);
  884. reg |= WM8961_DACSMM;
  885. snd_soc_write(codec, WM8961_ADC_DAC_CONTROL_2, reg);
  886. /* Use automatic clocking mode by default; for now this is all
  887. * we support.
  888. */
  889. reg = snd_soc_read(codec, WM8961_CLOCKING_3);
  890. reg &= ~WM8961_MANUAL_MODE;
  891. snd_soc_write(codec, WM8961_CLOCKING_3, reg);
  892. wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  893. snd_soc_add_codec_controls(codec, wm8961_snd_controls,
  894. ARRAY_SIZE(wm8961_snd_controls));
  895. snd_soc_dapm_new_controls(dapm, wm8961_dapm_widgets,
  896. ARRAY_SIZE(wm8961_dapm_widgets));
  897. snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
  898. return 0;
  899. }
  900. static int wm8961_remove(struct snd_soc_codec *codec)
  901. {
  902. wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
  903. return 0;
  904. }
  905. #ifdef CONFIG_PM
  906. static int wm8961_suspend(struct snd_soc_codec *codec)
  907. {
  908. wm8961_set_bias_level(codec, SND_SOC_BIAS_OFF);
  909. return 0;
  910. }
  911. static int wm8961_resume(struct snd_soc_codec *codec)
  912. {
  913. snd_soc_cache_sync(codec);
  914. wm8961_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  915. return 0;
  916. }
  917. #else
  918. #define wm8961_suspend NULL
  919. #define wm8961_resume NULL
  920. #endif
  921. static struct snd_soc_codec_driver soc_codec_dev_wm8961 = {
  922. .probe = wm8961_probe,
  923. .remove = wm8961_remove,
  924. .suspend = wm8961_suspend,
  925. .resume = wm8961_resume,
  926. .set_bias_level = wm8961_set_bias_level,
  927. .reg_cache_size = ARRAY_SIZE(wm8961_reg_defaults),
  928. .reg_word_size = sizeof(u16),
  929. .reg_cache_default = wm8961_reg_defaults,
  930. .volatile_register = wm8961_volatile_register,
  931. };
  932. static __devinit int wm8961_i2c_probe(struct i2c_client *i2c,
  933. const struct i2c_device_id *id)
  934. {
  935. struct wm8961_priv *wm8961;
  936. int ret;
  937. wm8961 = devm_kzalloc(&i2c->dev, sizeof(struct wm8961_priv),
  938. GFP_KERNEL);
  939. if (wm8961 == NULL)
  940. return -ENOMEM;
  941. i2c_set_clientdata(i2c, wm8961);
  942. ret = snd_soc_register_codec(&i2c->dev,
  943. &soc_codec_dev_wm8961, &wm8961_dai, 1);
  944. return ret;
  945. }
  946. static __devexit int wm8961_i2c_remove(struct i2c_client *client)
  947. {
  948. snd_soc_unregister_codec(&client->dev);
  949. return 0;
  950. }
  951. static const struct i2c_device_id wm8961_i2c_id[] = {
  952. { "wm8961", 0 },
  953. { }
  954. };
  955. MODULE_DEVICE_TABLE(i2c, wm8961_i2c_id);
  956. static struct i2c_driver wm8961_i2c_driver = {
  957. .driver = {
  958. .name = "wm8961",
  959. .owner = THIS_MODULE,
  960. },
  961. .probe = wm8961_i2c_probe,
  962. .remove = __devexit_p(wm8961_i2c_remove),
  963. .id_table = wm8961_i2c_id,
  964. };
  965. static int __init wm8961_modinit(void)
  966. {
  967. int ret = 0;
  968. ret = i2c_add_driver(&wm8961_i2c_driver);
  969. if (ret != 0) {
  970. printk(KERN_ERR "Failed to register wm8961 I2C driver: %d\n",
  971. ret);
  972. }
  973. return ret;
  974. }
  975. module_init(wm8961_modinit);
  976. static void __exit wm8961_exit(void)
  977. {
  978. i2c_del_driver(&wm8961_i2c_driver);
  979. }
  980. module_exit(wm8961_exit);
  981. MODULE_DESCRIPTION("ASoC WM8961 driver");
  982. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  983. MODULE_LICENSE("GPL");