wm8904.c 62 KB

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  1. /*
  2. * wm8904.c -- WM8904 ALSA SoC Audio driver
  3. *
  4. * Copyright 2009-12 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/i2c.h>
  19. #include <linux/regmap.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <sound/wm8904.h>
  29. #include "wm8904.h"
  30. enum wm8904_type {
  31. WM8904,
  32. WM8912,
  33. };
  34. #define WM8904_NUM_DCS_CHANNELS 4
  35. #define WM8904_NUM_SUPPLIES 5
  36. static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
  37. "DCVDD",
  38. "DBVDD",
  39. "AVDD",
  40. "CPVDD",
  41. "MICVDD",
  42. };
  43. /* codec private data */
  44. struct wm8904_priv {
  45. struct regmap *regmap;
  46. enum wm8904_type devtype;
  47. struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
  48. struct wm8904_pdata *pdata;
  49. int deemph;
  50. /* Platform provided DRC configuration */
  51. const char **drc_texts;
  52. int drc_cfg;
  53. struct soc_enum drc_enum;
  54. /* Platform provided ReTune mobile configuration */
  55. int num_retune_mobile_texts;
  56. const char **retune_mobile_texts;
  57. int retune_mobile_cfg;
  58. struct soc_enum retune_mobile_enum;
  59. /* FLL setup */
  60. int fll_src;
  61. int fll_fref;
  62. int fll_fout;
  63. /* Clocking configuration */
  64. unsigned int mclk_rate;
  65. int sysclk_src;
  66. unsigned int sysclk_rate;
  67. int tdm_width;
  68. int tdm_slots;
  69. int bclk;
  70. int fs;
  71. /* DC servo configuration - cached offset values */
  72. int dcs_state[WM8904_NUM_DCS_CHANNELS];
  73. };
  74. static const struct reg_default wm8904_reg_defaults[] = {
  75. { 4, 0x0018 }, /* R4 - Bias Control 0 */
  76. { 5, 0x0000 }, /* R5 - VMID Control 0 */
  77. { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
  78. { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
  79. { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
  80. { 9, 0x9696 }, /* R9 - mic Filter Control */
  81. { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
  82. { 12, 0x0000 }, /* R12 - Power Management 0 */
  83. { 14, 0x0000 }, /* R14 - Power Management 2 */
  84. { 15, 0x0000 }, /* R15 - Power Management 3 */
  85. { 18, 0x0000 }, /* R18 - Power Management 6 */
  86. { 19, 0x945E }, /* R20 - Clock Rates 0 */
  87. { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
  88. { 22, 0x0006 }, /* R22 - Clock Rates 2 */
  89. { 24, 0x0050 }, /* R24 - Audio Interface 0 */
  90. { 25, 0x000A }, /* R25 - Audio Interface 1 */
  91. { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
  92. { 27, 0x0040 }, /* R27 - Audio Interface 3 */
  93. { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
  94. { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
  95. { 32, 0x0000 }, /* R32 - DAC Digital 0 */
  96. { 33, 0x0008 }, /* R33 - DAC Digital 1 */
  97. { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
  98. { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
  99. { 38, 0x0010 }, /* R38 - ADC Digital 0 */
  100. { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
  101. { 40, 0x01AF }, /* R40 - DRC 0 */
  102. { 41, 0x3248 }, /* R41 - DRC 1 */
  103. { 42, 0x0000 }, /* R42 - DRC 2 */
  104. { 43, 0x0000 }, /* R43 - DRC 3 */
  105. { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
  106. { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
  107. { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
  108. { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
  109. { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
  110. { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
  111. { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
  112. { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
  113. { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
  114. { 67, 0x0000 }, /* R67 - DC Servo 0 */
  115. { 69, 0xAAAA }, /* R69 - DC Servo 2 */
  116. { 71, 0xAAAA }, /* R71 - DC Servo 4 */
  117. { 72, 0xAAAA }, /* R72 - DC Servo 5 */
  118. { 90, 0x0000 }, /* R90 - Analogue HP 0 */
  119. { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
  120. { 98, 0x0000 }, /* R98 - Charge Pump 0 */
  121. { 104, 0x0004 }, /* R104 - Class W 0 */
  122. { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
  123. { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
  124. { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
  125. { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
  126. { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
  127. { 116, 0x0000 }, /* R116 - FLL Control 1 */
  128. { 117, 0x0007 }, /* R117 - FLL Control 2 */
  129. { 118, 0x0000 }, /* R118 - FLL Control 3 */
  130. { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
  131. { 120, 0x0004 }, /* R120 - FLL Control 5 */
  132. { 121, 0x0014 }, /* R121 - GPIO Control 1 */
  133. { 122, 0x0010 }, /* R122 - GPIO Control 2 */
  134. { 123, 0x0010 }, /* R123 - GPIO Control 3 */
  135. { 124, 0x0000 }, /* R124 - GPIO Control 4 */
  136. { 126, 0x0000 }, /* R126 - Digital Pulls */
  137. { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
  138. { 129, 0x0000 }, /* R129 - Interrupt Polarity */
  139. { 130, 0x0000 }, /* R130 - Interrupt Debounce */
  140. { 134, 0x0000 }, /* R134 - EQ1 */
  141. { 135, 0x000C }, /* R135 - EQ2 */
  142. { 136, 0x000C }, /* R136 - EQ3 */
  143. { 137, 0x000C }, /* R137 - EQ4 */
  144. { 138, 0x000C }, /* R138 - EQ5 */
  145. { 139, 0x000C }, /* R139 - EQ6 */
  146. { 140, 0x0FCA }, /* R140 - EQ7 */
  147. { 141, 0x0400 }, /* R141 - EQ8 */
  148. { 142, 0x00D8 }, /* R142 - EQ9 */
  149. { 143, 0x1EB5 }, /* R143 - EQ10 */
  150. { 144, 0xF145 }, /* R144 - EQ11 */
  151. { 145, 0x0B75 }, /* R145 - EQ12 */
  152. { 146, 0x01C5 }, /* R146 - EQ13 */
  153. { 147, 0x1C58 }, /* R147 - EQ14 */
  154. { 148, 0xF373 }, /* R148 - EQ15 */
  155. { 149, 0x0A54 }, /* R149 - EQ16 */
  156. { 150, 0x0558 }, /* R150 - EQ17 */
  157. { 151, 0x168E }, /* R151 - EQ18 */
  158. { 152, 0xF829 }, /* R152 - EQ19 */
  159. { 153, 0x07AD }, /* R153 - EQ20 */
  160. { 154, 0x1103 }, /* R154 - EQ21 */
  161. { 155, 0x0564 }, /* R155 - EQ22 */
  162. { 156, 0x0559 }, /* R156 - EQ23 */
  163. { 157, 0x4000 }, /* R157 - EQ24 */
  164. { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
  165. { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
  166. { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
  167. { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
  168. };
  169. static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
  170. {
  171. switch (reg) {
  172. case WM8904_SW_RESET_AND_ID:
  173. case WM8904_REVISION:
  174. case WM8904_DC_SERVO_1:
  175. case WM8904_DC_SERVO_6:
  176. case WM8904_DC_SERVO_7:
  177. case WM8904_DC_SERVO_8:
  178. case WM8904_DC_SERVO_9:
  179. case WM8904_DC_SERVO_READBACK_0:
  180. case WM8904_INTERRUPT_STATUS:
  181. return true;
  182. default:
  183. return false;
  184. }
  185. }
  186. static bool wm8904_readable_register(struct device *dev, unsigned int reg)
  187. {
  188. switch (reg) {
  189. case WM8904_SW_RESET_AND_ID:
  190. case WM8904_REVISION:
  191. case WM8904_BIAS_CONTROL_0:
  192. case WM8904_VMID_CONTROL_0:
  193. case WM8904_MIC_BIAS_CONTROL_0:
  194. case WM8904_MIC_BIAS_CONTROL_1:
  195. case WM8904_ANALOGUE_DAC_0:
  196. case WM8904_MIC_FILTER_CONTROL:
  197. case WM8904_ANALOGUE_ADC_0:
  198. case WM8904_POWER_MANAGEMENT_0:
  199. case WM8904_POWER_MANAGEMENT_2:
  200. case WM8904_POWER_MANAGEMENT_3:
  201. case WM8904_POWER_MANAGEMENT_6:
  202. case WM8904_CLOCK_RATES_0:
  203. case WM8904_CLOCK_RATES_1:
  204. case WM8904_CLOCK_RATES_2:
  205. case WM8904_AUDIO_INTERFACE_0:
  206. case WM8904_AUDIO_INTERFACE_1:
  207. case WM8904_AUDIO_INTERFACE_2:
  208. case WM8904_AUDIO_INTERFACE_3:
  209. case WM8904_DAC_DIGITAL_VOLUME_LEFT:
  210. case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
  211. case WM8904_DAC_DIGITAL_0:
  212. case WM8904_DAC_DIGITAL_1:
  213. case WM8904_ADC_DIGITAL_VOLUME_LEFT:
  214. case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
  215. case WM8904_ADC_DIGITAL_0:
  216. case WM8904_DIGITAL_MICROPHONE_0:
  217. case WM8904_DRC_0:
  218. case WM8904_DRC_1:
  219. case WM8904_DRC_2:
  220. case WM8904_DRC_3:
  221. case WM8904_ANALOGUE_LEFT_INPUT_0:
  222. case WM8904_ANALOGUE_RIGHT_INPUT_0:
  223. case WM8904_ANALOGUE_LEFT_INPUT_1:
  224. case WM8904_ANALOGUE_RIGHT_INPUT_1:
  225. case WM8904_ANALOGUE_OUT1_LEFT:
  226. case WM8904_ANALOGUE_OUT1_RIGHT:
  227. case WM8904_ANALOGUE_OUT2_LEFT:
  228. case WM8904_ANALOGUE_OUT2_RIGHT:
  229. case WM8904_ANALOGUE_OUT12_ZC:
  230. case WM8904_DC_SERVO_0:
  231. case WM8904_DC_SERVO_1:
  232. case WM8904_DC_SERVO_2:
  233. case WM8904_DC_SERVO_4:
  234. case WM8904_DC_SERVO_5:
  235. case WM8904_DC_SERVO_6:
  236. case WM8904_DC_SERVO_7:
  237. case WM8904_DC_SERVO_8:
  238. case WM8904_DC_SERVO_9:
  239. case WM8904_DC_SERVO_READBACK_0:
  240. case WM8904_ANALOGUE_HP_0:
  241. case WM8904_ANALOGUE_LINEOUT_0:
  242. case WM8904_CHARGE_PUMP_0:
  243. case WM8904_CLASS_W_0:
  244. case WM8904_WRITE_SEQUENCER_0:
  245. case WM8904_WRITE_SEQUENCER_1:
  246. case WM8904_WRITE_SEQUENCER_2:
  247. case WM8904_WRITE_SEQUENCER_3:
  248. case WM8904_WRITE_SEQUENCER_4:
  249. case WM8904_FLL_CONTROL_1:
  250. case WM8904_FLL_CONTROL_2:
  251. case WM8904_FLL_CONTROL_3:
  252. case WM8904_FLL_CONTROL_4:
  253. case WM8904_FLL_CONTROL_5:
  254. case WM8904_GPIO_CONTROL_1:
  255. case WM8904_GPIO_CONTROL_2:
  256. case WM8904_GPIO_CONTROL_3:
  257. case WM8904_GPIO_CONTROL_4:
  258. case WM8904_DIGITAL_PULLS:
  259. case WM8904_INTERRUPT_STATUS:
  260. case WM8904_INTERRUPT_STATUS_MASK:
  261. case WM8904_INTERRUPT_POLARITY:
  262. case WM8904_INTERRUPT_DEBOUNCE:
  263. case WM8904_EQ1:
  264. case WM8904_EQ2:
  265. case WM8904_EQ3:
  266. case WM8904_EQ4:
  267. case WM8904_EQ5:
  268. case WM8904_EQ6:
  269. case WM8904_EQ7:
  270. case WM8904_EQ8:
  271. case WM8904_EQ9:
  272. case WM8904_EQ10:
  273. case WM8904_EQ11:
  274. case WM8904_EQ12:
  275. case WM8904_EQ13:
  276. case WM8904_EQ14:
  277. case WM8904_EQ15:
  278. case WM8904_EQ16:
  279. case WM8904_EQ17:
  280. case WM8904_EQ18:
  281. case WM8904_EQ19:
  282. case WM8904_EQ20:
  283. case WM8904_EQ21:
  284. case WM8904_EQ22:
  285. case WM8904_EQ23:
  286. case WM8904_EQ24:
  287. case WM8904_CONTROL_INTERFACE_TEST_1:
  288. case WM8904_ADC_TEST_0:
  289. case WM8904_ANALOGUE_OUTPUT_BIAS_0:
  290. case WM8904_FLL_NCO_TEST_0:
  291. case WM8904_FLL_NCO_TEST_1:
  292. return true;
  293. default:
  294. return true;
  295. }
  296. }
  297. static int wm8904_configure_clocking(struct snd_soc_codec *codec)
  298. {
  299. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  300. unsigned int clock0, clock2, rate;
  301. /* Gate the clock while we're updating to avoid misclocking */
  302. clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
  303. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  304. WM8904_SYSCLK_SRC, 0);
  305. /* This should be done on init() for bypass paths */
  306. switch (wm8904->sysclk_src) {
  307. case WM8904_CLK_MCLK:
  308. dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
  309. clock2 &= ~WM8904_SYSCLK_SRC;
  310. rate = wm8904->mclk_rate;
  311. /* Ensure the FLL is stopped */
  312. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  313. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  314. break;
  315. case WM8904_CLK_FLL:
  316. dev_dbg(codec->dev, "Using %dHz FLL clock\n",
  317. wm8904->fll_fout);
  318. clock2 |= WM8904_SYSCLK_SRC;
  319. rate = wm8904->fll_fout;
  320. break;
  321. default:
  322. dev_err(codec->dev, "System clock not configured\n");
  323. return -EINVAL;
  324. }
  325. /* SYSCLK shouldn't be over 13.5MHz */
  326. if (rate > 13500000) {
  327. clock0 = WM8904_MCLK_DIV;
  328. wm8904->sysclk_rate = rate / 2;
  329. } else {
  330. clock0 = 0;
  331. wm8904->sysclk_rate = rate;
  332. }
  333. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
  334. clock0);
  335. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  336. WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
  337. dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
  338. return 0;
  339. }
  340. static void wm8904_set_drc(struct snd_soc_codec *codec)
  341. {
  342. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  343. struct wm8904_pdata *pdata = wm8904->pdata;
  344. int save, i;
  345. /* Save any enables; the configuration should clear them. */
  346. save = snd_soc_read(codec, WM8904_DRC_0);
  347. for (i = 0; i < WM8904_DRC_REGS; i++)
  348. snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
  349. pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
  350. /* Reenable the DRC */
  351. snd_soc_update_bits(codec, WM8904_DRC_0,
  352. WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
  353. }
  354. static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
  355. struct snd_ctl_elem_value *ucontrol)
  356. {
  357. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  358. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  359. struct wm8904_pdata *pdata = wm8904->pdata;
  360. int value = ucontrol->value.integer.value[0];
  361. if (value >= pdata->num_drc_cfgs)
  362. return -EINVAL;
  363. wm8904->drc_cfg = value;
  364. wm8904_set_drc(codec);
  365. return 0;
  366. }
  367. static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
  368. struct snd_ctl_elem_value *ucontrol)
  369. {
  370. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  371. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  372. ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
  373. return 0;
  374. }
  375. static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
  376. {
  377. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  378. struct wm8904_pdata *pdata = wm8904->pdata;
  379. int best, best_val, save, i, cfg;
  380. if (!pdata || !wm8904->num_retune_mobile_texts)
  381. return;
  382. /* Find the version of the currently selected configuration
  383. * with the nearest sample rate. */
  384. cfg = wm8904->retune_mobile_cfg;
  385. best = 0;
  386. best_val = INT_MAX;
  387. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  388. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  389. wm8904->retune_mobile_texts[cfg]) == 0 &&
  390. abs(pdata->retune_mobile_cfgs[i].rate
  391. - wm8904->fs) < best_val) {
  392. best = i;
  393. best_val = abs(pdata->retune_mobile_cfgs[i].rate
  394. - wm8904->fs);
  395. }
  396. }
  397. dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
  398. pdata->retune_mobile_cfgs[best].name,
  399. pdata->retune_mobile_cfgs[best].rate,
  400. wm8904->fs);
  401. /* The EQ will be disabled while reconfiguring it, remember the
  402. * current configuration.
  403. */
  404. save = snd_soc_read(codec, WM8904_EQ1);
  405. for (i = 0; i < WM8904_EQ_REGS; i++)
  406. snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
  407. pdata->retune_mobile_cfgs[best].regs[i]);
  408. snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
  409. }
  410. static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  411. struct snd_ctl_elem_value *ucontrol)
  412. {
  413. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  414. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  415. struct wm8904_pdata *pdata = wm8904->pdata;
  416. int value = ucontrol->value.integer.value[0];
  417. if (value >= pdata->num_retune_mobile_cfgs)
  418. return -EINVAL;
  419. wm8904->retune_mobile_cfg = value;
  420. wm8904_set_retune_mobile(codec);
  421. return 0;
  422. }
  423. static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
  424. struct snd_ctl_elem_value *ucontrol)
  425. {
  426. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  427. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  428. ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
  429. return 0;
  430. }
  431. static int deemph_settings[] = { 0, 32000, 44100, 48000 };
  432. static int wm8904_set_deemph(struct snd_soc_codec *codec)
  433. {
  434. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  435. int val, i, best;
  436. /* If we're using deemphasis select the nearest available sample
  437. * rate.
  438. */
  439. if (wm8904->deemph) {
  440. best = 1;
  441. for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
  442. if (abs(deemph_settings[i] - wm8904->fs) <
  443. abs(deemph_settings[best] - wm8904->fs))
  444. best = i;
  445. }
  446. val = best << WM8904_DEEMPH_SHIFT;
  447. } else {
  448. val = 0;
  449. }
  450. dev_dbg(codec->dev, "Set deemphasis %d\n", val);
  451. return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
  452. WM8904_DEEMPH_MASK, val);
  453. }
  454. static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
  455. struct snd_ctl_elem_value *ucontrol)
  456. {
  457. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  458. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  459. ucontrol->value.enumerated.item[0] = wm8904->deemph;
  460. return 0;
  461. }
  462. static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
  463. struct snd_ctl_elem_value *ucontrol)
  464. {
  465. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  466. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  467. int deemph = ucontrol->value.enumerated.item[0];
  468. if (deemph > 1)
  469. return -EINVAL;
  470. wm8904->deemph = deemph;
  471. return wm8904_set_deemph(codec);
  472. }
  473. static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
  474. static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
  475. static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
  476. static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
  477. static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
  478. static const char *input_mode_text[] = {
  479. "Single-Ended", "Differential Line", "Differential Mic"
  480. };
  481. static const struct soc_enum lin_mode =
  482. SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
  483. static const struct soc_enum rin_mode =
  484. SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
  485. static const char *hpf_mode_text[] = {
  486. "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
  487. };
  488. static const struct soc_enum hpf_mode =
  489. SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
  490. static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
  491. struct snd_ctl_elem_value *ucontrol)
  492. {
  493. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  494. unsigned int val;
  495. int ret;
  496. ret = snd_soc_put_volsw(kcontrol, ucontrol);
  497. if (ret < 0)
  498. return ret;
  499. if (ucontrol->value.integer.value[0])
  500. val = 0;
  501. else
  502. val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
  503. snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
  504. WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
  505. val);
  506. return ret;
  507. }
  508. static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
  509. SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
  510. WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
  511. SOC_ENUM("Left Caputure Mode", lin_mode),
  512. SOC_ENUM("Right Capture Mode", rin_mode),
  513. /* No TLV since it depends on mode */
  514. SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
  515. WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
  516. SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
  517. WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
  518. SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
  519. SOC_ENUM("High Pass Filter Mode", hpf_mode),
  520. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  521. .name = "ADC 128x OSR Switch",
  522. .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,
  523. .put = wm8904_adc_osr_put,
  524. .private_value = SOC_SINGLE_VALUE(WM8904_ANALOGUE_ADC_0, 0, 1, 0),
  525. },
  526. };
  527. static const char *drc_path_text[] = {
  528. "ADC", "DAC"
  529. };
  530. static const struct soc_enum drc_path =
  531. SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
  532. static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
  533. SOC_SINGLE_TLV("Digital Playback Boost Volume",
  534. WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
  535. SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
  536. WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
  537. SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
  538. WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
  539. SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
  540. WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
  541. SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
  542. WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
  543. SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
  544. WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
  545. SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
  546. WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
  547. SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
  548. WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
  549. SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
  550. SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
  551. SOC_ENUM("DRC Path", drc_path),
  552. SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
  553. SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
  554. wm8904_get_deemph, wm8904_put_deemph),
  555. };
  556. static const struct snd_kcontrol_new wm8904_snd_controls[] = {
  557. SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
  558. sidetone_tlv),
  559. };
  560. static const struct snd_kcontrol_new wm8904_eq_controls[] = {
  561. SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
  562. SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
  563. SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
  564. SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
  565. SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
  566. };
  567. static int cp_event(struct snd_soc_dapm_widget *w,
  568. struct snd_kcontrol *kcontrol, int event)
  569. {
  570. BUG_ON(event != SND_SOC_DAPM_POST_PMU);
  571. /* Maximum startup time */
  572. udelay(500);
  573. return 0;
  574. }
  575. static int sysclk_event(struct snd_soc_dapm_widget *w,
  576. struct snd_kcontrol *kcontrol, int event)
  577. {
  578. struct snd_soc_codec *codec = w->codec;
  579. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  580. switch (event) {
  581. case SND_SOC_DAPM_PRE_PMU:
  582. /* If we're using the FLL then we only start it when
  583. * required; we assume that the configuration has been
  584. * done previously and all we need to do is kick it
  585. * off.
  586. */
  587. switch (wm8904->sysclk_src) {
  588. case WM8904_CLK_FLL:
  589. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  590. WM8904_FLL_OSC_ENA,
  591. WM8904_FLL_OSC_ENA);
  592. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  593. WM8904_FLL_ENA,
  594. WM8904_FLL_ENA);
  595. break;
  596. default:
  597. break;
  598. }
  599. break;
  600. case SND_SOC_DAPM_POST_PMD:
  601. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  602. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  603. break;
  604. }
  605. return 0;
  606. }
  607. static int out_pga_event(struct snd_soc_dapm_widget *w,
  608. struct snd_kcontrol *kcontrol, int event)
  609. {
  610. struct snd_soc_codec *codec = w->codec;
  611. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  612. int reg, val;
  613. int dcs_mask;
  614. int dcs_l, dcs_r;
  615. int dcs_l_reg, dcs_r_reg;
  616. int timeout;
  617. int pwr_reg;
  618. /* This code is shared between HP and LINEOUT; we do all our
  619. * power management in stereo pairs to avoid latency issues so
  620. * we reuse shift to identify which rather than strcmp() the
  621. * name. */
  622. reg = w->shift;
  623. switch (reg) {
  624. case WM8904_ANALOGUE_HP_0:
  625. pwr_reg = WM8904_POWER_MANAGEMENT_2;
  626. dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
  627. dcs_r_reg = WM8904_DC_SERVO_8;
  628. dcs_l_reg = WM8904_DC_SERVO_9;
  629. dcs_l = 0;
  630. dcs_r = 1;
  631. break;
  632. case WM8904_ANALOGUE_LINEOUT_0:
  633. pwr_reg = WM8904_POWER_MANAGEMENT_3;
  634. dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
  635. dcs_r_reg = WM8904_DC_SERVO_6;
  636. dcs_l_reg = WM8904_DC_SERVO_7;
  637. dcs_l = 2;
  638. dcs_r = 3;
  639. break;
  640. default:
  641. BUG();
  642. return -EINVAL;
  643. }
  644. switch (event) {
  645. case SND_SOC_DAPM_PRE_PMU:
  646. /* Power on the PGAs */
  647. snd_soc_update_bits(codec, pwr_reg,
  648. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
  649. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
  650. /* Power on the amplifier */
  651. snd_soc_update_bits(codec, reg,
  652. WM8904_HPL_ENA | WM8904_HPR_ENA,
  653. WM8904_HPL_ENA | WM8904_HPR_ENA);
  654. /* Enable the first stage */
  655. snd_soc_update_bits(codec, reg,
  656. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
  657. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
  658. /* Power up the DC servo */
  659. snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
  660. dcs_mask, dcs_mask);
  661. /* Either calibrate the DC servo or restore cached state
  662. * if we have that.
  663. */
  664. if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
  665. dev_dbg(codec->dev, "Restoring DC servo state\n");
  666. snd_soc_write(codec, dcs_l_reg,
  667. wm8904->dcs_state[dcs_l]);
  668. snd_soc_write(codec, dcs_r_reg,
  669. wm8904->dcs_state[dcs_r]);
  670. snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
  671. timeout = 20;
  672. } else {
  673. dev_dbg(codec->dev, "Calibrating DC servo\n");
  674. snd_soc_write(codec, WM8904_DC_SERVO_1,
  675. dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
  676. timeout = 500;
  677. }
  678. /* Wait for DC servo to complete */
  679. dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
  680. do {
  681. val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
  682. if ((val & dcs_mask) == dcs_mask)
  683. break;
  684. msleep(1);
  685. } while (--timeout);
  686. if ((val & dcs_mask) != dcs_mask)
  687. dev_warn(codec->dev, "DC servo timed out\n");
  688. else
  689. dev_dbg(codec->dev, "DC servo ready\n");
  690. /* Enable the output stage */
  691. snd_soc_update_bits(codec, reg,
  692. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
  693. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
  694. break;
  695. case SND_SOC_DAPM_POST_PMU:
  696. /* Unshort the output itself */
  697. snd_soc_update_bits(codec, reg,
  698. WM8904_HPL_RMV_SHORT |
  699. WM8904_HPR_RMV_SHORT,
  700. WM8904_HPL_RMV_SHORT |
  701. WM8904_HPR_RMV_SHORT);
  702. break;
  703. case SND_SOC_DAPM_PRE_PMD:
  704. /* Short the output */
  705. snd_soc_update_bits(codec, reg,
  706. WM8904_HPL_RMV_SHORT |
  707. WM8904_HPR_RMV_SHORT, 0);
  708. break;
  709. case SND_SOC_DAPM_POST_PMD:
  710. /* Cache the DC servo configuration; this will be
  711. * invalidated if we change the configuration. */
  712. wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
  713. wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
  714. snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
  715. dcs_mask, 0);
  716. /* Disable the amplifier input and output stages */
  717. snd_soc_update_bits(codec, reg,
  718. WM8904_HPL_ENA | WM8904_HPR_ENA |
  719. WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
  720. WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
  721. 0);
  722. /* PGAs too */
  723. snd_soc_update_bits(codec, pwr_reg,
  724. WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
  725. 0);
  726. break;
  727. }
  728. return 0;
  729. }
  730. static const char *lin_text[] = {
  731. "IN1L", "IN2L", "IN3L"
  732. };
  733. static const struct soc_enum lin_enum =
  734. SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
  735. static const struct snd_kcontrol_new lin_mux =
  736. SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
  737. static const struct soc_enum lin_inv_enum =
  738. SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
  739. static const struct snd_kcontrol_new lin_inv_mux =
  740. SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
  741. static const char *rin_text[] = {
  742. "IN1R", "IN2R", "IN3R"
  743. };
  744. static const struct soc_enum rin_enum =
  745. SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
  746. static const struct snd_kcontrol_new rin_mux =
  747. SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
  748. static const struct soc_enum rin_inv_enum =
  749. SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
  750. static const struct snd_kcontrol_new rin_inv_mux =
  751. SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
  752. static const char *aif_text[] = {
  753. "Left", "Right"
  754. };
  755. static const struct soc_enum aifoutl_enum =
  756. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
  757. static const struct snd_kcontrol_new aifoutl_mux =
  758. SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
  759. static const struct soc_enum aifoutr_enum =
  760. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
  761. static const struct snd_kcontrol_new aifoutr_mux =
  762. SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
  763. static const struct soc_enum aifinl_enum =
  764. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
  765. static const struct snd_kcontrol_new aifinl_mux =
  766. SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
  767. static const struct soc_enum aifinr_enum =
  768. SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
  769. static const struct snd_kcontrol_new aifinr_mux =
  770. SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
  771. static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
  772. SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
  773. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  774. SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
  775. SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
  776. };
  777. static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
  778. SND_SOC_DAPM_INPUT("IN1L"),
  779. SND_SOC_DAPM_INPUT("IN1R"),
  780. SND_SOC_DAPM_INPUT("IN2L"),
  781. SND_SOC_DAPM_INPUT("IN2R"),
  782. SND_SOC_DAPM_INPUT("IN3L"),
  783. SND_SOC_DAPM_INPUT("IN3R"),
  784. SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
  785. SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
  786. SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
  787. &lin_inv_mux),
  788. SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
  789. SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
  790. &rin_inv_mux),
  791. SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
  792. NULL, 0),
  793. SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
  794. NULL, 0),
  795. SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
  796. SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
  797. SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
  798. SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
  799. SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
  800. SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
  801. };
  802. static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
  803. SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
  804. SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
  805. SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
  806. SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
  807. SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
  808. SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
  809. SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
  810. SND_SOC_DAPM_POST_PMU),
  811. SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
  812. SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  813. SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
  814. SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
  815. SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
  816. 0, NULL, 0, out_pga_event,
  817. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  818. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  819. SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
  820. 0, NULL, 0, out_pga_event,
  821. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  822. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  823. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  824. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  825. SND_SOC_DAPM_OUTPUT("LINEOUTL"),
  826. SND_SOC_DAPM_OUTPUT("LINEOUTR"),
  827. };
  828. static const char *out_mux_text[] = {
  829. "DAC", "Bypass"
  830. };
  831. static const struct soc_enum hpl_enum =
  832. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
  833. static const struct snd_kcontrol_new hpl_mux =
  834. SOC_DAPM_ENUM("HPL Mux", hpl_enum);
  835. static const struct soc_enum hpr_enum =
  836. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
  837. static const struct snd_kcontrol_new hpr_mux =
  838. SOC_DAPM_ENUM("HPR Mux", hpr_enum);
  839. static const struct soc_enum linel_enum =
  840. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
  841. static const struct snd_kcontrol_new linel_mux =
  842. SOC_DAPM_ENUM("LINEL Mux", linel_enum);
  843. static const struct soc_enum liner_enum =
  844. SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
  845. static const struct snd_kcontrol_new liner_mux =
  846. SOC_DAPM_ENUM("LINEL Mux", liner_enum);
  847. static const char *sidetone_text[] = {
  848. "None", "Left", "Right"
  849. };
  850. static const struct soc_enum dacl_sidetone_enum =
  851. SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
  852. static const struct snd_kcontrol_new dacl_sidetone_mux =
  853. SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
  854. static const struct soc_enum dacr_sidetone_enum =
  855. SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
  856. static const struct snd_kcontrol_new dacr_sidetone_mux =
  857. SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
  858. static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
  859. SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
  860. SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  861. SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
  862. SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
  863. SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
  864. SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
  865. SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
  866. SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
  867. SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
  868. };
  869. static const struct snd_soc_dapm_route core_intercon[] = {
  870. { "CLK_DSP", NULL, "SYSCLK" },
  871. { "TOCLK", NULL, "SYSCLK" },
  872. };
  873. static const struct snd_soc_dapm_route adc_intercon[] = {
  874. { "Left Capture Mux", "IN1L", "IN1L" },
  875. { "Left Capture Mux", "IN2L", "IN2L" },
  876. { "Left Capture Mux", "IN3L", "IN3L" },
  877. { "Left Capture Inverting Mux", "IN1L", "IN1L" },
  878. { "Left Capture Inverting Mux", "IN2L", "IN2L" },
  879. { "Left Capture Inverting Mux", "IN3L", "IN3L" },
  880. { "Right Capture Mux", "IN1R", "IN1R" },
  881. { "Right Capture Mux", "IN2R", "IN2R" },
  882. { "Right Capture Mux", "IN3R", "IN3R" },
  883. { "Right Capture Inverting Mux", "IN1R", "IN1R" },
  884. { "Right Capture Inverting Mux", "IN2R", "IN2R" },
  885. { "Right Capture Inverting Mux", "IN3R", "IN3R" },
  886. { "Left Capture PGA", NULL, "Left Capture Mux" },
  887. { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
  888. { "Right Capture PGA", NULL, "Right Capture Mux" },
  889. { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
  890. { "AIFOUTL", "Left", "ADCL" },
  891. { "AIFOUTL", "Right", "ADCR" },
  892. { "AIFOUTR", "Left", "ADCL" },
  893. { "AIFOUTR", "Right", "ADCR" },
  894. { "ADCL", NULL, "CLK_DSP" },
  895. { "ADCL", NULL, "Left Capture PGA" },
  896. { "ADCR", NULL, "CLK_DSP" },
  897. { "ADCR", NULL, "Right Capture PGA" },
  898. };
  899. static const struct snd_soc_dapm_route dac_intercon[] = {
  900. { "DACL", "Right", "AIFINR" },
  901. { "DACL", "Left", "AIFINL" },
  902. { "DACL", NULL, "CLK_DSP" },
  903. { "DACR", "Right", "AIFINR" },
  904. { "DACR", "Left", "AIFINL" },
  905. { "DACR", NULL, "CLK_DSP" },
  906. { "Charge pump", NULL, "SYSCLK" },
  907. { "Headphone Output", NULL, "HPL PGA" },
  908. { "Headphone Output", NULL, "HPR PGA" },
  909. { "Headphone Output", NULL, "Charge pump" },
  910. { "Headphone Output", NULL, "TOCLK" },
  911. { "Line Output", NULL, "LINEL PGA" },
  912. { "Line Output", NULL, "LINER PGA" },
  913. { "Line Output", NULL, "Charge pump" },
  914. { "Line Output", NULL, "TOCLK" },
  915. { "HPOUTL", NULL, "Headphone Output" },
  916. { "HPOUTR", NULL, "Headphone Output" },
  917. { "LINEOUTL", NULL, "Line Output" },
  918. { "LINEOUTR", NULL, "Line Output" },
  919. };
  920. static const struct snd_soc_dapm_route wm8904_intercon[] = {
  921. { "Left Sidetone", "Left", "ADCL" },
  922. { "Left Sidetone", "Right", "ADCR" },
  923. { "DACL", NULL, "Left Sidetone" },
  924. { "Right Sidetone", "Left", "ADCL" },
  925. { "Right Sidetone", "Right", "ADCR" },
  926. { "DACR", NULL, "Right Sidetone" },
  927. { "Left Bypass", NULL, "Class G" },
  928. { "Left Bypass", NULL, "Left Capture PGA" },
  929. { "Right Bypass", NULL, "Class G" },
  930. { "Right Bypass", NULL, "Right Capture PGA" },
  931. { "HPL Mux", "DAC", "DACL" },
  932. { "HPL Mux", "Bypass", "Left Bypass" },
  933. { "HPR Mux", "DAC", "DACR" },
  934. { "HPR Mux", "Bypass", "Right Bypass" },
  935. { "LINEL Mux", "DAC", "DACL" },
  936. { "LINEL Mux", "Bypass", "Left Bypass" },
  937. { "LINER Mux", "DAC", "DACR" },
  938. { "LINER Mux", "Bypass", "Right Bypass" },
  939. { "HPL PGA", NULL, "HPL Mux" },
  940. { "HPR PGA", NULL, "HPR Mux" },
  941. { "LINEL PGA", NULL, "LINEL Mux" },
  942. { "LINER PGA", NULL, "LINER Mux" },
  943. };
  944. static const struct snd_soc_dapm_route wm8912_intercon[] = {
  945. { "HPL PGA", NULL, "DACL" },
  946. { "HPR PGA", NULL, "DACR" },
  947. { "LINEL PGA", NULL, "DACL" },
  948. { "LINER PGA", NULL, "DACR" },
  949. };
  950. static int wm8904_add_widgets(struct snd_soc_codec *codec)
  951. {
  952. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  953. struct snd_soc_dapm_context *dapm = &codec->dapm;
  954. snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
  955. ARRAY_SIZE(wm8904_core_dapm_widgets));
  956. snd_soc_dapm_add_routes(dapm, core_intercon,
  957. ARRAY_SIZE(core_intercon));
  958. switch (wm8904->devtype) {
  959. case WM8904:
  960. snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
  961. ARRAY_SIZE(wm8904_adc_snd_controls));
  962. snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
  963. ARRAY_SIZE(wm8904_dac_snd_controls));
  964. snd_soc_add_codec_controls(codec, wm8904_snd_controls,
  965. ARRAY_SIZE(wm8904_snd_controls));
  966. snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
  967. ARRAY_SIZE(wm8904_adc_dapm_widgets));
  968. snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
  969. ARRAY_SIZE(wm8904_dac_dapm_widgets));
  970. snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
  971. ARRAY_SIZE(wm8904_dapm_widgets));
  972. snd_soc_dapm_add_routes(dapm, core_intercon,
  973. ARRAY_SIZE(core_intercon));
  974. snd_soc_dapm_add_routes(dapm, adc_intercon,
  975. ARRAY_SIZE(adc_intercon));
  976. snd_soc_dapm_add_routes(dapm, dac_intercon,
  977. ARRAY_SIZE(dac_intercon));
  978. snd_soc_dapm_add_routes(dapm, wm8904_intercon,
  979. ARRAY_SIZE(wm8904_intercon));
  980. break;
  981. case WM8912:
  982. snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
  983. ARRAY_SIZE(wm8904_dac_snd_controls));
  984. snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
  985. ARRAY_SIZE(wm8904_dac_dapm_widgets));
  986. snd_soc_dapm_add_routes(dapm, dac_intercon,
  987. ARRAY_SIZE(dac_intercon));
  988. snd_soc_dapm_add_routes(dapm, wm8912_intercon,
  989. ARRAY_SIZE(wm8912_intercon));
  990. break;
  991. }
  992. snd_soc_dapm_new_widgets(dapm);
  993. return 0;
  994. }
  995. static struct {
  996. int ratio;
  997. unsigned int clk_sys_rate;
  998. } clk_sys_rates[] = {
  999. { 64, 0 },
  1000. { 128, 1 },
  1001. { 192, 2 },
  1002. { 256, 3 },
  1003. { 384, 4 },
  1004. { 512, 5 },
  1005. { 786, 6 },
  1006. { 1024, 7 },
  1007. { 1408, 8 },
  1008. { 1536, 9 },
  1009. };
  1010. static struct {
  1011. int rate;
  1012. int sample_rate;
  1013. } sample_rates[] = {
  1014. { 8000, 0 },
  1015. { 11025, 1 },
  1016. { 12000, 1 },
  1017. { 16000, 2 },
  1018. { 22050, 3 },
  1019. { 24000, 3 },
  1020. { 32000, 4 },
  1021. { 44100, 5 },
  1022. { 48000, 5 },
  1023. };
  1024. static struct {
  1025. int div; /* *10 due to .5s */
  1026. int bclk_div;
  1027. } bclk_divs[] = {
  1028. { 10, 0 },
  1029. { 15, 1 },
  1030. { 20, 2 },
  1031. { 30, 3 },
  1032. { 40, 4 },
  1033. { 50, 5 },
  1034. { 55, 6 },
  1035. { 60, 7 },
  1036. { 80, 8 },
  1037. { 100, 9 },
  1038. { 110, 10 },
  1039. { 120, 11 },
  1040. { 160, 12 },
  1041. { 200, 13 },
  1042. { 220, 14 },
  1043. { 240, 16 },
  1044. { 200, 17 },
  1045. { 320, 18 },
  1046. { 440, 19 },
  1047. { 480, 20 },
  1048. };
  1049. static int wm8904_hw_params(struct snd_pcm_substream *substream,
  1050. struct snd_pcm_hw_params *params,
  1051. struct snd_soc_dai *dai)
  1052. {
  1053. struct snd_soc_codec *codec = dai->codec;
  1054. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1055. int ret, i, best, best_val, cur_val;
  1056. unsigned int aif1 = 0;
  1057. unsigned int aif2 = 0;
  1058. unsigned int aif3 = 0;
  1059. unsigned int clock1 = 0;
  1060. unsigned int dac_digital1 = 0;
  1061. /* What BCLK do we need? */
  1062. wm8904->fs = params_rate(params);
  1063. if (wm8904->tdm_slots) {
  1064. dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
  1065. wm8904->tdm_slots, wm8904->tdm_width);
  1066. wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
  1067. wm8904->tdm_width, 2,
  1068. wm8904->tdm_slots);
  1069. } else {
  1070. wm8904->bclk = snd_soc_params_to_bclk(params);
  1071. }
  1072. switch (params_format(params)) {
  1073. case SNDRV_PCM_FORMAT_S16_LE:
  1074. break;
  1075. case SNDRV_PCM_FORMAT_S20_3LE:
  1076. aif1 |= 0x40;
  1077. break;
  1078. case SNDRV_PCM_FORMAT_S24_LE:
  1079. aif1 |= 0x80;
  1080. break;
  1081. case SNDRV_PCM_FORMAT_S32_LE:
  1082. aif1 |= 0xc0;
  1083. break;
  1084. default:
  1085. return -EINVAL;
  1086. }
  1087. dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
  1088. ret = wm8904_configure_clocking(codec);
  1089. if (ret != 0)
  1090. return ret;
  1091. /* Select nearest CLK_SYS_RATE */
  1092. best = 0;
  1093. best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
  1094. - wm8904->fs);
  1095. for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
  1096. cur_val = abs((wm8904->sysclk_rate /
  1097. clk_sys_rates[i].ratio) - wm8904->fs);
  1098. if (cur_val < best_val) {
  1099. best = i;
  1100. best_val = cur_val;
  1101. }
  1102. }
  1103. dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
  1104. clk_sys_rates[best].ratio);
  1105. clock1 |= (clk_sys_rates[best].clk_sys_rate
  1106. << WM8904_CLK_SYS_RATE_SHIFT);
  1107. /* SAMPLE_RATE */
  1108. best = 0;
  1109. best_val = abs(wm8904->fs - sample_rates[0].rate);
  1110. for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
  1111. /* Closest match */
  1112. cur_val = abs(wm8904->fs - sample_rates[i].rate);
  1113. if (cur_val < best_val) {
  1114. best = i;
  1115. best_val = cur_val;
  1116. }
  1117. }
  1118. dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
  1119. sample_rates[best].rate);
  1120. clock1 |= (sample_rates[best].sample_rate
  1121. << WM8904_SAMPLE_RATE_SHIFT);
  1122. /* Enable sloping stopband filter for low sample rates */
  1123. if (wm8904->fs <= 24000)
  1124. dac_digital1 |= WM8904_DAC_SB_FILT;
  1125. /* BCLK_DIV */
  1126. best = 0;
  1127. best_val = INT_MAX;
  1128. for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
  1129. cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
  1130. - wm8904->bclk;
  1131. if (cur_val < 0) /* Table is sorted */
  1132. break;
  1133. if (cur_val < best_val) {
  1134. best = i;
  1135. best_val = cur_val;
  1136. }
  1137. }
  1138. wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
  1139. dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
  1140. bclk_divs[best].div, wm8904->bclk);
  1141. aif2 |= bclk_divs[best].bclk_div;
  1142. /* LRCLK is a simple fraction of BCLK */
  1143. dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
  1144. aif3 |= wm8904->bclk / wm8904->fs;
  1145. /* Apply the settings */
  1146. snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
  1147. WM8904_DAC_SB_FILT, dac_digital1);
  1148. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
  1149. WM8904_AIF_WL_MASK, aif1);
  1150. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
  1151. WM8904_BCLK_DIV_MASK, aif2);
  1152. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
  1153. WM8904_LRCLK_RATE_MASK, aif3);
  1154. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
  1155. WM8904_SAMPLE_RATE_MASK |
  1156. WM8904_CLK_SYS_RATE_MASK, clock1);
  1157. /* Update filters for the new settings */
  1158. wm8904_set_retune_mobile(codec);
  1159. wm8904_set_deemph(codec);
  1160. return 0;
  1161. }
  1162. static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
  1163. unsigned int freq, int dir)
  1164. {
  1165. struct snd_soc_codec *codec = dai->codec;
  1166. struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
  1167. switch (clk_id) {
  1168. case WM8904_CLK_MCLK:
  1169. priv->sysclk_src = clk_id;
  1170. priv->mclk_rate = freq;
  1171. break;
  1172. case WM8904_CLK_FLL:
  1173. priv->sysclk_src = clk_id;
  1174. break;
  1175. default:
  1176. return -EINVAL;
  1177. }
  1178. dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
  1179. wm8904_configure_clocking(codec);
  1180. return 0;
  1181. }
  1182. static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1183. {
  1184. struct snd_soc_codec *codec = dai->codec;
  1185. unsigned int aif1 = 0;
  1186. unsigned int aif3 = 0;
  1187. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1188. case SND_SOC_DAIFMT_CBS_CFS:
  1189. break;
  1190. case SND_SOC_DAIFMT_CBS_CFM:
  1191. aif3 |= WM8904_LRCLK_DIR;
  1192. break;
  1193. case SND_SOC_DAIFMT_CBM_CFS:
  1194. aif1 |= WM8904_BCLK_DIR;
  1195. break;
  1196. case SND_SOC_DAIFMT_CBM_CFM:
  1197. aif1 |= WM8904_BCLK_DIR;
  1198. aif3 |= WM8904_LRCLK_DIR;
  1199. break;
  1200. default:
  1201. return -EINVAL;
  1202. }
  1203. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1204. case SND_SOC_DAIFMT_DSP_B:
  1205. aif1 |= WM8904_AIF_LRCLK_INV;
  1206. case SND_SOC_DAIFMT_DSP_A:
  1207. aif1 |= 0x3;
  1208. break;
  1209. case SND_SOC_DAIFMT_I2S:
  1210. aif1 |= 0x2;
  1211. break;
  1212. case SND_SOC_DAIFMT_RIGHT_J:
  1213. break;
  1214. case SND_SOC_DAIFMT_LEFT_J:
  1215. aif1 |= 0x1;
  1216. break;
  1217. default:
  1218. return -EINVAL;
  1219. }
  1220. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1221. case SND_SOC_DAIFMT_DSP_A:
  1222. case SND_SOC_DAIFMT_DSP_B:
  1223. /* frame inversion not valid for DSP modes */
  1224. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1225. case SND_SOC_DAIFMT_NB_NF:
  1226. break;
  1227. case SND_SOC_DAIFMT_IB_NF:
  1228. aif1 |= WM8904_AIF_BCLK_INV;
  1229. break;
  1230. default:
  1231. return -EINVAL;
  1232. }
  1233. break;
  1234. case SND_SOC_DAIFMT_I2S:
  1235. case SND_SOC_DAIFMT_RIGHT_J:
  1236. case SND_SOC_DAIFMT_LEFT_J:
  1237. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1238. case SND_SOC_DAIFMT_NB_NF:
  1239. break;
  1240. case SND_SOC_DAIFMT_IB_IF:
  1241. aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
  1242. break;
  1243. case SND_SOC_DAIFMT_IB_NF:
  1244. aif1 |= WM8904_AIF_BCLK_INV;
  1245. break;
  1246. case SND_SOC_DAIFMT_NB_IF:
  1247. aif1 |= WM8904_AIF_LRCLK_INV;
  1248. break;
  1249. default:
  1250. return -EINVAL;
  1251. }
  1252. break;
  1253. default:
  1254. return -EINVAL;
  1255. }
  1256. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
  1257. WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
  1258. WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
  1259. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
  1260. WM8904_LRCLK_DIR, aif3);
  1261. return 0;
  1262. }
  1263. static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
  1264. unsigned int rx_mask, int slots, int slot_width)
  1265. {
  1266. struct snd_soc_codec *codec = dai->codec;
  1267. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1268. int aif1 = 0;
  1269. /* Don't need to validate anything if we're turning off TDM */
  1270. if (slots == 0)
  1271. goto out;
  1272. /* Note that we allow configurations we can't handle ourselves -
  1273. * for example, we can generate clocks for slots 2 and up even if
  1274. * we can't use those slots ourselves.
  1275. */
  1276. aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
  1277. switch (rx_mask) {
  1278. case 3:
  1279. break;
  1280. case 0xc:
  1281. aif1 |= WM8904_AIFADC_TDM_CHAN;
  1282. break;
  1283. default:
  1284. return -EINVAL;
  1285. }
  1286. switch (tx_mask) {
  1287. case 3:
  1288. break;
  1289. case 0xc:
  1290. aif1 |= WM8904_AIFDAC_TDM_CHAN;
  1291. break;
  1292. default:
  1293. return -EINVAL;
  1294. }
  1295. out:
  1296. wm8904->tdm_width = slot_width;
  1297. wm8904->tdm_slots = slots / 2;
  1298. snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
  1299. WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
  1300. WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
  1301. return 0;
  1302. }
  1303. struct _fll_div {
  1304. u16 fll_fratio;
  1305. u16 fll_outdiv;
  1306. u16 fll_clk_ref_div;
  1307. u16 n;
  1308. u16 k;
  1309. };
  1310. /* The size in bits of the FLL divide multiplied by 10
  1311. * to allow rounding later */
  1312. #define FIXED_FLL_SIZE ((1 << 16) * 10)
  1313. static struct {
  1314. unsigned int min;
  1315. unsigned int max;
  1316. u16 fll_fratio;
  1317. int ratio;
  1318. } fll_fratios[] = {
  1319. { 0, 64000, 4, 16 },
  1320. { 64000, 128000, 3, 8 },
  1321. { 128000, 256000, 2, 4 },
  1322. { 256000, 1000000, 1, 2 },
  1323. { 1000000, 13500000, 0, 1 },
  1324. };
  1325. static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
  1326. unsigned int Fout)
  1327. {
  1328. u64 Kpart;
  1329. unsigned int K, Ndiv, Nmod, target;
  1330. unsigned int div;
  1331. int i;
  1332. /* Fref must be <=13.5MHz */
  1333. div = 1;
  1334. fll_div->fll_clk_ref_div = 0;
  1335. while ((Fref / div) > 13500000) {
  1336. div *= 2;
  1337. fll_div->fll_clk_ref_div++;
  1338. if (div > 8) {
  1339. pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
  1340. Fref);
  1341. return -EINVAL;
  1342. }
  1343. }
  1344. pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
  1345. /* Apply the division for our remaining calculations */
  1346. Fref /= div;
  1347. /* Fvco should be 90-100MHz; don't check the upper bound */
  1348. div = 4;
  1349. while (Fout * div < 90000000) {
  1350. div++;
  1351. if (div > 64) {
  1352. pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
  1353. Fout);
  1354. return -EINVAL;
  1355. }
  1356. }
  1357. target = Fout * div;
  1358. fll_div->fll_outdiv = div - 1;
  1359. pr_debug("Fvco=%dHz\n", target);
  1360. /* Find an appropriate FLL_FRATIO and factor it out of the target */
  1361. for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
  1362. if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
  1363. fll_div->fll_fratio = fll_fratios[i].fll_fratio;
  1364. target /= fll_fratios[i].ratio;
  1365. break;
  1366. }
  1367. }
  1368. if (i == ARRAY_SIZE(fll_fratios)) {
  1369. pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
  1370. return -EINVAL;
  1371. }
  1372. /* Now, calculate N.K */
  1373. Ndiv = target / Fref;
  1374. fll_div->n = Ndiv;
  1375. Nmod = target % Fref;
  1376. pr_debug("Nmod=%d\n", Nmod);
  1377. /* Calculate fractional part - scale up so we can round. */
  1378. Kpart = FIXED_FLL_SIZE * (long long)Nmod;
  1379. do_div(Kpart, Fref);
  1380. K = Kpart & 0xFFFFFFFF;
  1381. if ((K % 10) >= 5)
  1382. K += 5;
  1383. /* Move down to proper range now rounding is done */
  1384. fll_div->k = K / 10;
  1385. pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
  1386. fll_div->n, fll_div->k,
  1387. fll_div->fll_fratio, fll_div->fll_outdiv,
  1388. fll_div->fll_clk_ref_div);
  1389. return 0;
  1390. }
  1391. static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
  1392. unsigned int Fref, unsigned int Fout)
  1393. {
  1394. struct snd_soc_codec *codec = dai->codec;
  1395. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1396. struct _fll_div fll_div;
  1397. int ret, val;
  1398. int clock2, fll1;
  1399. /* Any change? */
  1400. if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
  1401. Fout == wm8904->fll_fout)
  1402. return 0;
  1403. clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
  1404. if (Fout == 0) {
  1405. dev_dbg(codec->dev, "FLL disabled\n");
  1406. wm8904->fll_fref = 0;
  1407. wm8904->fll_fout = 0;
  1408. /* Gate SYSCLK to avoid glitches */
  1409. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  1410. WM8904_CLK_SYS_ENA, 0);
  1411. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1412. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  1413. goto out;
  1414. }
  1415. /* Validate the FLL ID */
  1416. switch (source) {
  1417. case WM8904_FLL_MCLK:
  1418. case WM8904_FLL_LRCLK:
  1419. case WM8904_FLL_BCLK:
  1420. ret = fll_factors(&fll_div, Fref, Fout);
  1421. if (ret != 0)
  1422. return ret;
  1423. break;
  1424. case WM8904_FLL_FREE_RUNNING:
  1425. dev_dbg(codec->dev, "Using free running FLL\n");
  1426. /* Force 12MHz and output/4 for now */
  1427. Fout = 12000000;
  1428. Fref = 12000000;
  1429. memset(&fll_div, 0, sizeof(fll_div));
  1430. fll_div.fll_outdiv = 3;
  1431. break;
  1432. default:
  1433. dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
  1434. return -EINVAL;
  1435. }
  1436. /* Save current state then disable the FLL and SYSCLK to avoid
  1437. * misclocking */
  1438. fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
  1439. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  1440. WM8904_CLK_SYS_ENA, 0);
  1441. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1442. WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
  1443. /* Unlock forced oscilator control to switch it on/off */
  1444. snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
  1445. WM8904_USER_KEY, WM8904_USER_KEY);
  1446. if (fll_id == WM8904_FLL_FREE_RUNNING) {
  1447. val = WM8904_FLL_FRC_NCO;
  1448. } else {
  1449. val = 0;
  1450. }
  1451. snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
  1452. val);
  1453. snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
  1454. WM8904_USER_KEY, 0);
  1455. switch (fll_id) {
  1456. case WM8904_FLL_MCLK:
  1457. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1458. WM8904_FLL_CLK_REF_SRC_MASK, 0);
  1459. break;
  1460. case WM8904_FLL_LRCLK:
  1461. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1462. WM8904_FLL_CLK_REF_SRC_MASK, 1);
  1463. break;
  1464. case WM8904_FLL_BCLK:
  1465. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1466. WM8904_FLL_CLK_REF_SRC_MASK, 2);
  1467. break;
  1468. }
  1469. if (fll_div.k)
  1470. val = WM8904_FLL_FRACN_ENA;
  1471. else
  1472. val = 0;
  1473. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1474. WM8904_FLL_FRACN_ENA, val);
  1475. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
  1476. WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
  1477. (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
  1478. (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
  1479. snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
  1480. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
  1481. fll_div.n << WM8904_FLL_N_SHIFT);
  1482. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
  1483. WM8904_FLL_CLK_REF_DIV_MASK,
  1484. fll_div.fll_clk_ref_div
  1485. << WM8904_FLL_CLK_REF_DIV_SHIFT);
  1486. dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
  1487. wm8904->fll_fref = Fref;
  1488. wm8904->fll_fout = Fout;
  1489. wm8904->fll_src = source;
  1490. /* Enable the FLL if it was previously active */
  1491. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1492. WM8904_FLL_OSC_ENA, fll1);
  1493. snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
  1494. WM8904_FLL_ENA, fll1);
  1495. out:
  1496. /* Reenable SYSCLK if it was previously active */
  1497. snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
  1498. WM8904_CLK_SYS_ENA, clock2);
  1499. return 0;
  1500. }
  1501. static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
  1502. {
  1503. struct snd_soc_codec *codec = codec_dai->codec;
  1504. int val;
  1505. if (mute)
  1506. val = WM8904_DAC_MUTE;
  1507. else
  1508. val = 0;
  1509. snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
  1510. return 0;
  1511. }
  1512. static int wm8904_set_bias_level(struct snd_soc_codec *codec,
  1513. enum snd_soc_bias_level level)
  1514. {
  1515. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1516. int ret;
  1517. switch (level) {
  1518. case SND_SOC_BIAS_ON:
  1519. break;
  1520. case SND_SOC_BIAS_PREPARE:
  1521. /* VMID resistance 2*50k */
  1522. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1523. WM8904_VMID_RES_MASK,
  1524. 0x1 << WM8904_VMID_RES_SHIFT);
  1525. /* Normal bias current */
  1526. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1527. WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
  1528. break;
  1529. case SND_SOC_BIAS_STANDBY:
  1530. if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
  1531. ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
  1532. wm8904->supplies);
  1533. if (ret != 0) {
  1534. dev_err(codec->dev,
  1535. "Failed to enable supplies: %d\n",
  1536. ret);
  1537. return ret;
  1538. }
  1539. regcache_cache_only(wm8904->regmap, false);
  1540. regcache_sync(wm8904->regmap);
  1541. /* Enable bias */
  1542. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1543. WM8904_BIAS_ENA, WM8904_BIAS_ENA);
  1544. /* Enable VMID, VMID buffering, 2*5k resistance */
  1545. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1546. WM8904_VMID_ENA |
  1547. WM8904_VMID_RES_MASK,
  1548. WM8904_VMID_ENA |
  1549. 0x3 << WM8904_VMID_RES_SHIFT);
  1550. /* Let VMID ramp */
  1551. msleep(1);
  1552. }
  1553. /* Maintain VMID with 2*250k */
  1554. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1555. WM8904_VMID_RES_MASK,
  1556. 0x2 << WM8904_VMID_RES_SHIFT);
  1557. /* Bias current *0.5 */
  1558. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1559. WM8904_ISEL_MASK, 0);
  1560. break;
  1561. case SND_SOC_BIAS_OFF:
  1562. /* Turn off VMID */
  1563. snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
  1564. WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
  1565. /* Stop bias generation */
  1566. snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
  1567. WM8904_BIAS_ENA, 0);
  1568. regcache_cache_only(wm8904->regmap, true);
  1569. regcache_mark_dirty(wm8904->regmap);
  1570. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
  1571. wm8904->supplies);
  1572. break;
  1573. }
  1574. codec->dapm.bias_level = level;
  1575. return 0;
  1576. }
  1577. #define WM8904_RATES SNDRV_PCM_RATE_8000_96000
  1578. #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  1579. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1580. static const struct snd_soc_dai_ops wm8904_dai_ops = {
  1581. .set_sysclk = wm8904_set_sysclk,
  1582. .set_fmt = wm8904_set_fmt,
  1583. .set_tdm_slot = wm8904_set_tdm_slot,
  1584. .set_pll = wm8904_set_fll,
  1585. .hw_params = wm8904_hw_params,
  1586. .digital_mute = wm8904_digital_mute,
  1587. };
  1588. static struct snd_soc_dai_driver wm8904_dai = {
  1589. .name = "wm8904-hifi",
  1590. .playback = {
  1591. .stream_name = "Playback",
  1592. .channels_min = 2,
  1593. .channels_max = 2,
  1594. .rates = WM8904_RATES,
  1595. .formats = WM8904_FORMATS,
  1596. },
  1597. .capture = {
  1598. .stream_name = "Capture",
  1599. .channels_min = 2,
  1600. .channels_max = 2,
  1601. .rates = WM8904_RATES,
  1602. .formats = WM8904_FORMATS,
  1603. },
  1604. .ops = &wm8904_dai_ops,
  1605. .symmetric_rates = 1,
  1606. };
  1607. static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
  1608. {
  1609. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1610. struct wm8904_pdata *pdata = wm8904->pdata;
  1611. struct snd_kcontrol_new control =
  1612. SOC_ENUM_EXT("EQ Mode",
  1613. wm8904->retune_mobile_enum,
  1614. wm8904_get_retune_mobile_enum,
  1615. wm8904_put_retune_mobile_enum);
  1616. int ret, i, j;
  1617. const char **t;
  1618. /* We need an array of texts for the enum API but the number
  1619. * of texts is likely to be less than the number of
  1620. * configurations due to the sample rate dependency of the
  1621. * configurations. */
  1622. wm8904->num_retune_mobile_texts = 0;
  1623. wm8904->retune_mobile_texts = NULL;
  1624. for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
  1625. for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
  1626. if (strcmp(pdata->retune_mobile_cfgs[i].name,
  1627. wm8904->retune_mobile_texts[j]) == 0)
  1628. break;
  1629. }
  1630. if (j != wm8904->num_retune_mobile_texts)
  1631. continue;
  1632. /* Expand the array... */
  1633. t = krealloc(wm8904->retune_mobile_texts,
  1634. sizeof(char *) *
  1635. (wm8904->num_retune_mobile_texts + 1),
  1636. GFP_KERNEL);
  1637. if (t == NULL)
  1638. continue;
  1639. /* ...store the new entry... */
  1640. t[wm8904->num_retune_mobile_texts] =
  1641. pdata->retune_mobile_cfgs[i].name;
  1642. /* ...and remember the new version. */
  1643. wm8904->num_retune_mobile_texts++;
  1644. wm8904->retune_mobile_texts = t;
  1645. }
  1646. dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
  1647. wm8904->num_retune_mobile_texts);
  1648. wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
  1649. wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
  1650. ret = snd_soc_add_codec_controls(codec, &control, 1);
  1651. if (ret != 0)
  1652. dev_err(codec->dev,
  1653. "Failed to add ReTune Mobile control: %d\n", ret);
  1654. }
  1655. static void wm8904_handle_pdata(struct snd_soc_codec *codec)
  1656. {
  1657. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1658. struct wm8904_pdata *pdata = wm8904->pdata;
  1659. int ret, i;
  1660. if (!pdata) {
  1661. snd_soc_add_codec_controls(codec, wm8904_eq_controls,
  1662. ARRAY_SIZE(wm8904_eq_controls));
  1663. return;
  1664. }
  1665. dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
  1666. if (pdata->num_drc_cfgs) {
  1667. struct snd_kcontrol_new control =
  1668. SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
  1669. wm8904_get_drc_enum, wm8904_put_drc_enum);
  1670. /* We need an array of texts for the enum API */
  1671. wm8904->drc_texts = kmalloc(sizeof(char *)
  1672. * pdata->num_drc_cfgs, GFP_KERNEL);
  1673. if (!wm8904->drc_texts) {
  1674. dev_err(codec->dev,
  1675. "Failed to allocate %d DRC config texts\n",
  1676. pdata->num_drc_cfgs);
  1677. return;
  1678. }
  1679. for (i = 0; i < pdata->num_drc_cfgs; i++)
  1680. wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
  1681. wm8904->drc_enum.max = pdata->num_drc_cfgs;
  1682. wm8904->drc_enum.texts = wm8904->drc_texts;
  1683. ret = snd_soc_add_codec_controls(codec, &control, 1);
  1684. if (ret != 0)
  1685. dev_err(codec->dev,
  1686. "Failed to add DRC mode control: %d\n", ret);
  1687. wm8904_set_drc(codec);
  1688. }
  1689. dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
  1690. pdata->num_retune_mobile_cfgs);
  1691. if (pdata->num_retune_mobile_cfgs)
  1692. wm8904_handle_retune_mobile_pdata(codec);
  1693. else
  1694. snd_soc_add_codec_controls(codec, wm8904_eq_controls,
  1695. ARRAY_SIZE(wm8904_eq_controls));
  1696. }
  1697. static int wm8904_probe(struct snd_soc_codec *codec)
  1698. {
  1699. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1700. int ret;
  1701. codec->control_data = wm8904->regmap;
  1702. switch (wm8904->devtype) {
  1703. case WM8904:
  1704. break;
  1705. case WM8912:
  1706. memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
  1707. break;
  1708. default:
  1709. dev_err(codec->dev, "Unknown device type %d\n",
  1710. wm8904->devtype);
  1711. return -EINVAL;
  1712. }
  1713. ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
  1714. if (ret != 0) {
  1715. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1716. return ret;
  1717. }
  1718. wm8904_handle_pdata(codec);
  1719. wm8904_add_widgets(codec);
  1720. return 0;
  1721. }
  1722. static int wm8904_remove(struct snd_soc_codec *codec)
  1723. {
  1724. struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
  1725. kfree(wm8904->retune_mobile_texts);
  1726. kfree(wm8904->drc_texts);
  1727. return 0;
  1728. }
  1729. static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
  1730. .probe = wm8904_probe,
  1731. .remove = wm8904_remove,
  1732. .set_bias_level = wm8904_set_bias_level,
  1733. .idle_bias_off = true,
  1734. };
  1735. static const struct regmap_config wm8904_regmap = {
  1736. .reg_bits = 8,
  1737. .val_bits = 16,
  1738. .max_register = WM8904_MAX_REGISTER,
  1739. .volatile_reg = wm8904_volatile_register,
  1740. .readable_reg = wm8904_readable_register,
  1741. .cache_type = REGCACHE_RBTREE,
  1742. .reg_defaults = wm8904_reg_defaults,
  1743. .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
  1744. };
  1745. static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
  1746. const struct i2c_device_id *id)
  1747. {
  1748. struct wm8904_priv *wm8904;
  1749. unsigned int val;
  1750. int ret, i;
  1751. wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
  1752. GFP_KERNEL);
  1753. if (wm8904 == NULL)
  1754. return -ENOMEM;
  1755. wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
  1756. if (IS_ERR(wm8904->regmap)) {
  1757. ret = PTR_ERR(wm8904->regmap);
  1758. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1759. ret);
  1760. return ret;
  1761. }
  1762. wm8904->devtype = id->driver_data;
  1763. i2c_set_clientdata(i2c, wm8904);
  1764. wm8904->pdata = i2c->dev.platform_data;
  1765. for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
  1766. wm8904->supplies[i].supply = wm8904_supply_names[i];
  1767. ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
  1768. wm8904->supplies);
  1769. if (ret != 0) {
  1770. dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
  1771. return ret;
  1772. }
  1773. ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
  1774. wm8904->supplies);
  1775. if (ret != 0) {
  1776. dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
  1777. return ret;
  1778. }
  1779. ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
  1780. if (ret < 0) {
  1781. dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
  1782. goto err_enable;
  1783. }
  1784. if (val != 0x8904) {
  1785. dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
  1786. ret = -EINVAL;
  1787. goto err_enable;
  1788. }
  1789. ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
  1790. if (ret < 0) {
  1791. dev_err(&i2c->dev, "Failed to read device revision: %d\n",
  1792. ret);
  1793. goto err_enable;
  1794. }
  1795. dev_info(&i2c->dev, "revision %c\n", val + 'A');
  1796. ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
  1797. if (ret < 0) {
  1798. dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
  1799. goto err_enable;
  1800. }
  1801. /* Change some default settings - latch VU and enable ZC */
  1802. regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
  1803. WM8904_ADC_VU, WM8904_ADC_VU);
  1804. regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
  1805. WM8904_ADC_VU, WM8904_ADC_VU);
  1806. regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
  1807. WM8904_DAC_VU, WM8904_DAC_VU);
  1808. regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
  1809. WM8904_DAC_VU, WM8904_DAC_VU);
  1810. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
  1811. WM8904_HPOUT_VU | WM8904_HPOUTLZC,
  1812. WM8904_HPOUT_VU | WM8904_HPOUTLZC);
  1813. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
  1814. WM8904_HPOUT_VU | WM8904_HPOUTRZC,
  1815. WM8904_HPOUT_VU | WM8904_HPOUTRZC);
  1816. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
  1817. WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
  1818. WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
  1819. regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
  1820. WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
  1821. WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
  1822. regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
  1823. WM8904_SR_MODE, 0);
  1824. /* Apply configuration from the platform data. */
  1825. if (wm8904->pdata) {
  1826. for (i = 0; i < WM8904_GPIO_REGS; i++) {
  1827. if (!wm8904->pdata->gpio_cfg[i])
  1828. continue;
  1829. regmap_update_bits(wm8904->regmap,
  1830. WM8904_GPIO_CONTROL_1 + i,
  1831. 0xffff,
  1832. wm8904->pdata->gpio_cfg[i]);
  1833. }
  1834. /* Zero is the default value for these anyway */
  1835. for (i = 0; i < WM8904_MIC_REGS; i++)
  1836. regmap_update_bits(wm8904->regmap,
  1837. WM8904_MIC_BIAS_CONTROL_0 + i,
  1838. 0xffff,
  1839. wm8904->pdata->mic_cfg[i]);
  1840. }
  1841. /* Set Class W by default - this will be managed by the Class
  1842. * G widget at runtime where bypass paths are available.
  1843. */
  1844. regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
  1845. WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
  1846. /* Use normal bias source */
  1847. regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
  1848. WM8904_POBCTRL, 0);
  1849. /* Can leave the device powered off until we need it */
  1850. regcache_cache_only(wm8904->regmap, true);
  1851. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  1852. ret = snd_soc_register_codec(&i2c->dev,
  1853. &soc_codec_dev_wm8904, &wm8904_dai, 1);
  1854. if (ret != 0)
  1855. return ret;
  1856. return 0;
  1857. err_enable:
  1858. regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
  1859. return ret;
  1860. }
  1861. static __devexit int wm8904_i2c_remove(struct i2c_client *client)
  1862. {
  1863. snd_soc_unregister_codec(&client->dev);
  1864. return 0;
  1865. }
  1866. static const struct i2c_device_id wm8904_i2c_id[] = {
  1867. { "wm8904", WM8904 },
  1868. { "wm8912", WM8912 },
  1869. { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
  1870. { }
  1871. };
  1872. MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
  1873. static struct i2c_driver wm8904_i2c_driver = {
  1874. .driver = {
  1875. .name = "wm8904",
  1876. .owner = THIS_MODULE,
  1877. },
  1878. .probe = wm8904_i2c_probe,
  1879. .remove = __devexit_p(wm8904_i2c_remove),
  1880. .id_table = wm8904_i2c_id,
  1881. };
  1882. module_i2c_driver(wm8904_i2c_driver);
  1883. MODULE_DESCRIPTION("ASoC WM8904 driver");
  1884. MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
  1885. MODULE_LICENSE("GPL");