iTCO_wdt.c 17 KB

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  1. /*
  2. * intel TCO Watchdog Driver
  3. *
  4. * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12. * provide warranty for any of this software. This material is
  13. * provided "AS-IS" and at no charge.
  14. *
  15. * The TCO watchdog is implemented in the following I/O controller hubs:
  16. * (See the intel documentation on http://developer.intel.com.)
  17. * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
  18. * document number 290687-002, 298242-027: 82801BA (ICH2)
  19. * document number 290733-003, 290739-013: 82801CA (ICH3-S)
  20. * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
  21. * document number 290744-001, 290745-025: 82801DB (ICH4)
  22. * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
  23. * document number 273599-001, 273645-002: 82801E (C-ICH)
  24. * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
  25. * document number 300641-004, 300884-013: 6300ESB
  26. * document number 301473-002, 301474-026: 82801F (ICH6)
  27. * document number 313082-001, 313075-006: 631xESB, 632xESB
  28. * document number 307013-003, 307014-024: 82801G (ICH7)
  29. * document number 322896-001, 322897-001: NM10
  30. * document number 313056-003, 313057-017: 82801H (ICH8)
  31. * document number 316972-004, 316973-012: 82801I (ICH9)
  32. * document number 319973-002, 319974-002: 82801J (ICH10)
  33. * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
  34. * document number 320066-003, 320257-008: EP80597 (IICH)
  35. * document number 324645-001, 324646-001: Cougar Point (CPT)
  36. * document number TBD : Patsburg (PBG)
  37. * document number TBD : DH89xxCC
  38. * document number TBD : Panther Point
  39. * document number TBD : Lynx Point
  40. */
  41. /*
  42. * Includes, defines, variables, module parameters, ...
  43. */
  44. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  45. /* Module and version information */
  46. #define DRV_NAME "iTCO_wdt"
  47. #define DRV_VERSION "1.10"
  48. /* Includes */
  49. #include <linux/module.h> /* For module specific items */
  50. #include <linux/moduleparam.h> /* For new moduleparam's */
  51. #include <linux/types.h> /* For standard types (like size_t) */
  52. #include <linux/errno.h> /* For the -ENODEV/... values */
  53. #include <linux/kernel.h> /* For printk/panic/... */
  54. #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
  55. (WATCHDOG_MINOR) */
  56. #include <linux/watchdog.h> /* For the watchdog specific items */
  57. #include <linux/init.h> /* For __init/__exit/... */
  58. #include <linux/fs.h> /* For file operations */
  59. #include <linux/platform_device.h> /* For platform_driver framework */
  60. #include <linux/pci.h> /* For pci functions */
  61. #include <linux/ioport.h> /* For io-port access */
  62. #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
  63. #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
  64. #include <linux/io.h> /* For inb/outb/... */
  65. #include <linux/mfd/core.h>
  66. #include <linux/mfd/lpc_ich.h>
  67. #include "iTCO_vendor.h"
  68. /* Address definitions for the TCO */
  69. /* TCO base address */
  70. #define TCOBASE (iTCO_wdt_private.tco_res->start)
  71. /* SMI Control and Enable Register */
  72. #define SMI_EN (iTCO_wdt_private.smi_res->start)
  73. #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
  74. #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
  75. #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
  76. #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
  77. #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
  78. #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
  79. #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
  80. #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
  81. #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
  82. /* internal variables */
  83. static struct { /* this is private data for the iTCO_wdt device */
  84. /* TCO version/generation */
  85. unsigned int iTCO_version;
  86. struct resource *tco_res;
  87. struct resource *smi_res;
  88. struct resource *gcs_res;
  89. /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
  90. unsigned long __iomem *gcs;
  91. /* the lock for io operations */
  92. spinlock_t io_lock;
  93. struct platform_device *dev;
  94. /* the PCI-device */
  95. struct pci_dev *pdev;
  96. } iTCO_wdt_private;
  97. /* module parameters */
  98. #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
  99. static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
  100. module_param(heartbeat, int, 0);
  101. MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
  102. "5..76 (TCO v1) or 3..614 (TCO v2), default="
  103. __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
  104. static bool nowayout = WATCHDOG_NOWAYOUT;
  105. module_param(nowayout, bool, 0);
  106. MODULE_PARM_DESC(nowayout,
  107. "Watchdog cannot be stopped once started (default="
  108. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  109. static int turn_SMI_watchdog_clear_off = 1;
  110. module_param(turn_SMI_watchdog_clear_off, int, 0);
  111. MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
  112. "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
  113. /*
  114. * Some TCO specific functions
  115. */
  116. static inline unsigned int seconds_to_ticks(int seconds)
  117. {
  118. /* the internal timer is stored as ticks which decrement
  119. * every 0.6 seconds */
  120. return (seconds * 10) / 6;
  121. }
  122. static void iTCO_wdt_set_NO_REBOOT_bit(void)
  123. {
  124. u32 val32;
  125. /* Set the NO_REBOOT bit: this disables reboots */
  126. if (iTCO_wdt_private.iTCO_version == 2) {
  127. val32 = readl(iTCO_wdt_private.gcs);
  128. val32 |= 0x00000020;
  129. writel(val32, iTCO_wdt_private.gcs);
  130. } else if (iTCO_wdt_private.iTCO_version == 1) {
  131. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  132. val32 |= 0x00000002;
  133. pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
  134. }
  135. }
  136. static int iTCO_wdt_unset_NO_REBOOT_bit(void)
  137. {
  138. int ret = 0;
  139. u32 val32;
  140. /* Unset the NO_REBOOT bit: this enables reboots */
  141. if (iTCO_wdt_private.iTCO_version == 2) {
  142. val32 = readl(iTCO_wdt_private.gcs);
  143. val32 &= 0xffffffdf;
  144. writel(val32, iTCO_wdt_private.gcs);
  145. val32 = readl(iTCO_wdt_private.gcs);
  146. if (val32 & 0x00000020)
  147. ret = -EIO;
  148. } else if (iTCO_wdt_private.iTCO_version == 1) {
  149. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  150. val32 &= 0xfffffffd;
  151. pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
  152. pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
  153. if (val32 & 0x00000002)
  154. ret = -EIO;
  155. }
  156. return ret; /* returns: 0 = OK, -EIO = Error */
  157. }
  158. static int iTCO_wdt_start(struct watchdog_device *wd_dev)
  159. {
  160. unsigned int val;
  161. spin_lock(&iTCO_wdt_private.io_lock);
  162. iTCO_vendor_pre_start(iTCO_wdt_private.smi_res, wd_dev->timeout);
  163. /* disable chipset's NO_REBOOT bit */
  164. if (iTCO_wdt_unset_NO_REBOOT_bit()) {
  165. spin_unlock(&iTCO_wdt_private.io_lock);
  166. pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
  167. return -EIO;
  168. }
  169. /* Force the timer to its reload value by writing to the TCO_RLD
  170. register */
  171. if (iTCO_wdt_private.iTCO_version == 2)
  172. outw(0x01, TCO_RLD);
  173. else if (iTCO_wdt_private.iTCO_version == 1)
  174. outb(0x01, TCO_RLD);
  175. /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
  176. val = inw(TCO1_CNT);
  177. val &= 0xf7ff;
  178. outw(val, TCO1_CNT);
  179. val = inw(TCO1_CNT);
  180. spin_unlock(&iTCO_wdt_private.io_lock);
  181. if (val & 0x0800)
  182. return -1;
  183. return 0;
  184. }
  185. static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
  186. {
  187. unsigned int val;
  188. spin_lock(&iTCO_wdt_private.io_lock);
  189. iTCO_vendor_pre_stop(iTCO_wdt_private.smi_res);
  190. /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
  191. val = inw(TCO1_CNT);
  192. val |= 0x0800;
  193. outw(val, TCO1_CNT);
  194. val = inw(TCO1_CNT);
  195. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  196. iTCO_wdt_set_NO_REBOOT_bit();
  197. spin_unlock(&iTCO_wdt_private.io_lock);
  198. if ((val & 0x0800) == 0)
  199. return -1;
  200. return 0;
  201. }
  202. static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
  203. {
  204. spin_lock(&iTCO_wdt_private.io_lock);
  205. iTCO_vendor_pre_keepalive(iTCO_wdt_private.smi_res, wd_dev->timeout);
  206. /* Reload the timer by writing to the TCO Timer Counter register */
  207. if (iTCO_wdt_private.iTCO_version == 2)
  208. outw(0x01, TCO_RLD);
  209. else if (iTCO_wdt_private.iTCO_version == 1) {
  210. /* Reset the timeout status bit so that the timer
  211. * needs to count down twice again before rebooting */
  212. outw(0x0008, TCO1_STS); /* write 1 to clear bit */
  213. outb(0x01, TCO_RLD);
  214. }
  215. spin_unlock(&iTCO_wdt_private.io_lock);
  216. return 0;
  217. }
  218. static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
  219. {
  220. unsigned int val16;
  221. unsigned char val8;
  222. unsigned int tmrval;
  223. tmrval = seconds_to_ticks(t);
  224. /* For TCO v1 the timer counts down twice before rebooting */
  225. if (iTCO_wdt_private.iTCO_version == 1)
  226. tmrval /= 2;
  227. /* from the specs: */
  228. /* "Values of 0h-3h are ignored and should not be attempted" */
  229. if (tmrval < 0x04)
  230. return -EINVAL;
  231. if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
  232. ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
  233. return -EINVAL;
  234. iTCO_vendor_pre_set_heartbeat(tmrval);
  235. /* Write new heartbeat to watchdog */
  236. if (iTCO_wdt_private.iTCO_version == 2) {
  237. spin_lock(&iTCO_wdt_private.io_lock);
  238. val16 = inw(TCOv2_TMR);
  239. val16 &= 0xfc00;
  240. val16 |= tmrval;
  241. outw(val16, TCOv2_TMR);
  242. val16 = inw(TCOv2_TMR);
  243. spin_unlock(&iTCO_wdt_private.io_lock);
  244. if ((val16 & 0x3ff) != tmrval)
  245. return -EINVAL;
  246. } else if (iTCO_wdt_private.iTCO_version == 1) {
  247. spin_lock(&iTCO_wdt_private.io_lock);
  248. val8 = inb(TCOv1_TMR);
  249. val8 &= 0xc0;
  250. val8 |= (tmrval & 0xff);
  251. outb(val8, TCOv1_TMR);
  252. val8 = inb(TCOv1_TMR);
  253. spin_unlock(&iTCO_wdt_private.io_lock);
  254. if ((val8 & 0x3f) != tmrval)
  255. return -EINVAL;
  256. }
  257. wd_dev->timeout = t;
  258. return 0;
  259. }
  260. static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
  261. {
  262. unsigned int val16;
  263. unsigned char val8;
  264. unsigned int time_left = 0;
  265. /* read the TCO Timer */
  266. if (iTCO_wdt_private.iTCO_version == 2) {
  267. spin_lock(&iTCO_wdt_private.io_lock);
  268. val16 = inw(TCO_RLD);
  269. val16 &= 0x3ff;
  270. spin_unlock(&iTCO_wdt_private.io_lock);
  271. time_left = (val16 * 6) / 10;
  272. } else if (iTCO_wdt_private.iTCO_version == 1) {
  273. spin_lock(&iTCO_wdt_private.io_lock);
  274. val8 = inb(TCO_RLD);
  275. val8 &= 0x3f;
  276. if (!(inw(TCO1_STS) & 0x0008))
  277. val8 += (inb(TCOv1_TMR) & 0x3f);
  278. spin_unlock(&iTCO_wdt_private.io_lock);
  279. time_left = (val8 * 6) / 10;
  280. }
  281. return time_left;
  282. }
  283. /*
  284. * Kernel Interfaces
  285. */
  286. static const struct watchdog_info ident = {
  287. .options = WDIOF_SETTIMEOUT |
  288. WDIOF_KEEPALIVEPING |
  289. WDIOF_MAGICCLOSE,
  290. .firmware_version = 0,
  291. .identity = DRV_NAME,
  292. };
  293. static const struct watchdog_ops iTCO_wdt_ops = {
  294. .owner = THIS_MODULE,
  295. .start = iTCO_wdt_start,
  296. .stop = iTCO_wdt_stop,
  297. .ping = iTCO_wdt_ping,
  298. .set_timeout = iTCO_wdt_set_timeout,
  299. .get_timeleft = iTCO_wdt_get_timeleft,
  300. };
  301. static struct watchdog_device iTCO_wdt_watchdog_dev = {
  302. .info = &ident,
  303. .ops = &iTCO_wdt_ops,
  304. };
  305. /*
  306. * Init & exit routines
  307. */
  308. static void __devexit iTCO_wdt_cleanup(void)
  309. {
  310. /* Stop the timer before we leave */
  311. if (!nowayout)
  312. iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
  313. /* Deregister */
  314. watchdog_unregister_device(&iTCO_wdt_watchdog_dev);
  315. /* release resources */
  316. release_region(iTCO_wdt_private.tco_res->start,
  317. resource_size(iTCO_wdt_private.tco_res));
  318. release_region(iTCO_wdt_private.smi_res->start,
  319. resource_size(iTCO_wdt_private.smi_res));
  320. if (iTCO_wdt_private.iTCO_version == 2) {
  321. iounmap(iTCO_wdt_private.gcs);
  322. release_mem_region(iTCO_wdt_private.gcs_res->start,
  323. resource_size(iTCO_wdt_private.gcs_res));
  324. }
  325. iTCO_wdt_private.tco_res = NULL;
  326. iTCO_wdt_private.smi_res = NULL;
  327. iTCO_wdt_private.gcs_res = NULL;
  328. iTCO_wdt_private.gcs = NULL;
  329. }
  330. static int __devinit iTCO_wdt_probe(struct platform_device *dev)
  331. {
  332. int ret = -ENODEV;
  333. unsigned long val32;
  334. struct lpc_ich_info *ich_info = dev->dev.platform_data;
  335. if (!ich_info)
  336. goto out;
  337. spin_lock_init(&iTCO_wdt_private.io_lock);
  338. iTCO_wdt_private.tco_res =
  339. platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_TCO);
  340. if (!iTCO_wdt_private.tco_res)
  341. goto out;
  342. iTCO_wdt_private.smi_res =
  343. platform_get_resource(dev, IORESOURCE_IO, ICH_RES_IO_SMI);
  344. if (!iTCO_wdt_private.smi_res)
  345. goto out;
  346. iTCO_wdt_private.iTCO_version = ich_info->iTCO_version;
  347. iTCO_wdt_private.dev = dev;
  348. iTCO_wdt_private.pdev = to_pci_dev(dev->dev.parent);
  349. /*
  350. * Get the Memory-Mapped GCS register, we need it for the
  351. * NO_REBOOT flag (TCO v2).
  352. */
  353. if (iTCO_wdt_private.iTCO_version == 2) {
  354. iTCO_wdt_private.gcs_res = platform_get_resource(dev,
  355. IORESOURCE_MEM,
  356. ICH_RES_MEM_GCS);
  357. if (!iTCO_wdt_private.gcs_res)
  358. goto out;
  359. if (!request_mem_region(iTCO_wdt_private.gcs_res->start,
  360. resource_size(iTCO_wdt_private.gcs_res), dev->name)) {
  361. ret = -EBUSY;
  362. goto out;
  363. }
  364. iTCO_wdt_private.gcs = ioremap(iTCO_wdt_private.gcs_res->start,
  365. resource_size(iTCO_wdt_private.gcs_res));
  366. if (!iTCO_wdt_private.gcs) {
  367. ret = -EIO;
  368. goto unreg_gcs;
  369. }
  370. }
  371. /* Check chipset's NO_REBOOT bit */
  372. if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
  373. pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
  374. ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
  375. goto unmap_gcs;
  376. }
  377. /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
  378. iTCO_wdt_set_NO_REBOOT_bit();
  379. /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
  380. if (!request_region(iTCO_wdt_private.smi_res->start,
  381. resource_size(iTCO_wdt_private.smi_res), dev->name)) {
  382. pr_err("I/O address 0x%04llx already in use, device disabled\n",
  383. (u64)SMI_EN);
  384. ret = -EBUSY;
  385. goto unmap_gcs;
  386. }
  387. if (turn_SMI_watchdog_clear_off >= iTCO_wdt_private.iTCO_version) {
  388. /*
  389. * Bit 13: TCO_EN -> 0
  390. * Disables TCO logic generating an SMI#
  391. */
  392. val32 = inl(SMI_EN);
  393. val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
  394. outl(val32, SMI_EN);
  395. }
  396. if (!request_region(iTCO_wdt_private.tco_res->start,
  397. resource_size(iTCO_wdt_private.tco_res), dev->name)) {
  398. pr_err("I/O address 0x%04llx already in use, device disabled\n",
  399. (u64)TCOBASE);
  400. ret = -EBUSY;
  401. goto unreg_smi;
  402. }
  403. pr_info("Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
  404. ich_info->name, ich_info->iTCO_version, (u64)TCOBASE);
  405. /* Clear out the (probably old) status */
  406. outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
  407. outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
  408. outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
  409. iTCO_wdt_watchdog_dev.bootstatus = 0;
  410. iTCO_wdt_watchdog_dev.timeout = WATCHDOG_TIMEOUT;
  411. watchdog_set_nowayout(&iTCO_wdt_watchdog_dev, nowayout);
  412. iTCO_wdt_watchdog_dev.parent = dev->dev.parent;
  413. /* Make sure the watchdog is not running */
  414. iTCO_wdt_stop(&iTCO_wdt_watchdog_dev);
  415. /* Check that the heartbeat value is within it's range;
  416. if not reset to the default */
  417. if (iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, heartbeat)) {
  418. iTCO_wdt_set_timeout(&iTCO_wdt_watchdog_dev, WATCHDOG_TIMEOUT);
  419. pr_info("timeout value out of range, using %d\n",
  420. WATCHDOG_TIMEOUT);
  421. }
  422. ret = watchdog_register_device(&iTCO_wdt_watchdog_dev);
  423. if (ret != 0) {
  424. pr_err("cannot register watchdog device (err=%d)\n", ret);
  425. goto unreg_tco;
  426. }
  427. pr_info("initialized. heartbeat=%d sec (nowayout=%d)\n",
  428. heartbeat, nowayout);
  429. return 0;
  430. unreg_tco:
  431. release_region(iTCO_wdt_private.tco_res->start,
  432. resource_size(iTCO_wdt_private.tco_res));
  433. unreg_smi:
  434. release_region(iTCO_wdt_private.smi_res->start,
  435. resource_size(iTCO_wdt_private.smi_res));
  436. unmap_gcs:
  437. if (iTCO_wdt_private.iTCO_version == 2)
  438. iounmap(iTCO_wdt_private.gcs);
  439. unreg_gcs:
  440. if (iTCO_wdt_private.iTCO_version == 2)
  441. release_mem_region(iTCO_wdt_private.gcs_res->start,
  442. resource_size(iTCO_wdt_private.gcs_res));
  443. out:
  444. iTCO_wdt_private.tco_res = NULL;
  445. iTCO_wdt_private.smi_res = NULL;
  446. iTCO_wdt_private.gcs_res = NULL;
  447. iTCO_wdt_private.gcs = NULL;
  448. return ret;
  449. }
  450. static int __devexit iTCO_wdt_remove(struct platform_device *dev)
  451. {
  452. if (iTCO_wdt_private.tco_res || iTCO_wdt_private.smi_res)
  453. iTCO_wdt_cleanup();
  454. return 0;
  455. }
  456. static void iTCO_wdt_shutdown(struct platform_device *dev)
  457. {
  458. iTCO_wdt_stop(NULL);
  459. }
  460. static struct platform_driver iTCO_wdt_driver = {
  461. .probe = iTCO_wdt_probe,
  462. .remove = __devexit_p(iTCO_wdt_remove),
  463. .shutdown = iTCO_wdt_shutdown,
  464. .driver = {
  465. .owner = THIS_MODULE,
  466. .name = DRV_NAME,
  467. },
  468. };
  469. static int __init iTCO_wdt_init_module(void)
  470. {
  471. int err;
  472. pr_info("Intel TCO WatchDog Timer Driver v%s\n", DRV_VERSION);
  473. err = platform_driver_register(&iTCO_wdt_driver);
  474. if (err)
  475. return err;
  476. return 0;
  477. }
  478. static void __exit iTCO_wdt_cleanup_module(void)
  479. {
  480. platform_driver_unregister(&iTCO_wdt_driver);
  481. pr_info("Watchdog Module Unloaded\n");
  482. }
  483. module_init(iTCO_wdt_init_module);
  484. module_exit(iTCO_wdt_cleanup_module);
  485. MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
  486. MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
  487. MODULE_VERSION(DRV_VERSION);
  488. MODULE_LICENSE("GPL");
  489. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  490. MODULE_ALIAS("platform:" DRV_NAME);