sh_mipi_dsi.c 15 KB

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  1. /*
  2. * Renesas SH-mobile MIPI DSI support
  3. *
  4. * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. *
  6. * This is free software; you can redistribute it and/or modify
  7. * it under the terms of version 2 of the GNU General Public License as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/bitmap.h>
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/slab.h>
  18. #include <linux/string.h>
  19. #include <linux/types.h>
  20. #include <linux/module.h>
  21. #include <video/mipi_display.h>
  22. #include <video/sh_mipi_dsi.h>
  23. #include <video/sh_mobile_lcdc.h>
  24. #include "sh_mobile_lcdcfb.h"
  25. #define SYSCTRL 0x0000
  26. #define SYSCONF 0x0004
  27. #define TIMSET 0x0008
  28. #define RESREQSET0 0x0018
  29. #define RESREQSET1 0x001c
  30. #define HSTTOVSET 0x0020
  31. #define LPRTOVSET 0x0024
  32. #define TATOVSET 0x0028
  33. #define PRTOVSET 0x002c
  34. #define DSICTRL 0x0030
  35. #define DSIINTE 0x0060
  36. #define PHYCTRL 0x0070
  37. /* relative to linkbase */
  38. #define DTCTR 0x0000
  39. #define VMCTR1 0x0020
  40. #define VMCTR2 0x0024
  41. #define VMLEN1 0x0028
  42. #define VMLEN2 0x002c
  43. #define CMTSRTREQ 0x0070
  44. #define CMTSRTCTR 0x00d0
  45. /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
  46. #define MAX_SH_MIPI_DSI 2
  47. struct sh_mipi {
  48. struct sh_mobile_lcdc_entity entity;
  49. void __iomem *base;
  50. void __iomem *linkbase;
  51. struct clk *dsit_clk;
  52. struct platform_device *pdev;
  53. };
  54. #define to_sh_mipi(e) container_of(e, struct sh_mipi, entity)
  55. static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
  56. /* Protect the above array */
  57. static DEFINE_MUTEX(array_lock);
  58. static struct sh_mipi *sh_mipi_by_handle(int handle)
  59. {
  60. if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
  61. return NULL;
  62. return mipi_dsi[handle];
  63. }
  64. static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
  65. u8 cmd, u8 param)
  66. {
  67. u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
  68. int cnt = 100;
  69. /* transmit a short packet to LCD panel */
  70. iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
  71. iowrite32(1, mipi->linkbase + CMTSRTREQ);
  72. while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
  73. udelay(1);
  74. return cnt ? 0 : -ETIMEDOUT;
  75. }
  76. #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
  77. -EINVAL : (c) - 1)
  78. static int sh_mipi_dcs(int handle, u8 cmd)
  79. {
  80. struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
  81. if (!mipi)
  82. return -ENODEV;
  83. return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
  84. }
  85. static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
  86. {
  87. struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
  88. if (!mipi)
  89. return -ENODEV;
  90. return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
  91. param);
  92. }
  93. static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
  94. {
  95. /*
  96. * enable LCDC data tx, transition to LPS after completion of each HS
  97. * packet
  98. */
  99. iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
  100. }
  101. static void sh_mipi_shutdown(struct platform_device *pdev)
  102. {
  103. struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
  104. sh_mipi_dsi_enable(mipi, false);
  105. }
  106. static int sh_mipi_setup(struct sh_mipi *mipi, struct sh_mipi_dsi_info *pdata)
  107. {
  108. void __iomem *base = mipi->base;
  109. struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
  110. u32 pctype, datatype, pixfmt, linelength, vmctr2;
  111. u32 tmp, top, bottom, delay, div;
  112. bool yuv;
  113. int bpp;
  114. /*
  115. * Select data format. MIPI DSI is not hot-pluggable, so, we just use
  116. * the default videomode. If this ever becomes a problem, We'll have to
  117. * move this to mipi_display_on() above and use info->var.xres
  118. */
  119. switch (pdata->data_format) {
  120. case MIPI_RGB888:
  121. pctype = 0;
  122. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  123. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  124. linelength = ch->lcd_modes[0].xres * 3;
  125. yuv = false;
  126. break;
  127. case MIPI_RGB565:
  128. pctype = 1;
  129. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  130. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  131. linelength = ch->lcd_modes[0].xres * 2;
  132. yuv = false;
  133. break;
  134. case MIPI_RGB666_LP:
  135. pctype = 2;
  136. datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  137. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  138. linelength = ch->lcd_modes[0].xres * 3;
  139. yuv = false;
  140. break;
  141. case MIPI_RGB666:
  142. pctype = 3;
  143. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  144. pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
  145. linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
  146. yuv = false;
  147. break;
  148. case MIPI_BGR888:
  149. pctype = 8;
  150. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  151. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  152. linelength = ch->lcd_modes[0].xres * 3;
  153. yuv = false;
  154. break;
  155. case MIPI_BGR565:
  156. pctype = 9;
  157. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  158. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  159. linelength = ch->lcd_modes[0].xres * 2;
  160. yuv = false;
  161. break;
  162. case MIPI_BGR666_LP:
  163. pctype = 0xa;
  164. datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  165. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  166. linelength = ch->lcd_modes[0].xres * 3;
  167. yuv = false;
  168. break;
  169. case MIPI_BGR666:
  170. pctype = 0xb;
  171. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  172. pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
  173. linelength = (ch->lcd_modes[0].xres * 18 + 7) / 8;
  174. yuv = false;
  175. break;
  176. case MIPI_YUYV:
  177. pctype = 4;
  178. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
  179. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  180. linelength = ch->lcd_modes[0].xres * 2;
  181. yuv = true;
  182. break;
  183. case MIPI_UYVY:
  184. pctype = 5;
  185. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
  186. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  187. linelength = ch->lcd_modes[0].xres * 2;
  188. yuv = true;
  189. break;
  190. case MIPI_YUV420_L:
  191. pctype = 6;
  192. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
  193. pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
  194. linelength = (ch->lcd_modes[0].xres * 12 + 7) / 8;
  195. yuv = true;
  196. break;
  197. case MIPI_YUV420:
  198. pctype = 7;
  199. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
  200. pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
  201. /* Length of U/V line */
  202. linelength = (ch->lcd_modes[0].xres + 1) / 2;
  203. yuv = true;
  204. break;
  205. default:
  206. return -EINVAL;
  207. }
  208. if ((yuv && ch->interface_type != YUV422) ||
  209. (!yuv && ch->interface_type != RGB24))
  210. return -EINVAL;
  211. if (!pdata->lane)
  212. return -EINVAL;
  213. /* reset DSI link */
  214. iowrite32(0x00000001, base + SYSCTRL);
  215. /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
  216. udelay(50);
  217. iowrite32(0x00000000, base + SYSCTRL);
  218. /* setup DSI link */
  219. /*
  220. * T_wakeup = 0x7000
  221. * T_hs-trail = 3
  222. * T_hs-prepare = 3
  223. * T_clk-trail = 3
  224. * T_clk-prepare = 2
  225. */
  226. iowrite32(0x70003332, base + TIMSET);
  227. /* no responses requested */
  228. iowrite32(0x00000000, base + RESREQSET0);
  229. /* request response to packets of type 0x28 */
  230. iowrite32(0x00000100, base + RESREQSET1);
  231. /* High-speed transmission timeout, default 0xffffffff */
  232. iowrite32(0x0fffffff, base + HSTTOVSET);
  233. /* LP reception timeout, default 0xffffffff */
  234. iowrite32(0x0fffffff, base + LPRTOVSET);
  235. /* Turn-around timeout, default 0xffffffff */
  236. iowrite32(0x0fffffff, base + TATOVSET);
  237. /* Peripheral reset timeout, default 0xffffffff */
  238. iowrite32(0x0fffffff, base + PRTOVSET);
  239. /* Interrupts not used, disable all */
  240. iowrite32(0, base + DSIINTE);
  241. /* DSI-Tx bias on */
  242. iowrite32(0x00000001, base + PHYCTRL);
  243. udelay(200);
  244. /* Deassert resets, power on */
  245. iowrite32(0x03070001 | pdata->phyctrl, base + PHYCTRL);
  246. /*
  247. * Default = ULPS enable |
  248. * Contention detection enabled |
  249. * EoT packet transmission enable |
  250. * CRC check enable |
  251. * ECC check enable
  252. */
  253. bitmap_fill((unsigned long *)&tmp, pdata->lane);
  254. tmp |= 0x00003700;
  255. iowrite32(tmp, base + SYSCONF);
  256. /* setup l-bridge */
  257. /*
  258. * Enable transmission of all packets,
  259. * transmit LPS after each HS packet completion
  260. */
  261. iowrite32(0x00000006, mipi->linkbase + DTCTR);
  262. /* VSYNC width = 2 (<< 17) */
  263. iowrite32((ch->lcd_modes[0].vsync_len << pdata->vsynw_offset) |
  264. (pdata->clksrc << 16) | (pctype << 12) | datatype,
  265. mipi->linkbase + VMCTR1);
  266. /*
  267. * Non-burst mode with sync pulses: VSE and HSE are output,
  268. * HSA period allowed, no commands in LP
  269. */
  270. vmctr2 = 0;
  271. if (pdata->flags & SH_MIPI_DSI_VSEE)
  272. vmctr2 |= 1 << 23;
  273. if (pdata->flags & SH_MIPI_DSI_HSEE)
  274. vmctr2 |= 1 << 22;
  275. if (pdata->flags & SH_MIPI_DSI_HSAE)
  276. vmctr2 |= 1 << 21;
  277. if (pdata->flags & SH_MIPI_DSI_BL2E)
  278. vmctr2 |= 1 << 17;
  279. if (pdata->flags & SH_MIPI_DSI_HSABM)
  280. vmctr2 |= 1 << 5;
  281. if (pdata->flags & SH_MIPI_DSI_HBPBM)
  282. vmctr2 |= 1 << 4;
  283. if (pdata->flags & SH_MIPI_DSI_HFPBM)
  284. vmctr2 |= 1 << 3;
  285. iowrite32(vmctr2, mipi->linkbase + VMCTR2);
  286. /*
  287. * VMLEN1 = RGBLEN | HSALEN
  288. *
  289. * see
  290. * Video mode - Blanking Packet setting
  291. */
  292. top = linelength << 16; /* RGBLEN */
  293. bottom = 0x00000001;
  294. if (pdata->flags & SH_MIPI_DSI_HSABM) /* HSALEN */
  295. bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
  296. iowrite32(top | bottom , mipi->linkbase + VMLEN1);
  297. /*
  298. * VMLEN2 = HBPLEN | HFPLEN
  299. *
  300. * see
  301. * Video mode - Blanking Packet setting
  302. */
  303. top = 0x00010000;
  304. bottom = 0x00000001;
  305. delay = 0;
  306. div = 1; /* HSbyteCLK is calculation base
  307. * HS4divCLK = HSbyteCLK/2
  308. * HS6divCLK is not supported for now */
  309. if (pdata->flags & SH_MIPI_DSI_HS4divCLK)
  310. div = 2;
  311. if (pdata->flags & SH_MIPI_DSI_HFPBM) { /* HBPLEN */
  312. top = ch->lcd_modes[0].hsync_len + ch->lcd_modes[0].left_margin;
  313. top = ((pdata->lane * top / div) - 10) << 16;
  314. }
  315. if (pdata->flags & SH_MIPI_DSI_HBPBM) { /* HFPLEN */
  316. bottom = ch->lcd_modes[0].right_margin;
  317. bottom = (pdata->lane * bottom / div) - 12;
  318. }
  319. bpp = linelength / ch->lcd_modes[0].xres; /* byte / pixel */
  320. if ((pdata->lane / div) > bpp) {
  321. tmp = ch->lcd_modes[0].xres / bpp; /* output cycle */
  322. tmp = ch->lcd_modes[0].xres - tmp; /* (input - output) cycle */
  323. delay = (pdata->lane * tmp);
  324. }
  325. iowrite32(top | (bottom + delay) , mipi->linkbase + VMLEN2);
  326. msleep(5);
  327. /* setup LCD panel */
  328. /* cf. drivers/video/omap/lcd_mipid.c */
  329. sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
  330. msleep(120);
  331. /*
  332. * [7] - Page Address Mode
  333. * [6] - Column Address Mode
  334. * [5] - Page / Column Address Mode
  335. * [4] - Display Device Line Refresh Order
  336. * [3] - RGB/BGR Order
  337. * [2] - Display Data Latch Data Order
  338. * [1] - Flip Horizontal
  339. * [0] - Flip Vertical
  340. */
  341. sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
  342. /* cf. set_data_lines() */
  343. sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
  344. pixfmt << 4);
  345. sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
  346. /* Enable timeout counters */
  347. iowrite32(0x00000f00, base + DSICTRL);
  348. return 0;
  349. }
  350. static int mipi_display_on(struct sh_mobile_lcdc_entity *entity)
  351. {
  352. struct sh_mipi *mipi = to_sh_mipi(entity);
  353. struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
  354. int ret;
  355. pm_runtime_get_sync(&mipi->pdev->dev);
  356. ret = pdata->set_dot_clock(mipi->pdev, mipi->base, 1);
  357. if (ret < 0)
  358. goto mipi_display_on_fail1;
  359. ret = sh_mipi_setup(mipi, pdata);
  360. if (ret < 0)
  361. goto mipi_display_on_fail2;
  362. sh_mipi_dsi_enable(mipi, true);
  363. return SH_MOBILE_LCDC_DISPLAY_CONNECTED;
  364. mipi_display_on_fail1:
  365. pm_runtime_put_sync(&mipi->pdev->dev);
  366. mipi_display_on_fail2:
  367. pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
  368. return ret;
  369. }
  370. static void mipi_display_off(struct sh_mobile_lcdc_entity *entity)
  371. {
  372. struct sh_mipi *mipi = to_sh_mipi(entity);
  373. struct sh_mipi_dsi_info *pdata = mipi->pdev->dev.platform_data;
  374. sh_mipi_dsi_enable(mipi, false);
  375. pdata->set_dot_clock(mipi->pdev, mipi->base, 0);
  376. pm_runtime_put_sync(&mipi->pdev->dev);
  377. }
  378. static const struct sh_mobile_lcdc_entity_ops mipi_ops = {
  379. .display_on = mipi_display_on,
  380. .display_off = mipi_display_off,
  381. };
  382. static int __init sh_mipi_probe(struct platform_device *pdev)
  383. {
  384. struct sh_mipi *mipi;
  385. struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
  386. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  387. struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  388. unsigned long rate, f_current;
  389. int idx = pdev->id, ret;
  390. if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
  391. return -ENODEV;
  392. if (!pdata->set_dot_clock)
  393. return -EINVAL;
  394. mutex_lock(&array_lock);
  395. if (idx < 0)
  396. for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
  397. ;
  398. if (idx == ARRAY_SIZE(mipi_dsi)) {
  399. ret = -EBUSY;
  400. goto efindslot;
  401. }
  402. mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
  403. if (!mipi) {
  404. ret = -ENOMEM;
  405. goto ealloc;
  406. }
  407. mipi->entity.owner = THIS_MODULE;
  408. mipi->entity.ops = &mipi_ops;
  409. if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
  410. dev_err(&pdev->dev, "MIPI register region already claimed\n");
  411. ret = -EBUSY;
  412. goto ereqreg;
  413. }
  414. mipi->base = ioremap(res->start, resource_size(res));
  415. if (!mipi->base) {
  416. ret = -ENOMEM;
  417. goto emap;
  418. }
  419. if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
  420. dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
  421. ret = -EBUSY;
  422. goto ereqreg2;
  423. }
  424. mipi->linkbase = ioremap(res2->start, resource_size(res2));
  425. if (!mipi->linkbase) {
  426. ret = -ENOMEM;
  427. goto emap2;
  428. }
  429. mipi->pdev = pdev;
  430. mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
  431. if (IS_ERR(mipi->dsit_clk)) {
  432. ret = PTR_ERR(mipi->dsit_clk);
  433. goto eclktget;
  434. }
  435. f_current = clk_get_rate(mipi->dsit_clk);
  436. /* 80MHz required by the datasheet */
  437. rate = clk_round_rate(mipi->dsit_clk, 80000000);
  438. if (rate > 0 && rate != f_current)
  439. ret = clk_set_rate(mipi->dsit_clk, rate);
  440. else
  441. ret = rate;
  442. if (ret < 0)
  443. goto esettrate;
  444. dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
  445. ret = clk_enable(mipi->dsit_clk);
  446. if (ret < 0)
  447. goto eclkton;
  448. mipi_dsi[idx] = mipi;
  449. pm_runtime_enable(&pdev->dev);
  450. pm_runtime_resume(&pdev->dev);
  451. mutex_unlock(&array_lock);
  452. platform_set_drvdata(pdev, &mipi->entity);
  453. return 0;
  454. eclkton:
  455. esettrate:
  456. clk_put(mipi->dsit_clk);
  457. eclktget:
  458. iounmap(mipi->linkbase);
  459. emap2:
  460. release_mem_region(res2->start, resource_size(res2));
  461. ereqreg2:
  462. iounmap(mipi->base);
  463. emap:
  464. release_mem_region(res->start, resource_size(res));
  465. ereqreg:
  466. kfree(mipi);
  467. ealloc:
  468. efindslot:
  469. mutex_unlock(&array_lock);
  470. return ret;
  471. }
  472. static int __devexit sh_mipi_remove(struct platform_device *pdev)
  473. {
  474. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  475. struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  476. struct sh_mipi *mipi = to_sh_mipi(platform_get_drvdata(pdev));
  477. int i, ret;
  478. mutex_lock(&array_lock);
  479. for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
  480. ;
  481. if (i == ARRAY_SIZE(mipi_dsi)) {
  482. ret = -EINVAL;
  483. } else {
  484. ret = 0;
  485. mipi_dsi[i] = NULL;
  486. }
  487. mutex_unlock(&array_lock);
  488. if (ret < 0)
  489. return ret;
  490. pm_runtime_disable(&pdev->dev);
  491. clk_disable(mipi->dsit_clk);
  492. clk_put(mipi->dsit_clk);
  493. iounmap(mipi->linkbase);
  494. if (res2)
  495. release_mem_region(res2->start, resource_size(res2));
  496. iounmap(mipi->base);
  497. if (res)
  498. release_mem_region(res->start, resource_size(res));
  499. platform_set_drvdata(pdev, NULL);
  500. kfree(mipi);
  501. return 0;
  502. }
  503. static struct platform_driver sh_mipi_driver = {
  504. .remove = __devexit_p(sh_mipi_remove),
  505. .shutdown = sh_mipi_shutdown,
  506. .driver = {
  507. .name = "sh-mipi-dsi",
  508. },
  509. };
  510. static int __init sh_mipi_init(void)
  511. {
  512. return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
  513. }
  514. module_init(sh_mipi_init);
  515. static void __exit sh_mipi_exit(void)
  516. {
  517. platform_driver_unregister(&sh_mipi_driver);
  518. }
  519. module_exit(sh_mipi_exit);
  520. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  521. MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
  522. MODULE_LICENSE("GPL v2");