da8xx.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602
  1. /*
  2. * Texas Instruments DA8xx/OMAP-L1x "glue layer"
  3. *
  4. * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  5. *
  6. * Based on the DaVinci "glue layer" code.
  7. * Copyright (C) 2005-2006 by Texas Instruments
  8. *
  9. * This file is part of the Inventra Controller Driver for Linux.
  10. *
  11. * The Inventra Controller Driver for Linux is free software; you
  12. * can redistribute it and/or modify it under the terms of the GNU
  13. * General Public License version 2 as published by the Free Software
  14. * Foundation.
  15. *
  16. * The Inventra Controller Driver for Linux is distributed in
  17. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  18. * without even the implied warranty of MERCHANTABILITY or
  19. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  20. * License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with The Inventra Controller Driver for Linux ; if not,
  24. * write to the Free Software Foundation, Inc., 59 Temple Place,
  25. * Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. */
  28. #include <linux/init.h>
  29. #include <linux/module.h>
  30. #include <linux/clk.h>
  31. #include <linux/err.h>
  32. #include <linux/io.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/dma-mapping.h>
  35. #include <mach/da8xx.h>
  36. #include <mach/usb.h>
  37. #include "musb_core.h"
  38. /*
  39. * DA8XX specific definitions
  40. */
  41. /* USB 2.0 OTG module registers */
  42. #define DA8XX_USB_REVISION_REG 0x00
  43. #define DA8XX_USB_CTRL_REG 0x04
  44. #define DA8XX_USB_STAT_REG 0x08
  45. #define DA8XX_USB_EMULATION_REG 0x0c
  46. #define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
  47. #define DA8XX_USB_AUTOREQ_REG 0x14
  48. #define DA8XX_USB_SRP_FIX_TIME_REG 0x18
  49. #define DA8XX_USB_TEARDOWN_REG 0x1c
  50. #define DA8XX_USB_INTR_SRC_REG 0x20
  51. #define DA8XX_USB_INTR_SRC_SET_REG 0x24
  52. #define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
  53. #define DA8XX_USB_INTR_MASK_REG 0x2c
  54. #define DA8XX_USB_INTR_MASK_SET_REG 0x30
  55. #define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
  56. #define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
  57. #define DA8XX_USB_END_OF_INTR_REG 0x3c
  58. #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
  59. /* Control register bits */
  60. #define DA8XX_SOFT_RESET_MASK 1
  61. #define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
  62. #define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
  63. /* USB interrupt register bits */
  64. #define DA8XX_INTR_USB_SHIFT 16
  65. #define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
  66. /* interrupts and DRVVBUS interrupt */
  67. #define DA8XX_INTR_DRVVBUS 0x100
  68. #define DA8XX_INTR_RX_SHIFT 8
  69. #define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
  70. #define DA8XX_INTR_TX_SHIFT 0
  71. #define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
  72. #define DA8XX_MENTOR_CORE_OFFSET 0x400
  73. #define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
  74. struct da8xx_glue {
  75. struct device *dev;
  76. struct platform_device *musb;
  77. struct clk *clk;
  78. };
  79. /*
  80. * REVISIT (PM): we should be able to keep the PHY in low power mode most
  81. * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
  82. * and, when in host mode, autosuspending idle root ports... PHY_PLLON
  83. * (overriding SUSPENDM?) then likely needs to stay off.
  84. */
  85. static inline void phy_on(void)
  86. {
  87. u32 cfgchip2 = __raw_readl(CFGCHIP2);
  88. /*
  89. * Start the on-chip PHY and its PLL.
  90. */
  91. cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
  92. cfgchip2 |= CFGCHIP2_PHY_PLLON;
  93. __raw_writel(cfgchip2, CFGCHIP2);
  94. pr_info("Waiting for USB PHY clock good...\n");
  95. while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
  96. cpu_relax();
  97. }
  98. static inline void phy_off(void)
  99. {
  100. u32 cfgchip2 = __raw_readl(CFGCHIP2);
  101. /*
  102. * Ensure that USB 1.1 reference clock is not being sourced from
  103. * USB 2.0 PHY. Otherwise do not power down the PHY.
  104. */
  105. if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
  106. (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
  107. pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
  108. "can't power it down\n");
  109. return;
  110. }
  111. /*
  112. * Power down the on-chip PHY.
  113. */
  114. cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
  115. __raw_writel(cfgchip2, CFGCHIP2);
  116. }
  117. /*
  118. * Because we don't set CTRL.UINT, it's "important" to:
  119. * - not read/write INTRUSB/INTRUSBE (except during
  120. * initial setup, as a workaround);
  121. * - use INTSET/INTCLR instead.
  122. */
  123. /**
  124. * da8xx_musb_enable - enable interrupts
  125. */
  126. static void da8xx_musb_enable(struct musb *musb)
  127. {
  128. void __iomem *reg_base = musb->ctrl_base;
  129. u32 mask;
  130. /* Workaround: setup IRQs through both register sets. */
  131. mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
  132. ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
  133. DA8XX_INTR_USB_MASK;
  134. musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
  135. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  136. if (is_otg_enabled(musb))
  137. musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
  138. DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
  139. }
  140. /**
  141. * da8xx_musb_disable - disable HDRC and flush interrupts
  142. */
  143. static void da8xx_musb_disable(struct musb *musb)
  144. {
  145. void __iomem *reg_base = musb->ctrl_base;
  146. musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
  147. DA8XX_INTR_USB_MASK |
  148. DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
  149. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  150. musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
  151. }
  152. #define portstate(stmt) stmt
  153. static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
  154. {
  155. WARN_ON(is_on && is_peripheral_active(musb));
  156. }
  157. #define POLL_SECONDS 2
  158. static struct timer_list otg_workaround;
  159. static void otg_timer(unsigned long _musb)
  160. {
  161. struct musb *musb = (void *)_musb;
  162. void __iomem *mregs = musb->mregs;
  163. u8 devctl;
  164. unsigned long flags;
  165. /*
  166. * We poll because DaVinci's won't expose several OTG-critical
  167. * status change events (from the transceiver) otherwise.
  168. */
  169. devctl = musb_readb(mregs, MUSB_DEVCTL);
  170. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  171. otg_state_string(musb->xceiv->state));
  172. spin_lock_irqsave(&musb->lock, flags);
  173. switch (musb->xceiv->state) {
  174. case OTG_STATE_A_WAIT_BCON:
  175. devctl &= ~MUSB_DEVCTL_SESSION;
  176. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  177. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  178. if (devctl & MUSB_DEVCTL_BDEVICE) {
  179. musb->xceiv->state = OTG_STATE_B_IDLE;
  180. MUSB_DEV_MODE(musb);
  181. } else {
  182. musb->xceiv->state = OTG_STATE_A_IDLE;
  183. MUSB_HST_MODE(musb);
  184. }
  185. break;
  186. case OTG_STATE_A_WAIT_VFALL:
  187. /*
  188. * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
  189. * RTL seems to mis-handle session "start" otherwise (or in
  190. * our case "recover"), in routine "VBUS was valid by the time
  191. * VBUSERR got reported during enumeration" cases.
  192. */
  193. if (devctl & MUSB_DEVCTL_VBUS) {
  194. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  195. break;
  196. }
  197. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  198. musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
  199. MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
  200. break;
  201. case OTG_STATE_B_IDLE:
  202. if (!is_peripheral_enabled(musb))
  203. break;
  204. /*
  205. * There's no ID-changed IRQ, so we have no good way to tell
  206. * when to switch to the A-Default state machine (by setting
  207. * the DEVCTL.Session bit).
  208. *
  209. * Workaround: whenever we're in B_IDLE, try setting the
  210. * session flag every few seconds. If it works, ID was
  211. * grounded and we're now in the A-Default state machine.
  212. *
  213. * NOTE: setting the session flag is _supposed_ to trigger
  214. * SRP but clearly it doesn't.
  215. */
  216. musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
  217. devctl = musb_readb(mregs, MUSB_DEVCTL);
  218. if (devctl & MUSB_DEVCTL_BDEVICE)
  219. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  220. else
  221. musb->xceiv->state = OTG_STATE_A_IDLE;
  222. break;
  223. default:
  224. break;
  225. }
  226. spin_unlock_irqrestore(&musb->lock, flags);
  227. }
  228. static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
  229. {
  230. static unsigned long last_timer;
  231. if (!is_otg_enabled(musb))
  232. return;
  233. if (timeout == 0)
  234. timeout = jiffies + msecs_to_jiffies(3);
  235. /* Never idle if active, or when VBUS timeout is not set as host */
  236. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  237. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  238. dev_dbg(musb->controller, "%s active, deleting timer\n",
  239. otg_state_string(musb->xceiv->state));
  240. del_timer(&otg_workaround);
  241. last_timer = jiffies;
  242. return;
  243. }
  244. if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
  245. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
  246. return;
  247. }
  248. last_timer = timeout;
  249. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  250. otg_state_string(musb->xceiv->state),
  251. jiffies_to_msecs(timeout - jiffies));
  252. mod_timer(&otg_workaround, timeout);
  253. }
  254. static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
  255. {
  256. struct musb *musb = hci;
  257. void __iomem *reg_base = musb->ctrl_base;
  258. struct usb_otg *otg = musb->xceiv->otg;
  259. unsigned long flags;
  260. irqreturn_t ret = IRQ_NONE;
  261. u32 status;
  262. spin_lock_irqsave(&musb->lock, flags);
  263. /*
  264. * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
  265. * the Mentor registers (except for setup), use the TI ones and EOI.
  266. */
  267. /* Acknowledge and handle non-CPPI interrupts */
  268. status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
  269. if (!status)
  270. goto eoi;
  271. musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
  272. dev_dbg(musb->controller, "USB IRQ %08x\n", status);
  273. musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
  274. musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
  275. musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
  276. /*
  277. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  278. * DA8xx's missing ID change IRQ. We need an ID change IRQ to
  279. * switch appropriately between halves of the OTG state machine.
  280. * Managing DEVCTL.Session per Mentor docs requires that we know its
  281. * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
  282. * Also, DRVVBUS pulses for SRP (but not at 5 V)...
  283. */
  284. if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
  285. int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
  286. void __iomem *mregs = musb->mregs;
  287. u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
  288. int err;
  289. err = is_host_enabled(musb) && (musb->int_usb &
  290. MUSB_INTR_VBUSERROR);
  291. if (err) {
  292. /*
  293. * The Mentor core doesn't debounce VBUS as needed
  294. * to cope with device connect current spikes. This
  295. * means it's not uncommon for bus-powered devices
  296. * to get VBUS errors during enumeration.
  297. *
  298. * This is a workaround, but newer RTL from Mentor
  299. * seems to allow a better one: "re"-starting sessions
  300. * without waiting for VBUS to stop registering in
  301. * devctl.
  302. */
  303. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  304. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  305. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  306. WARNING("VBUS error workaround (delay coming)\n");
  307. } else if (is_host_enabled(musb) && drvvbus) {
  308. MUSB_HST_MODE(musb);
  309. otg->default_a = 1;
  310. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  311. portstate(musb->port1_status |= USB_PORT_STAT_POWER);
  312. del_timer(&otg_workaround);
  313. } else {
  314. musb->is_active = 0;
  315. MUSB_DEV_MODE(musb);
  316. otg->default_a = 0;
  317. musb->xceiv->state = OTG_STATE_B_IDLE;
  318. portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
  319. }
  320. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  321. drvvbus ? "on" : "off",
  322. otg_state_string(musb->xceiv->state),
  323. err ? " ERROR" : "",
  324. devctl);
  325. ret = IRQ_HANDLED;
  326. }
  327. if (musb->int_tx || musb->int_rx || musb->int_usb)
  328. ret |= musb_interrupt(musb);
  329. eoi:
  330. /* EOI needs to be written for the IRQ to be re-asserted. */
  331. if (ret == IRQ_HANDLED || status)
  332. musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
  333. /* Poll for ID change */
  334. if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
  335. mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
  336. spin_unlock_irqrestore(&musb->lock, flags);
  337. return ret;
  338. }
  339. static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
  340. {
  341. u32 cfgchip2 = __raw_readl(CFGCHIP2);
  342. cfgchip2 &= ~CFGCHIP2_OTGMODE;
  343. switch (musb_mode) {
  344. case MUSB_HOST: /* Force VBUS valid, ID = 0 */
  345. cfgchip2 |= CFGCHIP2_FORCE_HOST;
  346. break;
  347. case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
  348. cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
  349. break;
  350. case MUSB_OTG: /* Don't override the VBUS/ID comparators */
  351. cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
  352. break;
  353. default:
  354. dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
  355. }
  356. __raw_writel(cfgchip2, CFGCHIP2);
  357. return 0;
  358. }
  359. static int da8xx_musb_init(struct musb *musb)
  360. {
  361. void __iomem *reg_base = musb->ctrl_base;
  362. u32 rev;
  363. musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
  364. /* Returns zero if e.g. not clocked */
  365. rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
  366. if (!rev)
  367. goto fail;
  368. usb_nop_xceiv_register();
  369. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  370. if (IS_ERR_OR_NULL(musb->xceiv))
  371. goto fail;
  372. if (is_host_enabled(musb))
  373. setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
  374. /* Reset the controller */
  375. musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
  376. /* Start the on-chip PHY and its PLL. */
  377. phy_on();
  378. msleep(5);
  379. /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
  380. pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
  381. rev, __raw_readl(CFGCHIP2),
  382. musb_readb(reg_base, DA8XX_USB_CTRL_REG));
  383. musb->isr = da8xx_musb_interrupt;
  384. return 0;
  385. fail:
  386. return -ENODEV;
  387. }
  388. static int da8xx_musb_exit(struct musb *musb)
  389. {
  390. if (is_host_enabled(musb))
  391. del_timer_sync(&otg_workaround);
  392. phy_off();
  393. usb_put_phy(musb->xceiv);
  394. usb_nop_xceiv_unregister();
  395. return 0;
  396. }
  397. static const struct musb_platform_ops da8xx_ops = {
  398. .init = da8xx_musb_init,
  399. .exit = da8xx_musb_exit,
  400. .enable = da8xx_musb_enable,
  401. .disable = da8xx_musb_disable,
  402. .set_mode = da8xx_musb_set_mode,
  403. .try_idle = da8xx_musb_try_idle,
  404. .set_vbus = da8xx_musb_set_vbus,
  405. };
  406. static u64 da8xx_dmamask = DMA_BIT_MASK(32);
  407. static int __devinit da8xx_probe(struct platform_device *pdev)
  408. {
  409. struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
  410. struct platform_device *musb;
  411. struct da8xx_glue *glue;
  412. struct clk *clk;
  413. int ret = -ENOMEM;
  414. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  415. if (!glue) {
  416. dev_err(&pdev->dev, "failed to allocate glue context\n");
  417. goto err0;
  418. }
  419. musb = platform_device_alloc("musb-hdrc", -1);
  420. if (!musb) {
  421. dev_err(&pdev->dev, "failed to allocate musb device\n");
  422. goto err1;
  423. }
  424. clk = clk_get(&pdev->dev, "usb20");
  425. if (IS_ERR(clk)) {
  426. dev_err(&pdev->dev, "failed to get clock\n");
  427. ret = PTR_ERR(clk);
  428. goto err2;
  429. }
  430. ret = clk_enable(clk);
  431. if (ret) {
  432. dev_err(&pdev->dev, "failed to enable clock\n");
  433. goto err3;
  434. }
  435. musb->dev.parent = &pdev->dev;
  436. musb->dev.dma_mask = &da8xx_dmamask;
  437. musb->dev.coherent_dma_mask = da8xx_dmamask;
  438. glue->dev = &pdev->dev;
  439. glue->musb = musb;
  440. glue->clk = clk;
  441. pdata->platform_ops = &da8xx_ops;
  442. platform_set_drvdata(pdev, glue);
  443. ret = platform_device_add_resources(musb, pdev->resource,
  444. pdev->num_resources);
  445. if (ret) {
  446. dev_err(&pdev->dev, "failed to add resources\n");
  447. goto err4;
  448. }
  449. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  450. if (ret) {
  451. dev_err(&pdev->dev, "failed to add platform_data\n");
  452. goto err4;
  453. }
  454. ret = platform_device_add(musb);
  455. if (ret) {
  456. dev_err(&pdev->dev, "failed to register musb device\n");
  457. goto err4;
  458. }
  459. return 0;
  460. err4:
  461. clk_disable(clk);
  462. err3:
  463. clk_put(clk);
  464. err2:
  465. platform_device_put(musb);
  466. err1:
  467. kfree(glue);
  468. err0:
  469. return ret;
  470. }
  471. static int __devexit da8xx_remove(struct platform_device *pdev)
  472. {
  473. struct da8xx_glue *glue = platform_get_drvdata(pdev);
  474. platform_device_del(glue->musb);
  475. platform_device_put(glue->musb);
  476. clk_disable(glue->clk);
  477. clk_put(glue->clk);
  478. kfree(glue);
  479. return 0;
  480. }
  481. static struct platform_driver da8xx_driver = {
  482. .probe = da8xx_probe,
  483. .remove = __devexit_p(da8xx_remove),
  484. .driver = {
  485. .name = "musb-da8xx",
  486. },
  487. };
  488. MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
  489. MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
  490. MODULE_LICENSE("GPL v2");
  491. static int __init da8xx_init(void)
  492. {
  493. return platform_driver_register(&da8xx_driver);
  494. }
  495. module_init(da8xx_init);
  496. static void __exit da8xx_exit(void)
  497. {
  498. platform_driver_unregister(&da8xx_driver);
  499. }
  500. module_exit(da8xx_exit);