pinctrl.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526
  1. /*
  2. * SuperH Pin Function Controller pinmux support.
  3. *
  4. * Copyright (C) 2012 Paul Mundt
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #define DRV_NAME "pinctrl-sh_pfc"
  11. #define pr_fmt(fmt) DRV_NAME " " KBUILD_MODNAME ": " fmt
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/sh_pfc.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/pinctrl/consumer.h>
  20. #include <linux/pinctrl/pinctrl.h>
  21. #include <linux/pinctrl/pinconf.h>
  22. #include <linux/pinctrl/pinmux.h>
  23. #include <linux/pinctrl/pinconf-generic.h>
  24. struct sh_pfc_pinctrl {
  25. struct pinctrl_dev *pctl;
  26. struct sh_pfc *pfc;
  27. struct pinmux_gpio **functions;
  28. unsigned int nr_functions;
  29. struct pinctrl_pin_desc *pads;
  30. unsigned int nr_pads;
  31. spinlock_t lock;
  32. };
  33. static struct sh_pfc_pinctrl *sh_pfc_pmx;
  34. static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
  35. {
  36. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  37. return pmx->nr_pads;
  38. }
  39. static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
  40. unsigned selector)
  41. {
  42. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  43. return pmx->pads[selector].name;
  44. }
  45. static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
  46. const unsigned **pins, unsigned *num_pins)
  47. {
  48. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  49. *pins = &pmx->pads[group].number;
  50. *num_pins = 1;
  51. return 0;
  52. }
  53. static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  54. unsigned offset)
  55. {
  56. seq_printf(s, "%s", DRV_NAME);
  57. }
  58. static struct pinctrl_ops sh_pfc_pinctrl_ops = {
  59. .get_groups_count = sh_pfc_get_groups_count,
  60. .get_group_name = sh_pfc_get_group_name,
  61. .get_group_pins = sh_pfc_get_group_pins,
  62. .pin_dbg_show = sh_pfc_pin_dbg_show,
  63. };
  64. static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
  65. {
  66. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  67. return pmx->nr_functions;
  68. }
  69. static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
  70. unsigned selector)
  71. {
  72. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  73. return pmx->functions[selector]->name;
  74. }
  75. static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func,
  76. const char * const **groups,
  77. unsigned * const num_groups)
  78. {
  79. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  80. *groups = &pmx->functions[func]->name;
  81. *num_groups = 1;
  82. return 0;
  83. }
  84. static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func,
  85. unsigned group)
  86. {
  87. return 0;
  88. }
  89. static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func,
  90. unsigned group)
  91. {
  92. }
  93. static inline int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset)
  94. {
  95. if (sh_pfc_config_gpio(pfc, offset,
  96. PINMUX_TYPE_FUNCTION,
  97. GPIO_CFG_DRYRUN) != 0)
  98. return -EINVAL;
  99. if (sh_pfc_config_gpio(pfc, offset,
  100. PINMUX_TYPE_FUNCTION,
  101. GPIO_CFG_REQ) != 0)
  102. return -EINVAL;
  103. return 0;
  104. }
  105. static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset,
  106. int new_type)
  107. {
  108. unsigned long flags;
  109. int pinmux_type;
  110. int ret = -EINVAL;
  111. spin_lock_irqsave(&pfc->lock, flags);
  112. pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
  113. /*
  114. * See if the present config needs to first be de-configured.
  115. */
  116. switch (pinmux_type) {
  117. case PINMUX_TYPE_GPIO:
  118. break;
  119. case PINMUX_TYPE_OUTPUT:
  120. case PINMUX_TYPE_INPUT:
  121. case PINMUX_TYPE_INPUT_PULLUP:
  122. case PINMUX_TYPE_INPUT_PULLDOWN:
  123. sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
  124. break;
  125. default:
  126. goto err;
  127. }
  128. /*
  129. * Dry run
  130. */
  131. if (sh_pfc_config_gpio(pfc, offset, new_type,
  132. GPIO_CFG_DRYRUN) != 0)
  133. goto err;
  134. /*
  135. * Request
  136. */
  137. if (sh_pfc_config_gpio(pfc, offset, new_type,
  138. GPIO_CFG_REQ) != 0)
  139. goto err;
  140. pfc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
  141. pfc->gpios[offset].flags |= new_type;
  142. ret = 0;
  143. err:
  144. spin_unlock_irqrestore(&pfc->lock, flags);
  145. return ret;
  146. }
  147. static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
  148. struct pinctrl_gpio_range *range,
  149. unsigned offset)
  150. {
  151. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  152. struct sh_pfc *pfc = pmx->pfc;
  153. unsigned long flags;
  154. int ret, pinmux_type;
  155. spin_lock_irqsave(&pfc->lock, flags);
  156. pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
  157. switch (pinmux_type) {
  158. case PINMUX_TYPE_FUNCTION:
  159. pr_notice_once("Use of GPIO API for function requests is "
  160. "deprecated, convert to pinctrl\n");
  161. /* handle for now */
  162. ret = sh_pfc_config_function(pfc, offset);
  163. if (unlikely(ret < 0))
  164. goto err;
  165. break;
  166. case PINMUX_TYPE_GPIO:
  167. break;
  168. default:
  169. pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
  170. return -ENOTSUPP;
  171. }
  172. ret = 0;
  173. err:
  174. spin_unlock_irqrestore(&pfc->lock, flags);
  175. return ret;
  176. }
  177. static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
  178. struct pinctrl_gpio_range *range,
  179. unsigned offset)
  180. {
  181. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  182. struct sh_pfc *pfc = pmx->pfc;
  183. unsigned long flags;
  184. int pinmux_type;
  185. spin_lock_irqsave(&pfc->lock, flags);
  186. pinmux_type = pfc->gpios[offset].flags & PINMUX_FLAG_TYPE;
  187. sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
  188. spin_unlock_irqrestore(&pfc->lock, flags);
  189. }
  190. static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
  191. struct pinctrl_gpio_range *range,
  192. unsigned offset, bool input)
  193. {
  194. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  195. int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
  196. return sh_pfc_reconfig_pin(pmx->pfc, offset, type);
  197. }
  198. static struct pinmux_ops sh_pfc_pinmux_ops = {
  199. .get_functions_count = sh_pfc_get_functions_count,
  200. .get_function_name = sh_pfc_get_function_name,
  201. .get_function_groups = sh_pfc_get_function_groups,
  202. .enable = sh_pfc_noop_enable,
  203. .disable = sh_pfc_noop_disable,
  204. .gpio_request_enable = sh_pfc_gpio_request_enable,
  205. .gpio_disable_free = sh_pfc_gpio_disable_free,
  206. .gpio_set_direction = sh_pfc_gpio_set_direction,
  207. };
  208. static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
  209. unsigned long *config)
  210. {
  211. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  212. struct sh_pfc *pfc = pmx->pfc;
  213. *config = pfc->gpios[pin].flags & PINMUX_FLAG_TYPE;
  214. return 0;
  215. }
  216. static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
  217. unsigned long config)
  218. {
  219. struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
  220. /* Validate the new type */
  221. if (config >= PINMUX_FLAG_TYPE)
  222. return -EINVAL;
  223. return sh_pfc_reconfig_pin(pmx->pfc, pin, config);
  224. }
  225. static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  226. struct seq_file *s, unsigned pin)
  227. {
  228. const char *pinmux_type_str[] = {
  229. [PINMUX_TYPE_NONE] = "none",
  230. [PINMUX_TYPE_FUNCTION] = "function",
  231. [PINMUX_TYPE_GPIO] = "gpio",
  232. [PINMUX_TYPE_OUTPUT] = "output",
  233. [PINMUX_TYPE_INPUT] = "input",
  234. [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
  235. [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
  236. };
  237. unsigned long config;
  238. int rc;
  239. rc = sh_pfc_pinconf_get(pctldev, pin, &config);
  240. if (unlikely(rc != 0))
  241. return;
  242. seq_printf(s, " %s", pinmux_type_str[config]);
  243. }
  244. static struct pinconf_ops sh_pfc_pinconf_ops = {
  245. .pin_config_get = sh_pfc_pinconf_get,
  246. .pin_config_set = sh_pfc_pinconf_set,
  247. .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
  248. };
  249. static struct pinctrl_gpio_range sh_pfc_gpio_range = {
  250. .name = DRV_NAME,
  251. .id = 0,
  252. };
  253. static struct pinctrl_desc sh_pfc_pinctrl_desc = {
  254. .name = DRV_NAME,
  255. .owner = THIS_MODULE,
  256. .pctlops = &sh_pfc_pinctrl_ops,
  257. .pmxops = &sh_pfc_pinmux_ops,
  258. .confops = &sh_pfc_pinconf_ops,
  259. };
  260. static inline void __devinit sh_pfc_map_one_gpio(struct sh_pfc *pfc,
  261. struct sh_pfc_pinctrl *pmx,
  262. struct pinmux_gpio *gpio,
  263. unsigned offset)
  264. {
  265. struct pinmux_data_reg *dummy;
  266. unsigned long flags;
  267. int bit;
  268. gpio->flags &= ~PINMUX_FLAG_TYPE;
  269. if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0)
  270. gpio->flags |= PINMUX_TYPE_GPIO;
  271. else {
  272. gpio->flags |= PINMUX_TYPE_FUNCTION;
  273. spin_lock_irqsave(&pmx->lock, flags);
  274. pmx->nr_functions++;
  275. spin_unlock_irqrestore(&pmx->lock, flags);
  276. }
  277. }
  278. /* pinmux ranges -> pinctrl pin descs */
  279. static int __devinit sh_pfc_map_gpios(struct sh_pfc *pfc,
  280. struct sh_pfc_pinctrl *pmx)
  281. {
  282. unsigned long flags;
  283. int i;
  284. pmx->nr_pads = pfc->last_gpio - pfc->first_gpio + 1;
  285. pmx->pads = kmalloc(sizeof(struct pinctrl_pin_desc) * pmx->nr_pads,
  286. GFP_KERNEL);
  287. if (unlikely(!pmx->pads)) {
  288. pmx->nr_pads = 0;
  289. return -ENOMEM;
  290. }
  291. spin_lock_irqsave(&pfc->lock, flags);
  292. /*
  293. * We don't necessarily have a 1:1 mapping between pin and linux
  294. * GPIO number, as the latter maps to the associated enum_id.
  295. * Care needs to be taken to translate back to pin space when
  296. * dealing with any pin configurations.
  297. */
  298. for (i = 0; i < pmx->nr_pads; i++) {
  299. struct pinctrl_pin_desc *pin = pmx->pads + i;
  300. struct pinmux_gpio *gpio = pfc->gpios + i;
  301. pin->number = pfc->first_gpio + i;
  302. pin->name = gpio->name;
  303. /* XXX */
  304. if (unlikely(!gpio->enum_id))
  305. continue;
  306. sh_pfc_map_one_gpio(pfc, pmx, gpio, i);
  307. }
  308. spin_unlock_irqrestore(&pfc->lock, flags);
  309. sh_pfc_pinctrl_desc.pins = pmx->pads;
  310. sh_pfc_pinctrl_desc.npins = pmx->nr_pads;
  311. return 0;
  312. }
  313. static int __devinit sh_pfc_map_functions(struct sh_pfc *pfc,
  314. struct sh_pfc_pinctrl *pmx)
  315. {
  316. unsigned long flags;
  317. int i, fn;
  318. pmx->functions = kzalloc(pmx->nr_functions * sizeof(void *),
  319. GFP_KERNEL);
  320. if (unlikely(!pmx->functions))
  321. return -ENOMEM;
  322. spin_lock_irqsave(&pmx->lock, flags);
  323. for (i = fn = 0; i < pmx->nr_pads; i++) {
  324. struct pinmux_gpio *gpio = pfc->gpios + i;
  325. if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION)
  326. pmx->functions[fn++] = gpio;
  327. }
  328. spin_unlock_irqrestore(&pmx->lock, flags);
  329. return 0;
  330. }
  331. static int __devinit sh_pfc_pinctrl_probe(struct platform_device *pdev)
  332. {
  333. struct sh_pfc *pfc;
  334. int ret;
  335. if (unlikely(!sh_pfc_pmx))
  336. return -ENODEV;
  337. pfc = sh_pfc_pmx->pfc;
  338. ret = sh_pfc_map_gpios(pfc, sh_pfc_pmx);
  339. if (unlikely(ret != 0))
  340. return ret;
  341. ret = sh_pfc_map_functions(pfc, sh_pfc_pmx);
  342. if (unlikely(ret != 0))
  343. goto free_pads;
  344. sh_pfc_pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, &pdev->dev,
  345. sh_pfc_pmx);
  346. if (IS_ERR(sh_pfc_pmx->pctl)) {
  347. ret = PTR_ERR(sh_pfc_pmx->pctl);
  348. goto free_functions;
  349. }
  350. sh_pfc_gpio_range.npins = pfc->last_gpio - pfc->first_gpio + 1;
  351. sh_pfc_gpio_range.base = pfc->first_gpio;
  352. sh_pfc_gpio_range.pin_base = pfc->first_gpio;
  353. pinctrl_add_gpio_range(sh_pfc_pmx->pctl, &sh_pfc_gpio_range);
  354. platform_set_drvdata(pdev, sh_pfc_pmx);
  355. return 0;
  356. free_functions:
  357. kfree(sh_pfc_pmx->functions);
  358. free_pads:
  359. kfree(sh_pfc_pmx->pads);
  360. kfree(sh_pfc_pmx);
  361. return ret;
  362. }
  363. static int __devexit sh_pfc_pinctrl_remove(struct platform_device *pdev)
  364. {
  365. struct sh_pfc_pinctrl *pmx = platform_get_drvdata(pdev);
  366. pinctrl_unregister(pmx->pctl);
  367. platform_set_drvdata(pdev, NULL);
  368. kfree(sh_pfc_pmx->functions);
  369. kfree(sh_pfc_pmx->pads);
  370. kfree(sh_pfc_pmx);
  371. return 0;
  372. }
  373. static struct platform_driver sh_pfc_pinctrl_driver = {
  374. .probe = sh_pfc_pinctrl_probe,
  375. .remove = __devexit_p(sh_pfc_pinctrl_remove),
  376. .driver = {
  377. .name = DRV_NAME,
  378. .owner = THIS_MODULE,
  379. },
  380. };
  381. static struct platform_device sh_pfc_pinctrl_device = {
  382. .name = DRV_NAME,
  383. .id = -1,
  384. };
  385. static int sh_pfc_pinctrl_init(void)
  386. {
  387. int rc;
  388. rc = platform_driver_register(&sh_pfc_pinctrl_driver);
  389. if (likely(!rc)) {
  390. rc = platform_device_register(&sh_pfc_pinctrl_device);
  391. if (unlikely(rc))
  392. platform_driver_unregister(&sh_pfc_pinctrl_driver);
  393. }
  394. return rc;
  395. }
  396. int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
  397. {
  398. sh_pfc_pmx = kzalloc(sizeof(struct sh_pfc_pinctrl), GFP_KERNEL);
  399. if (unlikely(!sh_pfc_pmx))
  400. return -ENOMEM;
  401. spin_lock_init(&sh_pfc_pmx->lock);
  402. sh_pfc_pmx->pfc = pfc;
  403. return sh_pfc_pinctrl_init();
  404. }
  405. EXPORT_SYMBOL_GPL(sh_pfc_register_pinctrl);
  406. static void __exit sh_pfc_pinctrl_exit(void)
  407. {
  408. platform_driver_unregister(&sh_pfc_pinctrl_driver);
  409. }
  410. module_exit(sh_pfc_pinctrl_exit);