pn544_hci.c 23 KB

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  1. /*
  2. * HCI based Driver for NXP PN544 NFC Chip
  3. *
  4. * Copyright (C) 2012 Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the
  17. * Free Software Foundation, Inc.,
  18. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/crc-ccitt.h>
  21. #include <linux/module.h>
  22. #include <linux/delay.h>
  23. #include <linux/slab.h>
  24. #include <linux/miscdevice.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/gpio.h>
  27. #include <linux/i2c.h>
  28. #include <linux/nfc.h>
  29. #include <net/nfc/hci.h>
  30. #include <net/nfc/shdlc.h>
  31. #include <linux/nfc/pn544.h>
  32. #define DRIVER_DESC "HCI NFC driver for PN544"
  33. #define PN544_HCI_DRIVER_NAME "pn544_hci"
  34. /* Timing restrictions (ms) */
  35. #define PN544_HCI_RESETVEN_TIME 30
  36. static struct i2c_device_id pn544_hci_id_table[] = {
  37. {"pn544", 0},
  38. {}
  39. };
  40. MODULE_DEVICE_TABLE(i2c, pn544_hci_id_table);
  41. #define HCI_MODE 0
  42. #define FW_MODE 1
  43. /* framing in HCI mode */
  44. #define PN544_HCI_LLC_LEN 1
  45. #define PN544_HCI_LLC_CRC 2
  46. #define PN544_HCI_LLC_LEN_CRC (PN544_HCI_LLC_LEN + PN544_HCI_LLC_CRC)
  47. #define PN544_HCI_LLC_MIN_SIZE (1 + PN544_HCI_LLC_LEN_CRC)
  48. #define PN544_HCI_LLC_MAX_PAYLOAD 29
  49. #define PN544_HCI_LLC_MAX_SIZE (PN544_HCI_LLC_LEN_CRC + 1 + \
  50. PN544_HCI_LLC_MAX_PAYLOAD)
  51. enum pn544_state {
  52. PN544_ST_COLD,
  53. PN544_ST_FW_READY,
  54. PN544_ST_READY,
  55. };
  56. #define FULL_VERSION_LEN 11
  57. /* Proprietary commands */
  58. #define PN544_WRITE 0x3f
  59. /* Proprietary gates, events, commands and registers */
  60. /* NFC_HCI_RF_READER_A_GATE additional registers and commands */
  61. #define PN544_RF_READER_A_AUTO_ACTIVATION 0x10
  62. #define PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION 0x12
  63. #define PN544_MIFARE_CMD 0x21
  64. /* Commands that apply to all RF readers */
  65. #define PN544_RF_READER_CMD_PRESENCE_CHECK 0x30
  66. #define PN544_RF_READER_CMD_ACTIVATE_NEXT 0x32
  67. /* NFC_HCI_ID_MGMT_GATE additional registers */
  68. #define PN544_ID_MGMT_FULL_VERSION_SW 0x10
  69. #define PN544_RF_READER_ISO15693_GATE 0x12
  70. #define PN544_RF_READER_F_GATE 0x14
  71. #define PN544_FELICA_ID 0x04
  72. #define PN544_FELICA_RAW 0x20
  73. #define PN544_RF_READER_JEWEL_GATE 0x15
  74. #define PN544_JEWEL_RAW_CMD 0x23
  75. #define PN544_RF_READER_NFCIP1_INITIATOR_GATE 0x30
  76. #define PN544_RF_READER_NFCIP1_TARGET_GATE 0x31
  77. #define PN544_SYS_MGMT_GATE 0x90
  78. #define PN544_SYS_MGMT_INFO_NOTIFICATION 0x02
  79. #define PN544_POLLING_LOOP_MGMT_GATE 0x94
  80. #define PN544_PL_RDPHASES 0x06
  81. #define PN544_PL_EMULATION 0x07
  82. #define PN544_PL_NFCT_DEACTIVATED 0x09
  83. #define PN544_SWP_MGMT_GATE 0xA0
  84. #define PN544_NFC_WI_MGMT_GATE 0xA1
  85. static struct nfc_hci_gate pn544_gates[] = {
  86. {NFC_HCI_ADMIN_GATE, NFC_HCI_INVALID_PIPE},
  87. {NFC_HCI_LOOPBACK_GATE, NFC_HCI_INVALID_PIPE},
  88. {NFC_HCI_ID_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  89. {NFC_HCI_LINK_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  90. {NFC_HCI_RF_READER_B_GATE, NFC_HCI_INVALID_PIPE},
  91. {NFC_HCI_RF_READER_A_GATE, NFC_HCI_INVALID_PIPE},
  92. {PN544_SYS_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  93. {PN544_SWP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  94. {PN544_POLLING_LOOP_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  95. {PN544_NFC_WI_MGMT_GATE, NFC_HCI_INVALID_PIPE},
  96. {PN544_RF_READER_F_GATE, NFC_HCI_INVALID_PIPE},
  97. {PN544_RF_READER_JEWEL_GATE, NFC_HCI_INVALID_PIPE},
  98. {PN544_RF_READER_ISO15693_GATE, NFC_HCI_INVALID_PIPE},
  99. {PN544_RF_READER_NFCIP1_INITIATOR_GATE, NFC_HCI_INVALID_PIPE},
  100. {PN544_RF_READER_NFCIP1_TARGET_GATE, NFC_HCI_INVALID_PIPE}
  101. };
  102. /* Largest headroom needed for outgoing custom commands */
  103. #define PN544_CMDS_HEADROOM 2
  104. struct pn544_hci_info {
  105. struct i2c_client *i2c_dev;
  106. struct nfc_shdlc *shdlc;
  107. enum pn544_state state;
  108. struct mutex info_lock;
  109. unsigned int gpio_en;
  110. unsigned int gpio_irq;
  111. unsigned int gpio_fw;
  112. unsigned int en_polarity;
  113. int hard_fault; /*
  114. * < 0 if hardware error occured (e.g. i2c err)
  115. * and prevents normal operation.
  116. */
  117. };
  118. static void pn544_hci_platform_init(struct pn544_hci_info *info)
  119. {
  120. int polarity, retry, ret;
  121. char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
  122. int count = sizeof(rset_cmd);
  123. pr_info(DRIVER_DESC ": %s\n", __func__);
  124. dev_info(&info->i2c_dev->dev, "Detecting nfc_en polarity\n");
  125. /* Disable fw download */
  126. gpio_set_value(info->gpio_fw, 0);
  127. for (polarity = 0; polarity < 2; polarity++) {
  128. info->en_polarity = polarity;
  129. retry = 3;
  130. while (retry--) {
  131. /* power off */
  132. gpio_set_value(info->gpio_en, !info->en_polarity);
  133. usleep_range(10000, 15000);
  134. /* power on */
  135. gpio_set_value(info->gpio_en, info->en_polarity);
  136. usleep_range(10000, 15000);
  137. /* send reset */
  138. dev_dbg(&info->i2c_dev->dev, "Sending reset cmd\n");
  139. ret = i2c_master_send(info->i2c_dev, rset_cmd, count);
  140. if (ret == count) {
  141. dev_info(&info->i2c_dev->dev,
  142. "nfc_en polarity : active %s\n",
  143. (polarity == 0 ? "low" : "high"));
  144. goto out;
  145. }
  146. }
  147. }
  148. dev_err(&info->i2c_dev->dev,
  149. "Could not detect nfc_en polarity, fallback to active high\n");
  150. out:
  151. gpio_set_value(info->gpio_en, !info->en_polarity);
  152. }
  153. static int pn544_hci_enable(struct pn544_hci_info *info, int mode)
  154. {
  155. pr_info(DRIVER_DESC ": %s\n", __func__);
  156. gpio_set_value(info->gpio_fw, 0);
  157. gpio_set_value(info->gpio_en, info->en_polarity);
  158. usleep_range(10000, 15000);
  159. return 0;
  160. }
  161. static void pn544_hci_disable(struct pn544_hci_info *info)
  162. {
  163. pr_info(DRIVER_DESC ": %s\n", __func__);
  164. gpio_set_value(info->gpio_fw, 0);
  165. gpio_set_value(info->gpio_en, !info->en_polarity);
  166. usleep_range(10000, 15000);
  167. gpio_set_value(info->gpio_en, info->en_polarity);
  168. usleep_range(10000, 15000);
  169. gpio_set_value(info->gpio_en, !info->en_polarity);
  170. usleep_range(10000, 15000);
  171. }
  172. static int pn544_hci_i2c_write(struct i2c_client *client, u8 *buf, int len)
  173. {
  174. int r;
  175. usleep_range(3000, 6000);
  176. r = i2c_master_send(client, buf, len);
  177. if (r == -EREMOTEIO) { /* Retry, chip was in standby */
  178. usleep_range(6000, 10000);
  179. r = i2c_master_send(client, buf, len);
  180. }
  181. if (r >= 0 && r != len)
  182. r = -EREMOTEIO;
  183. return r;
  184. }
  185. static int check_crc(u8 *buf, int buflen)
  186. {
  187. int len;
  188. u16 crc;
  189. len = buf[0] + 1;
  190. crc = crc_ccitt(0xffff, buf, len - 2);
  191. crc = ~crc;
  192. if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
  193. pr_err(PN544_HCI_DRIVER_NAME ": CRC error 0x%x != 0x%x 0x%x\n",
  194. crc, buf[len - 1], buf[len - 2]);
  195. pr_info(DRIVER_DESC ": %s : BAD CRC\n", __func__);
  196. print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
  197. 16, 2, buf, buflen, false);
  198. return -EPERM;
  199. }
  200. return 0;
  201. }
  202. /*
  203. * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
  204. * that i2c bus will be flushed and that next read will start on a new frame.
  205. * returned skb contains only LLC header and payload.
  206. * returns:
  207. * -EREMOTEIO : i2c read error (fatal)
  208. * -EBADMSG : frame was incorrect and discarded
  209. * -ENOMEM : cannot allocate skb, frame dropped
  210. */
  211. static int pn544_hci_i2c_read(struct i2c_client *client, struct sk_buff **skb)
  212. {
  213. int r;
  214. u8 len;
  215. u8 tmp[PN544_HCI_LLC_MAX_SIZE - 1];
  216. r = i2c_master_recv(client, &len, 1);
  217. if (r != 1) {
  218. dev_err(&client->dev, "cannot read len byte\n");
  219. return -EREMOTEIO;
  220. }
  221. if ((len < (PN544_HCI_LLC_MIN_SIZE - 1)) ||
  222. (len > (PN544_HCI_LLC_MAX_SIZE - 1))) {
  223. dev_err(&client->dev, "invalid len byte\n");
  224. r = -EBADMSG;
  225. goto flush;
  226. }
  227. *skb = alloc_skb(1 + len, GFP_KERNEL);
  228. if (*skb == NULL) {
  229. r = -ENOMEM;
  230. goto flush;
  231. }
  232. *skb_put(*skb, 1) = len;
  233. r = i2c_master_recv(client, skb_put(*skb, len), len);
  234. if (r != len) {
  235. kfree_skb(*skb);
  236. return -EREMOTEIO;
  237. }
  238. r = check_crc((*skb)->data, (*skb)->len);
  239. if (r != 0) {
  240. kfree_skb(*skb);
  241. r = -EBADMSG;
  242. goto flush;
  243. }
  244. skb_pull(*skb, 1);
  245. skb_trim(*skb, (*skb)->len - 2);
  246. usleep_range(3000, 6000);
  247. return 0;
  248. flush:
  249. if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
  250. r = -EREMOTEIO;
  251. usleep_range(3000, 6000);
  252. return r;
  253. }
  254. /*
  255. * Reads an shdlc frame from the chip. This is not as straightforward as it
  256. * seems. There are cases where we could loose the frame start synchronization.
  257. * The frame format is len-data-crc, and corruption can occur anywhere while
  258. * transiting on i2c bus, such that we could read an invalid len.
  259. * In order to recover synchronization with the next frame, we must be sure
  260. * to read the real amount of data without using the len byte. We do this by
  261. * assuming the following:
  262. * - the chip will always present only one single complete frame on the bus
  263. * before triggering the interrupt
  264. * - the chip will not present a new frame until we have completely read
  265. * the previous one (or until we have handled the interrupt).
  266. * The tricky case is when we read a corrupted len that is less than the real
  267. * len. We must detect this here in order to determine that we need to flush
  268. * the bus. This is the reason why we check the crc here.
  269. */
  270. static irqreturn_t pn544_hci_irq_thread_fn(int irq, void *dev_id)
  271. {
  272. struct pn544_hci_info *info = dev_id;
  273. struct i2c_client *client = info->i2c_dev;
  274. struct sk_buff *skb = NULL;
  275. int r;
  276. BUG_ON(!info);
  277. BUG_ON(irq != info->i2c_dev->irq);
  278. dev_dbg(&client->dev, "IRQ\n");
  279. if (info->hard_fault != 0)
  280. return IRQ_HANDLED;
  281. r = pn544_hci_i2c_read(client, &skb);
  282. if (r == -EREMOTEIO) {
  283. info->hard_fault = r;
  284. nfc_shdlc_recv_frame(info->shdlc, NULL);
  285. return IRQ_HANDLED;
  286. } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
  287. return IRQ_HANDLED;
  288. }
  289. nfc_shdlc_recv_frame(info->shdlc, skb);
  290. return IRQ_HANDLED;
  291. }
  292. static int pn544_hci_open(struct nfc_shdlc *shdlc)
  293. {
  294. struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
  295. int r = 0;
  296. mutex_lock(&info->info_lock);
  297. if (info->state != PN544_ST_COLD) {
  298. r = -EBUSY;
  299. goto out;
  300. }
  301. r = pn544_hci_enable(info, HCI_MODE);
  302. if (r == 0)
  303. info->state = PN544_ST_READY;
  304. out:
  305. mutex_unlock(&info->info_lock);
  306. return r;
  307. }
  308. static void pn544_hci_close(struct nfc_shdlc *shdlc)
  309. {
  310. struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
  311. mutex_lock(&info->info_lock);
  312. if (info->state == PN544_ST_COLD)
  313. goto out;
  314. pn544_hci_disable(info);
  315. info->state = PN544_ST_COLD;
  316. out:
  317. mutex_unlock(&info->info_lock);
  318. }
  319. static int pn544_hci_ready(struct nfc_shdlc *shdlc)
  320. {
  321. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  322. struct sk_buff *skb;
  323. static struct hw_config {
  324. u8 adr[2];
  325. u8 value;
  326. } hw_config[] = {
  327. {{0x9f, 0x9a}, 0x00},
  328. {{0x98, 0x10}, 0xbc},
  329. {{0x9e, 0x71}, 0x00},
  330. {{0x98, 0x09}, 0x00},
  331. {{0x9e, 0xb4}, 0x00},
  332. {{0x9e, 0xd9}, 0xff},
  333. {{0x9e, 0xda}, 0xff},
  334. {{0x9e, 0xdb}, 0x23},
  335. {{0x9e, 0xdc}, 0x21},
  336. {{0x9e, 0xdd}, 0x22},
  337. {{0x9e, 0xde}, 0x24},
  338. {{0x9c, 0x01}, 0x08},
  339. {{0x9e, 0xaa}, 0x01},
  340. {{0x9b, 0xd1}, 0x0d},
  341. {{0x9b, 0xd2}, 0x24},
  342. {{0x9b, 0xd3}, 0x0a},
  343. {{0x9b, 0xd4}, 0x22},
  344. {{0x9b, 0xd5}, 0x08},
  345. {{0x9b, 0xd6}, 0x1e},
  346. {{0x9b, 0xdd}, 0x1c},
  347. {{0x9b, 0x84}, 0x13},
  348. {{0x99, 0x81}, 0x7f},
  349. {{0x99, 0x31}, 0x70},
  350. {{0x98, 0x00}, 0x3f},
  351. {{0x9f, 0x09}, 0x00},
  352. {{0x9f, 0x0a}, 0x05},
  353. {{0x9e, 0xd1}, 0xa1},
  354. {{0x99, 0x23}, 0x00},
  355. {{0x9e, 0x74}, 0x80},
  356. {{0x9f, 0x28}, 0x10},
  357. {{0x9f, 0x35}, 0x14},
  358. {{0x9f, 0x36}, 0x60},
  359. {{0x9c, 0x31}, 0x00},
  360. {{0x9c, 0x32}, 0xc8},
  361. {{0x9c, 0x19}, 0x40},
  362. {{0x9c, 0x1a}, 0x40},
  363. {{0x9c, 0x0c}, 0x00},
  364. {{0x9c, 0x0d}, 0x00},
  365. {{0x9c, 0x12}, 0x00},
  366. {{0x9c, 0x13}, 0x00},
  367. {{0x98, 0xa2}, 0x0e},
  368. {{0x98, 0x93}, 0x40},
  369. {{0x98, 0x7d}, 0x02},
  370. {{0x98, 0x7e}, 0x00},
  371. {{0x9f, 0xc8}, 0x01},
  372. };
  373. struct hw_config *p = hw_config;
  374. int count = ARRAY_SIZE(hw_config);
  375. struct sk_buff *res_skb;
  376. u8 param[4];
  377. int r;
  378. param[0] = 0;
  379. while (count--) {
  380. param[1] = p->adr[0];
  381. param[2] = p->adr[1];
  382. param[3] = p->value;
  383. r = nfc_hci_send_cmd(hdev, PN544_SYS_MGMT_GATE, PN544_WRITE,
  384. param, 4, &res_skb);
  385. if (r < 0)
  386. return r;
  387. if (res_skb->len != 1) {
  388. kfree_skb(res_skb);
  389. return -EPROTO;
  390. }
  391. if (res_skb->data[0] != p->value) {
  392. kfree_skb(res_skb);
  393. return -EIO;
  394. }
  395. kfree_skb(res_skb);
  396. p++;
  397. }
  398. param[0] = NFC_HCI_UICC_HOST_ID;
  399. r = nfc_hci_set_param(hdev, NFC_HCI_ADMIN_GATE,
  400. NFC_HCI_ADMIN_WHITELIST, param, 1);
  401. if (r < 0)
  402. return r;
  403. param[0] = 0x3d;
  404. r = nfc_hci_set_param(hdev, PN544_SYS_MGMT_GATE,
  405. PN544_SYS_MGMT_INFO_NOTIFICATION, param, 1);
  406. if (r < 0)
  407. return r;
  408. param[0] = 0x0;
  409. r = nfc_hci_set_param(hdev, NFC_HCI_RF_READER_A_GATE,
  410. PN544_RF_READER_A_AUTO_ACTIVATION, param, 1);
  411. if (r < 0)
  412. return r;
  413. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  414. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  415. if (r < 0)
  416. return r;
  417. param[0] = 0x1;
  418. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  419. PN544_PL_NFCT_DEACTIVATED, param, 1);
  420. if (r < 0)
  421. return r;
  422. param[0] = 0x0;
  423. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  424. PN544_PL_RDPHASES, param, 1);
  425. if (r < 0)
  426. return r;
  427. r = nfc_hci_get_param(hdev, NFC_HCI_ID_MGMT_GATE,
  428. PN544_ID_MGMT_FULL_VERSION_SW, &skb);
  429. if (r < 0)
  430. return r;
  431. if (skb->len != FULL_VERSION_LEN) {
  432. kfree_skb(skb);
  433. return -EINVAL;
  434. }
  435. print_hex_dump(KERN_DEBUG, "FULL VERSION SOFTWARE INFO: ",
  436. DUMP_PREFIX_NONE, 16, 1,
  437. skb->data, FULL_VERSION_LEN, false);
  438. kfree_skb(skb);
  439. return 0;
  440. }
  441. static int pn544_hci_xmit(struct nfc_shdlc *shdlc, struct sk_buff *skb)
  442. {
  443. struct pn544_hci_info *info = nfc_shdlc_get_clientdata(shdlc);
  444. struct i2c_client *client = info->i2c_dev;
  445. if (info->hard_fault != 0)
  446. return info->hard_fault;
  447. return pn544_hci_i2c_write(client, skb->data, skb->len);
  448. }
  449. static int pn544_hci_start_poll(struct nfc_shdlc *shdlc,
  450. u32 im_protocols, u32 tm_protocols)
  451. {
  452. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  453. u8 phases = 0;
  454. int r;
  455. u8 duration[2];
  456. u8 activated;
  457. pr_info(DRIVER_DESC ": %s protocols 0x%x 0x%x\n",
  458. __func__, im_protocols, tm_protocols);
  459. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  460. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  461. if (r < 0)
  462. return r;
  463. duration[0] = 0x18;
  464. duration[1] = 0x6a;
  465. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  466. PN544_PL_EMULATION, duration, 2);
  467. if (r < 0)
  468. return r;
  469. activated = 0;
  470. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  471. PN544_PL_NFCT_DEACTIVATED, &activated, 1);
  472. if (r < 0)
  473. return r;
  474. if (im_protocols & (NFC_PROTO_ISO14443_MASK | NFC_PROTO_MIFARE_MASK |
  475. NFC_PROTO_JEWEL_MASK))
  476. phases |= 1; /* Type A */
  477. if (im_protocols & NFC_PROTO_FELICA_MASK) {
  478. phases |= (1 << 2); /* Type F 212 */
  479. phases |= (1 << 3); /* Type F 424 */
  480. }
  481. phases |= (1 << 5); /* NFC active */
  482. r = nfc_hci_set_param(hdev, PN544_POLLING_LOOP_MGMT_GATE,
  483. PN544_PL_RDPHASES, &phases, 1);
  484. if (r < 0)
  485. return r;
  486. r = nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  487. NFC_HCI_EVT_READER_REQUESTED, NULL, 0);
  488. if (r < 0)
  489. nfc_hci_send_event(hdev, NFC_HCI_RF_READER_A_GATE,
  490. NFC_HCI_EVT_END_OPERATION, NULL, 0);
  491. return r;
  492. }
  493. static int pn544_hci_target_from_gate(struct nfc_shdlc *shdlc, u8 gate,
  494. struct nfc_target *target)
  495. {
  496. switch (gate) {
  497. case PN544_RF_READER_F_GATE:
  498. target->supported_protocols = NFC_PROTO_FELICA_MASK;
  499. break;
  500. case PN544_RF_READER_JEWEL_GATE:
  501. target->supported_protocols = NFC_PROTO_JEWEL_MASK;
  502. target->sens_res = 0x0c00;
  503. break;
  504. default:
  505. return -EPROTO;
  506. }
  507. return 0;
  508. }
  509. static int pn544_hci_complete_target_discovered(struct nfc_shdlc *shdlc,
  510. u8 gate,
  511. struct nfc_target *target)
  512. {
  513. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  514. struct sk_buff *uid_skb;
  515. int r = 0;
  516. if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
  517. if (target->nfcid1_len != 4 && target->nfcid1_len != 7 &&
  518. target->nfcid1_len != 10)
  519. return -EPROTO;
  520. r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
  521. PN544_RF_READER_CMD_ACTIVATE_NEXT,
  522. target->nfcid1, target->nfcid1_len, NULL);
  523. } else if (target->supported_protocols & NFC_PROTO_FELICA_MASK) {
  524. r = nfc_hci_get_param(hdev, PN544_RF_READER_F_GATE,
  525. PN544_FELICA_ID, &uid_skb);
  526. if (r < 0)
  527. return r;
  528. if (uid_skb->len != 8) {
  529. kfree_skb(uid_skb);
  530. return -EPROTO;
  531. }
  532. r = nfc_hci_send_cmd(hdev, PN544_RF_READER_F_GATE,
  533. PN544_RF_READER_CMD_ACTIVATE_NEXT,
  534. uid_skb->data, uid_skb->len, NULL);
  535. kfree_skb(uid_skb);
  536. } else if (target->supported_protocols & NFC_PROTO_ISO14443_MASK) {
  537. /*
  538. * TODO: maybe other ISO 14443 require some kind of continue
  539. * activation, but for now we've seen only this one below.
  540. */
  541. if (target->sens_res == 0x4403) /* Type 4 Mifare DESFire */
  542. r = nfc_hci_send_cmd(hdev, NFC_HCI_RF_READER_A_GATE,
  543. PN544_RF_READER_A_CMD_CONTINUE_ACTIVATION,
  544. NULL, 0, NULL);
  545. }
  546. return r;
  547. }
  548. #define MIFARE_CMD_AUTH_KEY_A 0x60
  549. #define MIFARE_CMD_AUTH_KEY_B 0x61
  550. #define MIFARE_CMD_HEADER 2
  551. #define MIFARE_UID_LEN 4
  552. #define MIFARE_KEY_LEN 6
  553. #define MIFARE_CMD_LEN 12
  554. /*
  555. * Returns:
  556. * <= 0: driver handled the data exchange
  557. * 1: driver doesn't especially handle, please do standard processing
  558. */
  559. static int pn544_hci_data_exchange(struct nfc_shdlc *shdlc,
  560. struct nfc_target *target,
  561. struct sk_buff *skb,
  562. struct sk_buff **res_skb)
  563. {
  564. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  565. int r;
  566. pr_info(DRIVER_DESC ": %s for gate=%d\n", __func__,
  567. target->hci_reader_gate);
  568. switch (target->hci_reader_gate) {
  569. case NFC_HCI_RF_READER_A_GATE:
  570. if (target->supported_protocols & NFC_PROTO_MIFARE_MASK) {
  571. /*
  572. * It seems that pn544 is inverting key and UID for
  573. * MIFARE authentication commands.
  574. */
  575. if (skb->len == MIFARE_CMD_LEN &&
  576. (skb->data[0] == MIFARE_CMD_AUTH_KEY_A ||
  577. skb->data[0] == MIFARE_CMD_AUTH_KEY_B)) {
  578. u8 uid[MIFARE_UID_LEN];
  579. u8 *data = skb->data + MIFARE_CMD_HEADER;
  580. memcpy(uid, data + MIFARE_KEY_LEN,
  581. MIFARE_UID_LEN);
  582. memmove(data + MIFARE_UID_LEN, data,
  583. MIFARE_KEY_LEN);
  584. memcpy(data, uid, MIFARE_UID_LEN);
  585. }
  586. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  587. PN544_MIFARE_CMD,
  588. skb->data, skb->len, res_skb);
  589. } else
  590. return 1;
  591. case PN544_RF_READER_F_GATE:
  592. *skb_push(skb, 1) = 0;
  593. *skb_push(skb, 1) = 0;
  594. r = nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  595. PN544_FELICA_RAW,
  596. skb->data, skb->len, res_skb);
  597. if (r == 0)
  598. skb_pull(*res_skb, 1);
  599. return r;
  600. case PN544_RF_READER_JEWEL_GATE:
  601. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  602. PN544_JEWEL_RAW_CMD,
  603. skb->data, skb->len, res_skb);
  604. default:
  605. return 1;
  606. }
  607. }
  608. static int pn544_hci_check_presence(struct nfc_shdlc *shdlc,
  609. struct nfc_target *target)
  610. {
  611. struct nfc_hci_dev *hdev = nfc_shdlc_get_hci_dev(shdlc);
  612. return nfc_hci_send_cmd(hdev, target->hci_reader_gate,
  613. PN544_RF_READER_CMD_PRESENCE_CHECK,
  614. NULL, 0, NULL);
  615. }
  616. static struct nfc_shdlc_ops pn544_shdlc_ops = {
  617. .open = pn544_hci_open,
  618. .close = pn544_hci_close,
  619. .hci_ready = pn544_hci_ready,
  620. .xmit = pn544_hci_xmit,
  621. .start_poll = pn544_hci_start_poll,
  622. .target_from_gate = pn544_hci_target_from_gate,
  623. .complete_target_discovered = pn544_hci_complete_target_discovered,
  624. .data_exchange = pn544_hci_data_exchange,
  625. .check_presence = pn544_hci_check_presence,
  626. };
  627. static int __devinit pn544_hci_probe(struct i2c_client *client,
  628. const struct i2c_device_id *id)
  629. {
  630. struct pn544_hci_info *info;
  631. struct pn544_nfc_platform_data *pdata;
  632. int r = 0;
  633. u32 protocols;
  634. struct nfc_hci_init_data init_data;
  635. dev_dbg(&client->dev, "%s\n", __func__);
  636. dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
  637. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  638. dev_err(&client->dev, "Need I2C_FUNC_I2C\n");
  639. return -ENODEV;
  640. }
  641. info = kzalloc(sizeof(struct pn544_hci_info), GFP_KERNEL);
  642. if (!info) {
  643. dev_err(&client->dev,
  644. "Cannot allocate memory for pn544_hci_info.\n");
  645. r = -ENOMEM;
  646. goto err_info_alloc;
  647. }
  648. info->i2c_dev = client;
  649. info->state = PN544_ST_COLD;
  650. mutex_init(&info->info_lock);
  651. i2c_set_clientdata(client, info);
  652. pdata = client->dev.platform_data;
  653. if (pdata == NULL) {
  654. dev_err(&client->dev, "No platform data\n");
  655. r = -EINVAL;
  656. goto err_pdata;
  657. }
  658. if (pdata->request_resources == NULL) {
  659. dev_err(&client->dev, "request_resources() missing\n");
  660. r = -EINVAL;
  661. goto err_pdata;
  662. }
  663. r = pdata->request_resources(client);
  664. if (r) {
  665. dev_err(&client->dev, "Cannot get platform resources\n");
  666. goto err_pdata;
  667. }
  668. info->gpio_en = pdata->get_gpio(NFC_GPIO_ENABLE);
  669. info->gpio_fw = pdata->get_gpio(NFC_GPIO_FW_RESET);
  670. info->gpio_irq = pdata->get_gpio(NFC_GPIO_IRQ);
  671. pn544_hci_platform_init(info);
  672. r = request_threaded_irq(client->irq, NULL, pn544_hci_irq_thread_fn,
  673. IRQF_TRIGGER_RISING, PN544_HCI_DRIVER_NAME,
  674. info);
  675. if (r < 0) {
  676. dev_err(&client->dev, "Unable to register IRQ handler\n");
  677. goto err_rti;
  678. }
  679. init_data.gate_count = ARRAY_SIZE(pn544_gates);
  680. memcpy(init_data.gates, pn544_gates, sizeof(pn544_gates));
  681. /*
  682. * TODO: Session id must include the driver name + some bus addr
  683. * persistent info to discriminate 2 identical chips
  684. */
  685. strcpy(init_data.session_id, "ID544HCI");
  686. protocols = NFC_PROTO_JEWEL_MASK |
  687. NFC_PROTO_MIFARE_MASK |
  688. NFC_PROTO_FELICA_MASK |
  689. NFC_PROTO_ISO14443_MASK |
  690. NFC_PROTO_ISO14443_B_MASK |
  691. NFC_PROTO_NFC_DEP_MASK;
  692. info->shdlc = nfc_shdlc_allocate(&pn544_shdlc_ops,
  693. &init_data, protocols,
  694. PN544_CMDS_HEADROOM, 0,
  695. PN544_HCI_LLC_MAX_PAYLOAD,
  696. dev_name(&client->dev));
  697. if (!info->shdlc) {
  698. dev_err(&client->dev, "Cannot allocate nfc shdlc.\n");
  699. r = -ENOMEM;
  700. goto err_allocshdlc;
  701. }
  702. nfc_shdlc_set_clientdata(info->shdlc, info);
  703. return 0;
  704. err_allocshdlc:
  705. free_irq(client->irq, info);
  706. err_rti:
  707. if (pdata->free_resources != NULL)
  708. pdata->free_resources();
  709. err_pdata:
  710. kfree(info);
  711. err_info_alloc:
  712. return r;
  713. }
  714. static __devexit int pn544_hci_remove(struct i2c_client *client)
  715. {
  716. struct pn544_hci_info *info = i2c_get_clientdata(client);
  717. struct pn544_nfc_platform_data *pdata = client->dev.platform_data;
  718. dev_dbg(&client->dev, "%s\n", __func__);
  719. nfc_shdlc_free(info->shdlc);
  720. if (info->state != PN544_ST_COLD) {
  721. if (pdata->disable)
  722. pdata->disable();
  723. }
  724. free_irq(client->irq, info);
  725. if (pdata->free_resources)
  726. pdata->free_resources();
  727. kfree(info);
  728. return 0;
  729. }
  730. static struct i2c_driver pn544_hci_driver = {
  731. .driver = {
  732. .name = PN544_HCI_DRIVER_NAME,
  733. },
  734. .probe = pn544_hci_probe,
  735. .id_table = pn544_hci_id_table,
  736. .remove = __devexit_p(pn544_hci_remove),
  737. };
  738. static int __init pn544_hci_init(void)
  739. {
  740. int r;
  741. pr_debug(DRIVER_DESC ": %s\n", __func__);
  742. r = i2c_add_driver(&pn544_hci_driver);
  743. if (r) {
  744. pr_err(PN544_HCI_DRIVER_NAME ": driver registration failed\n");
  745. return r;
  746. }
  747. return 0;
  748. }
  749. static void __exit pn544_hci_exit(void)
  750. {
  751. i2c_del_driver(&pn544_hci_driver);
  752. }
  753. module_init(pn544_hci_init);
  754. module_exit(pn544_hci_exit);
  755. MODULE_LICENSE("GPL");
  756. MODULE_DESCRIPTION(DRIVER_DESC);