dm_common.c 54 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include <linux/export.h>
  30. #include "dm_common.h"
  31. #include "phy_common.h"
  32. #include "../pci.h"
  33. #include "../base.h"
  34. #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
  35. #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
  36. #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
  37. #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
  38. #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
  39. #define RTLPRIV (struct rtl_priv *)
  40. #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
  41. ((RTLPRIV(_priv))->mac80211.opmode == \
  42. NL80211_IFTYPE_ADHOC) ? \
  43. ((RTLPRIV(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) : \
  44. ((RTLPRIV(_priv))->dm.undecorated_smoothed_pwdb)
  45. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  46. 0x7f8001fe,
  47. 0x788001e2,
  48. 0x71c001c7,
  49. 0x6b8001ae,
  50. 0x65400195,
  51. 0x5fc0017f,
  52. 0x5a400169,
  53. 0x55400155,
  54. 0x50800142,
  55. 0x4c000130,
  56. 0x47c0011f,
  57. 0x43c0010f,
  58. 0x40000100,
  59. 0x3c8000f2,
  60. 0x390000e4,
  61. 0x35c000d7,
  62. 0x32c000cb,
  63. 0x300000c0,
  64. 0x2d4000b5,
  65. 0x2ac000ab,
  66. 0x288000a2,
  67. 0x26000098,
  68. 0x24000090,
  69. 0x22000088,
  70. 0x20000080,
  71. 0x1e400079,
  72. 0x1c800072,
  73. 0x1b00006c,
  74. 0x19800066,
  75. 0x18000060,
  76. 0x16c0005b,
  77. 0x15800056,
  78. 0x14400051,
  79. 0x1300004c,
  80. 0x12000048,
  81. 0x11000044,
  82. 0x10000040,
  83. };
  84. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  85. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  86. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  87. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  88. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  89. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  90. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  91. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  92. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  93. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  94. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  95. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  96. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  97. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  98. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  99. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  100. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  101. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  102. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  103. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  104. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  105. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  106. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  107. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  108. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  109. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  110. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  111. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  112. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  113. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  114. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  115. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  116. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  117. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  118. };
  119. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  120. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  121. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  122. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  123. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  124. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  125. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  126. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  127. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  128. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  129. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  130. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  131. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  132. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  133. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  134. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  135. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  136. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  137. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  138. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  139. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  140. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  141. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  142. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  143. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  144. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  145. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  146. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  147. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  148. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  149. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  150. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  151. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  152. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  153. };
  154. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  155. {
  156. struct rtl_priv *rtlpriv = rtl_priv(hw);
  157. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  158. dm_digtable->dig_enable_flag = true;
  159. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  160. dm_digtable->cur_igvalue = 0x20;
  161. dm_digtable->pre_igvalue = 0x0;
  162. dm_digtable->cursta_connectctate = DIG_STA_DISCONNECT;
  163. dm_digtable->presta_connectstate = DIG_STA_DISCONNECT;
  164. dm_digtable->curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
  165. dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
  166. dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
  167. dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  168. dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  169. dm_digtable->rx_gain_range_max = DM_DIG_MAX;
  170. dm_digtable->rx_gain_range_min = DM_DIG_MIN;
  171. dm_digtable->backoff_val = DM_DIG_BACKOFF_DEFAULT;
  172. dm_digtable->backoff_val_range_max = DM_DIG_BACKOFF_MAX;
  173. dm_digtable->backoff_val_range_min = DM_DIG_BACKOFF_MIN;
  174. dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
  175. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
  176. }
  177. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  178. {
  179. struct rtl_priv *rtlpriv = rtl_priv(hw);
  180. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  181. long rssi_val_min = 0;
  182. if ((dm_digtable->curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
  183. (dm_digtable->cursta_connectctate == DIG_STA_CONNECT)) {
  184. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
  185. rssi_val_min =
  186. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
  187. rtlpriv->dm.undecorated_smoothed_pwdb) ?
  188. rtlpriv->dm.undecorated_smoothed_pwdb :
  189. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  190. else
  191. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  192. } else if (dm_digtable->cursta_connectctate == DIG_STA_CONNECT ||
  193. dm_digtable->cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
  194. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  195. } else if (dm_digtable->curmultista_connectstate ==
  196. DIG_MULTISTA_CONNECT) {
  197. rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  198. }
  199. return (u8) rssi_val_min;
  200. }
  201. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  202. {
  203. u32 ret_value;
  204. struct rtl_priv *rtlpriv = rtl_priv(hw);
  205. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  206. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  207. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  208. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  209. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  210. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  211. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  212. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  213. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  214. falsealm_cnt->cnt_rate_illegal +
  215. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  216. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  217. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  218. falsealm_cnt->cnt_cck_fail = ret_value;
  219. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  220. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  221. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  222. falsealm_cnt->cnt_rate_illegal +
  223. falsealm_cnt->cnt_crc8_fail +
  224. falsealm_cnt->cnt_mcs_fail +
  225. falsealm_cnt->cnt_cck_fail);
  226. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  227. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  228. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  229. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  230. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  231. "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  232. falsealm_cnt->cnt_parity_fail,
  233. falsealm_cnt->cnt_rate_illegal,
  234. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
  235. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  236. "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  237. falsealm_cnt->cnt_ofdm_fail,
  238. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
  239. }
  240. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  241. {
  242. struct rtl_priv *rtlpriv = rtl_priv(hw);
  243. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  244. u8 value_igi = dm_digtable->cur_igvalue;
  245. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  246. value_igi--;
  247. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  248. value_igi += 0;
  249. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  250. value_igi++;
  251. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  252. value_igi += 2;
  253. if (value_igi > DM_DIG_FA_UPPER)
  254. value_igi = DM_DIG_FA_UPPER;
  255. else if (value_igi < DM_DIG_FA_LOWER)
  256. value_igi = DM_DIG_FA_LOWER;
  257. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  258. value_igi = 0x32;
  259. dm_digtable->cur_igvalue = value_igi;
  260. rtl92c_dm_write_dig(hw);
  261. }
  262. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  263. {
  264. struct rtl_priv *rtlpriv = rtl_priv(hw);
  265. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  266. if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable->fa_highthresh) {
  267. if ((dm_digtable->backoff_val - 2) <
  268. dm_digtable->backoff_val_range_min)
  269. dm_digtable->backoff_val =
  270. dm_digtable->backoff_val_range_min;
  271. else
  272. dm_digtable->backoff_val -= 2;
  273. } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable->fa_lowthresh) {
  274. if ((dm_digtable->backoff_val + 2) >
  275. dm_digtable->backoff_val_range_max)
  276. dm_digtable->backoff_val =
  277. dm_digtable->backoff_val_range_max;
  278. else
  279. dm_digtable->backoff_val += 2;
  280. }
  281. if ((dm_digtable->rssi_val_min + 10 - dm_digtable->backoff_val) >
  282. dm_digtable->rx_gain_range_max)
  283. dm_digtable->cur_igvalue = dm_digtable->rx_gain_range_max;
  284. else if ((dm_digtable->rssi_val_min + 10 -
  285. dm_digtable->backoff_val) < dm_digtable->rx_gain_range_min)
  286. dm_digtable->cur_igvalue = dm_digtable->rx_gain_range_min;
  287. else
  288. dm_digtable->cur_igvalue = dm_digtable->rssi_val_min + 10 -
  289. dm_digtable->backoff_val;
  290. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  291. "rssi_val_min = %x backoff_val %x\n",
  292. dm_digtable->rssi_val_min, dm_digtable->backoff_val);
  293. rtl92c_dm_write_dig(hw);
  294. }
  295. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  296. {
  297. static u8 initialized; /* initialized to false */
  298. struct rtl_priv *rtlpriv = rtl_priv(hw);
  299. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  300. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  301. long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  302. bool multi_sta = false;
  303. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  304. multi_sta = true;
  305. if (!multi_sta ||
  306. dm_digtable->cursta_connectctate != DIG_STA_DISCONNECT) {
  307. initialized = false;
  308. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  309. return;
  310. } else if (initialized == false) {
  311. initialized = true;
  312. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  313. dm_digtable->cur_igvalue = 0x20;
  314. rtl92c_dm_write_dig(hw);
  315. }
  316. if (dm_digtable->curmultista_connectstate == DIG_MULTISTA_CONNECT) {
  317. if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
  318. (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  319. if (dm_digtable->dig_ext_port_stage ==
  320. DIG_EXT_PORT_STAGE_2) {
  321. dm_digtable->cur_igvalue = 0x20;
  322. rtl92c_dm_write_dig(hw);
  323. }
  324. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  325. } else if (rssi_strength > dm_digtable->rssi_highthresh) {
  326. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  327. rtl92c_dm_ctrl_initgain_by_fa(hw);
  328. }
  329. } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  330. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  331. dm_digtable->cur_igvalue = 0x20;
  332. rtl92c_dm_write_dig(hw);
  333. }
  334. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  335. "curmultista_connectstate = %x dig_ext_port_stage %x\n",
  336. dm_digtable->curmultista_connectstate,
  337. dm_digtable->dig_ext_port_stage);
  338. }
  339. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  340. {
  341. struct rtl_priv *rtlpriv = rtl_priv(hw);
  342. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  343. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  344. "presta_connectstate = %x, cursta_connectctate = %x\n",
  345. dm_digtable->presta_connectstate,
  346. dm_digtable->cursta_connectctate);
  347. if (dm_digtable->presta_connectstate == dm_digtable->cursta_connectctate
  348. || dm_digtable->cursta_connectctate == DIG_STA_BEFORE_CONNECT
  349. || dm_digtable->cursta_connectctate == DIG_STA_CONNECT) {
  350. if (dm_digtable->cursta_connectctate != DIG_STA_DISCONNECT) {
  351. dm_digtable->rssi_val_min =
  352. rtl92c_dm_initial_gain_min_pwdb(hw);
  353. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  354. }
  355. } else {
  356. dm_digtable->rssi_val_min = 0;
  357. dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  358. dm_digtable->backoff_val = DM_DIG_BACKOFF_DEFAULT;
  359. dm_digtable->cur_igvalue = 0x20;
  360. dm_digtable->pre_igvalue = 0;
  361. rtl92c_dm_write_dig(hw);
  362. }
  363. }
  364. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  365. {
  366. struct rtl_priv *rtlpriv = rtl_priv(hw);
  367. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  368. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  369. if (dm_digtable->cursta_connectctate == DIG_STA_CONNECT) {
  370. dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  371. if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  372. if (dm_digtable->rssi_val_min <= 25)
  373. dm_digtable->cur_cck_pd_state =
  374. CCK_PD_STAGE_LowRssi;
  375. else
  376. dm_digtable->cur_cck_pd_state =
  377. CCK_PD_STAGE_HighRssi;
  378. } else {
  379. if (dm_digtable->rssi_val_min <= 20)
  380. dm_digtable->cur_cck_pd_state =
  381. CCK_PD_STAGE_LowRssi;
  382. else
  383. dm_digtable->cur_cck_pd_state =
  384. CCK_PD_STAGE_HighRssi;
  385. }
  386. } else {
  387. dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
  388. }
  389. if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
  390. if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  391. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  392. dm_digtable->cur_cck_fa_state =
  393. CCK_FA_STAGE_High;
  394. else
  395. dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
  396. if (dm_digtable->pre_cck_fa_state !=
  397. dm_digtable->cur_cck_fa_state) {
  398. if (dm_digtable->cur_cck_fa_state ==
  399. CCK_FA_STAGE_Low)
  400. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  401. 0x83);
  402. else
  403. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  404. 0xcd);
  405. dm_digtable->pre_cck_fa_state =
  406. dm_digtable->cur_cck_fa_state;
  407. }
  408. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  409. if (IS_92C_SERIAL(rtlhal->version))
  410. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  411. MASKBYTE2, 0xd7);
  412. } else {
  413. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  414. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  415. if (IS_92C_SERIAL(rtlhal->version))
  416. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  417. MASKBYTE2, 0xd3);
  418. }
  419. dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
  420. }
  421. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
  422. dm_digtable->cur_cck_pd_state);
  423. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
  424. IS_92C_SERIAL(rtlhal->version));
  425. }
  426. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  427. {
  428. struct rtl_priv *rtlpriv = rtl_priv(hw);
  429. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  430. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  431. if (mac->act_scanning)
  432. return;
  433. if (mac->link_state >= MAC80211_LINKED)
  434. dm_digtable->cursta_connectctate = DIG_STA_CONNECT;
  435. else
  436. dm_digtable->cursta_connectctate = DIG_STA_DISCONNECT;
  437. rtl92c_dm_initial_gain_sta(hw);
  438. rtl92c_dm_initial_gain_multi_sta(hw);
  439. rtl92c_dm_cck_packet_detection_thresh(hw);
  440. dm_digtable->presta_connectstate = dm_digtable->cursta_connectctate;
  441. }
  442. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  443. {
  444. struct rtl_priv *rtlpriv = rtl_priv(hw);
  445. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  446. if (rtlpriv->dm.dm_initialgain_enable == false)
  447. return;
  448. if (dm_digtable->dig_enable_flag == false)
  449. return;
  450. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  451. }
  452. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  453. {
  454. struct rtl_priv *rtlpriv = rtl_priv(hw);
  455. rtlpriv->dm.dynamic_txpower_enable = false;
  456. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  457. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  458. }
  459. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  460. {
  461. struct rtl_priv *rtlpriv = rtl_priv(hw);
  462. struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
  463. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  464. "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
  465. dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
  466. dm_digtable->backoff_val);
  467. dm_digtable->cur_igvalue += 2;
  468. if (dm_digtable->cur_igvalue > 0x3f)
  469. dm_digtable->cur_igvalue = 0x3f;
  470. if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
  471. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  472. dm_digtable->cur_igvalue);
  473. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  474. dm_digtable->cur_igvalue);
  475. dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
  476. }
  477. }
  478. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  479. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  480. {
  481. struct rtl_priv *rtlpriv = rtl_priv(hw);
  482. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  483. u8 h2c_parameter[3] = { 0 };
  484. return;
  485. if (tmpentry_max_pwdb != 0) {
  486. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
  487. tmpentry_max_pwdb;
  488. } else {
  489. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
  490. }
  491. if (tmpentry_min_pwdb != 0xff) {
  492. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
  493. tmpentry_min_pwdb;
  494. } else {
  495. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
  496. }
  497. h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
  498. h2c_parameter[0] = 0;
  499. rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
  500. }
  501. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  502. {
  503. struct rtl_priv *rtlpriv = rtl_priv(hw);
  504. rtlpriv->dm.current_turbo_edca = false;
  505. rtlpriv->dm.is_any_nonbepkts = false;
  506. rtlpriv->dm.is_cur_rdlstate = false;
  507. }
  508. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  509. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  510. {
  511. struct rtl_priv *rtlpriv = rtl_priv(hw);
  512. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  513. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  514. static u64 last_txok_cnt;
  515. static u64 last_rxok_cnt;
  516. static u32 last_bt_edca_ul;
  517. static u32 last_bt_edca_dl;
  518. u64 cur_txok_cnt = 0;
  519. u64 cur_rxok_cnt = 0;
  520. u32 edca_be_ul = 0x5ea42b;
  521. u32 edca_be_dl = 0x5ea42b;
  522. bool bt_change_edca = false;
  523. if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
  524. (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
  525. rtlpriv->dm.current_turbo_edca = false;
  526. last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  527. last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
  528. }
  529. if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
  530. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  531. bt_change_edca = true;
  532. }
  533. if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
  534. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
  535. bt_change_edca = true;
  536. }
  537. if (mac->link_state != MAC80211_LINKED) {
  538. rtlpriv->dm.current_turbo_edca = false;
  539. return;
  540. }
  541. if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
  542. if (!(edca_be_ul & 0xffff0000))
  543. edca_be_ul |= 0x005e0000;
  544. if (!(edca_be_dl & 0xffff0000))
  545. edca_be_dl |= 0x005e0000;
  546. }
  547. if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
  548. (!rtlpriv->dm.disable_framebursting))) {
  549. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  550. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  551. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  552. if (!rtlpriv->dm.is_cur_rdlstate ||
  553. !rtlpriv->dm.current_turbo_edca) {
  554. rtl_write_dword(rtlpriv,
  555. REG_EDCA_BE_PARAM,
  556. edca_be_dl);
  557. rtlpriv->dm.is_cur_rdlstate = true;
  558. }
  559. } else {
  560. if (rtlpriv->dm.is_cur_rdlstate ||
  561. !rtlpriv->dm.current_turbo_edca) {
  562. rtl_write_dword(rtlpriv,
  563. REG_EDCA_BE_PARAM,
  564. edca_be_ul);
  565. rtlpriv->dm.is_cur_rdlstate = false;
  566. }
  567. }
  568. rtlpriv->dm.current_turbo_edca = true;
  569. } else {
  570. if (rtlpriv->dm.current_turbo_edca) {
  571. u8 tmp = AC0_BE;
  572. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
  573. &tmp);
  574. rtlpriv->dm.current_turbo_edca = false;
  575. }
  576. }
  577. rtlpriv->dm.is_any_nonbepkts = false;
  578. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  579. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  580. }
  581. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  582. *hw)
  583. {
  584. struct rtl_priv *rtlpriv = rtl_priv(hw);
  585. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  586. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  587. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  588. u8 thermalvalue, delta, delta_lck, delta_iqk;
  589. long ele_a, ele_d, temp_cck, val_x, value32;
  590. long val_y, ele_c = 0;
  591. u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
  592. int i;
  593. bool is2t = IS_92C_SERIAL(rtlhal->version);
  594. s8 txpwr_level[2] = {0, 0};
  595. u8 ofdm_min_index = 6, rf;
  596. rtlpriv->dm.txpower_trackinginit = true;
  597. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  598. "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
  599. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  600. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  601. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
  602. thermalvalue, rtlpriv->dm.thermalvalue,
  603. rtlefuse->eeprom_thermalmeter);
  604. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  605. rtlefuse->eeprom_thermalmeter));
  606. if (is2t)
  607. rf = 2;
  608. else
  609. rf = 1;
  610. if (thermalvalue) {
  611. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  612. MASKDWORD) & MASKOFDM_D;
  613. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  614. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  615. ofdm_index_old[0] = (u8) i;
  616. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  617. "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  618. ROFDM0_XATXIQIMBALANCE,
  619. ele_d, ofdm_index_old[0]);
  620. break;
  621. }
  622. }
  623. if (is2t) {
  624. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  625. MASKDWORD) & MASKOFDM_D;
  626. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  627. if (ele_d == (ofdmswing_table[i] &
  628. MASKOFDM_D)) {
  629. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  630. DBG_LOUD,
  631. "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  632. ROFDM0_XBTXIQIMBALANCE, ele_d,
  633. ofdm_index_old[1]);
  634. break;
  635. }
  636. }
  637. }
  638. temp_cck =
  639. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  640. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  641. if (rtlpriv->dm.cck_inch14) {
  642. if (memcmp((void *)&temp_cck,
  643. (void *)&cckswing_table_ch14[i][2],
  644. 4) == 0) {
  645. cck_index_old = (u8) i;
  646. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  647. DBG_LOUD,
  648. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
  649. RCCK0_TXFILTER2, temp_cck,
  650. cck_index_old,
  651. rtlpriv->dm.cck_inch14);
  652. break;
  653. }
  654. } else {
  655. if (memcmp((void *)&temp_cck,
  656. (void *)
  657. &cckswing_table_ch1ch13[i][2],
  658. 4) == 0) {
  659. cck_index_old = (u8) i;
  660. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  661. DBG_LOUD,
  662. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
  663. RCCK0_TXFILTER2, temp_cck,
  664. cck_index_old,
  665. rtlpriv->dm.cck_inch14);
  666. break;
  667. }
  668. }
  669. }
  670. if (!rtlpriv->dm.thermalvalue) {
  671. rtlpriv->dm.thermalvalue =
  672. rtlefuse->eeprom_thermalmeter;
  673. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  674. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  675. for (i = 0; i < rf; i++)
  676. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  677. rtlpriv->dm.cck_index = cck_index_old;
  678. }
  679. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  680. (thermalvalue - rtlpriv->dm.thermalvalue) :
  681. (rtlpriv->dm.thermalvalue - thermalvalue);
  682. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  683. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  684. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  685. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  686. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  687. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  688. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  689. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
  690. thermalvalue, rtlpriv->dm.thermalvalue,
  691. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  692. delta_iqk);
  693. if (delta_lck > 1) {
  694. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  695. rtl92c_phy_lc_calibrate(hw);
  696. }
  697. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  698. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  699. for (i = 0; i < rf; i++)
  700. rtlpriv->dm.ofdm_index[i] -= delta;
  701. rtlpriv->dm.cck_index -= delta;
  702. } else {
  703. for (i = 0; i < rf; i++)
  704. rtlpriv->dm.ofdm_index[i] += delta;
  705. rtlpriv->dm.cck_index += delta;
  706. }
  707. if (is2t) {
  708. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  709. "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  710. rtlpriv->dm.ofdm_index[0],
  711. rtlpriv->dm.ofdm_index[1],
  712. rtlpriv->dm.cck_index);
  713. } else {
  714. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  715. "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
  716. rtlpriv->dm.ofdm_index[0],
  717. rtlpriv->dm.cck_index);
  718. }
  719. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  720. for (i = 0; i < rf; i++)
  721. ofdm_index[i] =
  722. rtlpriv->dm.ofdm_index[i]
  723. + 1;
  724. cck_index = rtlpriv->dm.cck_index + 1;
  725. } else {
  726. for (i = 0; i < rf; i++)
  727. ofdm_index[i] =
  728. rtlpriv->dm.ofdm_index[i];
  729. cck_index = rtlpriv->dm.cck_index;
  730. }
  731. for (i = 0; i < rf; i++) {
  732. if (txpwr_level[i] >= 0 &&
  733. txpwr_level[i] <= 26) {
  734. if (thermalvalue >
  735. rtlefuse->eeprom_thermalmeter) {
  736. if (delta < 5)
  737. ofdm_index[i] -= 1;
  738. else
  739. ofdm_index[i] -= 2;
  740. } else if (delta > 5 && thermalvalue <
  741. rtlefuse->
  742. eeprom_thermalmeter) {
  743. ofdm_index[i] += 1;
  744. }
  745. } else if (txpwr_level[i] >= 27 &&
  746. txpwr_level[i] <= 32
  747. && thermalvalue >
  748. rtlefuse->eeprom_thermalmeter) {
  749. if (delta < 5)
  750. ofdm_index[i] -= 1;
  751. else
  752. ofdm_index[i] -= 2;
  753. } else if (txpwr_level[i] >= 32 &&
  754. txpwr_level[i] <= 38 &&
  755. thermalvalue >
  756. rtlefuse->eeprom_thermalmeter
  757. && delta > 5) {
  758. ofdm_index[i] -= 1;
  759. }
  760. }
  761. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  762. if (thermalvalue >
  763. rtlefuse->eeprom_thermalmeter) {
  764. if (delta < 5)
  765. cck_index -= 1;
  766. else
  767. cck_index -= 2;
  768. } else if (delta > 5 && thermalvalue <
  769. rtlefuse->eeprom_thermalmeter) {
  770. cck_index += 1;
  771. }
  772. } else if (txpwr_level[i] >= 27 &&
  773. txpwr_level[i] <= 32 &&
  774. thermalvalue >
  775. rtlefuse->eeprom_thermalmeter) {
  776. if (delta < 5)
  777. cck_index -= 1;
  778. else
  779. cck_index -= 2;
  780. } else if (txpwr_level[i] >= 32 &&
  781. txpwr_level[i] <= 38 &&
  782. thermalvalue > rtlefuse->eeprom_thermalmeter
  783. && delta > 5) {
  784. cck_index -= 1;
  785. }
  786. for (i = 0; i < rf; i++) {
  787. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  788. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  789. else if (ofdm_index[i] < ofdm_min_index)
  790. ofdm_index[i] = ofdm_min_index;
  791. }
  792. if (cck_index > CCK_TABLE_SIZE - 1)
  793. cck_index = CCK_TABLE_SIZE - 1;
  794. else if (cck_index < 0)
  795. cck_index = 0;
  796. if (is2t) {
  797. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  798. "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  799. ofdm_index[0], ofdm_index[1],
  800. cck_index);
  801. } else {
  802. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  803. "new OFDM_A_index=0x%x, cck_index=0x%x\n",
  804. ofdm_index[0], cck_index);
  805. }
  806. }
  807. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  808. ele_d =
  809. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  810. val_x = rtlphy->reg_e94;
  811. val_y = rtlphy->reg_e9c;
  812. if (val_x != 0) {
  813. if ((val_x & 0x00000200) != 0)
  814. val_x = val_x | 0xFFFFFC00;
  815. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  816. if ((val_y & 0x00000200) != 0)
  817. val_y = val_y | 0xFFFFFC00;
  818. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  819. value32 = (ele_d << 22) |
  820. ((ele_c & 0x3F) << 16) | ele_a;
  821. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  822. MASKDWORD, value32);
  823. value32 = (ele_c & 0x000003C0) >> 6;
  824. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  825. value32);
  826. value32 = ((val_x * ele_d) >> 7) & 0x01;
  827. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  828. BIT(31), value32);
  829. value32 = ((val_y * ele_d) >> 7) & 0x01;
  830. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  831. BIT(29), value32);
  832. } else {
  833. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  834. MASKDWORD,
  835. ofdmswing_table[ofdm_index[0]]);
  836. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  837. 0x00);
  838. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  839. BIT(31) | BIT(29), 0x00);
  840. }
  841. if (!rtlpriv->dm.cck_inch14) {
  842. rtl_write_byte(rtlpriv, 0xa22,
  843. cckswing_table_ch1ch13[cck_index]
  844. [0]);
  845. rtl_write_byte(rtlpriv, 0xa23,
  846. cckswing_table_ch1ch13[cck_index]
  847. [1]);
  848. rtl_write_byte(rtlpriv, 0xa24,
  849. cckswing_table_ch1ch13[cck_index]
  850. [2]);
  851. rtl_write_byte(rtlpriv, 0xa25,
  852. cckswing_table_ch1ch13[cck_index]
  853. [3]);
  854. rtl_write_byte(rtlpriv, 0xa26,
  855. cckswing_table_ch1ch13[cck_index]
  856. [4]);
  857. rtl_write_byte(rtlpriv, 0xa27,
  858. cckswing_table_ch1ch13[cck_index]
  859. [5]);
  860. rtl_write_byte(rtlpriv, 0xa28,
  861. cckswing_table_ch1ch13[cck_index]
  862. [6]);
  863. rtl_write_byte(rtlpriv, 0xa29,
  864. cckswing_table_ch1ch13[cck_index]
  865. [7]);
  866. } else {
  867. rtl_write_byte(rtlpriv, 0xa22,
  868. cckswing_table_ch14[cck_index]
  869. [0]);
  870. rtl_write_byte(rtlpriv, 0xa23,
  871. cckswing_table_ch14[cck_index]
  872. [1]);
  873. rtl_write_byte(rtlpriv, 0xa24,
  874. cckswing_table_ch14[cck_index]
  875. [2]);
  876. rtl_write_byte(rtlpriv, 0xa25,
  877. cckswing_table_ch14[cck_index]
  878. [3]);
  879. rtl_write_byte(rtlpriv, 0xa26,
  880. cckswing_table_ch14[cck_index]
  881. [4]);
  882. rtl_write_byte(rtlpriv, 0xa27,
  883. cckswing_table_ch14[cck_index]
  884. [5]);
  885. rtl_write_byte(rtlpriv, 0xa28,
  886. cckswing_table_ch14[cck_index]
  887. [6]);
  888. rtl_write_byte(rtlpriv, 0xa29,
  889. cckswing_table_ch14[cck_index]
  890. [7]);
  891. }
  892. if (is2t) {
  893. ele_d = (ofdmswing_table[ofdm_index[1]] &
  894. 0xFFC00000) >> 22;
  895. val_x = rtlphy->reg_eb4;
  896. val_y = rtlphy->reg_ebc;
  897. if (val_x != 0) {
  898. if ((val_x & 0x00000200) != 0)
  899. val_x = val_x | 0xFFFFFC00;
  900. ele_a = ((val_x * ele_d) >> 8) &
  901. 0x000003FF;
  902. if ((val_y & 0x00000200) != 0)
  903. val_y = val_y | 0xFFFFFC00;
  904. ele_c = ((val_y * ele_d) >> 8) &
  905. 0x00003FF;
  906. value32 = (ele_d << 22) |
  907. ((ele_c & 0x3F) << 16) | ele_a;
  908. rtl_set_bbreg(hw,
  909. ROFDM0_XBTXIQIMBALANCE,
  910. MASKDWORD, value32);
  911. value32 = (ele_c & 0x000003C0) >> 6;
  912. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  913. MASKH4BITS, value32);
  914. value32 = ((val_x * ele_d) >> 7) & 0x01;
  915. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  916. BIT(27), value32);
  917. value32 = ((val_y * ele_d) >> 7) & 0x01;
  918. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  919. BIT(25), value32);
  920. } else {
  921. rtl_set_bbreg(hw,
  922. ROFDM0_XBTXIQIMBALANCE,
  923. MASKDWORD,
  924. ofdmswing_table[ofdm_index
  925. [1]]);
  926. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  927. MASKH4BITS, 0x00);
  928. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  929. BIT(27) | BIT(25), 0x00);
  930. }
  931. }
  932. }
  933. if (delta_iqk > 3) {
  934. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  935. rtl92c_phy_iq_calibrate(hw, false);
  936. }
  937. if (rtlpriv->dm.txpower_track_control)
  938. rtlpriv->dm.thermalvalue = thermalvalue;
  939. }
  940. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
  941. }
  942. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  943. struct ieee80211_hw *hw)
  944. {
  945. struct rtl_priv *rtlpriv = rtl_priv(hw);
  946. rtlpriv->dm.txpower_tracking = true;
  947. rtlpriv->dm.txpower_trackinginit = false;
  948. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  949. "pMgntInfo->txpower_tracking = %d\n",
  950. rtlpriv->dm.txpower_tracking);
  951. }
  952. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  953. {
  954. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  955. }
  956. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  957. {
  958. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  959. }
  960. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  961. struct ieee80211_hw *hw)
  962. {
  963. struct rtl_priv *rtlpriv = rtl_priv(hw);
  964. static u8 tm_trigger;
  965. if (!rtlpriv->dm.txpower_tracking)
  966. return;
  967. if (!tm_trigger) {
  968. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  969. 0x60);
  970. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  971. "Trigger 92S Thermal Meter!!\n");
  972. tm_trigger = 1;
  973. return;
  974. } else {
  975. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  976. "Schedule TxPowerTracking direct call!!\n");
  977. rtl92c_dm_txpower_tracking_directcall(hw);
  978. tm_trigger = 0;
  979. }
  980. }
  981. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  982. {
  983. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  984. }
  985. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  986. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  987. {
  988. struct rtl_priv *rtlpriv = rtl_priv(hw);
  989. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  990. p_ra->ratr_state = DM_RATR_STA_INIT;
  991. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  992. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  993. rtlpriv->dm.useramask = true;
  994. else
  995. rtlpriv->dm.useramask = false;
  996. }
  997. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  998. static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
  999. {
  1000. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1001. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1002. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1003. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  1004. u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
  1005. struct ieee80211_sta *sta = NULL;
  1006. if (is_hal_stop(rtlhal)) {
  1007. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1008. "<---- driver is going to unload\n");
  1009. return;
  1010. }
  1011. if (!rtlpriv->dm.useramask) {
  1012. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1013. "<---- driver does not control rate adaptive mask\n");
  1014. return;
  1015. }
  1016. if (mac->link_state == MAC80211_LINKED &&
  1017. mac->opmode == NL80211_IFTYPE_STATION) {
  1018. switch (p_ra->pre_ratr_state) {
  1019. case DM_RATR_STA_HIGH:
  1020. high_rssithresh_for_ra = 50;
  1021. low_rssithresh_for_ra = 20;
  1022. break;
  1023. case DM_RATR_STA_MIDDLE:
  1024. high_rssithresh_for_ra = 55;
  1025. low_rssithresh_for_ra = 20;
  1026. break;
  1027. case DM_RATR_STA_LOW:
  1028. high_rssithresh_for_ra = 50;
  1029. low_rssithresh_for_ra = 25;
  1030. break;
  1031. default:
  1032. high_rssithresh_for_ra = 50;
  1033. low_rssithresh_for_ra = 20;
  1034. break;
  1035. }
  1036. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1037. (long)high_rssithresh_for_ra)
  1038. p_ra->ratr_state = DM_RATR_STA_HIGH;
  1039. else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1040. (long)low_rssithresh_for_ra)
  1041. p_ra->ratr_state = DM_RATR_STA_MIDDLE;
  1042. else
  1043. p_ra->ratr_state = DM_RATR_STA_LOW;
  1044. if (p_ra->pre_ratr_state != p_ra->ratr_state) {
  1045. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, "RSSI = %ld\n",
  1046. rtlpriv->dm.undecorated_smoothed_pwdb);
  1047. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1048. "RSSI_LEVEL = %d\n", p_ra->ratr_state);
  1049. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1050. "PreState = %d, CurState = %d\n",
  1051. p_ra->pre_ratr_state, p_ra->ratr_state);
  1052. /* Only the PCI card uses sta in the update rate table
  1053. * callback routine */
  1054. if (rtlhal->interface == INTF_PCI) {
  1055. rcu_read_lock();
  1056. sta = ieee80211_find_sta(mac->vif, mac->bssid);
  1057. }
  1058. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  1059. p_ra->ratr_state);
  1060. p_ra->pre_ratr_state = p_ra->ratr_state;
  1061. if (rtlhal->interface == INTF_PCI)
  1062. rcu_read_unlock();
  1063. }
  1064. }
  1065. }
  1066. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1067. {
  1068. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1069. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1070. dm_pstable->pre_ccastate = CCA_MAX;
  1071. dm_pstable->cur_ccasate = CCA_MAX;
  1072. dm_pstable->pre_rfstate = RF_MAX;
  1073. dm_pstable->cur_rfstate = RF_MAX;
  1074. dm_pstable->rssi_val_min = 0;
  1075. }
  1076. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1077. {
  1078. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1079. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1080. static u8 initialize;
  1081. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  1082. if (initialize == 0) {
  1083. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1084. MASKDWORD) & 0x1CC000) >> 14;
  1085. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1086. MASKDWORD) & BIT(3)) >> 3;
  1087. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1088. MASKDWORD) & 0xFF000000) >> 24;
  1089. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  1090. initialize = 1;
  1091. }
  1092. if (!bforce_in_normal) {
  1093. if (dm_pstable->rssi_val_min != 0) {
  1094. if (dm_pstable->pre_rfstate == RF_NORMAL) {
  1095. if (dm_pstable->rssi_val_min >= 30)
  1096. dm_pstable->cur_rfstate = RF_SAVE;
  1097. else
  1098. dm_pstable->cur_rfstate = RF_NORMAL;
  1099. } else {
  1100. if (dm_pstable->rssi_val_min <= 25)
  1101. dm_pstable->cur_rfstate = RF_NORMAL;
  1102. else
  1103. dm_pstable->cur_rfstate = RF_SAVE;
  1104. }
  1105. } else {
  1106. dm_pstable->cur_rfstate = RF_MAX;
  1107. }
  1108. } else {
  1109. dm_pstable->cur_rfstate = RF_NORMAL;
  1110. }
  1111. if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
  1112. if (dm_pstable->cur_rfstate == RF_SAVE) {
  1113. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1114. 0x1C0000, 0x2);
  1115. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1116. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1117. 0xFF000000, 0x63);
  1118. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1119. 0xC000, 0x2);
  1120. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1121. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1122. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1123. } else {
  1124. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1125. 0x1CC000, reg_874);
  1126. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1127. reg_c70);
  1128. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1129. reg_85c);
  1130. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1131. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1132. }
  1133. dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
  1134. }
  1135. }
  1136. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1137. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1138. {
  1139. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1140. struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
  1141. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1142. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1143. if (((mac->link_state == MAC80211_NOLINK)) &&
  1144. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1145. dm_pstable->rssi_val_min = 0;
  1146. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
  1147. }
  1148. if (mac->link_state == MAC80211_LINKED) {
  1149. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1150. dm_pstable->rssi_val_min =
  1151. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1152. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1153. "AP Client PWDB = 0x%lx\n",
  1154. dm_pstable->rssi_val_min);
  1155. } else {
  1156. dm_pstable->rssi_val_min =
  1157. rtlpriv->dm.undecorated_smoothed_pwdb;
  1158. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1159. "STA Default Port PWDB = 0x%lx\n",
  1160. dm_pstable->rssi_val_min);
  1161. }
  1162. } else {
  1163. dm_pstable->rssi_val_min =
  1164. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1165. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1166. "AP Ext Port PWDB = 0x%lx\n",
  1167. dm_pstable->rssi_val_min);
  1168. }
  1169. if (IS_92C_SERIAL(rtlhal->version))
  1170. ;/* rtl92c_dm_1r_cca(hw); */
  1171. else
  1172. rtl92c_dm_rf_saving(hw, false);
  1173. }
  1174. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1175. {
  1176. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1177. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1178. rtl92c_dm_diginit(hw);
  1179. rtl92c_dm_init_dynamic_txpower(hw);
  1180. rtl92c_dm_init_edca_turbo(hw);
  1181. rtl92c_dm_init_rate_adaptive_mask(hw);
  1182. rtl92c_dm_initialize_txpower_tracking(hw);
  1183. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1184. }
  1185. EXPORT_SYMBOL(rtl92c_dm_init);
  1186. void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  1187. {
  1188. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1189. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1190. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1191. long undecorated_smoothed_pwdb;
  1192. if (!rtlpriv->dm.dynamic_txpower_enable)
  1193. return;
  1194. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  1195. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1196. return;
  1197. }
  1198. if ((mac->link_state < MAC80211_LINKED) &&
  1199. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1200. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1201. "Not connected to any\n");
  1202. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1203. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  1204. return;
  1205. }
  1206. if (mac->link_state >= MAC80211_LINKED) {
  1207. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1208. undecorated_smoothed_pwdb =
  1209. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1210. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1211. "AP Client PWDB = 0x%lx\n",
  1212. undecorated_smoothed_pwdb);
  1213. } else {
  1214. undecorated_smoothed_pwdb =
  1215. rtlpriv->dm.undecorated_smoothed_pwdb;
  1216. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1217. "STA Default Port PWDB = 0x%lx\n",
  1218. undecorated_smoothed_pwdb);
  1219. }
  1220. } else {
  1221. undecorated_smoothed_pwdb =
  1222. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1223. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1224. "AP Ext Port PWDB = 0x%lx\n",
  1225. undecorated_smoothed_pwdb);
  1226. }
  1227. if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  1228. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1229. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1230. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
  1231. } else if ((undecorated_smoothed_pwdb <
  1232. (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  1233. (undecorated_smoothed_pwdb >=
  1234. TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  1235. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1236. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1237. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
  1238. } else if (undecorated_smoothed_pwdb <
  1239. (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  1240. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1241. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1242. "TXHIGHPWRLEVEL_NORMAL\n");
  1243. }
  1244. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  1245. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1246. "PHY_SetTxPowerLevel8192S() Channel = %d\n",
  1247. rtlphy->current_channel);
  1248. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  1249. }
  1250. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  1251. }
  1252. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1253. {
  1254. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1255. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1256. bool fw_current_inpsmode = false;
  1257. bool fw_ps_awake = true;
  1258. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1259. (u8 *) (&fw_current_inpsmode));
  1260. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1261. (u8 *) (&fw_ps_awake));
  1262. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1263. fw_ps_awake)
  1264. && (!ppsc->rfchange_inprogress)) {
  1265. rtl92c_dm_pwdb_monitor(hw);
  1266. rtl92c_dm_dig(hw);
  1267. rtl92c_dm_false_alarm_counter_statistics(hw);
  1268. rtl92c_dm_dynamic_bb_powersaving(hw);
  1269. rtl92c_dm_dynamic_txpower(hw);
  1270. rtl92c_dm_check_txpower_tracking(hw);
  1271. rtl92c_dm_refresh_rate_adaptive_mask(hw);
  1272. rtl92c_dm_bt_coexist(hw);
  1273. rtl92c_dm_check_edca_turbo(hw);
  1274. }
  1275. }
  1276. EXPORT_SYMBOL(rtl92c_dm_watchdog);
  1277. u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
  1278. {
  1279. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1280. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1281. long undecorated_smoothed_pwdb;
  1282. u8 curr_bt_rssi_state = 0x00;
  1283. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1284. undecorated_smoothed_pwdb =
  1285. GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
  1286. } else {
  1287. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)
  1288. undecorated_smoothed_pwdb = 100;
  1289. else
  1290. undecorated_smoothed_pwdb =
  1291. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1292. }
  1293. /* Check RSSI to determine HighPower/NormalPower state for
  1294. * BT coexistence. */
  1295. if (undecorated_smoothed_pwdb >= 67)
  1296. curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
  1297. else if (undecorated_smoothed_pwdb < 62)
  1298. curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
  1299. /* Check RSSI to determine AMPDU setting for BT coexistence. */
  1300. if (undecorated_smoothed_pwdb >= 40)
  1301. curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
  1302. else if (undecorated_smoothed_pwdb <= 32)
  1303. curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
  1304. /* Marked RSSI state. It will be used to determine BT coexistence
  1305. * setting later. */
  1306. if (undecorated_smoothed_pwdb < 35)
  1307. curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
  1308. else
  1309. curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
  1310. /* Set Tx Power according to BT status. */
  1311. if (undecorated_smoothed_pwdb >= 30)
  1312. curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
  1313. else if (undecorated_smoothed_pwdb < 25)
  1314. curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
  1315. /* Check BT state related to BT_Idle in B/G mode. */
  1316. if (undecorated_smoothed_pwdb < 15)
  1317. curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
  1318. else
  1319. curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
  1320. if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
  1321. rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
  1322. return true;
  1323. } else {
  1324. return false;
  1325. }
  1326. }
  1327. EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
  1328. static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
  1329. {
  1330. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1331. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1332. u32 polling, ratio_tx, ratio_pri;
  1333. u32 bt_tx, bt_pri;
  1334. u8 bt_state;
  1335. u8 cur_service_type;
  1336. if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
  1337. return false;
  1338. bt_state = rtl_read_byte(rtlpriv, 0x4fd);
  1339. bt_tx = rtl_read_dword(rtlpriv, 0x488);
  1340. bt_tx = bt_tx & 0x00ffffff;
  1341. bt_pri = rtl_read_dword(rtlpriv, 0x48c);
  1342. bt_pri = bt_pri & 0x00ffffff;
  1343. polling = rtl_read_dword(rtlpriv, 0x490);
  1344. if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
  1345. polling == 0xffffffff && bt_state == 0xff)
  1346. return false;
  1347. bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
  1348. if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
  1349. rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
  1350. if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1351. rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
  1352. bt_state = bt_state |
  1353. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1354. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1355. BIT_OFFSET_LEN_MASK_32(2, 1);
  1356. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1357. }
  1358. return true;
  1359. }
  1360. ratio_tx = bt_tx * 1000 / polling;
  1361. ratio_pri = bt_pri * 1000 / polling;
  1362. rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
  1363. rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
  1364. if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1365. if ((ratio_tx < 30) && (ratio_pri < 30))
  1366. cur_service_type = BT_IDLE;
  1367. else if ((ratio_pri > 110) && (ratio_pri < 250))
  1368. cur_service_type = BT_SCO;
  1369. else if ((ratio_tx >= 200) && (ratio_pri >= 200))
  1370. cur_service_type = BT_BUSY;
  1371. else if ((ratio_tx >= 350) && (ratio_tx < 500))
  1372. cur_service_type = BT_OTHERBUSY;
  1373. else if (ratio_tx >= 500)
  1374. cur_service_type = BT_PAN;
  1375. else
  1376. cur_service_type = BT_OTHER_ACTION;
  1377. if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
  1378. rtlpcipriv->bt_coexist.bt_service = cur_service_type;
  1379. bt_state = bt_state |
  1380. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1381. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1382. ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
  1383. 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
  1384. /* Add interrupt migration when bt is not ini
  1385. * idle state (no traffic). */
  1386. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1387. rtl_write_word(rtlpriv, 0x504, 0x0ccc);
  1388. rtl_write_byte(rtlpriv, 0x506, 0x54);
  1389. rtl_write_byte(rtlpriv, 0x507, 0x54);
  1390. } else {
  1391. rtl_write_byte(rtlpriv, 0x506, 0x00);
  1392. rtl_write_byte(rtlpriv, 0x507, 0x00);
  1393. }
  1394. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1395. return true;
  1396. }
  1397. }
  1398. return false;
  1399. }
  1400. static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
  1401. {
  1402. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1403. static bool media_connect;
  1404. if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1405. media_connect = false;
  1406. } else {
  1407. if (!media_connect) {
  1408. media_connect = true;
  1409. return true;
  1410. }
  1411. media_connect = true;
  1412. }
  1413. return false;
  1414. }
  1415. static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
  1416. {
  1417. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1418. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1419. if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
  1420. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
  1421. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
  1422. } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
  1423. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
  1424. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
  1425. } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
  1426. if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
  1427. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
  1428. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
  1429. } else {
  1430. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
  1431. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
  1432. }
  1433. } else {
  1434. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1435. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1436. }
  1437. if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
  1438. (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
  1439. (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
  1440. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1441. BT_RSSI_STATE_BG_EDCA_LOW)) {
  1442. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
  1443. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
  1444. }
  1445. }
  1446. static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
  1447. {
  1448. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1449. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1450. /* Only enable HW BT coexist when BT in "Busy" state. */
  1451. if (rtlpriv->mac80211.vendor == PEER_CISCO &&
  1452. rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
  1453. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1454. } else {
  1455. if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
  1456. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1457. BT_RSSI_STATE_NORMAL_POWER)) {
  1458. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1459. } else if ((rtlpcipriv->bt_coexist.bt_service ==
  1460. BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
  1461. WIRELESS_MODE_N_24G) &&
  1462. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1463. BT_RSSI_STATE_SPECIAL_LOW)) {
  1464. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1465. } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
  1466. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1467. } else {
  1468. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1469. }
  1470. }
  1471. if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
  1472. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
  1473. else
  1474. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
  1475. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1476. BT_RSSI_STATE_NORMAL_POWER) {
  1477. rtl92c_bt_set_normal(hw);
  1478. } else {
  1479. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1480. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1481. }
  1482. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1483. rtlpriv->cfg->ops->set_rfreg(hw,
  1484. RF90_PATH_A,
  1485. 0x1e,
  1486. 0xf0, 0xf);
  1487. } else {
  1488. rtlpriv->cfg->ops->set_rfreg(hw,
  1489. RF90_PATH_A, 0x1e, 0xf0,
  1490. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1491. }
  1492. if (!rtlpriv->dm.dynamic_txpower_enable) {
  1493. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1494. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1495. BT_RSSI_STATE_TXPOWER_LOW) {
  1496. rtlpriv->dm.dynamic_txhighpower_lvl =
  1497. TXHIGHPWRLEVEL_BT2;
  1498. } else {
  1499. rtlpriv->dm.dynamic_txhighpower_lvl =
  1500. TXHIGHPWRLEVEL_BT1;
  1501. }
  1502. } else {
  1503. rtlpriv->dm.dynamic_txhighpower_lvl =
  1504. TXHIGHPWRLEVEL_NORMAL;
  1505. }
  1506. rtl92c_phy_set_txpower_level(hw,
  1507. rtlpriv->phy.current_channel);
  1508. }
  1509. }
  1510. static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
  1511. {
  1512. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1513. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1514. if (rtlpcipriv->bt_coexist.bt_cur_state) {
  1515. if (rtlpcipriv->bt_coexist.bt_ant_isolation)
  1516. rtl92c_bt_ant_isolation(hw);
  1517. } else {
  1518. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1519. rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
  1520. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1521. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1522. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1523. }
  1524. }
  1525. void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
  1526. {
  1527. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1528. bool wifi_connect_change;
  1529. bool bt_state_change;
  1530. bool rssi_state_change;
  1531. if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
  1532. (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
  1533. wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
  1534. bt_state_change = rtl92c_bt_state_change(hw);
  1535. rssi_state_change = rtl92c_bt_rssi_state_change(hw);
  1536. if (wifi_connect_change || bt_state_change || rssi_state_change)
  1537. rtl92c_check_bt_change(hw);
  1538. }
  1539. }
  1540. EXPORT_SYMBOL(rtl92c_dm_bt_coexist);