main.c 59 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK))) {
  117. mode = ATH9K_PM_NETWORK_SLEEP;
  118. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  119. ath9k_btcoex_stop_gen_timer(sc);
  120. } else {
  121. goto unlock;
  122. }
  123. spin_lock(&common->cc_lock);
  124. ath_hw_cycle_counters_update(common);
  125. spin_unlock(&common->cc_lock);
  126. ath9k_hw_setpower(sc->sc_ah, mode);
  127. unlock:
  128. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  129. }
  130. static void __ath_cancel_work(struct ath_softc *sc)
  131. {
  132. cancel_work_sync(&sc->paprd_work);
  133. cancel_work_sync(&sc->hw_check_work);
  134. cancel_delayed_work_sync(&sc->tx_complete_work);
  135. cancel_delayed_work_sync(&sc->hw_pll_work);
  136. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  137. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  138. cancel_work_sync(&sc->mci_work);
  139. #endif
  140. }
  141. static void ath_cancel_work(struct ath_softc *sc)
  142. {
  143. __ath_cancel_work(sc);
  144. cancel_work_sync(&sc->hw_reset_work);
  145. }
  146. static void ath_restart_work(struct ath_softc *sc)
  147. {
  148. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  149. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  150. AR_SREV_9550(sc->sc_ah))
  151. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  152. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  153. ath_start_rx_poll(sc, 3);
  154. ath_start_ani(sc);
  155. }
  156. static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
  157. {
  158. struct ath_hw *ah = sc->sc_ah;
  159. bool ret = true;
  160. ieee80211_stop_queues(sc->hw);
  161. sc->hw_busy_count = 0;
  162. ath_stop_ani(sc);
  163. del_timer_sync(&sc->rx_poll_timer);
  164. ath9k_debug_samp_bb_mac(sc);
  165. ath9k_hw_disable_interrupts(ah);
  166. if (!ath_stoprecv(sc))
  167. ret = false;
  168. if (!ath_drain_all_txq(sc, retry_tx))
  169. ret = false;
  170. if (!flush) {
  171. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  172. ath_rx_tasklet(sc, 1, true);
  173. ath_rx_tasklet(sc, 1, false);
  174. } else {
  175. ath_flushrecv(sc);
  176. }
  177. return ret;
  178. }
  179. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  180. {
  181. struct ath_hw *ah = sc->sc_ah;
  182. struct ath_common *common = ath9k_hw_common(ah);
  183. unsigned long flags;
  184. if (ath_startrecv(sc) != 0) {
  185. ath_err(common, "Unable to restart recv logic\n");
  186. return false;
  187. }
  188. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  189. sc->config.txpowlimit, &sc->curtxpow);
  190. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  191. ath9k_hw_set_interrupts(ah);
  192. ath9k_hw_enable_interrupts(ah);
  193. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  194. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  195. goto work;
  196. ath9k_set_beacon(sc);
  197. if (ah->opmode == NL80211_IFTYPE_STATION &&
  198. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  199. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  200. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  201. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  202. }
  203. work:
  204. ath_restart_work(sc);
  205. }
  206. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  207. ath_ant_comb_update(sc);
  208. ieee80211_wake_queues(sc->hw);
  209. return true;
  210. }
  211. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
  212. bool retry_tx)
  213. {
  214. struct ath_hw *ah = sc->sc_ah;
  215. struct ath_common *common = ath9k_hw_common(ah);
  216. struct ath9k_hw_cal_data *caldata = NULL;
  217. bool fastcc = true;
  218. bool flush = false;
  219. int r;
  220. __ath_cancel_work(sc);
  221. spin_lock_bh(&sc->sc_pcu_lock);
  222. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  223. fastcc = false;
  224. caldata = &sc->caldata;
  225. }
  226. if (!hchan) {
  227. fastcc = false;
  228. flush = true;
  229. hchan = ah->curchan;
  230. }
  231. if (!ath_prepare_reset(sc, retry_tx, flush))
  232. fastcc = false;
  233. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  234. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  235. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  236. if (r) {
  237. ath_err(common,
  238. "Unable to reset channel, reset status %d\n", r);
  239. goto out;
  240. }
  241. if (!ath_complete_reset(sc, true))
  242. r = -EIO;
  243. out:
  244. spin_unlock_bh(&sc->sc_pcu_lock);
  245. return r;
  246. }
  247. /*
  248. * Set/change channels. If the channel is really being changed, it's done
  249. * by reseting the chip. To accomplish this we must first cleanup any pending
  250. * DMA, then restart stuff.
  251. */
  252. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  253. struct ath9k_channel *hchan)
  254. {
  255. int r;
  256. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  257. return -EIO;
  258. r = ath_reset_internal(sc, hchan, false);
  259. return r;
  260. }
  261. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  262. struct ieee80211_vif *vif)
  263. {
  264. struct ath_node *an;
  265. u8 density;
  266. an = (struct ath_node *)sta->drv_priv;
  267. #ifdef CONFIG_ATH9K_DEBUGFS
  268. spin_lock(&sc->nodes_lock);
  269. list_add(&an->list, &sc->nodes);
  270. spin_unlock(&sc->nodes_lock);
  271. #endif
  272. an->sta = sta;
  273. an->vif = vif;
  274. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  275. ath_tx_node_init(sc, an);
  276. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  277. sta->ht_cap.ampdu_factor);
  278. density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  279. an->mpdudensity = density;
  280. }
  281. }
  282. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  283. {
  284. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  285. #ifdef CONFIG_ATH9K_DEBUGFS
  286. spin_lock(&sc->nodes_lock);
  287. list_del(&an->list);
  288. spin_unlock(&sc->nodes_lock);
  289. an->sta = NULL;
  290. #endif
  291. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  292. ath_tx_node_cleanup(sc, an);
  293. }
  294. void ath9k_tasklet(unsigned long data)
  295. {
  296. struct ath_softc *sc = (struct ath_softc *)data;
  297. struct ath_hw *ah = sc->sc_ah;
  298. struct ath_common *common = ath9k_hw_common(ah);
  299. enum ath_reset_type type;
  300. unsigned long flags;
  301. u32 status = sc->intrstatus;
  302. u32 rxmask;
  303. ath9k_ps_wakeup(sc);
  304. spin_lock(&sc->sc_pcu_lock);
  305. if ((status & ATH9K_INT_FATAL) ||
  306. (status & ATH9K_INT_BB_WATCHDOG)) {
  307. if (status & ATH9K_INT_FATAL)
  308. type = RESET_TYPE_FATAL_INT;
  309. else
  310. type = RESET_TYPE_BB_WATCHDOG;
  311. ath9k_queue_reset(sc, type);
  312. goto out;
  313. }
  314. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  315. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  316. /*
  317. * TSF sync does not look correct; remain awake to sync with
  318. * the next Beacon.
  319. */
  320. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  321. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  322. }
  323. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  324. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  325. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  326. ATH9K_INT_RXORN);
  327. else
  328. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  329. if (status & rxmask) {
  330. /* Check for high priority Rx first */
  331. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  332. (status & ATH9K_INT_RXHP))
  333. ath_rx_tasklet(sc, 0, true);
  334. ath_rx_tasklet(sc, 0, false);
  335. }
  336. if (status & ATH9K_INT_TX) {
  337. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  338. ath_tx_edma_tasklet(sc);
  339. else
  340. ath_tx_tasklet(sc);
  341. }
  342. ath9k_btcoex_handle_interrupt(sc, status);
  343. out:
  344. /* re-enable hardware interrupt */
  345. ath9k_hw_enable_interrupts(ah);
  346. spin_unlock(&sc->sc_pcu_lock);
  347. ath9k_ps_restore(sc);
  348. }
  349. irqreturn_t ath_isr(int irq, void *dev)
  350. {
  351. #define SCHED_INTR ( \
  352. ATH9K_INT_FATAL | \
  353. ATH9K_INT_BB_WATCHDOG | \
  354. ATH9K_INT_RXORN | \
  355. ATH9K_INT_RXEOL | \
  356. ATH9K_INT_RX | \
  357. ATH9K_INT_RXLP | \
  358. ATH9K_INT_RXHP | \
  359. ATH9K_INT_TX | \
  360. ATH9K_INT_BMISS | \
  361. ATH9K_INT_CST | \
  362. ATH9K_INT_TSFOOR | \
  363. ATH9K_INT_GENTIMER | \
  364. ATH9K_INT_MCI)
  365. struct ath_softc *sc = dev;
  366. struct ath_hw *ah = sc->sc_ah;
  367. struct ath_common *common = ath9k_hw_common(ah);
  368. enum ath9k_int status;
  369. bool sched = false;
  370. /*
  371. * The hardware is not ready/present, don't
  372. * touch anything. Note this can happen early
  373. * on if the IRQ is shared.
  374. */
  375. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  376. return IRQ_NONE;
  377. /* shared irq, not for us */
  378. if (!ath9k_hw_intrpend(ah))
  379. return IRQ_NONE;
  380. if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
  381. return IRQ_HANDLED;
  382. /*
  383. * Figure out the reason(s) for the interrupt. Note
  384. * that the hal returns a pseudo-ISR that may include
  385. * bits we haven't explicitly enabled so we mask the
  386. * value to insure we only process bits we requested.
  387. */
  388. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  389. status &= ah->imask; /* discard unasked-for bits */
  390. /*
  391. * If there are no status bits set, then this interrupt was not
  392. * for me (should have been caught above).
  393. */
  394. if (!status)
  395. return IRQ_NONE;
  396. /* Cache the status */
  397. sc->intrstatus = status;
  398. if (status & SCHED_INTR)
  399. sched = true;
  400. #ifdef CONFIG_PM_SLEEP
  401. if (status & ATH9K_INT_BMISS) {
  402. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  403. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  404. atomic_inc(&sc->wow_got_bmiss_intr);
  405. atomic_dec(&sc->wow_sleep_proc_intr);
  406. }
  407. ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
  408. }
  409. #endif
  410. /*
  411. * If a FATAL or RXORN interrupt is received, we have to reset the
  412. * chip immediately.
  413. */
  414. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  415. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  416. goto chip_reset;
  417. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  418. (status & ATH9K_INT_BB_WATCHDOG)) {
  419. spin_lock(&common->cc_lock);
  420. ath_hw_cycle_counters_update(common);
  421. ar9003_hw_bb_watchdog_dbg_info(ah);
  422. spin_unlock(&common->cc_lock);
  423. goto chip_reset;
  424. }
  425. if (status & ATH9K_INT_SWBA)
  426. tasklet_schedule(&sc->bcon_tasklet);
  427. if (status & ATH9K_INT_TXURN)
  428. ath9k_hw_updatetxtriglevel(ah, true);
  429. if (status & ATH9K_INT_RXEOL) {
  430. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  431. ath9k_hw_set_interrupts(ah);
  432. }
  433. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  434. if (status & ATH9K_INT_TIM_TIMER) {
  435. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  436. goto chip_reset;
  437. /* Clear RxAbort bit so that we can
  438. * receive frames */
  439. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  440. spin_lock(&sc->sc_pm_lock);
  441. ath9k_hw_setrxabort(sc->sc_ah, 0);
  442. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  443. spin_unlock(&sc->sc_pm_lock);
  444. }
  445. chip_reset:
  446. ath_debug_stat_interrupt(sc, status);
  447. if (sched) {
  448. /* turn off every interrupt */
  449. ath9k_hw_disable_interrupts(ah);
  450. tasklet_schedule(&sc->intr_tq);
  451. }
  452. return IRQ_HANDLED;
  453. #undef SCHED_INTR
  454. }
  455. static int ath_reset(struct ath_softc *sc, bool retry_tx)
  456. {
  457. int r;
  458. ath9k_ps_wakeup(sc);
  459. r = ath_reset_internal(sc, NULL, retry_tx);
  460. if (retry_tx) {
  461. int i;
  462. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  463. if (ATH_TXQ_SETUP(sc, i)) {
  464. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  465. ath_txq_schedule(sc, &sc->tx.txq[i]);
  466. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  467. }
  468. }
  469. }
  470. ath9k_ps_restore(sc);
  471. return r;
  472. }
  473. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  474. {
  475. #ifdef CONFIG_ATH9K_DEBUGFS
  476. RESET_STAT_INC(sc, type);
  477. #endif
  478. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  479. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  480. }
  481. void ath_reset_work(struct work_struct *work)
  482. {
  483. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  484. ath_reset(sc, true);
  485. }
  486. /**********************/
  487. /* mac80211 callbacks */
  488. /**********************/
  489. static int ath9k_start(struct ieee80211_hw *hw)
  490. {
  491. struct ath_softc *sc = hw->priv;
  492. struct ath_hw *ah = sc->sc_ah;
  493. struct ath_common *common = ath9k_hw_common(ah);
  494. struct ieee80211_channel *curchan = hw->conf.channel;
  495. struct ath9k_channel *init_channel;
  496. int r;
  497. ath_dbg(common, CONFIG,
  498. "Starting driver with initial channel: %d MHz\n",
  499. curchan->center_freq);
  500. ath9k_ps_wakeup(sc);
  501. mutex_lock(&sc->mutex);
  502. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  503. /* Reset SERDES registers */
  504. ath9k_hw_configpcipowersave(ah, false);
  505. /*
  506. * The basic interface to setting the hardware in a good
  507. * state is ``reset''. On return the hardware is known to
  508. * be powered up and with interrupts disabled. This must
  509. * be followed by initialization of the appropriate bits
  510. * and then setup of the interrupt mask.
  511. */
  512. spin_lock_bh(&sc->sc_pcu_lock);
  513. atomic_set(&ah->intr_ref_cnt, -1);
  514. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  515. if (r) {
  516. ath_err(common,
  517. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  518. r, curchan->center_freq);
  519. spin_unlock_bh(&sc->sc_pcu_lock);
  520. goto mutex_unlock;
  521. }
  522. /* Setup our intr mask. */
  523. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  524. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  525. ATH9K_INT_GLOBAL;
  526. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  527. ah->imask |= ATH9K_INT_RXHP |
  528. ATH9K_INT_RXLP |
  529. ATH9K_INT_BB_WATCHDOG;
  530. else
  531. ah->imask |= ATH9K_INT_RX;
  532. ah->imask |= ATH9K_INT_GTT;
  533. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  534. ah->imask |= ATH9K_INT_CST;
  535. ath_mci_enable(sc);
  536. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  537. sc->sc_ah->is_monitoring = false;
  538. if (!ath_complete_reset(sc, false)) {
  539. r = -EIO;
  540. spin_unlock_bh(&sc->sc_pcu_lock);
  541. goto mutex_unlock;
  542. }
  543. if (ah->led_pin >= 0) {
  544. ath9k_hw_cfg_output(ah, ah->led_pin,
  545. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  546. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  547. }
  548. /*
  549. * Reset key cache to sane defaults (all entries cleared) instead of
  550. * semi-random values after suspend/resume.
  551. */
  552. ath9k_cmn_init_crypto(sc->sc_ah);
  553. spin_unlock_bh(&sc->sc_pcu_lock);
  554. if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
  555. common->bus_ops->extn_synch_en(common);
  556. mutex_unlock:
  557. mutex_unlock(&sc->mutex);
  558. ath9k_ps_restore(sc);
  559. return r;
  560. }
  561. static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  562. {
  563. struct ath_softc *sc = hw->priv;
  564. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  565. struct ath_tx_control txctl;
  566. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  567. unsigned long flags;
  568. if (sc->ps_enabled) {
  569. /*
  570. * mac80211 does not set PM field for normal data frames, so we
  571. * need to update that based on the current PS mode.
  572. */
  573. if (ieee80211_is_data(hdr->frame_control) &&
  574. !ieee80211_is_nullfunc(hdr->frame_control) &&
  575. !ieee80211_has_pm(hdr->frame_control)) {
  576. ath_dbg(common, PS,
  577. "Add PM=1 for a TX frame while in PS mode\n");
  578. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  579. }
  580. }
  581. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  582. /*
  583. * We are using PS-Poll and mac80211 can request TX while in
  584. * power save mode. Need to wake up hardware for the TX to be
  585. * completed and if needed, also for RX of buffered frames.
  586. */
  587. ath9k_ps_wakeup(sc);
  588. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  589. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  590. ath9k_hw_setrxabort(sc->sc_ah, 0);
  591. if (ieee80211_is_pspoll(hdr->frame_control)) {
  592. ath_dbg(common, PS,
  593. "Sending PS-Poll to pick a buffered frame\n");
  594. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  595. } else {
  596. ath_dbg(common, PS, "Wake up to complete TX\n");
  597. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  598. }
  599. /*
  600. * The actual restore operation will happen only after
  601. * the ps_flags bit is cleared. We are just dropping
  602. * the ps_usecount here.
  603. */
  604. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  605. ath9k_ps_restore(sc);
  606. }
  607. /*
  608. * Cannot tx while the hardware is in full sleep, it first needs a full
  609. * chip reset to recover from that
  610. */
  611. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  612. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  613. goto exit;
  614. }
  615. memset(&txctl, 0, sizeof(struct ath_tx_control));
  616. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  617. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  618. if (ath_tx_start(hw, skb, &txctl) != 0) {
  619. ath_dbg(common, XMIT, "TX failed\n");
  620. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  621. goto exit;
  622. }
  623. return;
  624. exit:
  625. dev_kfree_skb_any(skb);
  626. }
  627. static void ath9k_stop(struct ieee80211_hw *hw)
  628. {
  629. struct ath_softc *sc = hw->priv;
  630. struct ath_hw *ah = sc->sc_ah;
  631. struct ath_common *common = ath9k_hw_common(ah);
  632. bool prev_idle;
  633. mutex_lock(&sc->mutex);
  634. ath_cancel_work(sc);
  635. del_timer_sync(&sc->rx_poll_timer);
  636. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  637. ath_dbg(common, ANY, "Device not present\n");
  638. mutex_unlock(&sc->mutex);
  639. return;
  640. }
  641. /* Ensure HW is awake when we try to shut it down. */
  642. ath9k_ps_wakeup(sc);
  643. spin_lock_bh(&sc->sc_pcu_lock);
  644. /* prevent tasklets to enable interrupts once we disable them */
  645. ah->imask &= ~ATH9K_INT_GLOBAL;
  646. /* make sure h/w will not generate any interrupt
  647. * before setting the invalid flag. */
  648. ath9k_hw_disable_interrupts(ah);
  649. spin_unlock_bh(&sc->sc_pcu_lock);
  650. /* we can now sync irq and kill any running tasklets, since we already
  651. * disabled interrupts and not holding a spin lock */
  652. synchronize_irq(sc->irq);
  653. tasklet_kill(&sc->intr_tq);
  654. tasklet_kill(&sc->bcon_tasklet);
  655. prev_idle = sc->ps_idle;
  656. sc->ps_idle = true;
  657. spin_lock_bh(&sc->sc_pcu_lock);
  658. if (ah->led_pin >= 0) {
  659. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  660. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  661. }
  662. ath_prepare_reset(sc, false, true);
  663. if (sc->rx.frag) {
  664. dev_kfree_skb_any(sc->rx.frag);
  665. sc->rx.frag = NULL;
  666. }
  667. if (!ah->curchan)
  668. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  669. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  670. ath9k_hw_phy_disable(ah);
  671. ath9k_hw_configpcipowersave(ah, true);
  672. spin_unlock_bh(&sc->sc_pcu_lock);
  673. ath9k_ps_restore(sc);
  674. set_bit(SC_OP_INVALID, &sc->sc_flags);
  675. sc->ps_idle = prev_idle;
  676. mutex_unlock(&sc->mutex);
  677. ath_dbg(common, CONFIG, "Driver halt\n");
  678. }
  679. bool ath9k_uses_beacons(int type)
  680. {
  681. switch (type) {
  682. case NL80211_IFTYPE_AP:
  683. case NL80211_IFTYPE_ADHOC:
  684. case NL80211_IFTYPE_MESH_POINT:
  685. return true;
  686. default:
  687. return false;
  688. }
  689. }
  690. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  691. {
  692. struct ath9k_vif_iter_data *iter_data = data;
  693. int i;
  694. if (iter_data->hw_macaddr)
  695. for (i = 0; i < ETH_ALEN; i++)
  696. iter_data->mask[i] &=
  697. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  698. switch (vif->type) {
  699. case NL80211_IFTYPE_AP:
  700. iter_data->naps++;
  701. break;
  702. case NL80211_IFTYPE_STATION:
  703. iter_data->nstations++;
  704. break;
  705. case NL80211_IFTYPE_ADHOC:
  706. iter_data->nadhocs++;
  707. break;
  708. case NL80211_IFTYPE_MESH_POINT:
  709. iter_data->nmeshes++;
  710. break;
  711. case NL80211_IFTYPE_WDS:
  712. iter_data->nwds++;
  713. break;
  714. default:
  715. break;
  716. }
  717. }
  718. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  719. {
  720. struct ath_softc *sc = data;
  721. struct ath_vif *avp = (void *)vif->drv_priv;
  722. if (vif->type != NL80211_IFTYPE_STATION)
  723. return;
  724. if (avp->primary_sta_vif)
  725. ath9k_set_assoc_state(sc, vif);
  726. }
  727. /* Called with sc->mutex held. */
  728. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  729. struct ieee80211_vif *vif,
  730. struct ath9k_vif_iter_data *iter_data)
  731. {
  732. struct ath_softc *sc = hw->priv;
  733. struct ath_hw *ah = sc->sc_ah;
  734. struct ath_common *common = ath9k_hw_common(ah);
  735. /*
  736. * Use the hardware MAC address as reference, the hardware uses it
  737. * together with the BSSID mask when matching addresses.
  738. */
  739. memset(iter_data, 0, sizeof(*iter_data));
  740. iter_data->hw_macaddr = common->macaddr;
  741. memset(&iter_data->mask, 0xff, ETH_ALEN);
  742. if (vif)
  743. ath9k_vif_iter(iter_data, vif->addr, vif);
  744. /* Get list of all active MAC addresses */
  745. ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
  746. iter_data);
  747. }
  748. /* Called with sc->mutex held. */
  749. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  750. struct ieee80211_vif *vif)
  751. {
  752. struct ath_softc *sc = hw->priv;
  753. struct ath_hw *ah = sc->sc_ah;
  754. struct ath_common *common = ath9k_hw_common(ah);
  755. struct ath9k_vif_iter_data iter_data;
  756. enum nl80211_iftype old_opmode = ah->opmode;
  757. ath9k_calculate_iter_data(hw, vif, &iter_data);
  758. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  759. ath_hw_setbssidmask(common);
  760. if (iter_data.naps > 0) {
  761. ath9k_hw_set_tsfadjust(ah, true);
  762. ah->opmode = NL80211_IFTYPE_AP;
  763. } else {
  764. ath9k_hw_set_tsfadjust(ah, false);
  765. if (iter_data.nmeshes)
  766. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  767. else if (iter_data.nwds)
  768. ah->opmode = NL80211_IFTYPE_AP;
  769. else if (iter_data.nadhocs)
  770. ah->opmode = NL80211_IFTYPE_ADHOC;
  771. else
  772. ah->opmode = NL80211_IFTYPE_STATION;
  773. }
  774. ath9k_hw_setopmode(ah);
  775. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  776. ah->imask |= ATH9K_INT_TSFOOR;
  777. else
  778. ah->imask &= ~ATH9K_INT_TSFOOR;
  779. ath9k_hw_set_interrupts(ah);
  780. /*
  781. * If we are changing the opmode to STATION,
  782. * a beacon sync needs to be done.
  783. */
  784. if (ah->opmode == NL80211_IFTYPE_STATION &&
  785. old_opmode == NL80211_IFTYPE_AP &&
  786. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  787. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  788. ath9k_sta_vif_iter, sc);
  789. }
  790. }
  791. static int ath9k_add_interface(struct ieee80211_hw *hw,
  792. struct ieee80211_vif *vif)
  793. {
  794. struct ath_softc *sc = hw->priv;
  795. struct ath_hw *ah = sc->sc_ah;
  796. struct ath_common *common = ath9k_hw_common(ah);
  797. int ret = 0;
  798. ath9k_ps_wakeup(sc);
  799. mutex_lock(&sc->mutex);
  800. switch (vif->type) {
  801. case NL80211_IFTYPE_STATION:
  802. case NL80211_IFTYPE_WDS:
  803. case NL80211_IFTYPE_ADHOC:
  804. case NL80211_IFTYPE_AP:
  805. case NL80211_IFTYPE_MESH_POINT:
  806. break;
  807. default:
  808. ath_err(common, "Interface type %d not yet supported\n",
  809. vif->type);
  810. ret = -EOPNOTSUPP;
  811. goto out;
  812. }
  813. if (ath9k_uses_beacons(vif->type)) {
  814. if (sc->nbcnvifs >= ATH_BCBUF) {
  815. ath_err(common, "Not enough beacon buffers when adding"
  816. " new interface of type: %i\n",
  817. vif->type);
  818. ret = -ENOBUFS;
  819. goto out;
  820. }
  821. }
  822. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  823. sc->nvifs++;
  824. ath9k_calculate_summary_state(hw, vif);
  825. if (ath9k_uses_beacons(vif->type))
  826. ath9k_beacon_assign_slot(sc, vif);
  827. out:
  828. mutex_unlock(&sc->mutex);
  829. ath9k_ps_restore(sc);
  830. return ret;
  831. }
  832. static int ath9k_change_interface(struct ieee80211_hw *hw,
  833. struct ieee80211_vif *vif,
  834. enum nl80211_iftype new_type,
  835. bool p2p)
  836. {
  837. struct ath_softc *sc = hw->priv;
  838. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  839. int ret = 0;
  840. ath_dbg(common, CONFIG, "Change Interface\n");
  841. mutex_lock(&sc->mutex);
  842. ath9k_ps_wakeup(sc);
  843. if (ath9k_uses_beacons(new_type) &&
  844. !ath9k_uses_beacons(vif->type)) {
  845. if (sc->nbcnvifs >= ATH_BCBUF) {
  846. ath_err(common, "No beacon slot available\n");
  847. ret = -ENOBUFS;
  848. goto out;
  849. }
  850. }
  851. if (ath9k_uses_beacons(vif->type))
  852. ath9k_beacon_remove_slot(sc, vif);
  853. vif->type = new_type;
  854. vif->p2p = p2p;
  855. ath9k_calculate_summary_state(hw, vif);
  856. if (ath9k_uses_beacons(vif->type))
  857. ath9k_beacon_assign_slot(sc, vif);
  858. out:
  859. ath9k_ps_restore(sc);
  860. mutex_unlock(&sc->mutex);
  861. return ret;
  862. }
  863. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  864. struct ieee80211_vif *vif)
  865. {
  866. struct ath_softc *sc = hw->priv;
  867. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  868. ath_dbg(common, CONFIG, "Detach Interface\n");
  869. ath9k_ps_wakeup(sc);
  870. mutex_lock(&sc->mutex);
  871. sc->nvifs--;
  872. if (ath9k_uses_beacons(vif->type))
  873. ath9k_beacon_remove_slot(sc, vif);
  874. ath9k_calculate_summary_state(hw, NULL);
  875. mutex_unlock(&sc->mutex);
  876. ath9k_ps_restore(sc);
  877. }
  878. static void ath9k_enable_ps(struct ath_softc *sc)
  879. {
  880. struct ath_hw *ah = sc->sc_ah;
  881. struct ath_common *common = ath9k_hw_common(ah);
  882. sc->ps_enabled = true;
  883. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  884. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  885. ah->imask |= ATH9K_INT_TIM_TIMER;
  886. ath9k_hw_set_interrupts(ah);
  887. }
  888. ath9k_hw_setrxabort(ah, 1);
  889. }
  890. ath_dbg(common, PS, "PowerSave enabled\n");
  891. }
  892. static void ath9k_disable_ps(struct ath_softc *sc)
  893. {
  894. struct ath_hw *ah = sc->sc_ah;
  895. struct ath_common *common = ath9k_hw_common(ah);
  896. sc->ps_enabled = false;
  897. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  898. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  899. ath9k_hw_setrxabort(ah, 0);
  900. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  901. PS_WAIT_FOR_CAB |
  902. PS_WAIT_FOR_PSPOLL_DATA |
  903. PS_WAIT_FOR_TX_ACK);
  904. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  905. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  906. ath9k_hw_set_interrupts(ah);
  907. }
  908. }
  909. ath_dbg(common, PS, "PowerSave disabled\n");
  910. }
  911. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  912. {
  913. struct ath_softc *sc = hw->priv;
  914. struct ath_hw *ah = sc->sc_ah;
  915. struct ath_common *common = ath9k_hw_common(ah);
  916. struct ieee80211_conf *conf = &hw->conf;
  917. bool reset_channel = false;
  918. ath9k_ps_wakeup(sc);
  919. mutex_lock(&sc->mutex);
  920. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  921. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  922. if (sc->ps_idle) {
  923. ath_cancel_work(sc);
  924. ath9k_stop_btcoex(sc);
  925. } else {
  926. ath9k_start_btcoex(sc);
  927. /*
  928. * The chip needs a reset to properly wake up from
  929. * full sleep
  930. */
  931. reset_channel = ah->chip_fullsleep;
  932. }
  933. }
  934. /*
  935. * We just prepare to enable PS. We have to wait until our AP has
  936. * ACK'd our null data frame to disable RX otherwise we'll ignore
  937. * those ACKs and end up retransmitting the same null data frames.
  938. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  939. */
  940. if (changed & IEEE80211_CONF_CHANGE_PS) {
  941. unsigned long flags;
  942. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  943. if (conf->flags & IEEE80211_CONF_PS)
  944. ath9k_enable_ps(sc);
  945. else
  946. ath9k_disable_ps(sc);
  947. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  948. }
  949. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  950. if (conf->flags & IEEE80211_CONF_MONITOR) {
  951. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  952. sc->sc_ah->is_monitoring = true;
  953. } else {
  954. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  955. sc->sc_ah->is_monitoring = false;
  956. }
  957. }
  958. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  959. struct ieee80211_channel *curchan = hw->conf.channel;
  960. int pos = curchan->hw_value;
  961. int old_pos = -1;
  962. unsigned long flags;
  963. if (ah->curchan)
  964. old_pos = ah->curchan - &ah->channels[0];
  965. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  966. curchan->center_freq, conf->channel_type);
  967. /* update survey stats for the old channel before switching */
  968. spin_lock_irqsave(&common->cc_lock, flags);
  969. ath_update_survey_stats(sc);
  970. spin_unlock_irqrestore(&common->cc_lock, flags);
  971. /*
  972. * Preserve the current channel values, before updating
  973. * the same channel
  974. */
  975. if (ah->curchan && (old_pos == pos))
  976. ath9k_hw_getnf(ah, ah->curchan);
  977. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  978. curchan, conf->channel_type);
  979. /*
  980. * If the operating channel changes, change the survey in-use flags
  981. * along with it.
  982. * Reset the survey data for the new channel, unless we're switching
  983. * back to the operating channel from an off-channel operation.
  984. */
  985. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  986. sc->cur_survey != &sc->survey[pos]) {
  987. if (sc->cur_survey)
  988. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  989. sc->cur_survey = &sc->survey[pos];
  990. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  991. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  992. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  993. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  994. }
  995. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  996. ath_err(common, "Unable to set channel\n");
  997. mutex_unlock(&sc->mutex);
  998. ath9k_ps_restore(sc);
  999. return -EINVAL;
  1000. }
  1001. /*
  1002. * The most recent snapshot of channel->noisefloor for the old
  1003. * channel is only available after the hardware reset. Copy it to
  1004. * the survey stats now.
  1005. */
  1006. if (old_pos >= 0)
  1007. ath_update_survey_nf(sc, old_pos);
  1008. }
  1009. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1010. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1011. sc->config.txpowlimit = 2 * conf->power_level;
  1012. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1013. sc->config.txpowlimit, &sc->curtxpow);
  1014. }
  1015. mutex_unlock(&sc->mutex);
  1016. ath9k_ps_restore(sc);
  1017. return 0;
  1018. }
  1019. #define SUPPORTED_FILTERS \
  1020. (FIF_PROMISC_IN_BSS | \
  1021. FIF_ALLMULTI | \
  1022. FIF_CONTROL | \
  1023. FIF_PSPOLL | \
  1024. FIF_OTHER_BSS | \
  1025. FIF_BCN_PRBRESP_PROMISC | \
  1026. FIF_PROBE_REQ | \
  1027. FIF_FCSFAIL)
  1028. /* FIXME: sc->sc_full_reset ? */
  1029. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1030. unsigned int changed_flags,
  1031. unsigned int *total_flags,
  1032. u64 multicast)
  1033. {
  1034. struct ath_softc *sc = hw->priv;
  1035. u32 rfilt;
  1036. changed_flags &= SUPPORTED_FILTERS;
  1037. *total_flags &= SUPPORTED_FILTERS;
  1038. sc->rx.rxfilter = *total_flags;
  1039. ath9k_ps_wakeup(sc);
  1040. rfilt = ath_calcrxfilter(sc);
  1041. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1042. ath9k_ps_restore(sc);
  1043. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1044. rfilt);
  1045. }
  1046. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1047. struct ieee80211_vif *vif,
  1048. struct ieee80211_sta *sta)
  1049. {
  1050. struct ath_softc *sc = hw->priv;
  1051. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1052. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1053. struct ieee80211_key_conf ps_key = { };
  1054. ath_node_attach(sc, sta, vif);
  1055. if (vif->type != NL80211_IFTYPE_AP &&
  1056. vif->type != NL80211_IFTYPE_AP_VLAN)
  1057. return 0;
  1058. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1059. return 0;
  1060. }
  1061. static void ath9k_del_ps_key(struct ath_softc *sc,
  1062. struct ieee80211_vif *vif,
  1063. struct ieee80211_sta *sta)
  1064. {
  1065. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1066. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1067. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1068. if (!an->ps_key)
  1069. return;
  1070. ath_key_delete(common, &ps_key);
  1071. }
  1072. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1073. struct ieee80211_vif *vif,
  1074. struct ieee80211_sta *sta)
  1075. {
  1076. struct ath_softc *sc = hw->priv;
  1077. ath9k_del_ps_key(sc, vif, sta);
  1078. ath_node_detach(sc, sta);
  1079. return 0;
  1080. }
  1081. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1082. struct ieee80211_vif *vif,
  1083. enum sta_notify_cmd cmd,
  1084. struct ieee80211_sta *sta)
  1085. {
  1086. struct ath_softc *sc = hw->priv;
  1087. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1088. if (!sta->ht_cap.ht_supported)
  1089. return;
  1090. switch (cmd) {
  1091. case STA_NOTIFY_SLEEP:
  1092. an->sleeping = true;
  1093. ath_tx_aggr_sleep(sta, sc, an);
  1094. break;
  1095. case STA_NOTIFY_AWAKE:
  1096. an->sleeping = false;
  1097. ath_tx_aggr_wakeup(sc, an);
  1098. break;
  1099. }
  1100. }
  1101. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1102. struct ieee80211_vif *vif, u16 queue,
  1103. const struct ieee80211_tx_queue_params *params)
  1104. {
  1105. struct ath_softc *sc = hw->priv;
  1106. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1107. struct ath_txq *txq;
  1108. struct ath9k_tx_queue_info qi;
  1109. int ret = 0;
  1110. if (queue >= WME_NUM_AC)
  1111. return 0;
  1112. txq = sc->tx.txq_map[queue];
  1113. ath9k_ps_wakeup(sc);
  1114. mutex_lock(&sc->mutex);
  1115. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1116. qi.tqi_aifs = params->aifs;
  1117. qi.tqi_cwmin = params->cw_min;
  1118. qi.tqi_cwmax = params->cw_max;
  1119. qi.tqi_burstTime = params->txop * 32;
  1120. ath_dbg(common, CONFIG,
  1121. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1122. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1123. params->cw_max, params->txop);
  1124. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1125. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1126. if (ret)
  1127. ath_err(common, "TXQ Update failed\n");
  1128. mutex_unlock(&sc->mutex);
  1129. ath9k_ps_restore(sc);
  1130. return ret;
  1131. }
  1132. static int ath9k_set_key(struct ieee80211_hw *hw,
  1133. enum set_key_cmd cmd,
  1134. struct ieee80211_vif *vif,
  1135. struct ieee80211_sta *sta,
  1136. struct ieee80211_key_conf *key)
  1137. {
  1138. struct ath_softc *sc = hw->priv;
  1139. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1140. int ret = 0;
  1141. if (ath9k_modparam_nohwcrypt)
  1142. return -ENOSPC;
  1143. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1144. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1145. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1146. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1147. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1148. /*
  1149. * For now, disable hw crypto for the RSN IBSS group keys. This
  1150. * could be optimized in the future to use a modified key cache
  1151. * design to support per-STA RX GTK, but until that gets
  1152. * implemented, use of software crypto for group addressed
  1153. * frames is a acceptable to allow RSN IBSS to be used.
  1154. */
  1155. return -EOPNOTSUPP;
  1156. }
  1157. mutex_lock(&sc->mutex);
  1158. ath9k_ps_wakeup(sc);
  1159. ath_dbg(common, CONFIG, "Set HW Key\n");
  1160. switch (cmd) {
  1161. case SET_KEY:
  1162. if (sta)
  1163. ath9k_del_ps_key(sc, vif, sta);
  1164. ret = ath_key_config(common, vif, sta, key);
  1165. if (ret >= 0) {
  1166. key->hw_key_idx = ret;
  1167. /* push IV and Michael MIC generation to stack */
  1168. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1169. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1170. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1171. if (sc->sc_ah->sw_mgmt_crypto &&
  1172. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1173. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1174. ret = 0;
  1175. }
  1176. break;
  1177. case DISABLE_KEY:
  1178. ath_key_delete(common, key);
  1179. break;
  1180. default:
  1181. ret = -EINVAL;
  1182. }
  1183. ath9k_ps_restore(sc);
  1184. mutex_unlock(&sc->mutex);
  1185. return ret;
  1186. }
  1187. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1188. struct ieee80211_vif *vif)
  1189. {
  1190. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1191. struct ath_vif *avp = (void *)vif->drv_priv;
  1192. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1193. unsigned long flags;
  1194. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1195. avp->primary_sta_vif = true;
  1196. /*
  1197. * Set the AID, BSSID and do beacon-sync only when
  1198. * the HW opmode is STATION.
  1199. *
  1200. * But the primary bit is set above in any case.
  1201. */
  1202. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1203. return;
  1204. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1205. common->curaid = bss_conf->aid;
  1206. ath9k_hw_write_associd(sc->sc_ah);
  1207. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1208. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1209. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1210. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1211. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1212. ath_dbg(common, CONFIG,
  1213. "Primary Station interface: %pM, BSSID: %pM\n",
  1214. vif->addr, common->curbssid);
  1215. }
  1216. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1217. {
  1218. struct ath_softc *sc = data;
  1219. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1220. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1221. return;
  1222. if (bss_conf->assoc)
  1223. ath9k_set_assoc_state(sc, vif);
  1224. }
  1225. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1226. struct ieee80211_vif *vif,
  1227. struct ieee80211_bss_conf *bss_conf,
  1228. u32 changed)
  1229. {
  1230. #define CHECK_ANI \
  1231. (BSS_CHANGED_ASSOC | \
  1232. BSS_CHANGED_IBSS | \
  1233. BSS_CHANGED_BEACON_ENABLED)
  1234. struct ath_softc *sc = hw->priv;
  1235. struct ath_hw *ah = sc->sc_ah;
  1236. struct ath_common *common = ath9k_hw_common(ah);
  1237. struct ath_vif *avp = (void *)vif->drv_priv;
  1238. int slottime;
  1239. ath9k_ps_wakeup(sc);
  1240. mutex_lock(&sc->mutex);
  1241. if (changed & BSS_CHANGED_ASSOC) {
  1242. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1243. bss_conf->bssid, bss_conf->assoc);
  1244. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1245. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1246. avp->primary_sta_vif = false;
  1247. if (ah->opmode == NL80211_IFTYPE_STATION)
  1248. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1249. }
  1250. ieee80211_iterate_active_interfaces_atomic(sc->hw,
  1251. ath9k_bss_assoc_iter, sc);
  1252. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1253. ah->opmode == NL80211_IFTYPE_STATION) {
  1254. memset(common->curbssid, 0, ETH_ALEN);
  1255. common->curaid = 0;
  1256. ath9k_hw_write_associd(sc->sc_ah);
  1257. }
  1258. }
  1259. if (changed & BSS_CHANGED_IBSS) {
  1260. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1261. common->curaid = bss_conf->aid;
  1262. ath9k_hw_write_associd(sc->sc_ah);
  1263. }
  1264. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1265. (changed & BSS_CHANGED_BEACON_INT)) {
  1266. if (ah->opmode == NL80211_IFTYPE_AP &&
  1267. bss_conf->enable_beacon)
  1268. ath9k_set_tsfadjust(sc, vif);
  1269. if (ath9k_allow_beacon_config(sc, vif))
  1270. ath9k_beacon_config(sc, vif, changed);
  1271. }
  1272. if (changed & BSS_CHANGED_ERP_SLOT) {
  1273. if (bss_conf->use_short_slot)
  1274. slottime = 9;
  1275. else
  1276. slottime = 20;
  1277. if (vif->type == NL80211_IFTYPE_AP) {
  1278. /*
  1279. * Defer update, so that connected stations can adjust
  1280. * their settings at the same time.
  1281. * See beacon.c for more details
  1282. */
  1283. sc->beacon.slottime = slottime;
  1284. sc->beacon.updateslot = UPDATE;
  1285. } else {
  1286. ah->slottime = slottime;
  1287. ath9k_hw_init_global_settings(ah);
  1288. }
  1289. }
  1290. if (changed & CHECK_ANI)
  1291. ath_check_ani(sc);
  1292. mutex_unlock(&sc->mutex);
  1293. ath9k_ps_restore(sc);
  1294. #undef CHECK_ANI
  1295. }
  1296. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1297. {
  1298. struct ath_softc *sc = hw->priv;
  1299. u64 tsf;
  1300. mutex_lock(&sc->mutex);
  1301. ath9k_ps_wakeup(sc);
  1302. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1303. ath9k_ps_restore(sc);
  1304. mutex_unlock(&sc->mutex);
  1305. return tsf;
  1306. }
  1307. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1308. struct ieee80211_vif *vif,
  1309. u64 tsf)
  1310. {
  1311. struct ath_softc *sc = hw->priv;
  1312. mutex_lock(&sc->mutex);
  1313. ath9k_ps_wakeup(sc);
  1314. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1315. ath9k_ps_restore(sc);
  1316. mutex_unlock(&sc->mutex);
  1317. }
  1318. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1319. {
  1320. struct ath_softc *sc = hw->priv;
  1321. mutex_lock(&sc->mutex);
  1322. ath9k_ps_wakeup(sc);
  1323. ath9k_hw_reset_tsf(sc->sc_ah);
  1324. ath9k_ps_restore(sc);
  1325. mutex_unlock(&sc->mutex);
  1326. }
  1327. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1328. struct ieee80211_vif *vif,
  1329. enum ieee80211_ampdu_mlme_action action,
  1330. struct ieee80211_sta *sta,
  1331. u16 tid, u16 *ssn, u8 buf_size)
  1332. {
  1333. struct ath_softc *sc = hw->priv;
  1334. int ret = 0;
  1335. local_bh_disable();
  1336. switch (action) {
  1337. case IEEE80211_AMPDU_RX_START:
  1338. break;
  1339. case IEEE80211_AMPDU_RX_STOP:
  1340. break;
  1341. case IEEE80211_AMPDU_TX_START:
  1342. ath9k_ps_wakeup(sc);
  1343. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1344. if (!ret)
  1345. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1346. ath9k_ps_restore(sc);
  1347. break;
  1348. case IEEE80211_AMPDU_TX_STOP:
  1349. ath9k_ps_wakeup(sc);
  1350. ath_tx_aggr_stop(sc, sta, tid);
  1351. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1352. ath9k_ps_restore(sc);
  1353. break;
  1354. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1355. ath9k_ps_wakeup(sc);
  1356. ath_tx_aggr_resume(sc, sta, tid);
  1357. ath9k_ps_restore(sc);
  1358. break;
  1359. default:
  1360. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1361. }
  1362. local_bh_enable();
  1363. return ret;
  1364. }
  1365. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1366. struct survey_info *survey)
  1367. {
  1368. struct ath_softc *sc = hw->priv;
  1369. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1370. struct ieee80211_supported_band *sband;
  1371. struct ieee80211_channel *chan;
  1372. unsigned long flags;
  1373. int pos;
  1374. spin_lock_irqsave(&common->cc_lock, flags);
  1375. if (idx == 0)
  1376. ath_update_survey_stats(sc);
  1377. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1378. if (sband && idx >= sband->n_channels) {
  1379. idx -= sband->n_channels;
  1380. sband = NULL;
  1381. }
  1382. if (!sband)
  1383. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1384. if (!sband || idx >= sband->n_channels) {
  1385. spin_unlock_irqrestore(&common->cc_lock, flags);
  1386. return -ENOENT;
  1387. }
  1388. chan = &sband->channels[idx];
  1389. pos = chan->hw_value;
  1390. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1391. survey->channel = chan;
  1392. spin_unlock_irqrestore(&common->cc_lock, flags);
  1393. return 0;
  1394. }
  1395. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1396. {
  1397. struct ath_softc *sc = hw->priv;
  1398. struct ath_hw *ah = sc->sc_ah;
  1399. mutex_lock(&sc->mutex);
  1400. ah->coverage_class = coverage_class;
  1401. ath9k_ps_wakeup(sc);
  1402. ath9k_hw_init_global_settings(ah);
  1403. ath9k_ps_restore(sc);
  1404. mutex_unlock(&sc->mutex);
  1405. }
  1406. static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
  1407. {
  1408. struct ath_softc *sc = hw->priv;
  1409. struct ath_hw *ah = sc->sc_ah;
  1410. struct ath_common *common = ath9k_hw_common(ah);
  1411. int timeout = 200; /* ms */
  1412. int i, j;
  1413. bool drain_txq;
  1414. mutex_lock(&sc->mutex);
  1415. cancel_delayed_work_sync(&sc->tx_complete_work);
  1416. if (ah->ah_flags & AH_UNPLUGGED) {
  1417. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1418. mutex_unlock(&sc->mutex);
  1419. return;
  1420. }
  1421. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1422. ath_dbg(common, ANY, "Device not present\n");
  1423. mutex_unlock(&sc->mutex);
  1424. return;
  1425. }
  1426. for (j = 0; j < timeout; j++) {
  1427. bool npend = false;
  1428. if (j)
  1429. usleep_range(1000, 2000);
  1430. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1431. if (!ATH_TXQ_SETUP(sc, i))
  1432. continue;
  1433. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1434. if (npend)
  1435. break;
  1436. }
  1437. if (!npend)
  1438. break;
  1439. }
  1440. if (drop) {
  1441. ath9k_ps_wakeup(sc);
  1442. spin_lock_bh(&sc->sc_pcu_lock);
  1443. drain_txq = ath_drain_all_txq(sc, false);
  1444. spin_unlock_bh(&sc->sc_pcu_lock);
  1445. if (!drain_txq)
  1446. ath_reset(sc, false);
  1447. ath9k_ps_restore(sc);
  1448. ieee80211_wake_queues(hw);
  1449. }
  1450. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1451. mutex_unlock(&sc->mutex);
  1452. }
  1453. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1454. {
  1455. struct ath_softc *sc = hw->priv;
  1456. int i;
  1457. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1458. if (!ATH_TXQ_SETUP(sc, i))
  1459. continue;
  1460. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1461. return true;
  1462. }
  1463. return false;
  1464. }
  1465. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1466. {
  1467. struct ath_softc *sc = hw->priv;
  1468. struct ath_hw *ah = sc->sc_ah;
  1469. struct ieee80211_vif *vif;
  1470. struct ath_vif *avp;
  1471. struct ath_buf *bf;
  1472. struct ath_tx_status ts;
  1473. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1474. int status;
  1475. vif = sc->beacon.bslot[0];
  1476. if (!vif)
  1477. return 0;
  1478. if (!vif->bss_conf.enable_beacon)
  1479. return 0;
  1480. avp = (void *)vif->drv_priv;
  1481. if (!sc->beacon.tx_processed && !edma) {
  1482. tasklet_disable(&sc->bcon_tasklet);
  1483. bf = avp->av_bcbuf;
  1484. if (!bf || !bf->bf_mpdu)
  1485. goto skip;
  1486. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1487. if (status == -EINPROGRESS)
  1488. goto skip;
  1489. sc->beacon.tx_processed = true;
  1490. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1491. skip:
  1492. tasklet_enable(&sc->bcon_tasklet);
  1493. }
  1494. return sc->beacon.tx_last;
  1495. }
  1496. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1497. struct ieee80211_low_level_stats *stats)
  1498. {
  1499. struct ath_softc *sc = hw->priv;
  1500. struct ath_hw *ah = sc->sc_ah;
  1501. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1502. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1503. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1504. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1505. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1506. return 0;
  1507. }
  1508. static u32 fill_chainmask(u32 cap, u32 new)
  1509. {
  1510. u32 filled = 0;
  1511. int i;
  1512. for (i = 0; cap && new; i++, cap >>= 1) {
  1513. if (!(cap & BIT(0)))
  1514. continue;
  1515. if (new & BIT(0))
  1516. filled |= BIT(i);
  1517. new >>= 1;
  1518. }
  1519. return filled;
  1520. }
  1521. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1522. {
  1523. switch (val & 0x7) {
  1524. case 0x1:
  1525. case 0x3:
  1526. case 0x7:
  1527. return true;
  1528. case 0x2:
  1529. return (ah->caps.rx_chainmask == 1);
  1530. default:
  1531. return false;
  1532. }
  1533. }
  1534. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1535. {
  1536. struct ath_softc *sc = hw->priv;
  1537. struct ath_hw *ah = sc->sc_ah;
  1538. if (ah->caps.rx_chainmask != 1)
  1539. rx_ant |= tx_ant;
  1540. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1541. return -EINVAL;
  1542. sc->ant_rx = rx_ant;
  1543. sc->ant_tx = tx_ant;
  1544. if (ah->caps.rx_chainmask == 1)
  1545. return 0;
  1546. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1547. if (AR_SREV_9100(ah))
  1548. ah->rxchainmask = 0x7;
  1549. else
  1550. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1551. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1552. ath9k_reload_chainmask_settings(sc);
  1553. return 0;
  1554. }
  1555. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1556. {
  1557. struct ath_softc *sc = hw->priv;
  1558. *tx_ant = sc->ant_tx;
  1559. *rx_ant = sc->ant_rx;
  1560. return 0;
  1561. }
  1562. #ifdef CONFIG_ATH9K_DEBUGFS
  1563. /* Ethtool support for get-stats */
  1564. #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
  1565. static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
  1566. "tx_pkts_nic",
  1567. "tx_bytes_nic",
  1568. "rx_pkts_nic",
  1569. "rx_bytes_nic",
  1570. AMKSTR(d_tx_pkts),
  1571. AMKSTR(d_tx_bytes),
  1572. AMKSTR(d_tx_mpdus_queued),
  1573. AMKSTR(d_tx_mpdus_completed),
  1574. AMKSTR(d_tx_mpdu_xretries),
  1575. AMKSTR(d_tx_aggregates),
  1576. AMKSTR(d_tx_ampdus_queued_hw),
  1577. AMKSTR(d_tx_ampdus_queued_sw),
  1578. AMKSTR(d_tx_ampdus_completed),
  1579. AMKSTR(d_tx_ampdu_retries),
  1580. AMKSTR(d_tx_ampdu_xretries),
  1581. AMKSTR(d_tx_fifo_underrun),
  1582. AMKSTR(d_tx_op_exceeded),
  1583. AMKSTR(d_tx_timer_expiry),
  1584. AMKSTR(d_tx_desc_cfg_err),
  1585. AMKSTR(d_tx_data_underrun),
  1586. AMKSTR(d_tx_delim_underrun),
  1587. "d_rx_decrypt_crc_err",
  1588. "d_rx_phy_err",
  1589. "d_rx_mic_err",
  1590. "d_rx_pre_delim_crc_err",
  1591. "d_rx_post_delim_crc_err",
  1592. "d_rx_decrypt_busy_err",
  1593. "d_rx_phyerr_radar",
  1594. "d_rx_phyerr_ofdm_timing",
  1595. "d_rx_phyerr_cck_timing",
  1596. };
  1597. #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
  1598. static void ath9k_get_et_strings(struct ieee80211_hw *hw,
  1599. struct ieee80211_vif *vif,
  1600. u32 sset, u8 *data)
  1601. {
  1602. if (sset == ETH_SS_STATS)
  1603. memcpy(data, *ath9k_gstrings_stats,
  1604. sizeof(ath9k_gstrings_stats));
  1605. }
  1606. static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
  1607. struct ieee80211_vif *vif, int sset)
  1608. {
  1609. if (sset == ETH_SS_STATS)
  1610. return ATH9K_SSTATS_LEN;
  1611. return 0;
  1612. }
  1613. #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
  1614. #define AWDATA(elem) \
  1615. do { \
  1616. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
  1617. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
  1618. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
  1619. data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
  1620. } while (0)
  1621. #define AWDATA_RX(elem) \
  1622. do { \
  1623. data[i++] = sc->debug.stats.rxstats.elem; \
  1624. } while (0)
  1625. static void ath9k_get_et_stats(struct ieee80211_hw *hw,
  1626. struct ieee80211_vif *vif,
  1627. struct ethtool_stats *stats, u64 *data)
  1628. {
  1629. struct ath_softc *sc = hw->priv;
  1630. int i = 0;
  1631. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
  1632. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
  1633. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
  1634. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
  1635. data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
  1636. sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
  1637. sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
  1638. sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
  1639. AWDATA_RX(rx_pkts_all);
  1640. AWDATA_RX(rx_bytes_all);
  1641. AWDATA(tx_pkts_all);
  1642. AWDATA(tx_bytes_all);
  1643. AWDATA(queued);
  1644. AWDATA(completed);
  1645. AWDATA(xretries);
  1646. AWDATA(a_aggr);
  1647. AWDATA(a_queued_hw);
  1648. AWDATA(a_queued_sw);
  1649. AWDATA(a_completed);
  1650. AWDATA(a_retries);
  1651. AWDATA(a_xretries);
  1652. AWDATA(fifo_underrun);
  1653. AWDATA(xtxop);
  1654. AWDATA(timer_exp);
  1655. AWDATA(desc_cfg_err);
  1656. AWDATA(data_underrun);
  1657. AWDATA(delim_underrun);
  1658. AWDATA_RX(decrypt_crc_err);
  1659. AWDATA_RX(phy_err);
  1660. AWDATA_RX(mic_err);
  1661. AWDATA_RX(pre_delim_crc_err);
  1662. AWDATA_RX(post_delim_crc_err);
  1663. AWDATA_RX(decrypt_busy_err);
  1664. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
  1665. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
  1666. AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
  1667. WARN_ON(i != ATH9K_SSTATS_LEN);
  1668. }
  1669. /* End of ethtool get-stats functions */
  1670. #endif
  1671. #ifdef CONFIG_PM_SLEEP
  1672. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1673. struct cfg80211_wowlan *wowlan,
  1674. u32 *wow_triggers)
  1675. {
  1676. if (wowlan->disconnect)
  1677. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1678. AH_WOW_BEACON_MISS;
  1679. if (wowlan->magic_pkt)
  1680. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1681. if (wowlan->n_patterns)
  1682. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1683. sc->wow_enabled = *wow_triggers;
  1684. }
  1685. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1686. {
  1687. struct ath_hw *ah = sc->sc_ah;
  1688. struct ath_common *common = ath9k_hw_common(ah);
  1689. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1690. int pattern_count = 0;
  1691. int i, byte_cnt;
  1692. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1693. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1694. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1695. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1696. /*
  1697. * Create Dissassociate / Deauthenticate packet filter
  1698. *
  1699. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1700. * +--------------+----------+---------+--------+--------+----
  1701. * + Frame Control+ Duration + DA + SA + BSSID +
  1702. * +--------------+----------+---------+--------+--------+----
  1703. *
  1704. * The above is the management frame format for disassociate/
  1705. * deauthenticate pattern, from this we need to match the first byte
  1706. * of 'Frame Control' and DA, SA, and BSSID fields
  1707. * (skipping 2nd byte of FC and Duration feild.
  1708. *
  1709. * Disassociate pattern
  1710. * --------------------
  1711. * Frame control = 00 00 1010
  1712. * DA, SA, BSSID = x:x:x:x:x:x
  1713. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1714. * | x:x:x:x:x:x -- 22 bytes
  1715. *
  1716. * Deauthenticate pattern
  1717. * ----------------------
  1718. * Frame control = 00 00 1100
  1719. * DA, SA, BSSID = x:x:x:x:x:x
  1720. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1721. * | x:x:x:x:x:x -- 22 bytes
  1722. */
  1723. /* Create Disassociate Pattern first */
  1724. byte_cnt = 0;
  1725. /* Fill out the mask with all FF's */
  1726. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1727. dis_deauth_mask[i] = 0xff;
  1728. /* copy the first byte of frame control field */
  1729. dis_deauth_pattern[byte_cnt] = 0xa0;
  1730. byte_cnt++;
  1731. /* skip 2nd byte of frame control and Duration field */
  1732. byte_cnt += 3;
  1733. /*
  1734. * need not match the destination mac address, it can be a broadcast
  1735. * mac address or an unicast to this station
  1736. */
  1737. byte_cnt += 6;
  1738. /* copy the source mac address */
  1739. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1740. byte_cnt += 6;
  1741. /* copy the bssid, its same as the source mac address */
  1742. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1743. /* Create Disassociate pattern mask */
  1744. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1745. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1746. /*
  1747. * for AR9280, because of hardware limitation, the
  1748. * first 4 bytes have to be matched for all patterns.
  1749. * the mask for disassociation and de-auth pattern
  1750. * matching need to enable the first 4 bytes.
  1751. * also the duration field needs to be filled.
  1752. */
  1753. dis_deauth_mask[0] = 0xf0;
  1754. /*
  1755. * fill in duration field
  1756. FIXME: what is the exact value ?
  1757. */
  1758. dis_deauth_pattern[2] = 0xff;
  1759. dis_deauth_pattern[3] = 0xff;
  1760. } else {
  1761. dis_deauth_mask[0] = 0xfe;
  1762. }
  1763. dis_deauth_mask[1] = 0x03;
  1764. dis_deauth_mask[2] = 0xc0;
  1765. } else {
  1766. dis_deauth_mask[0] = 0xef;
  1767. dis_deauth_mask[1] = 0x3f;
  1768. dis_deauth_mask[2] = 0x00;
  1769. dis_deauth_mask[3] = 0xfc;
  1770. }
  1771. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1772. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1773. pattern_count, byte_cnt);
  1774. pattern_count++;
  1775. /*
  1776. * for de-authenticate pattern, only the first byte of the frame
  1777. * control field gets changed from 0xA0 to 0xC0
  1778. */
  1779. dis_deauth_pattern[0] = 0xC0;
  1780. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1781. pattern_count, byte_cnt);
  1782. }
  1783. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1784. struct cfg80211_wowlan *wowlan)
  1785. {
  1786. struct ath_hw *ah = sc->sc_ah;
  1787. struct ath9k_wow_pattern *wow_pattern = NULL;
  1788. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1789. int mask_len;
  1790. s8 i = 0;
  1791. if (!wowlan->n_patterns)
  1792. return;
  1793. /*
  1794. * Add the new user configured patterns
  1795. */
  1796. for (i = 0; i < wowlan->n_patterns; i++) {
  1797. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1798. if (!wow_pattern)
  1799. return;
  1800. /*
  1801. * TODO: convert the generic user space pattern to
  1802. * appropriate chip specific/802.11 pattern.
  1803. */
  1804. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1805. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1806. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1807. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1808. patterns[i].pattern_len);
  1809. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1810. wow_pattern->pattern_len = patterns[i].pattern_len;
  1811. /*
  1812. * just need to take care of deauth and disssoc pattern,
  1813. * make sure we don't overwrite them.
  1814. */
  1815. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1816. wow_pattern->mask_bytes,
  1817. i + 2,
  1818. wow_pattern->pattern_len);
  1819. kfree(wow_pattern);
  1820. }
  1821. }
  1822. static int ath9k_suspend(struct ieee80211_hw *hw,
  1823. struct cfg80211_wowlan *wowlan)
  1824. {
  1825. struct ath_softc *sc = hw->priv;
  1826. struct ath_hw *ah = sc->sc_ah;
  1827. struct ath_common *common = ath9k_hw_common(ah);
  1828. u32 wow_triggers_enabled = 0;
  1829. int ret = 0;
  1830. mutex_lock(&sc->mutex);
  1831. ath_cancel_work(sc);
  1832. del_timer_sync(&common->ani.timer);
  1833. del_timer_sync(&sc->rx_poll_timer);
  1834. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1835. ath_dbg(common, ANY, "Device not present\n");
  1836. ret = -EINVAL;
  1837. goto fail_wow;
  1838. }
  1839. if (WARN_ON(!wowlan)) {
  1840. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1841. ret = -EINVAL;
  1842. goto fail_wow;
  1843. }
  1844. if (!device_can_wakeup(sc->dev)) {
  1845. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1846. ret = 1;
  1847. goto fail_wow;
  1848. }
  1849. /*
  1850. * none of the sta vifs are associated
  1851. * and we are not currently handling multivif
  1852. * cases, for instance we have to seperately
  1853. * configure 'keep alive frame' for each
  1854. * STA.
  1855. */
  1856. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1857. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1858. ret = 1;
  1859. goto fail_wow;
  1860. }
  1861. if (sc->nvifs > 1) {
  1862. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1863. ret = 1;
  1864. goto fail_wow;
  1865. }
  1866. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1867. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1868. wow_triggers_enabled);
  1869. ath9k_ps_wakeup(sc);
  1870. ath9k_stop_btcoex(sc);
  1871. /*
  1872. * Enable wake up on recieving disassoc/deauth
  1873. * frame by default.
  1874. */
  1875. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1876. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1877. ath9k_wow_add_pattern(sc, wowlan);
  1878. spin_lock_bh(&sc->sc_pcu_lock);
  1879. /*
  1880. * To avoid false wake, we enable beacon miss interrupt only
  1881. * when we go to sleep. We save the current interrupt mask
  1882. * so we can restore it after the system wakes up
  1883. */
  1884. sc->wow_intr_before_sleep = ah->imask;
  1885. ah->imask &= ~ATH9K_INT_GLOBAL;
  1886. ath9k_hw_disable_interrupts(ah);
  1887. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1888. ath9k_hw_set_interrupts(ah);
  1889. ath9k_hw_enable_interrupts(ah);
  1890. spin_unlock_bh(&sc->sc_pcu_lock);
  1891. /*
  1892. * we can now sync irq and kill any running tasklets, since we already
  1893. * disabled interrupts and not holding a spin lock
  1894. */
  1895. synchronize_irq(sc->irq);
  1896. tasklet_kill(&sc->intr_tq);
  1897. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1898. ath9k_ps_restore(sc);
  1899. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1900. atomic_inc(&sc->wow_sleep_proc_intr);
  1901. fail_wow:
  1902. mutex_unlock(&sc->mutex);
  1903. return ret;
  1904. }
  1905. static int ath9k_resume(struct ieee80211_hw *hw)
  1906. {
  1907. struct ath_softc *sc = hw->priv;
  1908. struct ath_hw *ah = sc->sc_ah;
  1909. struct ath_common *common = ath9k_hw_common(ah);
  1910. u32 wow_status;
  1911. mutex_lock(&sc->mutex);
  1912. ath9k_ps_wakeup(sc);
  1913. spin_lock_bh(&sc->sc_pcu_lock);
  1914. ath9k_hw_disable_interrupts(ah);
  1915. ah->imask = sc->wow_intr_before_sleep;
  1916. ath9k_hw_set_interrupts(ah);
  1917. ath9k_hw_enable_interrupts(ah);
  1918. spin_unlock_bh(&sc->sc_pcu_lock);
  1919. wow_status = ath9k_hw_wow_wakeup(ah);
  1920. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1921. /*
  1922. * some devices may not pick beacon miss
  1923. * as the reason they woke up so we add
  1924. * that here for that shortcoming.
  1925. */
  1926. wow_status |= AH_WOW_BEACON_MISS;
  1927. atomic_dec(&sc->wow_got_bmiss_intr);
  1928. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1929. }
  1930. atomic_dec(&sc->wow_sleep_proc_intr);
  1931. if (wow_status) {
  1932. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1933. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1934. }
  1935. ath_restart_work(sc);
  1936. ath9k_start_btcoex(sc);
  1937. ath9k_ps_restore(sc);
  1938. mutex_unlock(&sc->mutex);
  1939. return 0;
  1940. }
  1941. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1942. {
  1943. struct ath_softc *sc = hw->priv;
  1944. mutex_lock(&sc->mutex);
  1945. device_init_wakeup(sc->dev, 1);
  1946. device_set_wakeup_enable(sc->dev, enabled);
  1947. mutex_unlock(&sc->mutex);
  1948. }
  1949. #endif
  1950. struct ieee80211_ops ath9k_ops = {
  1951. .tx = ath9k_tx,
  1952. .start = ath9k_start,
  1953. .stop = ath9k_stop,
  1954. .add_interface = ath9k_add_interface,
  1955. .change_interface = ath9k_change_interface,
  1956. .remove_interface = ath9k_remove_interface,
  1957. .config = ath9k_config,
  1958. .configure_filter = ath9k_configure_filter,
  1959. .sta_add = ath9k_sta_add,
  1960. .sta_remove = ath9k_sta_remove,
  1961. .sta_notify = ath9k_sta_notify,
  1962. .conf_tx = ath9k_conf_tx,
  1963. .bss_info_changed = ath9k_bss_info_changed,
  1964. .set_key = ath9k_set_key,
  1965. .get_tsf = ath9k_get_tsf,
  1966. .set_tsf = ath9k_set_tsf,
  1967. .reset_tsf = ath9k_reset_tsf,
  1968. .ampdu_action = ath9k_ampdu_action,
  1969. .get_survey = ath9k_get_survey,
  1970. .rfkill_poll = ath9k_rfkill_poll_state,
  1971. .set_coverage_class = ath9k_set_coverage_class,
  1972. .flush = ath9k_flush,
  1973. .tx_frames_pending = ath9k_tx_frames_pending,
  1974. .tx_last_beacon = ath9k_tx_last_beacon,
  1975. .get_stats = ath9k_get_stats,
  1976. .set_antenna = ath9k_set_antenna,
  1977. .get_antenna = ath9k_get_antenna,
  1978. #ifdef CONFIG_PM_SLEEP
  1979. .suspend = ath9k_suspend,
  1980. .resume = ath9k_resume,
  1981. .set_wakeup = ath9k_set_wakeup,
  1982. #endif
  1983. #ifdef CONFIG_ATH9K_DEBUGFS
  1984. .get_et_sset_count = ath9k_get_et_sset_count,
  1985. .get_et_stats = ath9k_get_et_stats,
  1986. .get_et_strings = ath9k_get_et_strings,
  1987. #endif
  1988. };