init.c 42 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/moduleparam.h>
  19. #include <linux/errno.h>
  20. #include <linux/export.h>
  21. #include <linux/of.h>
  22. #include <linux/mmc/sdio_func.h>
  23. #include <linux/vmalloc.h>
  24. #include "core.h"
  25. #include "cfg80211.h"
  26. #include "target.h"
  27. #include "debug.h"
  28. #include "hif-ops.h"
  29. #include "htc-ops.h"
  30. static const struct ath6kl_hw hw_list[] = {
  31. {
  32. .id = AR6003_HW_2_0_VERSION,
  33. .name = "ar6003 hw 2.0",
  34. .dataset_patch_addr = 0x57e884,
  35. .app_load_addr = 0x543180,
  36. .board_ext_data_addr = 0x57e500,
  37. .reserved_ram_size = 6912,
  38. .refclk_hz = 26000000,
  39. .uarttx_pin = 8,
  40. .flags = 0,
  41. /* hw2.0 needs override address hardcoded */
  42. .app_start_override_addr = 0x944C00,
  43. .fw = {
  44. .dir = AR6003_HW_2_0_FW_DIR,
  45. .otp = AR6003_HW_2_0_OTP_FILE,
  46. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  47. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  48. .patch = AR6003_HW_2_0_PATCH_FILE,
  49. },
  50. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  51. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  52. },
  53. {
  54. .id = AR6003_HW_2_1_1_VERSION,
  55. .name = "ar6003 hw 2.1.1",
  56. .dataset_patch_addr = 0x57ff74,
  57. .app_load_addr = 0x1234,
  58. .board_ext_data_addr = 0x542330,
  59. .reserved_ram_size = 512,
  60. .refclk_hz = 26000000,
  61. .uarttx_pin = 8,
  62. .testscript_addr = 0x57ef74,
  63. .flags = 0,
  64. .fw = {
  65. .dir = AR6003_HW_2_1_1_FW_DIR,
  66. .otp = AR6003_HW_2_1_1_OTP_FILE,
  67. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  68. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  69. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  70. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  71. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  72. },
  73. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  74. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  75. },
  76. {
  77. .id = AR6004_HW_1_0_VERSION,
  78. .name = "ar6004 hw 1.0",
  79. .dataset_patch_addr = 0x57e884,
  80. .app_load_addr = 0x1234,
  81. .board_ext_data_addr = 0x437000,
  82. .reserved_ram_size = 19456,
  83. .board_addr = 0x433900,
  84. .refclk_hz = 26000000,
  85. .uarttx_pin = 11,
  86. .flags = ATH6KL_HW_FLAG_64BIT_RATES,
  87. .fw = {
  88. .dir = AR6004_HW_1_0_FW_DIR,
  89. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  90. },
  91. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  92. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  93. },
  94. {
  95. .id = AR6004_HW_1_1_VERSION,
  96. .name = "ar6004 hw 1.1",
  97. .dataset_patch_addr = 0x57e884,
  98. .app_load_addr = 0x1234,
  99. .board_ext_data_addr = 0x437000,
  100. .reserved_ram_size = 11264,
  101. .board_addr = 0x43d400,
  102. .refclk_hz = 40000000,
  103. .uarttx_pin = 11,
  104. .flags = ATH6KL_HW_FLAG_64BIT_RATES,
  105. .fw = {
  106. .dir = AR6004_HW_1_1_FW_DIR,
  107. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  108. },
  109. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  110. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  111. },
  112. {
  113. .id = AR6004_HW_1_2_VERSION,
  114. .name = "ar6004 hw 1.2",
  115. .dataset_patch_addr = 0x436ecc,
  116. .app_load_addr = 0x1234,
  117. .board_ext_data_addr = 0x437000,
  118. .reserved_ram_size = 9216,
  119. .board_addr = 0x435c00,
  120. .refclk_hz = 40000000,
  121. .uarttx_pin = 11,
  122. .flags = ATH6KL_HW_FLAG_64BIT_RATES,
  123. .fw = {
  124. .dir = AR6004_HW_1_2_FW_DIR,
  125. .fw = AR6004_HW_1_2_FIRMWARE_FILE,
  126. },
  127. .fw_board = AR6004_HW_1_2_BOARD_DATA_FILE,
  128. .fw_default_board = AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE,
  129. },
  130. };
  131. /*
  132. * Include definitions here that can be used to tune the WLAN module
  133. * behavior. Different customers can tune the behavior as per their needs,
  134. * here.
  135. */
  136. /*
  137. * This configuration item enable/disable keepalive support.
  138. * Keepalive support: In the absence of any data traffic to AP, null
  139. * frames will be sent to the AP at periodic interval, to keep the association
  140. * active. This configuration item defines the periodic interval.
  141. * Use value of zero to disable keepalive support
  142. * Default: 60 seconds
  143. */
  144. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  145. /*
  146. * This configuration item sets the value of disconnect timeout
  147. * Firmware delays sending the disconnec event to the host for this
  148. * timeout after is gets disconnected from the current AP.
  149. * If the firmware successly roams within the disconnect timeout
  150. * it sends a new connect event
  151. */
  152. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  153. #define ATH6KL_DATA_OFFSET 64
  154. struct sk_buff *ath6kl_buf_alloc(int size)
  155. {
  156. struct sk_buff *skb;
  157. u16 reserved;
  158. /* Add chacheline space at front and back of buffer */
  159. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  160. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  161. skb = dev_alloc_skb(size + reserved);
  162. if (skb)
  163. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  164. return skb;
  165. }
  166. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  167. {
  168. vif->ssid_len = 0;
  169. memset(vif->ssid, 0, sizeof(vif->ssid));
  170. vif->dot11_auth_mode = OPEN_AUTH;
  171. vif->auth_mode = NONE_AUTH;
  172. vif->prwise_crypto = NONE_CRYPT;
  173. vif->prwise_crypto_len = 0;
  174. vif->grp_crypto = NONE_CRYPT;
  175. vif->grp_crypto_len = 0;
  176. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  177. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  178. memset(vif->bssid, 0, sizeof(vif->bssid));
  179. vif->bss_ch = 0;
  180. }
  181. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  182. {
  183. u32 address, data;
  184. struct host_app_area host_app_area;
  185. /* Fetch the address of the host_app_area_s
  186. * instance in the host interest area */
  187. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  188. address = TARG_VTOP(ar->target_type, address);
  189. if (ath6kl_diag_read32(ar, address, &data))
  190. return -EIO;
  191. address = TARG_VTOP(ar->target_type, data);
  192. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  193. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  194. sizeof(struct host_app_area)))
  195. return -EIO;
  196. return 0;
  197. }
  198. static inline void set_ac2_ep_map(struct ath6kl *ar,
  199. u8 ac,
  200. enum htc_endpoint_id ep)
  201. {
  202. ar->ac2ep_map[ac] = ep;
  203. ar->ep2ac_map[ep] = ac;
  204. }
  205. /* connect to a service */
  206. static int ath6kl_connectservice(struct ath6kl *ar,
  207. struct htc_service_connect_req *con_req,
  208. char *desc)
  209. {
  210. int status;
  211. struct htc_service_connect_resp response;
  212. memset(&response, 0, sizeof(response));
  213. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  214. if (status) {
  215. ath6kl_err("failed to connect to %s service status:%d\n",
  216. desc, status);
  217. return status;
  218. }
  219. switch (con_req->svc_id) {
  220. case WMI_CONTROL_SVC:
  221. if (test_bit(WMI_ENABLED, &ar->flag))
  222. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  223. ar->ctrl_ep = response.endpoint;
  224. break;
  225. case WMI_DATA_BE_SVC:
  226. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  227. break;
  228. case WMI_DATA_BK_SVC:
  229. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  230. break;
  231. case WMI_DATA_VI_SVC:
  232. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  233. break;
  234. case WMI_DATA_VO_SVC:
  235. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  236. break;
  237. default:
  238. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  239. return -EINVAL;
  240. }
  241. return 0;
  242. }
  243. static int ath6kl_init_service_ep(struct ath6kl *ar)
  244. {
  245. struct htc_service_connect_req connect;
  246. memset(&connect, 0, sizeof(connect));
  247. /* these fields are the same for all service endpoints */
  248. connect.ep_cb.tx_comp_multi = ath6kl_tx_complete;
  249. connect.ep_cb.rx = ath6kl_rx;
  250. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  251. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  252. /*
  253. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  254. * gets called.
  255. */
  256. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  257. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  258. if (!connect.ep_cb.rx_refill_thresh)
  259. connect.ep_cb.rx_refill_thresh++;
  260. /* connect to control service */
  261. connect.svc_id = WMI_CONTROL_SVC;
  262. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  263. return -EIO;
  264. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  265. /*
  266. * Limit the HTC message size on the send path, although e can
  267. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  268. * (802.3) frames on the send path.
  269. */
  270. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  271. /*
  272. * To reduce the amount of committed memory for larger A_MSDU
  273. * frames, use the recv-alloc threshold mechanism for larger
  274. * packets.
  275. */
  276. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  277. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  278. /*
  279. * For the remaining data services set the connection flag to
  280. * reduce dribbling, if configured to do so.
  281. */
  282. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  283. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  284. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  285. connect.svc_id = WMI_DATA_BE_SVC;
  286. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  287. return -EIO;
  288. /* connect to back-ground map this to WMI LOW_PRI */
  289. connect.svc_id = WMI_DATA_BK_SVC;
  290. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  291. return -EIO;
  292. /* connect to Video service, map this to to HI PRI */
  293. connect.svc_id = WMI_DATA_VI_SVC;
  294. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  295. return -EIO;
  296. /*
  297. * Connect to VO service, this is currently not mapped to a WMI
  298. * priority stream due to historical reasons. WMI originally
  299. * defined 3 priorities over 3 mailboxes We can change this when
  300. * WMI is reworked so that priorities are not dependent on
  301. * mailboxes.
  302. */
  303. connect.svc_id = WMI_DATA_VO_SVC;
  304. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  305. return -EIO;
  306. return 0;
  307. }
  308. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  309. {
  310. ath6kl_init_profile_info(vif);
  311. vif->def_txkey_index = 0;
  312. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  313. vif->ch_hint = 0;
  314. }
  315. /*
  316. * Set HTC/Mbox operational parameters, this can only be called when the
  317. * target is in the BMI phase.
  318. */
  319. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  320. u8 htc_ctrl_buf)
  321. {
  322. int status;
  323. u32 blk_size;
  324. blk_size = ar->mbox_info.block_size;
  325. if (htc_ctrl_buf)
  326. blk_size |= ((u32)htc_ctrl_buf) << 16;
  327. /* set the host interest area for the block size */
  328. status = ath6kl_bmi_write_hi32(ar, hi_mbox_io_block_sz, blk_size);
  329. if (status) {
  330. ath6kl_err("bmi_write_memory for IO block size failed\n");
  331. goto out;
  332. }
  333. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  334. blk_size,
  335. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  336. if (mbox_isr_yield_val) {
  337. /* set the host interest area for the mbox ISR yield limit */
  338. status = ath6kl_bmi_write_hi32(ar, hi_mbox_isr_yield_limit,
  339. mbox_isr_yield_val);
  340. if (status) {
  341. ath6kl_err("bmi_write_memory for yield limit failed\n");
  342. goto out;
  343. }
  344. }
  345. out:
  346. return status;
  347. }
  348. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  349. {
  350. int ret;
  351. /*
  352. * Configure the device for rx dot11 header rules. "0,0" are the
  353. * default values. Required if checksum offload is needed. Set
  354. * RxMetaVersion to 2.
  355. */
  356. ret = ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  357. ar->rx_meta_ver, 0, 0);
  358. if (ret) {
  359. ath6kl_err("unable to set the rx frame format: %d\n", ret);
  360. return ret;
  361. }
  362. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN) {
  363. ret = ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  364. IGNORE_PS_FAIL_DURING_SCAN);
  365. if (ret) {
  366. ath6kl_err("unable to set power save fail event policy: %d\n",
  367. ret);
  368. return ret;
  369. }
  370. }
  371. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER)) {
  372. ret = ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  373. WMI_FOLLOW_BARKER_IN_ERP);
  374. if (ret) {
  375. ath6kl_err("unable to set barker preamble policy: %d\n",
  376. ret);
  377. return ret;
  378. }
  379. }
  380. ret = ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  381. WLAN_CONFIG_KEEP_ALIVE_INTERVAL);
  382. if (ret) {
  383. ath6kl_err("unable to set keep alive interval: %d\n", ret);
  384. return ret;
  385. }
  386. ret = ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  387. WLAN_CONFIG_DISCONNECT_TIMEOUT);
  388. if (ret) {
  389. ath6kl_err("unable to set disconnect timeout: %d\n", ret);
  390. return ret;
  391. }
  392. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST)) {
  393. ret = ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED);
  394. if (ret) {
  395. ath6kl_err("unable to set txop bursting: %d\n", ret);
  396. return ret;
  397. }
  398. }
  399. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  400. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  401. P2P_FLAG_CAPABILITIES_REQ |
  402. P2P_FLAG_MACADDR_REQ |
  403. P2P_FLAG_HMODEL_REQ);
  404. if (ret) {
  405. ath6kl_dbg(ATH6KL_DBG_TRC,
  406. "failed to request P2P capabilities (%d) - assuming P2P not supported\n",
  407. ret);
  408. ar->p2p = false;
  409. }
  410. }
  411. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  412. /* Enable Probe Request reporting for P2P */
  413. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  414. if (ret) {
  415. ath6kl_dbg(ATH6KL_DBG_TRC,
  416. "failed to enable Probe Request reporting (%d)\n",
  417. ret);
  418. }
  419. }
  420. return ret;
  421. }
  422. int ath6kl_configure_target(struct ath6kl *ar)
  423. {
  424. u32 param, ram_reserved_size;
  425. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  426. int i, status;
  427. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  428. if (ath6kl_bmi_write_hi32(ar, hi_serial_enable, param)) {
  429. ath6kl_err("bmi_write_memory for uart debug failed\n");
  430. return -EIO;
  431. }
  432. /*
  433. * Note: Even though the firmware interface type is
  434. * chosen as BSS_STA for all three interfaces, can
  435. * be configured to IBSS/AP as long as the fw submode
  436. * remains normal mode (0 - AP, STA and IBSS). But
  437. * due to an target assert in firmware only one interface is
  438. * configured for now.
  439. */
  440. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  441. for (i = 0; i < ar->vif_max; i++)
  442. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  443. /*
  444. * Submodes when fw does not support dynamic interface
  445. * switching:
  446. * vif[0] - AP/STA/IBSS
  447. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  448. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  449. * Otherwise, All the interface are initialized to p2p dev.
  450. */
  451. if (test_bit(ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
  452. ar->fw_capabilities)) {
  453. for (i = 0; i < ar->vif_max; i++)
  454. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  455. (i * HI_OPTION_FW_SUBMODE_BITS);
  456. } else {
  457. for (i = 0; i < ar->max_norm_iface; i++)
  458. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  459. (i * HI_OPTION_FW_SUBMODE_BITS);
  460. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  461. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  462. (i * HI_OPTION_FW_SUBMODE_BITS);
  463. if (ar->p2p && ar->vif_max == 1)
  464. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  465. }
  466. if (ath6kl_bmi_write_hi32(ar, hi_app_host_interest,
  467. HTC_PROTOCOL_VERSION) != 0) {
  468. ath6kl_err("bmi_write_memory for htc version failed\n");
  469. return -EIO;
  470. }
  471. /* set the firmware mode to STA/IBSS/AP */
  472. param = 0;
  473. if (ath6kl_bmi_read_hi32(ar, hi_option_flag, &param) != 0) {
  474. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  475. return -EIO;
  476. }
  477. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  478. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  479. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  480. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  481. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  482. if (ath6kl_bmi_write_hi32(ar, hi_option_flag, param) != 0) {
  483. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  484. return -EIO;
  485. }
  486. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  487. /*
  488. * Hardcode the address use for the extended board data
  489. * Ideally this should be pre-allocate by the OS at boot time
  490. * But since it is a new feature and board data is loaded
  491. * at init time, we have to workaround this from host.
  492. * It is difficult to patch the firmware boot code,
  493. * but possible in theory.
  494. */
  495. if (ar->target_type == TARGET_TYPE_AR6003) {
  496. param = ar->hw.board_ext_data_addr;
  497. ram_reserved_size = ar->hw.reserved_ram_size;
  498. if (ath6kl_bmi_write_hi32(ar, hi_board_ext_data, param) != 0) {
  499. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  500. return -EIO;
  501. }
  502. if (ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz,
  503. ram_reserved_size) != 0) {
  504. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  505. return -EIO;
  506. }
  507. }
  508. /* set the block size for the target */
  509. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  510. /* use default number of control buffers */
  511. return -EIO;
  512. /* Configure GPIO AR600x UART */
  513. status = ath6kl_bmi_write_hi32(ar, hi_dbg_uart_txpin,
  514. ar->hw.uarttx_pin);
  515. if (status)
  516. return status;
  517. /* Configure target refclk_hz */
  518. status = ath6kl_bmi_write_hi32(ar, hi_refclk_hz, ar->hw.refclk_hz);
  519. if (status)
  520. return status;
  521. return 0;
  522. }
  523. /* firmware upload */
  524. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  525. u8 **fw, size_t *fw_len)
  526. {
  527. const struct firmware *fw_entry;
  528. int ret;
  529. ret = request_firmware(&fw_entry, filename, ar->dev);
  530. if (ret)
  531. return ret;
  532. *fw_len = fw_entry->size;
  533. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  534. if (*fw == NULL)
  535. ret = -ENOMEM;
  536. release_firmware(fw_entry);
  537. return ret;
  538. }
  539. #ifdef CONFIG_OF
  540. /*
  541. * Check the device tree for a board-id and use it to construct
  542. * the pathname to the firmware file. Used (for now) to find a
  543. * fallback to the "bdata.bin" file--typically a symlink to the
  544. * appropriate board-specific file.
  545. */
  546. static bool check_device_tree(struct ath6kl *ar)
  547. {
  548. static const char *board_id_prop = "atheros,board-id";
  549. struct device_node *node;
  550. char board_filename[64];
  551. const char *board_id;
  552. int ret;
  553. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  554. board_id = of_get_property(node, board_id_prop, NULL);
  555. if (board_id == NULL) {
  556. ath6kl_warn("No \"%s\" property on %s node.\n",
  557. board_id_prop, node->name);
  558. continue;
  559. }
  560. snprintf(board_filename, sizeof(board_filename),
  561. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  562. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  563. &ar->fw_board_len);
  564. if (ret) {
  565. ath6kl_err("Failed to get DT board file %s: %d\n",
  566. board_filename, ret);
  567. continue;
  568. }
  569. return true;
  570. }
  571. return false;
  572. }
  573. #else
  574. static bool check_device_tree(struct ath6kl *ar)
  575. {
  576. return false;
  577. }
  578. #endif /* CONFIG_OF */
  579. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  580. {
  581. const char *filename;
  582. int ret;
  583. if (ar->fw_board != NULL)
  584. return 0;
  585. if (WARN_ON(ar->hw.fw_board == NULL))
  586. return -EINVAL;
  587. filename = ar->hw.fw_board;
  588. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  589. &ar->fw_board_len);
  590. if (ret == 0) {
  591. /* managed to get proper board file */
  592. return 0;
  593. }
  594. if (check_device_tree(ar)) {
  595. /* got board file from device tree */
  596. return 0;
  597. }
  598. /* there was no proper board file, try to use default instead */
  599. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  600. filename, ret);
  601. filename = ar->hw.fw_default_board;
  602. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  603. &ar->fw_board_len);
  604. if (ret) {
  605. ath6kl_err("Failed to get default board file %s: %d\n",
  606. filename, ret);
  607. return ret;
  608. }
  609. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  610. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  611. return 0;
  612. }
  613. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  614. {
  615. char filename[100];
  616. int ret;
  617. if (ar->fw_otp != NULL)
  618. return 0;
  619. if (ar->hw.fw.otp == NULL) {
  620. ath6kl_dbg(ATH6KL_DBG_BOOT,
  621. "no OTP file configured for this hw\n");
  622. return 0;
  623. }
  624. snprintf(filename, sizeof(filename), "%s/%s",
  625. ar->hw.fw.dir, ar->hw.fw.otp);
  626. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  627. &ar->fw_otp_len);
  628. if (ret) {
  629. ath6kl_err("Failed to get OTP file %s: %d\n",
  630. filename, ret);
  631. return ret;
  632. }
  633. return 0;
  634. }
  635. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  636. {
  637. char filename[100];
  638. int ret;
  639. if (ar->testmode == 0)
  640. return 0;
  641. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  642. if (ar->testmode == 2) {
  643. if (ar->hw.fw.utf == NULL) {
  644. ath6kl_warn("testmode 2 not supported\n");
  645. return -EOPNOTSUPP;
  646. }
  647. snprintf(filename, sizeof(filename), "%s/%s",
  648. ar->hw.fw.dir, ar->hw.fw.utf);
  649. } else {
  650. if (ar->hw.fw.tcmd == NULL) {
  651. ath6kl_warn("testmode 1 not supported\n");
  652. return -EOPNOTSUPP;
  653. }
  654. snprintf(filename, sizeof(filename), "%s/%s",
  655. ar->hw.fw.dir, ar->hw.fw.tcmd);
  656. }
  657. set_bit(TESTMODE, &ar->flag);
  658. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  659. if (ret) {
  660. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  661. ar->testmode, filename, ret);
  662. return ret;
  663. }
  664. return 0;
  665. }
  666. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  667. {
  668. char filename[100];
  669. int ret;
  670. if (ar->fw != NULL)
  671. return 0;
  672. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  673. if (WARN_ON(ar->hw.fw.fw == NULL))
  674. return -EINVAL;
  675. snprintf(filename, sizeof(filename), "%s/%s",
  676. ar->hw.fw.dir, ar->hw.fw.fw);
  677. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  678. if (ret) {
  679. ath6kl_err("Failed to get firmware file %s: %d\n",
  680. filename, ret);
  681. return ret;
  682. }
  683. return 0;
  684. }
  685. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  686. {
  687. char filename[100];
  688. int ret;
  689. if (ar->fw_patch != NULL)
  690. return 0;
  691. if (ar->hw.fw.patch == NULL)
  692. return 0;
  693. snprintf(filename, sizeof(filename), "%s/%s",
  694. ar->hw.fw.dir, ar->hw.fw.patch);
  695. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  696. &ar->fw_patch_len);
  697. if (ret) {
  698. ath6kl_err("Failed to get patch file %s: %d\n",
  699. filename, ret);
  700. return ret;
  701. }
  702. return 0;
  703. }
  704. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  705. {
  706. char filename[100];
  707. int ret;
  708. if (ar->testmode != 2)
  709. return 0;
  710. if (ar->fw_testscript != NULL)
  711. return 0;
  712. if (ar->hw.fw.testscript == NULL)
  713. return 0;
  714. snprintf(filename, sizeof(filename), "%s/%s",
  715. ar->hw.fw.dir, ar->hw.fw.testscript);
  716. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  717. &ar->fw_testscript_len);
  718. if (ret) {
  719. ath6kl_err("Failed to get testscript file %s: %d\n",
  720. filename, ret);
  721. return ret;
  722. }
  723. return 0;
  724. }
  725. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  726. {
  727. int ret;
  728. ret = ath6kl_fetch_otp_file(ar);
  729. if (ret)
  730. return ret;
  731. ret = ath6kl_fetch_fw_file(ar);
  732. if (ret)
  733. return ret;
  734. ret = ath6kl_fetch_patch_file(ar);
  735. if (ret)
  736. return ret;
  737. ret = ath6kl_fetch_testscript_file(ar);
  738. if (ret)
  739. return ret;
  740. return 0;
  741. }
  742. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  743. {
  744. size_t magic_len, len, ie_len;
  745. const struct firmware *fw;
  746. struct ath6kl_fw_ie *hdr;
  747. char filename[100];
  748. const u8 *data;
  749. int ret, ie_id, i, index, bit;
  750. __le32 *val;
  751. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  752. ret = request_firmware(&fw, filename, ar->dev);
  753. if (ret)
  754. return ret;
  755. data = fw->data;
  756. len = fw->size;
  757. /* magic also includes the null byte, check that as well */
  758. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  759. if (len < magic_len) {
  760. ret = -EINVAL;
  761. goto out;
  762. }
  763. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  764. ret = -EINVAL;
  765. goto out;
  766. }
  767. len -= magic_len;
  768. data += magic_len;
  769. /* loop elements */
  770. while (len > sizeof(struct ath6kl_fw_ie)) {
  771. /* hdr is unaligned! */
  772. hdr = (struct ath6kl_fw_ie *) data;
  773. ie_id = le32_to_cpup(&hdr->id);
  774. ie_len = le32_to_cpup(&hdr->len);
  775. len -= sizeof(*hdr);
  776. data += sizeof(*hdr);
  777. if (len < ie_len) {
  778. ret = -EINVAL;
  779. goto out;
  780. }
  781. switch (ie_id) {
  782. case ATH6KL_FW_IE_FW_VERSION:
  783. strlcpy(ar->wiphy->fw_version, data,
  784. sizeof(ar->wiphy->fw_version));
  785. ath6kl_dbg(ATH6KL_DBG_BOOT,
  786. "found fw version %s\n",
  787. ar->wiphy->fw_version);
  788. break;
  789. case ATH6KL_FW_IE_OTP_IMAGE:
  790. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  791. ie_len);
  792. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  793. if (ar->fw_otp == NULL) {
  794. ret = -ENOMEM;
  795. goto out;
  796. }
  797. ar->fw_otp_len = ie_len;
  798. break;
  799. case ATH6KL_FW_IE_FW_IMAGE:
  800. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  801. ie_len);
  802. /* in testmode we already might have a fw file */
  803. if (ar->fw != NULL)
  804. break;
  805. ar->fw = vmalloc(ie_len);
  806. if (ar->fw == NULL) {
  807. ret = -ENOMEM;
  808. goto out;
  809. }
  810. memcpy(ar->fw, data, ie_len);
  811. ar->fw_len = ie_len;
  812. break;
  813. case ATH6KL_FW_IE_PATCH_IMAGE:
  814. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  815. ie_len);
  816. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  817. if (ar->fw_patch == NULL) {
  818. ret = -ENOMEM;
  819. goto out;
  820. }
  821. ar->fw_patch_len = ie_len;
  822. break;
  823. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  824. val = (__le32 *) data;
  825. ar->hw.reserved_ram_size = le32_to_cpup(val);
  826. ath6kl_dbg(ATH6KL_DBG_BOOT,
  827. "found reserved ram size ie 0x%d\n",
  828. ar->hw.reserved_ram_size);
  829. break;
  830. case ATH6KL_FW_IE_CAPABILITIES:
  831. ath6kl_dbg(ATH6KL_DBG_BOOT,
  832. "found firmware capabilities ie (%zd B)\n",
  833. ie_len);
  834. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  835. index = i / 8;
  836. bit = i % 8;
  837. if (index == ie_len)
  838. break;
  839. if (data[index] & (1 << bit))
  840. __set_bit(i, ar->fw_capabilities);
  841. }
  842. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  843. ar->fw_capabilities,
  844. sizeof(ar->fw_capabilities));
  845. break;
  846. case ATH6KL_FW_IE_PATCH_ADDR:
  847. if (ie_len != sizeof(*val))
  848. break;
  849. val = (__le32 *) data;
  850. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  851. ath6kl_dbg(ATH6KL_DBG_BOOT,
  852. "found patch address ie 0x%x\n",
  853. ar->hw.dataset_patch_addr);
  854. break;
  855. case ATH6KL_FW_IE_BOARD_ADDR:
  856. if (ie_len != sizeof(*val))
  857. break;
  858. val = (__le32 *) data;
  859. ar->hw.board_addr = le32_to_cpup(val);
  860. ath6kl_dbg(ATH6KL_DBG_BOOT,
  861. "found board address ie 0x%x\n",
  862. ar->hw.board_addr);
  863. break;
  864. case ATH6KL_FW_IE_VIF_MAX:
  865. if (ie_len != sizeof(*val))
  866. break;
  867. val = (__le32 *) data;
  868. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  869. ATH6KL_VIF_MAX);
  870. if (ar->vif_max > 1 && !ar->p2p)
  871. ar->max_norm_iface = 2;
  872. ath6kl_dbg(ATH6KL_DBG_BOOT,
  873. "found vif max ie %d\n", ar->vif_max);
  874. break;
  875. default:
  876. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  877. le32_to_cpup(&hdr->id));
  878. break;
  879. }
  880. len -= ie_len;
  881. data += ie_len;
  882. };
  883. ret = 0;
  884. out:
  885. release_firmware(fw);
  886. return ret;
  887. }
  888. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  889. {
  890. int ret;
  891. ret = ath6kl_fetch_board_file(ar);
  892. if (ret)
  893. return ret;
  894. ret = ath6kl_fetch_testmode_file(ar);
  895. if (ret)
  896. return ret;
  897. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  898. if (ret == 0) {
  899. ar->fw_api = 3;
  900. goto out;
  901. }
  902. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  903. if (ret == 0) {
  904. ar->fw_api = 2;
  905. goto out;
  906. }
  907. ret = ath6kl_fetch_fw_api1(ar);
  908. if (ret)
  909. return ret;
  910. ar->fw_api = 1;
  911. out:
  912. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  913. return 0;
  914. }
  915. static int ath6kl_upload_board_file(struct ath6kl *ar)
  916. {
  917. u32 board_address, board_ext_address, param;
  918. u32 board_data_size, board_ext_data_size;
  919. int ret;
  920. if (WARN_ON(ar->fw_board == NULL))
  921. return -ENOENT;
  922. /*
  923. * Determine where in Target RAM to write Board Data.
  924. * For AR6004, host determine Target RAM address for
  925. * writing board data.
  926. */
  927. if (ar->hw.board_addr != 0) {
  928. board_address = ar->hw.board_addr;
  929. ath6kl_bmi_write_hi32(ar, hi_board_data,
  930. board_address);
  931. } else {
  932. ath6kl_bmi_read_hi32(ar, hi_board_data, &board_address);
  933. }
  934. /* determine where in target ram to write extended board data */
  935. ath6kl_bmi_read_hi32(ar, hi_board_ext_data, &board_ext_address);
  936. if (ar->target_type == TARGET_TYPE_AR6003 &&
  937. board_ext_address == 0) {
  938. ath6kl_err("Failed to get board file target address.\n");
  939. return -EINVAL;
  940. }
  941. switch (ar->target_type) {
  942. case TARGET_TYPE_AR6003:
  943. board_data_size = AR6003_BOARD_DATA_SZ;
  944. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  945. if (ar->fw_board_len > (board_data_size + board_ext_data_size))
  946. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ_V2;
  947. break;
  948. case TARGET_TYPE_AR6004:
  949. board_data_size = AR6004_BOARD_DATA_SZ;
  950. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  951. break;
  952. default:
  953. WARN_ON(1);
  954. return -EINVAL;
  955. break;
  956. }
  957. if (board_ext_address &&
  958. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  959. /* write extended board data */
  960. ath6kl_dbg(ATH6KL_DBG_BOOT,
  961. "writing extended board data to 0x%x (%d B)\n",
  962. board_ext_address, board_ext_data_size);
  963. ret = ath6kl_bmi_write(ar, board_ext_address,
  964. ar->fw_board + board_data_size,
  965. board_ext_data_size);
  966. if (ret) {
  967. ath6kl_err("Failed to write extended board data: %d\n",
  968. ret);
  969. return ret;
  970. }
  971. /* record that extended board data is initialized */
  972. param = (board_ext_data_size << 16) | 1;
  973. ath6kl_bmi_write_hi32(ar, hi_board_ext_data_config, param);
  974. }
  975. if (ar->fw_board_len < board_data_size) {
  976. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  977. ret = -EINVAL;
  978. return ret;
  979. }
  980. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  981. board_address, board_data_size);
  982. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  983. board_data_size);
  984. if (ret) {
  985. ath6kl_err("Board file bmi write failed: %d\n", ret);
  986. return ret;
  987. }
  988. /* record the fact that Board Data IS initialized */
  989. ath6kl_bmi_write_hi32(ar, hi_board_data_initialized, 1);
  990. return ret;
  991. }
  992. static int ath6kl_upload_otp(struct ath6kl *ar)
  993. {
  994. u32 address, param;
  995. bool from_hw = false;
  996. int ret;
  997. if (ar->fw_otp == NULL)
  998. return 0;
  999. address = ar->hw.app_load_addr;
  1000. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  1001. ar->fw_otp_len);
  1002. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  1003. ar->fw_otp_len);
  1004. if (ret) {
  1005. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  1006. return ret;
  1007. }
  1008. /* read firmware start address */
  1009. ret = ath6kl_bmi_read_hi32(ar, hi_app_start, &address);
  1010. if (ret) {
  1011. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  1012. return ret;
  1013. }
  1014. if (ar->hw.app_start_override_addr == 0) {
  1015. ar->hw.app_start_override_addr = address;
  1016. from_hw = true;
  1017. }
  1018. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  1019. from_hw ? " (from hw)" : "",
  1020. ar->hw.app_start_override_addr);
  1021. /* execute the OTP code */
  1022. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  1023. ar->hw.app_start_override_addr);
  1024. param = 0;
  1025. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  1026. return ret;
  1027. }
  1028. static int ath6kl_upload_firmware(struct ath6kl *ar)
  1029. {
  1030. u32 address;
  1031. int ret;
  1032. if (WARN_ON(ar->fw == NULL))
  1033. return 0;
  1034. address = ar->hw.app_load_addr;
  1035. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  1036. address, ar->fw_len);
  1037. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  1038. if (ret) {
  1039. ath6kl_err("Failed to write firmware: %d\n", ret);
  1040. return ret;
  1041. }
  1042. /*
  1043. * Set starting address for firmware
  1044. * Don't need to setup app_start override addr on AR6004
  1045. */
  1046. if (ar->target_type != TARGET_TYPE_AR6004) {
  1047. address = ar->hw.app_start_override_addr;
  1048. ath6kl_bmi_set_app_start(ar, address);
  1049. }
  1050. return ret;
  1051. }
  1052. static int ath6kl_upload_patch(struct ath6kl *ar)
  1053. {
  1054. u32 address;
  1055. int ret;
  1056. if (ar->fw_patch == NULL)
  1057. return 0;
  1058. address = ar->hw.dataset_patch_addr;
  1059. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1060. address, ar->fw_patch_len);
  1061. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1062. if (ret) {
  1063. ath6kl_err("Failed to write patch file: %d\n", ret);
  1064. return ret;
  1065. }
  1066. ath6kl_bmi_write_hi32(ar, hi_dset_list_head, address);
  1067. return 0;
  1068. }
  1069. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1070. {
  1071. u32 address;
  1072. int ret;
  1073. if (ar->testmode != 2)
  1074. return 0;
  1075. if (ar->fw_testscript == NULL)
  1076. return 0;
  1077. address = ar->hw.testscript_addr;
  1078. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1079. address, ar->fw_testscript_len);
  1080. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1081. ar->fw_testscript_len);
  1082. if (ret) {
  1083. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1084. return ret;
  1085. }
  1086. ath6kl_bmi_write_hi32(ar, hi_ota_testscript, address);
  1087. ath6kl_bmi_write_hi32(ar, hi_end_ram_reserve_sz, 4096);
  1088. ath6kl_bmi_write_hi32(ar, hi_test_apps_related, 1);
  1089. return 0;
  1090. }
  1091. static int ath6kl_init_upload(struct ath6kl *ar)
  1092. {
  1093. u32 param, options, sleep, address;
  1094. int status = 0;
  1095. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1096. ar->target_type != TARGET_TYPE_AR6004)
  1097. return -EINVAL;
  1098. /* temporarily disable system sleep */
  1099. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1100. status = ath6kl_bmi_reg_read(ar, address, &param);
  1101. if (status)
  1102. return status;
  1103. options = param;
  1104. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1105. status = ath6kl_bmi_reg_write(ar, address, param);
  1106. if (status)
  1107. return status;
  1108. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1109. status = ath6kl_bmi_reg_read(ar, address, &param);
  1110. if (status)
  1111. return status;
  1112. sleep = param;
  1113. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1114. status = ath6kl_bmi_reg_write(ar, address, param);
  1115. if (status)
  1116. return status;
  1117. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1118. options, sleep);
  1119. /* program analog PLL register */
  1120. /* no need to control 40/44MHz clock on AR6004 */
  1121. if (ar->target_type != TARGET_TYPE_AR6004) {
  1122. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1123. 0xF9104001);
  1124. if (status)
  1125. return status;
  1126. /* Run at 80/88MHz by default */
  1127. param = SM(CPU_CLOCK_STANDARD, 1);
  1128. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1129. status = ath6kl_bmi_reg_write(ar, address, param);
  1130. if (status)
  1131. return status;
  1132. }
  1133. param = 0;
  1134. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1135. param = SM(LPO_CAL_ENABLE, 1);
  1136. status = ath6kl_bmi_reg_write(ar, address, param);
  1137. if (status)
  1138. return status;
  1139. /* WAR to avoid SDIO CRC err */
  1140. if (ar->version.target_ver == AR6003_HW_2_0_VERSION ||
  1141. ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
  1142. ath6kl_err("temporary war to avoid sdio crc error\n");
  1143. param = 0x28;
  1144. address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS;
  1145. status = ath6kl_bmi_reg_write(ar, address, param);
  1146. if (status)
  1147. return status;
  1148. param = 0x20;
  1149. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1150. status = ath6kl_bmi_reg_write(ar, address, param);
  1151. if (status)
  1152. return status;
  1153. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1154. status = ath6kl_bmi_reg_write(ar, address, param);
  1155. if (status)
  1156. return status;
  1157. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1158. status = ath6kl_bmi_reg_write(ar, address, param);
  1159. if (status)
  1160. return status;
  1161. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1162. status = ath6kl_bmi_reg_write(ar, address, param);
  1163. if (status)
  1164. return status;
  1165. }
  1166. /* write EEPROM data to Target RAM */
  1167. status = ath6kl_upload_board_file(ar);
  1168. if (status)
  1169. return status;
  1170. /* transfer One time Programmable data */
  1171. status = ath6kl_upload_otp(ar);
  1172. if (status)
  1173. return status;
  1174. /* Download Target firmware */
  1175. status = ath6kl_upload_firmware(ar);
  1176. if (status)
  1177. return status;
  1178. status = ath6kl_upload_patch(ar);
  1179. if (status)
  1180. return status;
  1181. /* Download the test script */
  1182. status = ath6kl_upload_testscript(ar);
  1183. if (status)
  1184. return status;
  1185. /* Restore system sleep */
  1186. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1187. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1188. if (status)
  1189. return status;
  1190. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1191. param = options | 0x20;
  1192. status = ath6kl_bmi_reg_write(ar, address, param);
  1193. if (status)
  1194. return status;
  1195. return status;
  1196. }
  1197. int ath6kl_init_hw_params(struct ath6kl *ar)
  1198. {
  1199. const struct ath6kl_hw *uninitialized_var(hw);
  1200. int i;
  1201. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1202. hw = &hw_list[i];
  1203. if (hw->id == ar->version.target_ver)
  1204. break;
  1205. }
  1206. if (i == ARRAY_SIZE(hw_list)) {
  1207. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1208. ar->version.target_ver);
  1209. return -EINVAL;
  1210. }
  1211. ar->hw = *hw;
  1212. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1213. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1214. ar->version.target_ver, ar->target_type,
  1215. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1216. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1217. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1218. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1219. ar->hw.reserved_ram_size);
  1220. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1221. "refclk_hz %d uarttx_pin %d",
  1222. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1223. return 0;
  1224. }
  1225. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1226. {
  1227. switch (type) {
  1228. case ATH6KL_HIF_TYPE_SDIO:
  1229. return "sdio";
  1230. case ATH6KL_HIF_TYPE_USB:
  1231. return "usb";
  1232. }
  1233. return NULL;
  1234. }
  1235. int ath6kl_init_hw_start(struct ath6kl *ar)
  1236. {
  1237. long timeleft;
  1238. int ret, i;
  1239. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1240. ret = ath6kl_hif_power_on(ar);
  1241. if (ret)
  1242. return ret;
  1243. ret = ath6kl_configure_target(ar);
  1244. if (ret)
  1245. goto err_power_off;
  1246. ret = ath6kl_init_upload(ar);
  1247. if (ret)
  1248. goto err_power_off;
  1249. /* Do we need to finish the BMI phase */
  1250. /* FIXME: return error from ath6kl_bmi_done() */
  1251. if (ath6kl_bmi_done(ar)) {
  1252. ret = -EIO;
  1253. goto err_power_off;
  1254. }
  1255. /*
  1256. * The reason we have to wait for the target here is that the
  1257. * driver layer has to init BMI in order to set the host block
  1258. * size.
  1259. */
  1260. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1261. ret = -EIO;
  1262. goto err_power_off;
  1263. }
  1264. if (ath6kl_init_service_ep(ar)) {
  1265. ret = -EIO;
  1266. goto err_cleanup_scatter;
  1267. }
  1268. /* setup credit distribution */
  1269. ath6kl_htc_credit_setup(ar->htc_target, &ar->credit_state_info);
  1270. /* start HTC */
  1271. ret = ath6kl_htc_start(ar->htc_target);
  1272. if (ret) {
  1273. /* FIXME: call this */
  1274. ath6kl_cookie_cleanup(ar);
  1275. goto err_cleanup_scatter;
  1276. }
  1277. /* Wait for Wmi event to be ready */
  1278. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1279. test_bit(WMI_READY,
  1280. &ar->flag),
  1281. WMI_TIMEOUT);
  1282. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1283. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1284. ath6kl_info("%s %s fw %s api %d%s\n",
  1285. ar->hw.name,
  1286. ath6kl_init_get_hif_name(ar->hif_type),
  1287. ar->wiphy->fw_version,
  1288. ar->fw_api,
  1289. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1290. }
  1291. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1292. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1293. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1294. ret = -EIO;
  1295. goto err_htc_stop;
  1296. }
  1297. if (!timeleft || signal_pending(current)) {
  1298. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1299. ret = -EIO;
  1300. goto err_htc_stop;
  1301. }
  1302. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1303. /* communicate the wmi protocol verision to the target */
  1304. /* FIXME: return error */
  1305. if ((ath6kl_set_host_app_area(ar)) != 0)
  1306. ath6kl_err("unable to set the host app area\n");
  1307. for (i = 0; i < ar->vif_max; i++) {
  1308. ret = ath6kl_target_config_wlan_params(ar, i);
  1309. if (ret)
  1310. goto err_htc_stop;
  1311. }
  1312. ar->state = ATH6KL_STATE_ON;
  1313. return 0;
  1314. err_htc_stop:
  1315. ath6kl_htc_stop(ar->htc_target);
  1316. err_cleanup_scatter:
  1317. ath6kl_hif_cleanup_scatter(ar);
  1318. err_power_off:
  1319. ath6kl_hif_power_off(ar);
  1320. return ret;
  1321. }
  1322. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1323. {
  1324. int ret;
  1325. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1326. ath6kl_htc_stop(ar->htc_target);
  1327. ath6kl_hif_stop(ar);
  1328. ath6kl_bmi_reset(ar);
  1329. ret = ath6kl_hif_power_off(ar);
  1330. if (ret)
  1331. ath6kl_warn("failed to power off hif: %d\n", ret);
  1332. ar->state = ATH6KL_STATE_OFF;
  1333. return 0;
  1334. }
  1335. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1336. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1337. {
  1338. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1339. bool discon_issued;
  1340. netif_stop_queue(vif->ndev);
  1341. clear_bit(WLAN_ENABLED, &vif->flags);
  1342. if (wmi_ready) {
  1343. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1344. test_bit(CONNECT_PEND, &vif->flags);
  1345. ath6kl_disconnect(vif);
  1346. del_timer(&vif->disconnect_timer);
  1347. if (discon_issued)
  1348. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1349. (vif->nw_type & AP_NETWORK) ?
  1350. bcast_mac : vif->bssid,
  1351. 0, NULL, 0);
  1352. }
  1353. if (vif->scan_req) {
  1354. cfg80211_scan_done(vif->scan_req, true);
  1355. vif->scan_req = NULL;
  1356. }
  1357. /* need to clean up enhanced bmiss detection fw state */
  1358. ath6kl_cfg80211_sta_bmiss_enhance(vif, false);
  1359. }
  1360. void ath6kl_stop_txrx(struct ath6kl *ar)
  1361. {
  1362. struct ath6kl_vif *vif, *tmp_vif;
  1363. int i;
  1364. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1365. if (down_interruptible(&ar->sem)) {
  1366. ath6kl_err("down_interruptible failed\n");
  1367. return;
  1368. }
  1369. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1370. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1371. spin_lock_bh(&ar->list_lock);
  1372. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1373. list_del(&vif->list);
  1374. spin_unlock_bh(&ar->list_lock);
  1375. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1376. rtnl_lock();
  1377. ath6kl_cfg80211_vif_cleanup(vif);
  1378. rtnl_unlock();
  1379. spin_lock_bh(&ar->list_lock);
  1380. }
  1381. spin_unlock_bh(&ar->list_lock);
  1382. clear_bit(WMI_READY, &ar->flag);
  1383. /*
  1384. * After wmi_shudown all WMI events will be dropped. We
  1385. * need to cleanup the buffers allocated in AP mode and
  1386. * give disconnect notification to stack, which usually
  1387. * happens in the disconnect_event. Simulate the disconnect
  1388. * event by calling the function directly. Sometimes
  1389. * disconnect_event will be received when the debug logs
  1390. * are collected.
  1391. */
  1392. ath6kl_wmi_shutdown(ar->wmi);
  1393. clear_bit(WMI_ENABLED, &ar->flag);
  1394. if (ar->htc_target) {
  1395. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1396. ath6kl_htc_stop(ar->htc_target);
  1397. }
  1398. /*
  1399. * Try to reset the device if we can. The driver may have been
  1400. * configure NOT to reset the target during a debug session.
  1401. */
  1402. ath6kl_dbg(ATH6KL_DBG_TRC,
  1403. "attempting to reset target on instance destroy\n");
  1404. ath6kl_reset_device(ar, ar->target_type, true, true);
  1405. clear_bit(WLAN_ENABLED, &ar->flag);
  1406. up(&ar->sem);
  1407. }
  1408. EXPORT_SYMBOL(ath6kl_stop_txrx);