asix_devices.c 26 KB

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  1. /*
  2. * ASIX AX8817X based USB 2.0 Ethernet Devices
  3. * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
  4. * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
  5. * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
  6. * Copyright (c) 2002-2003 TiVo Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include "asix.h"
  23. #define PHY_MODE_MARVELL 0x0000
  24. #define MII_MARVELL_LED_CTRL 0x0018
  25. #define MII_MARVELL_STATUS 0x001b
  26. #define MII_MARVELL_CTRL 0x0014
  27. #define MARVELL_LED_MANUAL 0x0019
  28. #define MARVELL_STATUS_HWCFG 0x0004
  29. #define MARVELL_CTRL_TXDELAY 0x0002
  30. #define MARVELL_CTRL_RXDELAY 0x0080
  31. #define PHY_MODE_RTL8211CL 0x000C
  32. struct ax88172_int_data {
  33. __le16 res1;
  34. u8 link;
  35. __le16 res2;
  36. u8 status;
  37. __le16 res3;
  38. } __packed;
  39. static void asix_status(struct usbnet *dev, struct urb *urb)
  40. {
  41. struct ax88172_int_data *event;
  42. int link;
  43. if (urb->actual_length < 8)
  44. return;
  45. event = urb->transfer_buffer;
  46. link = event->link & 0x01;
  47. if (netif_carrier_ok(dev->net) != link) {
  48. if (link) {
  49. netif_carrier_on(dev->net);
  50. usbnet_defer_kevent (dev, EVENT_LINK_RESET );
  51. } else
  52. netif_carrier_off(dev->net);
  53. netdev_dbg(dev->net, "Link Status is: %d\n", link);
  54. }
  55. }
  56. /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
  57. static u32 asix_get_phyid(struct usbnet *dev)
  58. {
  59. int phy_reg;
  60. u32 phy_id;
  61. int i;
  62. /* Poll for the rare case the FW or phy isn't ready yet. */
  63. for (i = 0; i < 100; i++) {
  64. phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
  65. if (phy_reg != 0 && phy_reg != 0xFFFF)
  66. break;
  67. mdelay(1);
  68. }
  69. if (phy_reg <= 0 || phy_reg == 0xFFFF)
  70. return 0;
  71. phy_id = (phy_reg & 0xffff) << 16;
  72. phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
  73. if (phy_reg < 0)
  74. return 0;
  75. phy_id |= (phy_reg & 0xffff);
  76. return phy_id;
  77. }
  78. static u32 asix_get_link(struct net_device *net)
  79. {
  80. struct usbnet *dev = netdev_priv(net);
  81. return mii_link_ok(&dev->mii);
  82. }
  83. static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
  84. {
  85. struct usbnet *dev = netdev_priv(net);
  86. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  87. }
  88. /* We need to override some ethtool_ops so we require our
  89. own structure so we don't interfere with other usbnet
  90. devices that may be connected at the same time. */
  91. static const struct ethtool_ops ax88172_ethtool_ops = {
  92. .get_drvinfo = asix_get_drvinfo,
  93. .get_link = asix_get_link,
  94. .get_msglevel = usbnet_get_msglevel,
  95. .set_msglevel = usbnet_set_msglevel,
  96. .get_wol = asix_get_wol,
  97. .set_wol = asix_set_wol,
  98. .get_eeprom_len = asix_get_eeprom_len,
  99. .get_eeprom = asix_get_eeprom,
  100. .set_eeprom = asix_set_eeprom,
  101. .get_settings = usbnet_get_settings,
  102. .set_settings = usbnet_set_settings,
  103. .nway_reset = usbnet_nway_reset,
  104. };
  105. static void ax88172_set_multicast(struct net_device *net)
  106. {
  107. struct usbnet *dev = netdev_priv(net);
  108. struct asix_data *data = (struct asix_data *)&dev->data;
  109. u8 rx_ctl = 0x8c;
  110. if (net->flags & IFF_PROMISC) {
  111. rx_ctl |= 0x01;
  112. } else if (net->flags & IFF_ALLMULTI ||
  113. netdev_mc_count(net) > AX_MAX_MCAST) {
  114. rx_ctl |= 0x02;
  115. } else if (netdev_mc_empty(net)) {
  116. /* just broadcast and directed */
  117. } else {
  118. /* We use the 20 byte dev->data
  119. * for our 8 byte filter buffer
  120. * to avoid allocating memory that
  121. * is tricky to free later */
  122. struct netdev_hw_addr *ha;
  123. u32 crc_bits;
  124. memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
  125. /* Build the multicast hash filter. */
  126. netdev_for_each_mc_addr(ha, net) {
  127. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  128. data->multi_filter[crc_bits >> 3] |=
  129. 1 << (crc_bits & 7);
  130. }
  131. asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
  132. AX_MCAST_FILTER_SIZE, data->multi_filter);
  133. rx_ctl |= 0x10;
  134. }
  135. asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
  136. }
  137. static int ax88172_link_reset(struct usbnet *dev)
  138. {
  139. u8 mode;
  140. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  141. mii_check_media(&dev->mii, 1, 1);
  142. mii_ethtool_gset(&dev->mii, &ecmd);
  143. mode = AX88172_MEDIUM_DEFAULT;
  144. if (ecmd.duplex != DUPLEX_FULL)
  145. mode |= ~AX88172_MEDIUM_FD;
  146. netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  147. ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
  148. asix_write_medium_mode(dev, mode);
  149. return 0;
  150. }
  151. static const struct net_device_ops ax88172_netdev_ops = {
  152. .ndo_open = usbnet_open,
  153. .ndo_stop = usbnet_stop,
  154. .ndo_start_xmit = usbnet_start_xmit,
  155. .ndo_tx_timeout = usbnet_tx_timeout,
  156. .ndo_change_mtu = usbnet_change_mtu,
  157. .ndo_set_mac_address = eth_mac_addr,
  158. .ndo_validate_addr = eth_validate_addr,
  159. .ndo_do_ioctl = asix_ioctl,
  160. .ndo_set_rx_mode = ax88172_set_multicast,
  161. };
  162. static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
  163. {
  164. int ret = 0;
  165. u8 buf[ETH_ALEN];
  166. int i;
  167. unsigned long gpio_bits = dev->driver_info->data;
  168. usbnet_get_endpoints(dev,intf);
  169. /* Toggle the GPIOs in a manufacturer/model specific way */
  170. for (i = 2; i >= 0; i--) {
  171. ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
  172. (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
  173. if (ret < 0)
  174. goto out;
  175. msleep(5);
  176. }
  177. ret = asix_write_rx_ctl(dev, 0x80);
  178. if (ret < 0)
  179. goto out;
  180. /* Get the MAC address */
  181. ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  182. if (ret < 0) {
  183. dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
  184. goto out;
  185. }
  186. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  187. /* Initialize MII structure */
  188. dev->mii.dev = dev->net;
  189. dev->mii.mdio_read = asix_mdio_read;
  190. dev->mii.mdio_write = asix_mdio_write;
  191. dev->mii.phy_id_mask = 0x3f;
  192. dev->mii.reg_num_mask = 0x1f;
  193. dev->mii.phy_id = asix_get_phy_addr(dev);
  194. dev->net->netdev_ops = &ax88172_netdev_ops;
  195. dev->net->ethtool_ops = &ax88172_ethtool_ops;
  196. dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
  197. dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
  198. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  199. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  200. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  201. mii_nway_restart(&dev->mii);
  202. return 0;
  203. out:
  204. return ret;
  205. }
  206. static const struct ethtool_ops ax88772_ethtool_ops = {
  207. .get_drvinfo = asix_get_drvinfo,
  208. .get_link = asix_get_link,
  209. .get_msglevel = usbnet_get_msglevel,
  210. .set_msglevel = usbnet_set_msglevel,
  211. .get_wol = asix_get_wol,
  212. .set_wol = asix_set_wol,
  213. .get_eeprom_len = asix_get_eeprom_len,
  214. .get_eeprom = asix_get_eeprom,
  215. .set_eeprom = asix_set_eeprom,
  216. .get_settings = usbnet_get_settings,
  217. .set_settings = usbnet_set_settings,
  218. .nway_reset = usbnet_nway_reset,
  219. };
  220. static int ax88772_link_reset(struct usbnet *dev)
  221. {
  222. u16 mode;
  223. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  224. mii_check_media(&dev->mii, 1, 1);
  225. mii_ethtool_gset(&dev->mii, &ecmd);
  226. mode = AX88772_MEDIUM_DEFAULT;
  227. if (ethtool_cmd_speed(&ecmd) != SPEED_100)
  228. mode &= ~AX_MEDIUM_PS;
  229. if (ecmd.duplex != DUPLEX_FULL)
  230. mode &= ~AX_MEDIUM_FD;
  231. netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  232. ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
  233. asix_write_medium_mode(dev, mode);
  234. return 0;
  235. }
  236. static int ax88772_reset(struct usbnet *dev)
  237. {
  238. struct asix_data *data = (struct asix_data *)&dev->data;
  239. int ret, embd_phy;
  240. u16 rx_ctl;
  241. ret = asix_write_gpio(dev,
  242. AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
  243. if (ret < 0)
  244. goto out;
  245. embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
  246. ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
  247. if (ret < 0) {
  248. dbg("Select PHY #1 failed: %d", ret);
  249. goto out;
  250. }
  251. ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
  252. if (ret < 0)
  253. goto out;
  254. msleep(150);
  255. ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
  256. if (ret < 0)
  257. goto out;
  258. msleep(150);
  259. if (embd_phy) {
  260. ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
  261. if (ret < 0)
  262. goto out;
  263. } else {
  264. ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
  265. if (ret < 0)
  266. goto out;
  267. }
  268. msleep(150);
  269. rx_ctl = asix_read_rx_ctl(dev);
  270. dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
  271. ret = asix_write_rx_ctl(dev, 0x0000);
  272. if (ret < 0)
  273. goto out;
  274. rx_ctl = asix_read_rx_ctl(dev);
  275. dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
  276. ret = asix_sw_reset(dev, AX_SWRESET_PRL);
  277. if (ret < 0)
  278. goto out;
  279. msleep(150);
  280. ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
  281. if (ret < 0)
  282. goto out;
  283. msleep(150);
  284. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  285. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  286. ADVERTISE_ALL | ADVERTISE_CSMA);
  287. mii_nway_restart(&dev->mii);
  288. ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
  289. if (ret < 0)
  290. goto out;
  291. ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
  292. AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
  293. AX88772_IPG2_DEFAULT, 0, NULL);
  294. if (ret < 0) {
  295. dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
  296. goto out;
  297. }
  298. /* Rewrite MAC address */
  299. memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
  300. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
  301. data->mac_addr);
  302. if (ret < 0)
  303. goto out;
  304. /* Set RX_CTL to default values with 2k buffer, and enable cactus */
  305. ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
  306. if (ret < 0)
  307. goto out;
  308. rx_ctl = asix_read_rx_ctl(dev);
  309. dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
  310. rx_ctl = asix_read_medium_status(dev);
  311. dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
  312. return 0;
  313. out:
  314. return ret;
  315. }
  316. static const struct net_device_ops ax88772_netdev_ops = {
  317. .ndo_open = usbnet_open,
  318. .ndo_stop = usbnet_stop,
  319. .ndo_start_xmit = usbnet_start_xmit,
  320. .ndo_tx_timeout = usbnet_tx_timeout,
  321. .ndo_change_mtu = usbnet_change_mtu,
  322. .ndo_set_mac_address = asix_set_mac_address,
  323. .ndo_validate_addr = eth_validate_addr,
  324. .ndo_do_ioctl = asix_ioctl,
  325. .ndo_set_rx_mode = asix_set_multicast,
  326. };
  327. static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
  328. {
  329. int ret, embd_phy;
  330. u8 buf[ETH_ALEN];
  331. u32 phyid;
  332. usbnet_get_endpoints(dev,intf);
  333. /* Get the MAC address */
  334. ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  335. if (ret < 0) {
  336. dbg("Failed to read MAC address: %d", ret);
  337. return ret;
  338. }
  339. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  340. /* Initialize MII structure */
  341. dev->mii.dev = dev->net;
  342. dev->mii.mdio_read = asix_mdio_read;
  343. dev->mii.mdio_write = asix_mdio_write;
  344. dev->mii.phy_id_mask = 0x1f;
  345. dev->mii.reg_num_mask = 0x1f;
  346. dev->mii.phy_id = asix_get_phy_addr(dev);
  347. dev->net->netdev_ops = &ax88772_netdev_ops;
  348. dev->net->ethtool_ops = &ax88772_ethtool_ops;
  349. dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
  350. dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
  351. embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
  352. /* Reset the PHY to normal operation mode */
  353. ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
  354. if (ret < 0) {
  355. dbg("Select PHY #1 failed: %d", ret);
  356. return ret;
  357. }
  358. ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
  359. if (ret < 0)
  360. return ret;
  361. msleep(150);
  362. ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
  363. if (ret < 0)
  364. return ret;
  365. msleep(150);
  366. ret = asix_sw_reset(dev, embd_phy ? AX_SWRESET_IPRL : AX_SWRESET_PRTE);
  367. /* Read PHYID register *AFTER* the PHY was reset properly */
  368. phyid = asix_get_phyid(dev);
  369. dbg("PHYID=0x%08x", phyid);
  370. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  371. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  372. /* hard_mtu is still the default - the device does not support
  373. jumbo eth frames */
  374. dev->rx_urb_size = 2048;
  375. }
  376. return 0;
  377. }
  378. static const struct ethtool_ops ax88178_ethtool_ops = {
  379. .get_drvinfo = asix_get_drvinfo,
  380. .get_link = asix_get_link,
  381. .get_msglevel = usbnet_get_msglevel,
  382. .set_msglevel = usbnet_set_msglevel,
  383. .get_wol = asix_get_wol,
  384. .set_wol = asix_set_wol,
  385. .get_eeprom_len = asix_get_eeprom_len,
  386. .get_eeprom = asix_get_eeprom,
  387. .set_eeprom = asix_set_eeprom,
  388. .get_settings = usbnet_get_settings,
  389. .set_settings = usbnet_set_settings,
  390. .nway_reset = usbnet_nway_reset,
  391. };
  392. static int marvell_phy_init(struct usbnet *dev)
  393. {
  394. struct asix_data *data = (struct asix_data *)&dev->data;
  395. u16 reg;
  396. netdev_dbg(dev->net, "marvell_phy_init()\n");
  397. reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
  398. netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
  399. asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
  400. MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
  401. if (data->ledmode) {
  402. reg = asix_mdio_read(dev->net, dev->mii.phy_id,
  403. MII_MARVELL_LED_CTRL);
  404. netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
  405. reg &= 0xf8ff;
  406. reg |= (1 + 0x0100);
  407. asix_mdio_write(dev->net, dev->mii.phy_id,
  408. MII_MARVELL_LED_CTRL, reg);
  409. reg = asix_mdio_read(dev->net, dev->mii.phy_id,
  410. MII_MARVELL_LED_CTRL);
  411. netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
  412. reg &= 0xfc0f;
  413. }
  414. return 0;
  415. }
  416. static int rtl8211cl_phy_init(struct usbnet *dev)
  417. {
  418. struct asix_data *data = (struct asix_data *)&dev->data;
  419. netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
  420. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
  421. asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
  422. asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
  423. asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
  424. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
  425. if (data->ledmode == 12) {
  426. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
  427. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
  428. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
  429. }
  430. return 0;
  431. }
  432. static int marvell_led_status(struct usbnet *dev, u16 speed)
  433. {
  434. u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
  435. netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
  436. /* Clear out the center LED bits - 0x03F0 */
  437. reg &= 0xfc0f;
  438. switch (speed) {
  439. case SPEED_1000:
  440. reg |= 0x03e0;
  441. break;
  442. case SPEED_100:
  443. reg |= 0x03b0;
  444. break;
  445. default:
  446. reg |= 0x02f0;
  447. }
  448. netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
  449. asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
  450. return 0;
  451. }
  452. static int ax88178_reset(struct usbnet *dev)
  453. {
  454. struct asix_data *data = (struct asix_data *)&dev->data;
  455. int ret;
  456. __le16 eeprom;
  457. u8 status;
  458. int gpio0 = 0;
  459. u32 phyid;
  460. asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
  461. dbg("GPIO Status: 0x%04x", status);
  462. asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
  463. asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
  464. asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
  465. dbg("EEPROM index 0x17 is 0x%04x", eeprom);
  466. if (eeprom == cpu_to_le16(0xffff)) {
  467. data->phymode = PHY_MODE_MARVELL;
  468. data->ledmode = 0;
  469. gpio0 = 1;
  470. } else {
  471. data->phymode = le16_to_cpu(eeprom) & 0x7F;
  472. data->ledmode = le16_to_cpu(eeprom) >> 8;
  473. gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
  474. }
  475. dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
  476. /* Power up external GigaPHY through AX88178 GPIO pin */
  477. asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
  478. if ((le16_to_cpu(eeprom) >> 8) != 1) {
  479. asix_write_gpio(dev, 0x003c, 30);
  480. asix_write_gpio(dev, 0x001c, 300);
  481. asix_write_gpio(dev, 0x003c, 30);
  482. } else {
  483. dbg("gpio phymode == 1 path");
  484. asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
  485. asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
  486. }
  487. /* Read PHYID register *AFTER* powering up PHY */
  488. phyid = asix_get_phyid(dev);
  489. dbg("PHYID=0x%08x", phyid);
  490. /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
  491. asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
  492. asix_sw_reset(dev, 0);
  493. msleep(150);
  494. asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
  495. msleep(150);
  496. asix_write_rx_ctl(dev, 0);
  497. if (data->phymode == PHY_MODE_MARVELL) {
  498. marvell_phy_init(dev);
  499. msleep(60);
  500. } else if (data->phymode == PHY_MODE_RTL8211CL)
  501. rtl8211cl_phy_init(dev);
  502. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
  503. BMCR_RESET | BMCR_ANENABLE);
  504. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  505. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  506. asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  507. ADVERTISE_1000FULL);
  508. mii_nway_restart(&dev->mii);
  509. ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
  510. if (ret < 0)
  511. return ret;
  512. /* Rewrite MAC address */
  513. memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
  514. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
  515. data->mac_addr);
  516. if (ret < 0)
  517. return ret;
  518. ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
  519. if (ret < 0)
  520. return ret;
  521. return 0;
  522. }
  523. static int ax88178_link_reset(struct usbnet *dev)
  524. {
  525. u16 mode;
  526. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  527. struct asix_data *data = (struct asix_data *)&dev->data;
  528. u32 speed;
  529. netdev_dbg(dev->net, "ax88178_link_reset()\n");
  530. mii_check_media(&dev->mii, 1, 1);
  531. mii_ethtool_gset(&dev->mii, &ecmd);
  532. mode = AX88178_MEDIUM_DEFAULT;
  533. speed = ethtool_cmd_speed(&ecmd);
  534. if (speed == SPEED_1000)
  535. mode |= AX_MEDIUM_GM;
  536. else if (speed == SPEED_100)
  537. mode |= AX_MEDIUM_PS;
  538. else
  539. mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
  540. mode |= AX_MEDIUM_ENCK;
  541. if (ecmd.duplex == DUPLEX_FULL)
  542. mode |= AX_MEDIUM_FD;
  543. else
  544. mode &= ~AX_MEDIUM_FD;
  545. netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  546. speed, ecmd.duplex, mode);
  547. asix_write_medium_mode(dev, mode);
  548. if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
  549. marvell_led_status(dev, speed);
  550. return 0;
  551. }
  552. static void ax88178_set_mfb(struct usbnet *dev)
  553. {
  554. u16 mfb = AX_RX_CTL_MFB_16384;
  555. u16 rxctl;
  556. u16 medium;
  557. int old_rx_urb_size = dev->rx_urb_size;
  558. if (dev->hard_mtu < 2048) {
  559. dev->rx_urb_size = 2048;
  560. mfb = AX_RX_CTL_MFB_2048;
  561. } else if (dev->hard_mtu < 4096) {
  562. dev->rx_urb_size = 4096;
  563. mfb = AX_RX_CTL_MFB_4096;
  564. } else if (dev->hard_mtu < 8192) {
  565. dev->rx_urb_size = 8192;
  566. mfb = AX_RX_CTL_MFB_8192;
  567. } else if (dev->hard_mtu < 16384) {
  568. dev->rx_urb_size = 16384;
  569. mfb = AX_RX_CTL_MFB_16384;
  570. }
  571. rxctl = asix_read_rx_ctl(dev);
  572. asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
  573. medium = asix_read_medium_status(dev);
  574. if (dev->net->mtu > 1500)
  575. medium |= AX_MEDIUM_JFE;
  576. else
  577. medium &= ~AX_MEDIUM_JFE;
  578. asix_write_medium_mode(dev, medium);
  579. if (dev->rx_urb_size > old_rx_urb_size)
  580. usbnet_unlink_rx_urbs(dev);
  581. }
  582. static int ax88178_change_mtu(struct net_device *net, int new_mtu)
  583. {
  584. struct usbnet *dev = netdev_priv(net);
  585. int ll_mtu = new_mtu + net->hard_header_len + 4;
  586. netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
  587. if (new_mtu <= 0 || ll_mtu > 16384)
  588. return -EINVAL;
  589. if ((ll_mtu % dev->maxpacket) == 0)
  590. return -EDOM;
  591. net->mtu = new_mtu;
  592. dev->hard_mtu = net->mtu + net->hard_header_len;
  593. ax88178_set_mfb(dev);
  594. return 0;
  595. }
  596. static const struct net_device_ops ax88178_netdev_ops = {
  597. .ndo_open = usbnet_open,
  598. .ndo_stop = usbnet_stop,
  599. .ndo_start_xmit = usbnet_start_xmit,
  600. .ndo_tx_timeout = usbnet_tx_timeout,
  601. .ndo_set_mac_address = asix_set_mac_address,
  602. .ndo_validate_addr = eth_validate_addr,
  603. .ndo_set_rx_mode = asix_set_multicast,
  604. .ndo_do_ioctl = asix_ioctl,
  605. .ndo_change_mtu = ax88178_change_mtu,
  606. };
  607. static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
  608. {
  609. int ret;
  610. u8 buf[ETH_ALEN];
  611. usbnet_get_endpoints(dev,intf);
  612. /* Get the MAC address */
  613. ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  614. if (ret < 0) {
  615. dbg("Failed to read MAC address: %d", ret);
  616. return ret;
  617. }
  618. memcpy(dev->net->dev_addr, buf, ETH_ALEN);
  619. /* Initialize MII structure */
  620. dev->mii.dev = dev->net;
  621. dev->mii.mdio_read = asix_mdio_read;
  622. dev->mii.mdio_write = asix_mdio_write;
  623. dev->mii.phy_id_mask = 0x1f;
  624. dev->mii.reg_num_mask = 0xff;
  625. dev->mii.supports_gmii = 1;
  626. dev->mii.phy_id = asix_get_phy_addr(dev);
  627. dev->net->netdev_ops = &ax88178_netdev_ops;
  628. dev->net->ethtool_ops = &ax88178_ethtool_ops;
  629. /* Blink LEDS so users know driver saw dongle */
  630. asix_sw_reset(dev, 0);
  631. msleep(150);
  632. asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
  633. msleep(150);
  634. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  635. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  636. /* hard_mtu is still the default - the device does not support
  637. jumbo eth frames */
  638. dev->rx_urb_size = 2048;
  639. }
  640. return 0;
  641. }
  642. static const struct driver_info ax8817x_info = {
  643. .description = "ASIX AX8817x USB 2.0 Ethernet",
  644. .bind = ax88172_bind,
  645. .status = asix_status,
  646. .link_reset = ax88172_link_reset,
  647. .reset = ax88172_link_reset,
  648. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  649. .data = 0x00130103,
  650. };
  651. static const struct driver_info dlink_dub_e100_info = {
  652. .description = "DLink DUB-E100 USB Ethernet",
  653. .bind = ax88172_bind,
  654. .status = asix_status,
  655. .link_reset = ax88172_link_reset,
  656. .reset = ax88172_link_reset,
  657. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  658. .data = 0x009f9d9f,
  659. };
  660. static const struct driver_info netgear_fa120_info = {
  661. .description = "Netgear FA-120 USB Ethernet",
  662. .bind = ax88172_bind,
  663. .status = asix_status,
  664. .link_reset = ax88172_link_reset,
  665. .reset = ax88172_link_reset,
  666. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  667. .data = 0x00130103,
  668. };
  669. static const struct driver_info hawking_uf200_info = {
  670. .description = "Hawking UF200 USB Ethernet",
  671. .bind = ax88172_bind,
  672. .status = asix_status,
  673. .link_reset = ax88172_link_reset,
  674. .reset = ax88172_link_reset,
  675. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  676. .data = 0x001f1d1f,
  677. };
  678. static const struct driver_info ax88772_info = {
  679. .description = "ASIX AX88772 USB 2.0 Ethernet",
  680. .bind = ax88772_bind,
  681. .status = asix_status,
  682. .link_reset = ax88772_link_reset,
  683. .reset = ax88772_reset,
  684. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
  685. .rx_fixup = asix_rx_fixup,
  686. .tx_fixup = asix_tx_fixup,
  687. };
  688. static const struct driver_info ax88178_info = {
  689. .description = "ASIX AX88178 USB 2.0 Ethernet",
  690. .bind = ax88178_bind,
  691. .status = asix_status,
  692. .link_reset = ax88178_link_reset,
  693. .reset = ax88178_reset,
  694. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR,
  695. .rx_fixup = asix_rx_fixup,
  696. .tx_fixup = asix_tx_fixup,
  697. };
  698. extern const struct driver_info ax88172a_info;
  699. static const struct usb_device_id products [] = {
  700. {
  701. // Linksys USB200M
  702. USB_DEVICE (0x077b, 0x2226),
  703. .driver_info = (unsigned long) &ax8817x_info,
  704. }, {
  705. // Netgear FA120
  706. USB_DEVICE (0x0846, 0x1040),
  707. .driver_info = (unsigned long) &netgear_fa120_info,
  708. }, {
  709. // DLink DUB-E100
  710. USB_DEVICE (0x2001, 0x1a00),
  711. .driver_info = (unsigned long) &dlink_dub_e100_info,
  712. }, {
  713. // Intellinet, ST Lab USB Ethernet
  714. USB_DEVICE (0x0b95, 0x1720),
  715. .driver_info = (unsigned long) &ax8817x_info,
  716. }, {
  717. // Hawking UF200, TrendNet TU2-ET100
  718. USB_DEVICE (0x07b8, 0x420a),
  719. .driver_info = (unsigned long) &hawking_uf200_info,
  720. }, {
  721. // Billionton Systems, USB2AR
  722. USB_DEVICE (0x08dd, 0x90ff),
  723. .driver_info = (unsigned long) &ax8817x_info,
  724. }, {
  725. // ATEN UC210T
  726. USB_DEVICE (0x0557, 0x2009),
  727. .driver_info = (unsigned long) &ax8817x_info,
  728. }, {
  729. // Buffalo LUA-U2-KTX
  730. USB_DEVICE (0x0411, 0x003d),
  731. .driver_info = (unsigned long) &ax8817x_info,
  732. }, {
  733. // Buffalo LUA-U2-GT 10/100/1000
  734. USB_DEVICE (0x0411, 0x006e),
  735. .driver_info = (unsigned long) &ax88178_info,
  736. }, {
  737. // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
  738. USB_DEVICE (0x6189, 0x182d),
  739. .driver_info = (unsigned long) &ax8817x_info,
  740. }, {
  741. // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
  742. USB_DEVICE (0x0df6, 0x0056),
  743. .driver_info = (unsigned long) &ax88178_info,
  744. }, {
  745. // corega FEther USB2-TX
  746. USB_DEVICE (0x07aa, 0x0017),
  747. .driver_info = (unsigned long) &ax8817x_info,
  748. }, {
  749. // Surecom EP-1427X-2
  750. USB_DEVICE (0x1189, 0x0893),
  751. .driver_info = (unsigned long) &ax8817x_info,
  752. }, {
  753. // goodway corp usb gwusb2e
  754. USB_DEVICE (0x1631, 0x6200),
  755. .driver_info = (unsigned long) &ax8817x_info,
  756. }, {
  757. // JVC MP-PRX1 Port Replicator
  758. USB_DEVICE (0x04f1, 0x3008),
  759. .driver_info = (unsigned long) &ax8817x_info,
  760. }, {
  761. // ASIX AX88772B 10/100
  762. USB_DEVICE (0x0b95, 0x772b),
  763. .driver_info = (unsigned long) &ax88772_info,
  764. }, {
  765. // ASIX AX88772 10/100
  766. USB_DEVICE (0x0b95, 0x7720),
  767. .driver_info = (unsigned long) &ax88772_info,
  768. }, {
  769. // ASIX AX88178 10/100/1000
  770. USB_DEVICE (0x0b95, 0x1780),
  771. .driver_info = (unsigned long) &ax88178_info,
  772. }, {
  773. // Logitec LAN-GTJ/U2A
  774. USB_DEVICE (0x0789, 0x0160),
  775. .driver_info = (unsigned long) &ax88178_info,
  776. }, {
  777. // Linksys USB200M Rev 2
  778. USB_DEVICE (0x13b1, 0x0018),
  779. .driver_info = (unsigned long) &ax88772_info,
  780. }, {
  781. // 0Q0 cable ethernet
  782. USB_DEVICE (0x1557, 0x7720),
  783. .driver_info = (unsigned long) &ax88772_info,
  784. }, {
  785. // DLink DUB-E100 H/W Ver B1
  786. USB_DEVICE (0x07d1, 0x3c05),
  787. .driver_info = (unsigned long) &ax88772_info,
  788. }, {
  789. // DLink DUB-E100 H/W Ver B1 Alternate
  790. USB_DEVICE (0x2001, 0x3c05),
  791. .driver_info = (unsigned long) &ax88772_info,
  792. }, {
  793. // Linksys USB1000
  794. USB_DEVICE (0x1737, 0x0039),
  795. .driver_info = (unsigned long) &ax88178_info,
  796. }, {
  797. // IO-DATA ETG-US2
  798. USB_DEVICE (0x04bb, 0x0930),
  799. .driver_info = (unsigned long) &ax88178_info,
  800. }, {
  801. // Belkin F5D5055
  802. USB_DEVICE(0x050d, 0x5055),
  803. .driver_info = (unsigned long) &ax88178_info,
  804. }, {
  805. // Apple USB Ethernet Adapter
  806. USB_DEVICE(0x05ac, 0x1402),
  807. .driver_info = (unsigned long) &ax88772_info,
  808. }, {
  809. // Cables-to-Go USB Ethernet Adapter
  810. USB_DEVICE(0x0b95, 0x772a),
  811. .driver_info = (unsigned long) &ax88772_info,
  812. }, {
  813. // ABOCOM for pci
  814. USB_DEVICE(0x14ea, 0xab11),
  815. .driver_info = (unsigned long) &ax88178_info,
  816. }, {
  817. // ASIX 88772a
  818. USB_DEVICE(0x0db0, 0xa877),
  819. .driver_info = (unsigned long) &ax88772_info,
  820. }, {
  821. // Asus USB Ethernet Adapter
  822. USB_DEVICE (0x0b95, 0x7e2b),
  823. .driver_info = (unsigned long) &ax88772_info,
  824. }, {
  825. /* ASIX 88172a demo board */
  826. USB_DEVICE(0x0b95, 0x172a),
  827. .driver_info = (unsigned long) &ax88172a_info,
  828. },
  829. { }, // END
  830. };
  831. MODULE_DEVICE_TABLE(usb, products);
  832. static struct usb_driver asix_driver = {
  833. .name = DRIVER_NAME,
  834. .id_table = products,
  835. .probe = usbnet_probe,
  836. .suspend = usbnet_suspend,
  837. .resume = usbnet_resume,
  838. .disconnect = usbnet_disconnect,
  839. .supports_autosuspend = 1,
  840. .disable_hub_initiated_lpm = 1,
  841. };
  842. module_usb_driver(asix_driver);
  843. MODULE_AUTHOR("David Hollis");
  844. MODULE_VERSION(DRIVER_VERSION);
  845. MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
  846. MODULE_LICENSE("GPL");