cpsw.c 26 KB

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  1. /*
  2. * Texas Instruments Ethernet Switch Driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <linux/timer.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/irqreturn.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/if_ether.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/phy.h>
  27. #include <linux/workqueue.h>
  28. #include <linux/delay.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/platform_data/cpsw.h>
  31. #include "cpsw_ale.h"
  32. #include "davinci_cpdma.h"
  33. #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
  34. NETIF_MSG_DRV | NETIF_MSG_LINK | \
  35. NETIF_MSG_IFUP | NETIF_MSG_INTR | \
  36. NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
  37. NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
  38. NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
  39. NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
  40. NETIF_MSG_RX_STATUS)
  41. #define cpsw_info(priv, type, format, ...) \
  42. do { \
  43. if (netif_msg_##type(priv) && net_ratelimit()) \
  44. dev_info(priv->dev, format, ## __VA_ARGS__); \
  45. } while (0)
  46. #define cpsw_err(priv, type, format, ...) \
  47. do { \
  48. if (netif_msg_##type(priv) && net_ratelimit()) \
  49. dev_err(priv->dev, format, ## __VA_ARGS__); \
  50. } while (0)
  51. #define cpsw_dbg(priv, type, format, ...) \
  52. do { \
  53. if (netif_msg_##type(priv) && net_ratelimit()) \
  54. dev_dbg(priv->dev, format, ## __VA_ARGS__); \
  55. } while (0)
  56. #define cpsw_notice(priv, type, format, ...) \
  57. do { \
  58. if (netif_msg_##type(priv) && net_ratelimit()) \
  59. dev_notice(priv->dev, format, ## __VA_ARGS__); \
  60. } while (0)
  61. #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
  62. #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
  63. #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
  64. #define CPDMA_RXTHRESH 0x0c0
  65. #define CPDMA_RXFREE 0x0e0
  66. #define CPDMA_TXHDP 0x00
  67. #define CPDMA_RXHDP 0x20
  68. #define CPDMA_TXCP 0x40
  69. #define CPDMA_RXCP 0x60
  70. #define cpsw_dma_regs(base, offset) \
  71. (void __iomem *)((base) + (offset))
  72. #define cpsw_dma_rxthresh(base, offset) \
  73. (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
  74. #define cpsw_dma_rxfree(base, offset) \
  75. (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
  76. #define cpsw_dma_txhdp(base, offset) \
  77. (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
  78. #define cpsw_dma_rxhdp(base, offset) \
  79. (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
  80. #define cpsw_dma_txcp(base, offset) \
  81. (void __iomem *)((base) + (offset) + CPDMA_TXCP)
  82. #define cpsw_dma_rxcp(base, offset) \
  83. (void __iomem *)((base) + (offset) + CPDMA_RXCP)
  84. #define CPSW_POLL_WEIGHT 64
  85. #define CPSW_MIN_PACKET_SIZE 60
  86. #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
  87. #define RX_PRIORITY_MAPPING 0x76543210
  88. #define TX_PRIORITY_MAPPING 0x33221100
  89. #define CPDMA_TX_PRIORITY_MAP 0x76543210
  90. #define cpsw_enable_irq(priv) \
  91. do { \
  92. u32 i; \
  93. for (i = 0; i < priv->num_irqs; i++) \
  94. enable_irq(priv->irqs_table[i]); \
  95. } while (0);
  96. #define cpsw_disable_irq(priv) \
  97. do { \
  98. u32 i; \
  99. for (i = 0; i < priv->num_irqs; i++) \
  100. disable_irq_nosync(priv->irqs_table[i]); \
  101. } while (0);
  102. static int debug_level;
  103. module_param(debug_level, int, 0);
  104. MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
  105. static int ale_ageout = 10;
  106. module_param(ale_ageout, int, 0);
  107. MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
  108. static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
  109. module_param(rx_packet_max, int, 0);
  110. MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
  111. struct cpsw_ss_regs {
  112. u32 id_ver;
  113. u32 soft_reset;
  114. u32 control;
  115. u32 int_control;
  116. u32 rx_thresh_en;
  117. u32 rx_en;
  118. u32 tx_en;
  119. u32 misc_en;
  120. };
  121. struct cpsw_regs {
  122. u32 id_ver;
  123. u32 control;
  124. u32 soft_reset;
  125. u32 stat_port_en;
  126. u32 ptype;
  127. };
  128. struct cpsw_slave_regs {
  129. u32 max_blks;
  130. u32 blk_cnt;
  131. u32 flow_thresh;
  132. u32 port_vlan;
  133. u32 tx_pri_map;
  134. u32 ts_ctl;
  135. u32 ts_seq_ltype;
  136. u32 ts_vlan;
  137. u32 sa_lo;
  138. u32 sa_hi;
  139. };
  140. struct cpsw_host_regs {
  141. u32 max_blks;
  142. u32 blk_cnt;
  143. u32 flow_thresh;
  144. u32 port_vlan;
  145. u32 tx_pri_map;
  146. u32 cpdma_tx_pri_map;
  147. u32 cpdma_rx_chan_map;
  148. };
  149. struct cpsw_sliver_regs {
  150. u32 id_ver;
  151. u32 mac_control;
  152. u32 mac_status;
  153. u32 soft_reset;
  154. u32 rx_maxlen;
  155. u32 __reserved_0;
  156. u32 rx_pause;
  157. u32 tx_pause;
  158. u32 __reserved_1;
  159. u32 rx_pri_map;
  160. };
  161. struct cpsw_slave {
  162. struct cpsw_slave_regs __iomem *regs;
  163. struct cpsw_sliver_regs __iomem *sliver;
  164. int slave_num;
  165. u32 mac_control;
  166. struct cpsw_slave_data *data;
  167. struct phy_device *phy;
  168. };
  169. struct cpsw_priv {
  170. spinlock_t lock;
  171. struct platform_device *pdev;
  172. struct net_device *ndev;
  173. struct resource *cpsw_res;
  174. struct resource *cpsw_ss_res;
  175. struct napi_struct napi;
  176. struct device *dev;
  177. struct cpsw_platform_data data;
  178. struct cpsw_regs __iomem *regs;
  179. struct cpsw_ss_regs __iomem *ss_regs;
  180. struct cpsw_host_regs __iomem *host_port_regs;
  181. u32 msg_enable;
  182. struct net_device_stats stats;
  183. int rx_packet_max;
  184. int host_port;
  185. struct clk *clk;
  186. u8 mac_addr[ETH_ALEN];
  187. struct cpsw_slave *slaves;
  188. struct cpdma_ctlr *dma;
  189. struct cpdma_chan *txch, *rxch;
  190. struct cpsw_ale *ale;
  191. /* snapshot of IRQ numbers */
  192. u32 irqs_table[4];
  193. u32 num_irqs;
  194. };
  195. #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
  196. #define for_each_slave(priv, func, arg...) \
  197. do { \
  198. int idx; \
  199. for (idx = 0; idx < (priv)->data.slaves; idx++) \
  200. (func)((priv)->slaves + idx, ##arg); \
  201. } while (0)
  202. static void cpsw_intr_enable(struct cpsw_priv *priv)
  203. {
  204. __raw_writel(0xFF, &priv->ss_regs->tx_en);
  205. __raw_writel(0xFF, &priv->ss_regs->rx_en);
  206. cpdma_ctlr_int_ctrl(priv->dma, true);
  207. return;
  208. }
  209. static void cpsw_intr_disable(struct cpsw_priv *priv)
  210. {
  211. __raw_writel(0, &priv->ss_regs->tx_en);
  212. __raw_writel(0, &priv->ss_regs->rx_en);
  213. cpdma_ctlr_int_ctrl(priv->dma, false);
  214. return;
  215. }
  216. void cpsw_tx_handler(void *token, int len, int status)
  217. {
  218. struct sk_buff *skb = token;
  219. struct net_device *ndev = skb->dev;
  220. struct cpsw_priv *priv = netdev_priv(ndev);
  221. if (unlikely(netif_queue_stopped(ndev)))
  222. netif_start_queue(ndev);
  223. priv->stats.tx_packets++;
  224. priv->stats.tx_bytes += len;
  225. dev_kfree_skb_any(skb);
  226. }
  227. void cpsw_rx_handler(void *token, int len, int status)
  228. {
  229. struct sk_buff *skb = token;
  230. struct net_device *ndev = skb->dev;
  231. struct cpsw_priv *priv = netdev_priv(ndev);
  232. int ret = 0;
  233. /* free and bail if we are shutting down */
  234. if (unlikely(!netif_running(ndev)) ||
  235. unlikely(!netif_carrier_ok(ndev))) {
  236. dev_kfree_skb_any(skb);
  237. return;
  238. }
  239. if (likely(status >= 0)) {
  240. skb_put(skb, len);
  241. skb->protocol = eth_type_trans(skb, ndev);
  242. netif_receive_skb(skb);
  243. priv->stats.rx_bytes += len;
  244. priv->stats.rx_packets++;
  245. skb = NULL;
  246. }
  247. if (unlikely(!netif_running(ndev))) {
  248. if (skb)
  249. dev_kfree_skb_any(skb);
  250. return;
  251. }
  252. if (likely(!skb)) {
  253. skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
  254. if (WARN_ON(!skb))
  255. return;
  256. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  257. skb_tailroom(skb), GFP_KERNEL);
  258. }
  259. WARN_ON(ret < 0);
  260. }
  261. static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
  262. {
  263. struct cpsw_priv *priv = dev_id;
  264. if (likely(netif_running(priv->ndev))) {
  265. cpsw_intr_disable(priv);
  266. cpsw_disable_irq(priv);
  267. napi_schedule(&priv->napi);
  268. }
  269. return IRQ_HANDLED;
  270. }
  271. static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  272. {
  273. if (priv->host_port == 0)
  274. return slave_num + 1;
  275. else
  276. return slave_num;
  277. }
  278. static int cpsw_poll(struct napi_struct *napi, int budget)
  279. {
  280. struct cpsw_priv *priv = napi_to_priv(napi);
  281. int num_tx, num_rx;
  282. num_tx = cpdma_chan_process(priv->txch, 128);
  283. num_rx = cpdma_chan_process(priv->rxch, budget);
  284. if (num_rx || num_tx)
  285. cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
  286. num_rx, num_tx);
  287. if (num_rx < budget) {
  288. napi_complete(napi);
  289. cpsw_intr_enable(priv);
  290. cpdma_ctlr_eoi(priv->dma);
  291. cpsw_enable_irq(priv);
  292. }
  293. return num_rx;
  294. }
  295. static inline void soft_reset(const char *module, void __iomem *reg)
  296. {
  297. unsigned long timeout = jiffies + HZ;
  298. __raw_writel(1, reg);
  299. do {
  300. cpu_relax();
  301. } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
  302. WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
  303. }
  304. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  305. ((mac)[2] << 16) | ((mac)[3] << 24))
  306. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  307. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  308. struct cpsw_priv *priv)
  309. {
  310. __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi);
  311. __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo);
  312. }
  313. static void _cpsw_adjust_link(struct cpsw_slave *slave,
  314. struct cpsw_priv *priv, bool *link)
  315. {
  316. struct phy_device *phy = slave->phy;
  317. u32 mac_control = 0;
  318. u32 slave_port;
  319. if (!phy)
  320. return;
  321. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  322. if (phy->link) {
  323. mac_control = priv->data.mac_control;
  324. /* enable forwarding */
  325. cpsw_ale_control_set(priv->ale, slave_port,
  326. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  327. if (phy->speed == 1000)
  328. mac_control |= BIT(7); /* GIGABITEN */
  329. if (phy->duplex)
  330. mac_control |= BIT(0); /* FULLDUPLEXEN */
  331. *link = true;
  332. } else {
  333. mac_control = 0;
  334. /* disable forwarding */
  335. cpsw_ale_control_set(priv->ale, slave_port,
  336. ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
  337. }
  338. if (mac_control != slave->mac_control) {
  339. phy_print_status(phy);
  340. __raw_writel(mac_control, &slave->sliver->mac_control);
  341. }
  342. slave->mac_control = mac_control;
  343. }
  344. static void cpsw_adjust_link(struct net_device *ndev)
  345. {
  346. struct cpsw_priv *priv = netdev_priv(ndev);
  347. bool link = false;
  348. for_each_slave(priv, _cpsw_adjust_link, priv, &link);
  349. if (link) {
  350. netif_carrier_on(ndev);
  351. if (netif_running(ndev))
  352. netif_wake_queue(ndev);
  353. } else {
  354. netif_carrier_off(ndev);
  355. netif_stop_queue(ndev);
  356. }
  357. }
  358. static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
  359. {
  360. static char *leader = "........................................";
  361. if (!val)
  362. return 0;
  363. else
  364. return snprintf(buf, maxlen, "%s %s %10d\n", name,
  365. leader + strlen(name), val);
  366. }
  367. static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
  368. {
  369. char name[32];
  370. u32 slave_port;
  371. sprintf(name, "slave-%d", slave->slave_num);
  372. soft_reset(name, &slave->sliver->soft_reset);
  373. /* setup priority mapping */
  374. __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
  375. __raw_writel(TX_PRIORITY_MAPPING, &slave->regs->tx_pri_map);
  376. /* setup max packet size, and mac address */
  377. __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
  378. cpsw_set_slave_mac(slave, priv);
  379. slave->mac_control = 0; /* no link yet */
  380. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  381. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  382. 1 << slave_port, 0, ALE_MCAST_FWD_2);
  383. slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
  384. &cpsw_adjust_link, 0, slave->data->phy_if);
  385. if (IS_ERR(slave->phy)) {
  386. dev_err(priv->dev, "phy %s not found on slave %d\n",
  387. slave->data->phy_id, slave->slave_num);
  388. slave->phy = NULL;
  389. } else {
  390. dev_info(priv->dev, "phy found : id is : 0x%x\n",
  391. slave->phy->phy_id);
  392. phy_start(slave->phy);
  393. }
  394. }
  395. static void cpsw_init_host_port(struct cpsw_priv *priv)
  396. {
  397. /* soft reset the controller and initialize ale */
  398. soft_reset("cpsw", &priv->regs->soft_reset);
  399. cpsw_ale_start(priv->ale);
  400. /* switch to vlan unaware mode */
  401. cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
  402. /* setup host port priority mapping */
  403. __raw_writel(CPDMA_TX_PRIORITY_MAP,
  404. &priv->host_port_regs->cpdma_tx_pri_map);
  405. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  406. cpsw_ale_control_set(priv->ale, priv->host_port,
  407. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  408. cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
  409. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  410. 1 << priv->host_port, 0, ALE_MCAST_FWD_2);
  411. }
  412. static int cpsw_ndo_open(struct net_device *ndev)
  413. {
  414. struct cpsw_priv *priv = netdev_priv(ndev);
  415. int i, ret;
  416. u32 reg;
  417. cpsw_intr_disable(priv);
  418. netif_carrier_off(ndev);
  419. pm_runtime_get_sync(&priv->pdev->dev);
  420. reg = __raw_readl(&priv->regs->id_ver);
  421. dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
  422. CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
  423. CPSW_RTL_VERSION(reg));
  424. /* initialize host and slave ports */
  425. cpsw_init_host_port(priv);
  426. for_each_slave(priv, cpsw_slave_open, priv);
  427. /* setup tx dma to fixed prio and zero offset */
  428. cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
  429. cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
  430. /* disable priority elevation and enable statistics on all ports */
  431. __raw_writel(0, &priv->regs->ptype);
  432. /* enable statistics collection only on the host port */
  433. __raw_writel(0x7, &priv->regs->stat_port_en);
  434. if (WARN_ON(!priv->data.rx_descs))
  435. priv->data.rx_descs = 128;
  436. for (i = 0; i < priv->data.rx_descs; i++) {
  437. struct sk_buff *skb;
  438. ret = -ENOMEM;
  439. skb = netdev_alloc_skb_ip_align(priv->ndev,
  440. priv->rx_packet_max);
  441. if (!skb)
  442. break;
  443. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  444. skb_tailroom(skb), GFP_KERNEL);
  445. if (WARN_ON(ret < 0))
  446. break;
  447. }
  448. /* continue even if we didn't manage to submit all receive descs */
  449. cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
  450. cpdma_ctlr_start(priv->dma);
  451. cpsw_intr_enable(priv);
  452. napi_enable(&priv->napi);
  453. cpdma_ctlr_eoi(priv->dma);
  454. return 0;
  455. }
  456. static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
  457. {
  458. if (!slave->phy)
  459. return;
  460. phy_stop(slave->phy);
  461. phy_disconnect(slave->phy);
  462. slave->phy = NULL;
  463. }
  464. static int cpsw_ndo_stop(struct net_device *ndev)
  465. {
  466. struct cpsw_priv *priv = netdev_priv(ndev);
  467. cpsw_info(priv, ifdown, "shutting down cpsw device\n");
  468. cpsw_intr_disable(priv);
  469. cpdma_ctlr_int_ctrl(priv->dma, false);
  470. cpdma_ctlr_stop(priv->dma);
  471. netif_stop_queue(priv->ndev);
  472. napi_disable(&priv->napi);
  473. netif_carrier_off(priv->ndev);
  474. cpsw_ale_stop(priv->ale);
  475. for_each_slave(priv, cpsw_slave_stop, priv);
  476. pm_runtime_put_sync(&priv->pdev->dev);
  477. return 0;
  478. }
  479. static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
  480. struct net_device *ndev)
  481. {
  482. struct cpsw_priv *priv = netdev_priv(ndev);
  483. int ret;
  484. ndev->trans_start = jiffies;
  485. if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
  486. cpsw_err(priv, tx_err, "packet pad failed\n");
  487. priv->stats.tx_dropped++;
  488. return NETDEV_TX_OK;
  489. }
  490. ret = cpdma_chan_submit(priv->txch, skb, skb->data,
  491. skb->len, GFP_KERNEL);
  492. if (unlikely(ret != 0)) {
  493. cpsw_err(priv, tx_err, "desc submit failed\n");
  494. goto fail;
  495. }
  496. return NETDEV_TX_OK;
  497. fail:
  498. priv->stats.tx_dropped++;
  499. netif_stop_queue(ndev);
  500. return NETDEV_TX_BUSY;
  501. }
  502. static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
  503. {
  504. /*
  505. * The switch cannot operate in promiscuous mode without substantial
  506. * headache. For promiscuous mode to work, we would need to put the
  507. * ALE in bypass mode and route all traffic to the host port.
  508. * Subsequently, the host will need to operate as a "bridge", learn,
  509. * and flood as needed. For now, we simply complain here and
  510. * do nothing about it :-)
  511. */
  512. if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
  513. dev_err(&ndev->dev, "promiscuity ignored!\n");
  514. /*
  515. * The switch cannot filter multicast traffic unless it is configured
  516. * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
  517. * whole bunch of additional logic that this driver does not implement
  518. * at present.
  519. */
  520. if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
  521. dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
  522. }
  523. static void cpsw_ndo_tx_timeout(struct net_device *ndev)
  524. {
  525. struct cpsw_priv *priv = netdev_priv(ndev);
  526. cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
  527. priv->stats.tx_errors++;
  528. cpsw_intr_disable(priv);
  529. cpdma_ctlr_int_ctrl(priv->dma, false);
  530. cpdma_chan_stop(priv->txch);
  531. cpdma_chan_start(priv->txch);
  532. cpdma_ctlr_int_ctrl(priv->dma, true);
  533. cpsw_intr_enable(priv);
  534. cpdma_ctlr_eoi(priv->dma);
  535. }
  536. static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
  537. {
  538. struct cpsw_priv *priv = netdev_priv(ndev);
  539. return &priv->stats;
  540. }
  541. #ifdef CONFIG_NET_POLL_CONTROLLER
  542. static void cpsw_ndo_poll_controller(struct net_device *ndev)
  543. {
  544. struct cpsw_priv *priv = netdev_priv(ndev);
  545. cpsw_intr_disable(priv);
  546. cpdma_ctlr_int_ctrl(priv->dma, false);
  547. cpsw_interrupt(ndev->irq, priv);
  548. cpdma_ctlr_int_ctrl(priv->dma, true);
  549. cpsw_intr_enable(priv);
  550. cpdma_ctlr_eoi(priv->dma);
  551. }
  552. #endif
  553. static const struct net_device_ops cpsw_netdev_ops = {
  554. .ndo_open = cpsw_ndo_open,
  555. .ndo_stop = cpsw_ndo_stop,
  556. .ndo_start_xmit = cpsw_ndo_start_xmit,
  557. .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
  558. .ndo_validate_addr = eth_validate_addr,
  559. .ndo_change_mtu = eth_change_mtu,
  560. .ndo_tx_timeout = cpsw_ndo_tx_timeout,
  561. .ndo_get_stats = cpsw_ndo_get_stats,
  562. #ifdef CONFIG_NET_POLL_CONTROLLER
  563. .ndo_poll_controller = cpsw_ndo_poll_controller,
  564. #endif
  565. };
  566. static void cpsw_get_drvinfo(struct net_device *ndev,
  567. struct ethtool_drvinfo *info)
  568. {
  569. struct cpsw_priv *priv = netdev_priv(ndev);
  570. strcpy(info->driver, "TI CPSW Driver v1.0");
  571. strcpy(info->version, "1.0");
  572. strcpy(info->bus_info, priv->pdev->name);
  573. }
  574. static u32 cpsw_get_msglevel(struct net_device *ndev)
  575. {
  576. struct cpsw_priv *priv = netdev_priv(ndev);
  577. return priv->msg_enable;
  578. }
  579. static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
  580. {
  581. struct cpsw_priv *priv = netdev_priv(ndev);
  582. priv->msg_enable = value;
  583. }
  584. static const struct ethtool_ops cpsw_ethtool_ops = {
  585. .get_drvinfo = cpsw_get_drvinfo,
  586. .get_msglevel = cpsw_get_msglevel,
  587. .set_msglevel = cpsw_set_msglevel,
  588. .get_link = ethtool_op_get_link,
  589. };
  590. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  591. {
  592. void __iomem *regs = priv->regs;
  593. int slave_num = slave->slave_num;
  594. struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
  595. slave->data = data;
  596. slave->regs = regs + data->slave_reg_ofs;
  597. slave->sliver = regs + data->sliver_reg_ofs;
  598. }
  599. static int __devinit cpsw_probe(struct platform_device *pdev)
  600. {
  601. struct cpsw_platform_data *data = pdev->dev.platform_data;
  602. struct net_device *ndev;
  603. struct cpsw_priv *priv;
  604. struct cpdma_params dma_params;
  605. struct cpsw_ale_params ale_params;
  606. void __iomem *regs;
  607. struct resource *res;
  608. int ret = 0, i, k = 0;
  609. if (!data) {
  610. pr_err("platform data missing\n");
  611. return -ENODEV;
  612. }
  613. ndev = alloc_etherdev(sizeof(struct cpsw_priv));
  614. if (!ndev) {
  615. pr_err("error allocating net_device\n");
  616. return -ENOMEM;
  617. }
  618. platform_set_drvdata(pdev, ndev);
  619. priv = netdev_priv(ndev);
  620. spin_lock_init(&priv->lock);
  621. priv->data = *data;
  622. priv->pdev = pdev;
  623. priv->ndev = ndev;
  624. priv->dev = &ndev->dev;
  625. priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
  626. priv->rx_packet_max = max(rx_packet_max, 128);
  627. if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
  628. memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
  629. pr_info("Detected MACID = %pM", priv->mac_addr);
  630. } else {
  631. eth_random_addr(priv->mac_addr);
  632. pr_info("Random MACID = %pM", priv->mac_addr);
  633. }
  634. memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
  635. priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
  636. GFP_KERNEL);
  637. if (!priv->slaves) {
  638. ret = -EBUSY;
  639. goto clean_ndev_ret;
  640. }
  641. for (i = 0; i < data->slaves; i++)
  642. priv->slaves[i].slave_num = i;
  643. pm_runtime_enable(&pdev->dev);
  644. priv->clk = clk_get(&pdev->dev, "fck");
  645. if (IS_ERR(priv->clk)) {
  646. dev_err(&pdev->dev, "fck is not found\n");
  647. ret = -ENODEV;
  648. goto clean_slave_ret;
  649. }
  650. priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  651. if (!priv->cpsw_res) {
  652. dev_err(priv->dev, "error getting i/o resource\n");
  653. ret = -ENOENT;
  654. goto clean_clk_ret;
  655. }
  656. if (!request_mem_region(priv->cpsw_res->start,
  657. resource_size(priv->cpsw_res), ndev->name)) {
  658. dev_err(priv->dev, "failed request i/o region\n");
  659. ret = -ENXIO;
  660. goto clean_clk_ret;
  661. }
  662. regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
  663. if (!regs) {
  664. dev_err(priv->dev, "unable to map i/o region\n");
  665. goto clean_cpsw_iores_ret;
  666. }
  667. priv->regs = regs;
  668. priv->host_port = data->host_port_num;
  669. priv->host_port_regs = regs + data->host_port_reg_ofs;
  670. priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  671. if (!priv->cpsw_ss_res) {
  672. dev_err(priv->dev, "error getting i/o resource\n");
  673. ret = -ENOENT;
  674. goto clean_clk_ret;
  675. }
  676. if (!request_mem_region(priv->cpsw_ss_res->start,
  677. resource_size(priv->cpsw_ss_res), ndev->name)) {
  678. dev_err(priv->dev, "failed request i/o region\n");
  679. ret = -ENXIO;
  680. goto clean_clk_ret;
  681. }
  682. regs = ioremap(priv->cpsw_ss_res->start,
  683. resource_size(priv->cpsw_ss_res));
  684. if (!regs) {
  685. dev_err(priv->dev, "unable to map i/o region\n");
  686. goto clean_cpsw_ss_iores_ret;
  687. }
  688. priv->ss_regs = regs;
  689. for_each_slave(priv, cpsw_slave_init, priv);
  690. memset(&dma_params, 0, sizeof(dma_params));
  691. dma_params.dev = &pdev->dev;
  692. dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs,
  693. data->cpdma_reg_ofs);
  694. dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs,
  695. data->cpdma_reg_ofs);
  696. dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs,
  697. data->cpdma_reg_ofs);
  698. dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs,
  699. data->cpdma_sram_ofs);
  700. dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs,
  701. data->cpdma_sram_ofs);
  702. dma_params.txcp = cpsw_dma_txcp((u32)priv->regs,
  703. data->cpdma_sram_ofs);
  704. dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs,
  705. data->cpdma_sram_ofs);
  706. dma_params.num_chan = data->channels;
  707. dma_params.has_soft_reset = true;
  708. dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
  709. dma_params.desc_mem_size = data->bd_ram_size;
  710. dma_params.desc_align = 16;
  711. dma_params.has_ext_regs = true;
  712. dma_params.desc_mem_phys = data->no_bd_ram ? 0 :
  713. (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
  714. dma_params.desc_hw_addr = data->hw_ram_addr ?
  715. data->hw_ram_addr : dma_params.desc_mem_phys ;
  716. priv->dma = cpdma_ctlr_create(&dma_params);
  717. if (!priv->dma) {
  718. dev_err(priv->dev, "error initializing dma\n");
  719. ret = -ENOMEM;
  720. goto clean_iomap_ret;
  721. }
  722. priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
  723. cpsw_tx_handler);
  724. priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
  725. cpsw_rx_handler);
  726. if (WARN_ON(!priv->txch || !priv->rxch)) {
  727. dev_err(priv->dev, "error initializing dma channels\n");
  728. ret = -ENOMEM;
  729. goto clean_dma_ret;
  730. }
  731. memset(&ale_params, 0, sizeof(ale_params));
  732. ale_params.dev = &ndev->dev;
  733. ale_params.ale_regs = (void *)((u32)priv->regs) +
  734. ((u32)data->ale_reg_ofs);
  735. ale_params.ale_ageout = ale_ageout;
  736. ale_params.ale_entries = data->ale_entries;
  737. ale_params.ale_ports = data->slaves;
  738. priv->ale = cpsw_ale_create(&ale_params);
  739. if (!priv->ale) {
  740. dev_err(priv->dev, "error initializing ale engine\n");
  741. ret = -ENODEV;
  742. goto clean_dma_ret;
  743. }
  744. ndev->irq = platform_get_irq(pdev, 0);
  745. if (ndev->irq < 0) {
  746. dev_err(priv->dev, "error getting irq resource\n");
  747. ret = -ENOENT;
  748. goto clean_ale_ret;
  749. }
  750. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
  751. for (i = res->start; i <= res->end; i++) {
  752. if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
  753. dev_name(&pdev->dev), priv)) {
  754. dev_err(priv->dev, "error attaching irq\n");
  755. goto clean_ale_ret;
  756. }
  757. priv->irqs_table[k] = i;
  758. priv->num_irqs = k;
  759. }
  760. k++;
  761. }
  762. ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */
  763. ndev->netdev_ops = &cpsw_netdev_ops;
  764. SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
  765. netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
  766. /* register the network device */
  767. SET_NETDEV_DEV(ndev, &pdev->dev);
  768. ret = register_netdev(ndev);
  769. if (ret) {
  770. dev_err(priv->dev, "error registering net device\n");
  771. ret = -ENODEV;
  772. goto clean_irq_ret;
  773. }
  774. cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
  775. priv->cpsw_res->start, ndev->irq);
  776. return 0;
  777. clean_irq_ret:
  778. free_irq(ndev->irq, priv);
  779. clean_ale_ret:
  780. cpsw_ale_destroy(priv->ale);
  781. clean_dma_ret:
  782. cpdma_chan_destroy(priv->txch);
  783. cpdma_chan_destroy(priv->rxch);
  784. cpdma_ctlr_destroy(priv->dma);
  785. clean_iomap_ret:
  786. iounmap(priv->regs);
  787. clean_cpsw_ss_iores_ret:
  788. release_mem_region(priv->cpsw_ss_res->start,
  789. resource_size(priv->cpsw_ss_res));
  790. clean_cpsw_iores_ret:
  791. release_mem_region(priv->cpsw_res->start,
  792. resource_size(priv->cpsw_res));
  793. clean_clk_ret:
  794. clk_put(priv->clk);
  795. clean_slave_ret:
  796. pm_runtime_disable(&pdev->dev);
  797. kfree(priv->slaves);
  798. clean_ndev_ret:
  799. free_netdev(ndev);
  800. return ret;
  801. }
  802. static int __devexit cpsw_remove(struct platform_device *pdev)
  803. {
  804. struct net_device *ndev = platform_get_drvdata(pdev);
  805. struct cpsw_priv *priv = netdev_priv(ndev);
  806. pr_info("removing device");
  807. platform_set_drvdata(pdev, NULL);
  808. free_irq(ndev->irq, priv);
  809. cpsw_ale_destroy(priv->ale);
  810. cpdma_chan_destroy(priv->txch);
  811. cpdma_chan_destroy(priv->rxch);
  812. cpdma_ctlr_destroy(priv->dma);
  813. iounmap(priv->regs);
  814. release_mem_region(priv->cpsw_res->start,
  815. resource_size(priv->cpsw_res));
  816. release_mem_region(priv->cpsw_ss_res->start,
  817. resource_size(priv->cpsw_ss_res));
  818. pm_runtime_disable(&pdev->dev);
  819. clk_put(priv->clk);
  820. kfree(priv->slaves);
  821. free_netdev(ndev);
  822. return 0;
  823. }
  824. static int cpsw_suspend(struct device *dev)
  825. {
  826. struct platform_device *pdev = to_platform_device(dev);
  827. struct net_device *ndev = platform_get_drvdata(pdev);
  828. if (netif_running(ndev))
  829. cpsw_ndo_stop(ndev);
  830. pm_runtime_put_sync(&pdev->dev);
  831. return 0;
  832. }
  833. static int cpsw_resume(struct device *dev)
  834. {
  835. struct platform_device *pdev = to_platform_device(dev);
  836. struct net_device *ndev = platform_get_drvdata(pdev);
  837. pm_runtime_get_sync(&pdev->dev);
  838. if (netif_running(ndev))
  839. cpsw_ndo_open(ndev);
  840. return 0;
  841. }
  842. static const struct dev_pm_ops cpsw_pm_ops = {
  843. .suspend = cpsw_suspend,
  844. .resume = cpsw_resume,
  845. };
  846. static struct platform_driver cpsw_driver = {
  847. .driver = {
  848. .name = "cpsw",
  849. .owner = THIS_MODULE,
  850. .pm = &cpsw_pm_ops,
  851. },
  852. .probe = cpsw_probe,
  853. .remove = __devexit_p(cpsw_remove),
  854. };
  855. static int __init cpsw_init(void)
  856. {
  857. return platform_driver_register(&cpsw_driver);
  858. }
  859. late_initcall(cpsw_init);
  860. static void __exit cpsw_exit(void)
  861. {
  862. platform_driver_unregister(&cpsw_driver);
  863. }
  864. module_exit(cpsw_exit);
  865. MODULE_LICENSE("GPL");
  866. MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
  867. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  868. MODULE_DESCRIPTION("TI CPSW Ethernet driver");