resource_tracker.c 76 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include "mlx4.h"
  45. #include "fw.h"
  46. #define MLX4_MAC_VALID (1ull << 63)
  47. struct mac_res {
  48. struct list_head list;
  49. u64 mac;
  50. u8 port;
  51. };
  52. struct res_common {
  53. struct list_head list;
  54. struct rb_node node;
  55. u64 res_id;
  56. int owner;
  57. int state;
  58. int from_state;
  59. int to_state;
  60. int removing;
  61. };
  62. enum {
  63. RES_ANY_BUSY = 1
  64. };
  65. struct res_gid {
  66. struct list_head list;
  67. u8 gid[16];
  68. enum mlx4_protocol prot;
  69. enum mlx4_steer_type steer;
  70. };
  71. enum res_qp_states {
  72. RES_QP_BUSY = RES_ANY_BUSY,
  73. /* QP number was allocated */
  74. RES_QP_RESERVED,
  75. /* ICM memory for QP context was mapped */
  76. RES_QP_MAPPED,
  77. /* QP is in hw ownership */
  78. RES_QP_HW
  79. };
  80. struct res_qp {
  81. struct res_common com;
  82. struct res_mtt *mtt;
  83. struct res_cq *rcq;
  84. struct res_cq *scq;
  85. struct res_srq *srq;
  86. struct list_head mcg_list;
  87. spinlock_t mcg_spl;
  88. int local_qpn;
  89. };
  90. enum res_mtt_states {
  91. RES_MTT_BUSY = RES_ANY_BUSY,
  92. RES_MTT_ALLOCATED,
  93. };
  94. static inline const char *mtt_states_str(enum res_mtt_states state)
  95. {
  96. switch (state) {
  97. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  98. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  99. default: return "Unknown";
  100. }
  101. }
  102. struct res_mtt {
  103. struct res_common com;
  104. int order;
  105. atomic_t ref_count;
  106. };
  107. enum res_mpt_states {
  108. RES_MPT_BUSY = RES_ANY_BUSY,
  109. RES_MPT_RESERVED,
  110. RES_MPT_MAPPED,
  111. RES_MPT_HW,
  112. };
  113. struct res_mpt {
  114. struct res_common com;
  115. struct res_mtt *mtt;
  116. int key;
  117. };
  118. enum res_eq_states {
  119. RES_EQ_BUSY = RES_ANY_BUSY,
  120. RES_EQ_RESERVED,
  121. RES_EQ_HW,
  122. };
  123. struct res_eq {
  124. struct res_common com;
  125. struct res_mtt *mtt;
  126. };
  127. enum res_cq_states {
  128. RES_CQ_BUSY = RES_ANY_BUSY,
  129. RES_CQ_ALLOCATED,
  130. RES_CQ_HW,
  131. };
  132. struct res_cq {
  133. struct res_common com;
  134. struct res_mtt *mtt;
  135. atomic_t ref_count;
  136. };
  137. enum res_srq_states {
  138. RES_SRQ_BUSY = RES_ANY_BUSY,
  139. RES_SRQ_ALLOCATED,
  140. RES_SRQ_HW,
  141. };
  142. struct res_srq {
  143. struct res_common com;
  144. struct res_mtt *mtt;
  145. struct res_cq *cq;
  146. atomic_t ref_count;
  147. };
  148. enum res_counter_states {
  149. RES_COUNTER_BUSY = RES_ANY_BUSY,
  150. RES_COUNTER_ALLOCATED,
  151. };
  152. struct res_counter {
  153. struct res_common com;
  154. int port;
  155. };
  156. enum res_xrcdn_states {
  157. RES_XRCD_BUSY = RES_ANY_BUSY,
  158. RES_XRCD_ALLOCATED,
  159. };
  160. struct res_xrcdn {
  161. struct res_common com;
  162. int port;
  163. };
  164. enum res_fs_rule_states {
  165. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  166. RES_FS_RULE_ALLOCATED,
  167. };
  168. struct res_fs_rule {
  169. struct res_common com;
  170. };
  171. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  172. {
  173. struct rb_node *node = root->rb_node;
  174. while (node) {
  175. struct res_common *res = container_of(node, struct res_common,
  176. node);
  177. if (res_id < res->res_id)
  178. node = node->rb_left;
  179. else if (res_id > res->res_id)
  180. node = node->rb_right;
  181. else
  182. return res;
  183. }
  184. return NULL;
  185. }
  186. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  187. {
  188. struct rb_node **new = &(root->rb_node), *parent = NULL;
  189. /* Figure out where to put new node */
  190. while (*new) {
  191. struct res_common *this = container_of(*new, struct res_common,
  192. node);
  193. parent = *new;
  194. if (res->res_id < this->res_id)
  195. new = &((*new)->rb_left);
  196. else if (res->res_id > this->res_id)
  197. new = &((*new)->rb_right);
  198. else
  199. return -EEXIST;
  200. }
  201. /* Add new node and rebalance tree. */
  202. rb_link_node(&res->node, parent, new);
  203. rb_insert_color(&res->node, root);
  204. return 0;
  205. }
  206. /* For Debug uses */
  207. static const char *ResourceType(enum mlx4_resource rt)
  208. {
  209. switch (rt) {
  210. case RES_QP: return "RES_QP";
  211. case RES_CQ: return "RES_CQ";
  212. case RES_SRQ: return "RES_SRQ";
  213. case RES_MPT: return "RES_MPT";
  214. case RES_MTT: return "RES_MTT";
  215. case RES_MAC: return "RES_MAC";
  216. case RES_EQ: return "RES_EQ";
  217. case RES_COUNTER: return "RES_COUNTER";
  218. case RES_FS_RULE: return "RES_FS_RULE";
  219. case RES_XRCD: return "RES_XRCD";
  220. default: return "Unknown resource type !!!";
  221. };
  222. }
  223. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  224. {
  225. struct mlx4_priv *priv = mlx4_priv(dev);
  226. int i;
  227. int t;
  228. priv->mfunc.master.res_tracker.slave_list =
  229. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  230. GFP_KERNEL);
  231. if (!priv->mfunc.master.res_tracker.slave_list)
  232. return -ENOMEM;
  233. for (i = 0 ; i < dev->num_slaves; i++) {
  234. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  235. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  236. slave_list[i].res_list[t]);
  237. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  238. }
  239. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  240. dev->num_slaves);
  241. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  242. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  243. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  244. return 0 ;
  245. }
  246. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  247. enum mlx4_res_tracker_free_type type)
  248. {
  249. struct mlx4_priv *priv = mlx4_priv(dev);
  250. int i;
  251. if (priv->mfunc.master.res_tracker.slave_list) {
  252. if (type != RES_TR_FREE_STRUCTS_ONLY)
  253. for (i = 0 ; i < dev->num_slaves; i++)
  254. if (type == RES_TR_FREE_ALL ||
  255. dev->caps.function != i)
  256. mlx4_delete_all_resources_for_slave(dev, i);
  257. if (type != RES_TR_FREE_SLAVES_ONLY) {
  258. kfree(priv->mfunc.master.res_tracker.slave_list);
  259. priv->mfunc.master.res_tracker.slave_list = NULL;
  260. }
  261. }
  262. }
  263. static void update_ud_gid(struct mlx4_dev *dev,
  264. struct mlx4_qp_context *qp_ctx, u8 slave)
  265. {
  266. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  267. if (MLX4_QP_ST_UD == ts)
  268. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  269. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  270. slave, qp_ctx->pri_path.mgid_index);
  271. }
  272. static int mpt_mask(struct mlx4_dev *dev)
  273. {
  274. return dev->caps.num_mpts - 1;
  275. }
  276. static void *find_res(struct mlx4_dev *dev, int res_id,
  277. enum mlx4_resource type)
  278. {
  279. struct mlx4_priv *priv = mlx4_priv(dev);
  280. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  281. res_id);
  282. }
  283. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  284. enum mlx4_resource type,
  285. void *res)
  286. {
  287. struct res_common *r;
  288. int err = 0;
  289. spin_lock_irq(mlx4_tlock(dev));
  290. r = find_res(dev, res_id, type);
  291. if (!r) {
  292. err = -ENONET;
  293. goto exit;
  294. }
  295. if (r->state == RES_ANY_BUSY) {
  296. err = -EBUSY;
  297. goto exit;
  298. }
  299. if (r->owner != slave) {
  300. err = -EPERM;
  301. goto exit;
  302. }
  303. r->from_state = r->state;
  304. r->state = RES_ANY_BUSY;
  305. mlx4_dbg(dev, "res %s id 0x%llx to busy\n",
  306. ResourceType(type), r->res_id);
  307. if (res)
  308. *((struct res_common **)res) = r;
  309. exit:
  310. spin_unlock_irq(mlx4_tlock(dev));
  311. return err;
  312. }
  313. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  314. enum mlx4_resource type,
  315. u64 res_id, int *slave)
  316. {
  317. struct res_common *r;
  318. int err = -ENOENT;
  319. int id = res_id;
  320. if (type == RES_QP)
  321. id &= 0x7fffff;
  322. spin_lock(mlx4_tlock(dev));
  323. r = find_res(dev, id, type);
  324. if (r) {
  325. *slave = r->owner;
  326. err = 0;
  327. }
  328. spin_unlock(mlx4_tlock(dev));
  329. return err;
  330. }
  331. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  332. enum mlx4_resource type)
  333. {
  334. struct res_common *r;
  335. spin_lock_irq(mlx4_tlock(dev));
  336. r = find_res(dev, res_id, type);
  337. if (r)
  338. r->state = r->from_state;
  339. spin_unlock_irq(mlx4_tlock(dev));
  340. }
  341. static struct res_common *alloc_qp_tr(int id)
  342. {
  343. struct res_qp *ret;
  344. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  345. if (!ret)
  346. return NULL;
  347. ret->com.res_id = id;
  348. ret->com.state = RES_QP_RESERVED;
  349. ret->local_qpn = id;
  350. INIT_LIST_HEAD(&ret->mcg_list);
  351. spin_lock_init(&ret->mcg_spl);
  352. return &ret->com;
  353. }
  354. static struct res_common *alloc_mtt_tr(int id, int order)
  355. {
  356. struct res_mtt *ret;
  357. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  358. if (!ret)
  359. return NULL;
  360. ret->com.res_id = id;
  361. ret->order = order;
  362. ret->com.state = RES_MTT_ALLOCATED;
  363. atomic_set(&ret->ref_count, 0);
  364. return &ret->com;
  365. }
  366. static struct res_common *alloc_mpt_tr(int id, int key)
  367. {
  368. struct res_mpt *ret;
  369. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  370. if (!ret)
  371. return NULL;
  372. ret->com.res_id = id;
  373. ret->com.state = RES_MPT_RESERVED;
  374. ret->key = key;
  375. return &ret->com;
  376. }
  377. static struct res_common *alloc_eq_tr(int id)
  378. {
  379. struct res_eq *ret;
  380. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  381. if (!ret)
  382. return NULL;
  383. ret->com.res_id = id;
  384. ret->com.state = RES_EQ_RESERVED;
  385. return &ret->com;
  386. }
  387. static struct res_common *alloc_cq_tr(int id)
  388. {
  389. struct res_cq *ret;
  390. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  391. if (!ret)
  392. return NULL;
  393. ret->com.res_id = id;
  394. ret->com.state = RES_CQ_ALLOCATED;
  395. atomic_set(&ret->ref_count, 0);
  396. return &ret->com;
  397. }
  398. static struct res_common *alloc_srq_tr(int id)
  399. {
  400. struct res_srq *ret;
  401. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  402. if (!ret)
  403. return NULL;
  404. ret->com.res_id = id;
  405. ret->com.state = RES_SRQ_ALLOCATED;
  406. atomic_set(&ret->ref_count, 0);
  407. return &ret->com;
  408. }
  409. static struct res_common *alloc_counter_tr(int id)
  410. {
  411. struct res_counter *ret;
  412. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  413. if (!ret)
  414. return NULL;
  415. ret->com.res_id = id;
  416. ret->com.state = RES_COUNTER_ALLOCATED;
  417. return &ret->com;
  418. }
  419. static struct res_common *alloc_xrcdn_tr(int id)
  420. {
  421. struct res_xrcdn *ret;
  422. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  423. if (!ret)
  424. return NULL;
  425. ret->com.res_id = id;
  426. ret->com.state = RES_XRCD_ALLOCATED;
  427. return &ret->com;
  428. }
  429. static struct res_common *alloc_fs_rule_tr(u64 id)
  430. {
  431. struct res_fs_rule *ret;
  432. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  433. if (!ret)
  434. return NULL;
  435. ret->com.res_id = id;
  436. ret->com.state = RES_FS_RULE_ALLOCATED;
  437. return &ret->com;
  438. }
  439. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  440. int extra)
  441. {
  442. struct res_common *ret;
  443. switch (type) {
  444. case RES_QP:
  445. ret = alloc_qp_tr(id);
  446. break;
  447. case RES_MPT:
  448. ret = alloc_mpt_tr(id, extra);
  449. break;
  450. case RES_MTT:
  451. ret = alloc_mtt_tr(id, extra);
  452. break;
  453. case RES_EQ:
  454. ret = alloc_eq_tr(id);
  455. break;
  456. case RES_CQ:
  457. ret = alloc_cq_tr(id);
  458. break;
  459. case RES_SRQ:
  460. ret = alloc_srq_tr(id);
  461. break;
  462. case RES_MAC:
  463. printk(KERN_ERR "implementation missing\n");
  464. return NULL;
  465. case RES_COUNTER:
  466. ret = alloc_counter_tr(id);
  467. break;
  468. case RES_XRCD:
  469. ret = alloc_xrcdn_tr(id);
  470. break;
  471. case RES_FS_RULE:
  472. ret = alloc_fs_rule_tr(id);
  473. break;
  474. default:
  475. return NULL;
  476. }
  477. if (ret)
  478. ret->owner = slave;
  479. return ret;
  480. }
  481. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  482. enum mlx4_resource type, int extra)
  483. {
  484. int i;
  485. int err;
  486. struct mlx4_priv *priv = mlx4_priv(dev);
  487. struct res_common **res_arr;
  488. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  489. struct rb_root *root = &tracker->res_tree[type];
  490. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  491. if (!res_arr)
  492. return -ENOMEM;
  493. for (i = 0; i < count; ++i) {
  494. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  495. if (!res_arr[i]) {
  496. for (--i; i >= 0; --i)
  497. kfree(res_arr[i]);
  498. kfree(res_arr);
  499. return -ENOMEM;
  500. }
  501. }
  502. spin_lock_irq(mlx4_tlock(dev));
  503. for (i = 0; i < count; ++i) {
  504. if (find_res(dev, base + i, type)) {
  505. err = -EEXIST;
  506. goto undo;
  507. }
  508. err = res_tracker_insert(root, res_arr[i]);
  509. if (err)
  510. goto undo;
  511. list_add_tail(&res_arr[i]->list,
  512. &tracker->slave_list[slave].res_list[type]);
  513. }
  514. spin_unlock_irq(mlx4_tlock(dev));
  515. kfree(res_arr);
  516. return 0;
  517. undo:
  518. for (--i; i >= base; --i)
  519. rb_erase(&res_arr[i]->node, root);
  520. spin_unlock_irq(mlx4_tlock(dev));
  521. for (i = 0; i < count; ++i)
  522. kfree(res_arr[i]);
  523. kfree(res_arr);
  524. return err;
  525. }
  526. static int remove_qp_ok(struct res_qp *res)
  527. {
  528. if (res->com.state == RES_QP_BUSY)
  529. return -EBUSY;
  530. else if (res->com.state != RES_QP_RESERVED)
  531. return -EPERM;
  532. return 0;
  533. }
  534. static int remove_mtt_ok(struct res_mtt *res, int order)
  535. {
  536. if (res->com.state == RES_MTT_BUSY ||
  537. atomic_read(&res->ref_count)) {
  538. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  539. __func__, __LINE__,
  540. mtt_states_str(res->com.state),
  541. atomic_read(&res->ref_count));
  542. return -EBUSY;
  543. } else if (res->com.state != RES_MTT_ALLOCATED)
  544. return -EPERM;
  545. else if (res->order != order)
  546. return -EINVAL;
  547. return 0;
  548. }
  549. static int remove_mpt_ok(struct res_mpt *res)
  550. {
  551. if (res->com.state == RES_MPT_BUSY)
  552. return -EBUSY;
  553. else if (res->com.state != RES_MPT_RESERVED)
  554. return -EPERM;
  555. return 0;
  556. }
  557. static int remove_eq_ok(struct res_eq *res)
  558. {
  559. if (res->com.state == RES_MPT_BUSY)
  560. return -EBUSY;
  561. else if (res->com.state != RES_MPT_RESERVED)
  562. return -EPERM;
  563. return 0;
  564. }
  565. static int remove_counter_ok(struct res_counter *res)
  566. {
  567. if (res->com.state == RES_COUNTER_BUSY)
  568. return -EBUSY;
  569. else if (res->com.state != RES_COUNTER_ALLOCATED)
  570. return -EPERM;
  571. return 0;
  572. }
  573. static int remove_xrcdn_ok(struct res_xrcdn *res)
  574. {
  575. if (res->com.state == RES_XRCD_BUSY)
  576. return -EBUSY;
  577. else if (res->com.state != RES_XRCD_ALLOCATED)
  578. return -EPERM;
  579. return 0;
  580. }
  581. static int remove_fs_rule_ok(struct res_fs_rule *res)
  582. {
  583. if (res->com.state == RES_FS_RULE_BUSY)
  584. return -EBUSY;
  585. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  586. return -EPERM;
  587. return 0;
  588. }
  589. static int remove_cq_ok(struct res_cq *res)
  590. {
  591. if (res->com.state == RES_CQ_BUSY)
  592. return -EBUSY;
  593. else if (res->com.state != RES_CQ_ALLOCATED)
  594. return -EPERM;
  595. return 0;
  596. }
  597. static int remove_srq_ok(struct res_srq *res)
  598. {
  599. if (res->com.state == RES_SRQ_BUSY)
  600. return -EBUSY;
  601. else if (res->com.state != RES_SRQ_ALLOCATED)
  602. return -EPERM;
  603. return 0;
  604. }
  605. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  606. {
  607. switch (type) {
  608. case RES_QP:
  609. return remove_qp_ok((struct res_qp *)res);
  610. case RES_CQ:
  611. return remove_cq_ok((struct res_cq *)res);
  612. case RES_SRQ:
  613. return remove_srq_ok((struct res_srq *)res);
  614. case RES_MPT:
  615. return remove_mpt_ok((struct res_mpt *)res);
  616. case RES_MTT:
  617. return remove_mtt_ok((struct res_mtt *)res, extra);
  618. case RES_MAC:
  619. return -ENOSYS;
  620. case RES_EQ:
  621. return remove_eq_ok((struct res_eq *)res);
  622. case RES_COUNTER:
  623. return remove_counter_ok((struct res_counter *)res);
  624. case RES_XRCD:
  625. return remove_xrcdn_ok((struct res_xrcdn *)res);
  626. case RES_FS_RULE:
  627. return remove_fs_rule_ok((struct res_fs_rule *)res);
  628. default:
  629. return -EINVAL;
  630. }
  631. }
  632. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  633. enum mlx4_resource type, int extra)
  634. {
  635. u64 i;
  636. int err;
  637. struct mlx4_priv *priv = mlx4_priv(dev);
  638. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  639. struct res_common *r;
  640. spin_lock_irq(mlx4_tlock(dev));
  641. for (i = base; i < base + count; ++i) {
  642. r = res_tracker_lookup(&tracker->res_tree[type], i);
  643. if (!r) {
  644. err = -ENOENT;
  645. goto out;
  646. }
  647. if (r->owner != slave) {
  648. err = -EPERM;
  649. goto out;
  650. }
  651. err = remove_ok(r, type, extra);
  652. if (err)
  653. goto out;
  654. }
  655. for (i = base; i < base + count; ++i) {
  656. r = res_tracker_lookup(&tracker->res_tree[type], i);
  657. rb_erase(&r->node, &tracker->res_tree[type]);
  658. list_del(&r->list);
  659. kfree(r);
  660. }
  661. err = 0;
  662. out:
  663. spin_unlock_irq(mlx4_tlock(dev));
  664. return err;
  665. }
  666. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  667. enum res_qp_states state, struct res_qp **qp,
  668. int alloc)
  669. {
  670. struct mlx4_priv *priv = mlx4_priv(dev);
  671. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  672. struct res_qp *r;
  673. int err = 0;
  674. spin_lock_irq(mlx4_tlock(dev));
  675. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  676. if (!r)
  677. err = -ENOENT;
  678. else if (r->com.owner != slave)
  679. err = -EPERM;
  680. else {
  681. switch (state) {
  682. case RES_QP_BUSY:
  683. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  684. __func__, r->com.res_id);
  685. err = -EBUSY;
  686. break;
  687. case RES_QP_RESERVED:
  688. if (r->com.state == RES_QP_MAPPED && !alloc)
  689. break;
  690. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  691. err = -EINVAL;
  692. break;
  693. case RES_QP_MAPPED:
  694. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  695. r->com.state == RES_QP_HW)
  696. break;
  697. else {
  698. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  699. r->com.res_id);
  700. err = -EINVAL;
  701. }
  702. break;
  703. case RES_QP_HW:
  704. if (r->com.state != RES_QP_MAPPED)
  705. err = -EINVAL;
  706. break;
  707. default:
  708. err = -EINVAL;
  709. }
  710. if (!err) {
  711. r->com.from_state = r->com.state;
  712. r->com.to_state = state;
  713. r->com.state = RES_QP_BUSY;
  714. if (qp)
  715. *qp = r;
  716. }
  717. }
  718. spin_unlock_irq(mlx4_tlock(dev));
  719. return err;
  720. }
  721. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  722. enum res_mpt_states state, struct res_mpt **mpt)
  723. {
  724. struct mlx4_priv *priv = mlx4_priv(dev);
  725. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  726. struct res_mpt *r;
  727. int err = 0;
  728. spin_lock_irq(mlx4_tlock(dev));
  729. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  730. if (!r)
  731. err = -ENOENT;
  732. else if (r->com.owner != slave)
  733. err = -EPERM;
  734. else {
  735. switch (state) {
  736. case RES_MPT_BUSY:
  737. err = -EINVAL;
  738. break;
  739. case RES_MPT_RESERVED:
  740. if (r->com.state != RES_MPT_MAPPED)
  741. err = -EINVAL;
  742. break;
  743. case RES_MPT_MAPPED:
  744. if (r->com.state != RES_MPT_RESERVED &&
  745. r->com.state != RES_MPT_HW)
  746. err = -EINVAL;
  747. break;
  748. case RES_MPT_HW:
  749. if (r->com.state != RES_MPT_MAPPED)
  750. err = -EINVAL;
  751. break;
  752. default:
  753. err = -EINVAL;
  754. }
  755. if (!err) {
  756. r->com.from_state = r->com.state;
  757. r->com.to_state = state;
  758. r->com.state = RES_MPT_BUSY;
  759. if (mpt)
  760. *mpt = r;
  761. }
  762. }
  763. spin_unlock_irq(mlx4_tlock(dev));
  764. return err;
  765. }
  766. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  767. enum res_eq_states state, struct res_eq **eq)
  768. {
  769. struct mlx4_priv *priv = mlx4_priv(dev);
  770. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  771. struct res_eq *r;
  772. int err = 0;
  773. spin_lock_irq(mlx4_tlock(dev));
  774. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  775. if (!r)
  776. err = -ENOENT;
  777. else if (r->com.owner != slave)
  778. err = -EPERM;
  779. else {
  780. switch (state) {
  781. case RES_EQ_BUSY:
  782. err = -EINVAL;
  783. break;
  784. case RES_EQ_RESERVED:
  785. if (r->com.state != RES_EQ_HW)
  786. err = -EINVAL;
  787. break;
  788. case RES_EQ_HW:
  789. if (r->com.state != RES_EQ_RESERVED)
  790. err = -EINVAL;
  791. break;
  792. default:
  793. err = -EINVAL;
  794. }
  795. if (!err) {
  796. r->com.from_state = r->com.state;
  797. r->com.to_state = state;
  798. r->com.state = RES_EQ_BUSY;
  799. if (eq)
  800. *eq = r;
  801. }
  802. }
  803. spin_unlock_irq(mlx4_tlock(dev));
  804. return err;
  805. }
  806. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  807. enum res_cq_states state, struct res_cq **cq)
  808. {
  809. struct mlx4_priv *priv = mlx4_priv(dev);
  810. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  811. struct res_cq *r;
  812. int err;
  813. spin_lock_irq(mlx4_tlock(dev));
  814. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  815. if (!r)
  816. err = -ENOENT;
  817. else if (r->com.owner != slave)
  818. err = -EPERM;
  819. else {
  820. switch (state) {
  821. case RES_CQ_BUSY:
  822. err = -EBUSY;
  823. break;
  824. case RES_CQ_ALLOCATED:
  825. if (r->com.state != RES_CQ_HW)
  826. err = -EINVAL;
  827. else if (atomic_read(&r->ref_count))
  828. err = -EBUSY;
  829. else
  830. err = 0;
  831. break;
  832. case RES_CQ_HW:
  833. if (r->com.state != RES_CQ_ALLOCATED)
  834. err = -EINVAL;
  835. else
  836. err = 0;
  837. break;
  838. default:
  839. err = -EINVAL;
  840. }
  841. if (!err) {
  842. r->com.from_state = r->com.state;
  843. r->com.to_state = state;
  844. r->com.state = RES_CQ_BUSY;
  845. if (cq)
  846. *cq = r;
  847. }
  848. }
  849. spin_unlock_irq(mlx4_tlock(dev));
  850. return err;
  851. }
  852. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  853. enum res_cq_states state, struct res_srq **srq)
  854. {
  855. struct mlx4_priv *priv = mlx4_priv(dev);
  856. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  857. struct res_srq *r;
  858. int err = 0;
  859. spin_lock_irq(mlx4_tlock(dev));
  860. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  861. if (!r)
  862. err = -ENOENT;
  863. else if (r->com.owner != slave)
  864. err = -EPERM;
  865. else {
  866. switch (state) {
  867. case RES_SRQ_BUSY:
  868. err = -EINVAL;
  869. break;
  870. case RES_SRQ_ALLOCATED:
  871. if (r->com.state != RES_SRQ_HW)
  872. err = -EINVAL;
  873. else if (atomic_read(&r->ref_count))
  874. err = -EBUSY;
  875. break;
  876. case RES_SRQ_HW:
  877. if (r->com.state != RES_SRQ_ALLOCATED)
  878. err = -EINVAL;
  879. break;
  880. default:
  881. err = -EINVAL;
  882. }
  883. if (!err) {
  884. r->com.from_state = r->com.state;
  885. r->com.to_state = state;
  886. r->com.state = RES_SRQ_BUSY;
  887. if (srq)
  888. *srq = r;
  889. }
  890. }
  891. spin_unlock_irq(mlx4_tlock(dev));
  892. return err;
  893. }
  894. static void res_abort_move(struct mlx4_dev *dev, int slave,
  895. enum mlx4_resource type, int id)
  896. {
  897. struct mlx4_priv *priv = mlx4_priv(dev);
  898. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  899. struct res_common *r;
  900. spin_lock_irq(mlx4_tlock(dev));
  901. r = res_tracker_lookup(&tracker->res_tree[type], id);
  902. if (r && (r->owner == slave))
  903. r->state = r->from_state;
  904. spin_unlock_irq(mlx4_tlock(dev));
  905. }
  906. static void res_end_move(struct mlx4_dev *dev, int slave,
  907. enum mlx4_resource type, int id)
  908. {
  909. struct mlx4_priv *priv = mlx4_priv(dev);
  910. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  911. struct res_common *r;
  912. spin_lock_irq(mlx4_tlock(dev));
  913. r = res_tracker_lookup(&tracker->res_tree[type], id);
  914. if (r && (r->owner == slave))
  915. r->state = r->to_state;
  916. spin_unlock_irq(mlx4_tlock(dev));
  917. }
  918. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  919. {
  920. return mlx4_is_qp_reserved(dev, qpn);
  921. }
  922. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  923. u64 in_param, u64 *out_param)
  924. {
  925. int err;
  926. int count;
  927. int align;
  928. int base;
  929. int qpn;
  930. switch (op) {
  931. case RES_OP_RESERVE:
  932. count = get_param_l(&in_param);
  933. align = get_param_h(&in_param);
  934. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  935. if (err)
  936. return err;
  937. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  938. if (err) {
  939. __mlx4_qp_release_range(dev, base, count);
  940. return err;
  941. }
  942. set_param_l(out_param, base);
  943. break;
  944. case RES_OP_MAP_ICM:
  945. qpn = get_param_l(&in_param) & 0x7fffff;
  946. if (valid_reserved(dev, slave, qpn)) {
  947. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  948. if (err)
  949. return err;
  950. }
  951. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  952. NULL, 1);
  953. if (err)
  954. return err;
  955. if (!valid_reserved(dev, slave, qpn)) {
  956. err = __mlx4_qp_alloc_icm(dev, qpn);
  957. if (err) {
  958. res_abort_move(dev, slave, RES_QP, qpn);
  959. return err;
  960. }
  961. }
  962. res_end_move(dev, slave, RES_QP, qpn);
  963. break;
  964. default:
  965. err = -EINVAL;
  966. break;
  967. }
  968. return err;
  969. }
  970. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  971. u64 in_param, u64 *out_param)
  972. {
  973. int err = -EINVAL;
  974. int base;
  975. int order;
  976. if (op != RES_OP_RESERVE_AND_MAP)
  977. return err;
  978. order = get_param_l(&in_param);
  979. base = __mlx4_alloc_mtt_range(dev, order);
  980. if (base == -1)
  981. return -ENOMEM;
  982. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  983. if (err)
  984. __mlx4_free_mtt_range(dev, base, order);
  985. else
  986. set_param_l(out_param, base);
  987. return err;
  988. }
  989. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  990. u64 in_param, u64 *out_param)
  991. {
  992. int err = -EINVAL;
  993. int index;
  994. int id;
  995. struct res_mpt *mpt;
  996. switch (op) {
  997. case RES_OP_RESERVE:
  998. index = __mlx4_mr_reserve(dev);
  999. if (index == -1)
  1000. break;
  1001. id = index & mpt_mask(dev);
  1002. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1003. if (err) {
  1004. __mlx4_mr_release(dev, index);
  1005. break;
  1006. }
  1007. set_param_l(out_param, index);
  1008. break;
  1009. case RES_OP_MAP_ICM:
  1010. index = get_param_l(&in_param);
  1011. id = index & mpt_mask(dev);
  1012. err = mr_res_start_move_to(dev, slave, id,
  1013. RES_MPT_MAPPED, &mpt);
  1014. if (err)
  1015. return err;
  1016. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  1017. if (err) {
  1018. res_abort_move(dev, slave, RES_MPT, id);
  1019. return err;
  1020. }
  1021. res_end_move(dev, slave, RES_MPT, id);
  1022. break;
  1023. }
  1024. return err;
  1025. }
  1026. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1027. u64 in_param, u64 *out_param)
  1028. {
  1029. int cqn;
  1030. int err;
  1031. switch (op) {
  1032. case RES_OP_RESERVE_AND_MAP:
  1033. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1034. if (err)
  1035. break;
  1036. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1037. if (err) {
  1038. __mlx4_cq_free_icm(dev, cqn);
  1039. break;
  1040. }
  1041. set_param_l(out_param, cqn);
  1042. break;
  1043. default:
  1044. err = -EINVAL;
  1045. }
  1046. return err;
  1047. }
  1048. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1049. u64 in_param, u64 *out_param)
  1050. {
  1051. int srqn;
  1052. int err;
  1053. switch (op) {
  1054. case RES_OP_RESERVE_AND_MAP:
  1055. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1056. if (err)
  1057. break;
  1058. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1059. if (err) {
  1060. __mlx4_srq_free_icm(dev, srqn);
  1061. break;
  1062. }
  1063. set_param_l(out_param, srqn);
  1064. break;
  1065. default:
  1066. err = -EINVAL;
  1067. }
  1068. return err;
  1069. }
  1070. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1071. {
  1072. struct mlx4_priv *priv = mlx4_priv(dev);
  1073. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1074. struct mac_res *res;
  1075. res = kzalloc(sizeof *res, GFP_KERNEL);
  1076. if (!res)
  1077. return -ENOMEM;
  1078. res->mac = mac;
  1079. res->port = (u8) port;
  1080. list_add_tail(&res->list,
  1081. &tracker->slave_list[slave].res_list[RES_MAC]);
  1082. return 0;
  1083. }
  1084. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1085. int port)
  1086. {
  1087. struct mlx4_priv *priv = mlx4_priv(dev);
  1088. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1089. struct list_head *mac_list =
  1090. &tracker->slave_list[slave].res_list[RES_MAC];
  1091. struct mac_res *res, *tmp;
  1092. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1093. if (res->mac == mac && res->port == (u8) port) {
  1094. list_del(&res->list);
  1095. kfree(res);
  1096. break;
  1097. }
  1098. }
  1099. }
  1100. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1101. {
  1102. struct mlx4_priv *priv = mlx4_priv(dev);
  1103. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1104. struct list_head *mac_list =
  1105. &tracker->slave_list[slave].res_list[RES_MAC];
  1106. struct mac_res *res, *tmp;
  1107. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1108. list_del(&res->list);
  1109. __mlx4_unregister_mac(dev, res->port, res->mac);
  1110. kfree(res);
  1111. }
  1112. }
  1113. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1114. u64 in_param, u64 *out_param)
  1115. {
  1116. int err = -EINVAL;
  1117. int port;
  1118. u64 mac;
  1119. if (op != RES_OP_RESERVE_AND_MAP)
  1120. return err;
  1121. port = get_param_l(out_param);
  1122. mac = in_param;
  1123. err = __mlx4_register_mac(dev, port, mac);
  1124. if (err >= 0) {
  1125. set_param_l(out_param, err);
  1126. err = 0;
  1127. }
  1128. if (!err) {
  1129. err = mac_add_to_slave(dev, slave, mac, port);
  1130. if (err)
  1131. __mlx4_unregister_mac(dev, port, mac);
  1132. }
  1133. return err;
  1134. }
  1135. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1136. u64 in_param, u64 *out_param)
  1137. {
  1138. return 0;
  1139. }
  1140. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1141. u64 in_param, u64 *out_param)
  1142. {
  1143. u32 index;
  1144. int err;
  1145. if (op != RES_OP_RESERVE)
  1146. return -EINVAL;
  1147. err = __mlx4_counter_alloc(dev, &index);
  1148. if (err)
  1149. return err;
  1150. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1151. if (err)
  1152. __mlx4_counter_free(dev, index);
  1153. else
  1154. set_param_l(out_param, index);
  1155. return err;
  1156. }
  1157. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1158. u64 in_param, u64 *out_param)
  1159. {
  1160. u32 xrcdn;
  1161. int err;
  1162. if (op != RES_OP_RESERVE)
  1163. return -EINVAL;
  1164. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1165. if (err)
  1166. return err;
  1167. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1168. if (err)
  1169. __mlx4_xrcd_free(dev, xrcdn);
  1170. else
  1171. set_param_l(out_param, xrcdn);
  1172. return err;
  1173. }
  1174. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1175. struct mlx4_vhcr *vhcr,
  1176. struct mlx4_cmd_mailbox *inbox,
  1177. struct mlx4_cmd_mailbox *outbox,
  1178. struct mlx4_cmd_info *cmd)
  1179. {
  1180. int err;
  1181. int alop = vhcr->op_modifier;
  1182. switch (vhcr->in_modifier) {
  1183. case RES_QP:
  1184. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1185. vhcr->in_param, &vhcr->out_param);
  1186. break;
  1187. case RES_MTT:
  1188. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1189. vhcr->in_param, &vhcr->out_param);
  1190. break;
  1191. case RES_MPT:
  1192. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1193. vhcr->in_param, &vhcr->out_param);
  1194. break;
  1195. case RES_CQ:
  1196. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1197. vhcr->in_param, &vhcr->out_param);
  1198. break;
  1199. case RES_SRQ:
  1200. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1201. vhcr->in_param, &vhcr->out_param);
  1202. break;
  1203. case RES_MAC:
  1204. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1205. vhcr->in_param, &vhcr->out_param);
  1206. break;
  1207. case RES_VLAN:
  1208. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1209. vhcr->in_param, &vhcr->out_param);
  1210. break;
  1211. case RES_COUNTER:
  1212. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1213. vhcr->in_param, &vhcr->out_param);
  1214. break;
  1215. case RES_XRCD:
  1216. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1217. vhcr->in_param, &vhcr->out_param);
  1218. break;
  1219. default:
  1220. err = -EINVAL;
  1221. break;
  1222. }
  1223. return err;
  1224. }
  1225. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1226. u64 in_param)
  1227. {
  1228. int err;
  1229. int count;
  1230. int base;
  1231. int qpn;
  1232. switch (op) {
  1233. case RES_OP_RESERVE:
  1234. base = get_param_l(&in_param) & 0x7fffff;
  1235. count = get_param_h(&in_param);
  1236. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1237. if (err)
  1238. break;
  1239. __mlx4_qp_release_range(dev, base, count);
  1240. break;
  1241. case RES_OP_MAP_ICM:
  1242. qpn = get_param_l(&in_param) & 0x7fffff;
  1243. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1244. NULL, 0);
  1245. if (err)
  1246. return err;
  1247. if (!valid_reserved(dev, slave, qpn))
  1248. __mlx4_qp_free_icm(dev, qpn);
  1249. res_end_move(dev, slave, RES_QP, qpn);
  1250. if (valid_reserved(dev, slave, qpn))
  1251. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1252. break;
  1253. default:
  1254. err = -EINVAL;
  1255. break;
  1256. }
  1257. return err;
  1258. }
  1259. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1260. u64 in_param, u64 *out_param)
  1261. {
  1262. int err = -EINVAL;
  1263. int base;
  1264. int order;
  1265. if (op != RES_OP_RESERVE_AND_MAP)
  1266. return err;
  1267. base = get_param_l(&in_param);
  1268. order = get_param_h(&in_param);
  1269. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1270. if (!err)
  1271. __mlx4_free_mtt_range(dev, base, order);
  1272. return err;
  1273. }
  1274. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1275. u64 in_param)
  1276. {
  1277. int err = -EINVAL;
  1278. int index;
  1279. int id;
  1280. struct res_mpt *mpt;
  1281. switch (op) {
  1282. case RES_OP_RESERVE:
  1283. index = get_param_l(&in_param);
  1284. id = index & mpt_mask(dev);
  1285. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1286. if (err)
  1287. break;
  1288. index = mpt->key;
  1289. put_res(dev, slave, id, RES_MPT);
  1290. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1291. if (err)
  1292. break;
  1293. __mlx4_mr_release(dev, index);
  1294. break;
  1295. case RES_OP_MAP_ICM:
  1296. index = get_param_l(&in_param);
  1297. id = index & mpt_mask(dev);
  1298. err = mr_res_start_move_to(dev, slave, id,
  1299. RES_MPT_RESERVED, &mpt);
  1300. if (err)
  1301. return err;
  1302. __mlx4_mr_free_icm(dev, mpt->key);
  1303. res_end_move(dev, slave, RES_MPT, id);
  1304. return err;
  1305. break;
  1306. default:
  1307. err = -EINVAL;
  1308. break;
  1309. }
  1310. return err;
  1311. }
  1312. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1313. u64 in_param, u64 *out_param)
  1314. {
  1315. int cqn;
  1316. int err;
  1317. switch (op) {
  1318. case RES_OP_RESERVE_AND_MAP:
  1319. cqn = get_param_l(&in_param);
  1320. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1321. if (err)
  1322. break;
  1323. __mlx4_cq_free_icm(dev, cqn);
  1324. break;
  1325. default:
  1326. err = -EINVAL;
  1327. break;
  1328. }
  1329. return err;
  1330. }
  1331. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1332. u64 in_param, u64 *out_param)
  1333. {
  1334. int srqn;
  1335. int err;
  1336. switch (op) {
  1337. case RES_OP_RESERVE_AND_MAP:
  1338. srqn = get_param_l(&in_param);
  1339. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1340. if (err)
  1341. break;
  1342. __mlx4_srq_free_icm(dev, srqn);
  1343. break;
  1344. default:
  1345. err = -EINVAL;
  1346. break;
  1347. }
  1348. return err;
  1349. }
  1350. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1351. u64 in_param, u64 *out_param)
  1352. {
  1353. int port;
  1354. int err = 0;
  1355. switch (op) {
  1356. case RES_OP_RESERVE_AND_MAP:
  1357. port = get_param_l(out_param);
  1358. mac_del_from_slave(dev, slave, in_param, port);
  1359. __mlx4_unregister_mac(dev, port, in_param);
  1360. break;
  1361. default:
  1362. err = -EINVAL;
  1363. break;
  1364. }
  1365. return err;
  1366. }
  1367. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1368. u64 in_param, u64 *out_param)
  1369. {
  1370. return 0;
  1371. }
  1372. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1373. u64 in_param, u64 *out_param)
  1374. {
  1375. int index;
  1376. int err;
  1377. if (op != RES_OP_RESERVE)
  1378. return -EINVAL;
  1379. index = get_param_l(&in_param);
  1380. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1381. if (err)
  1382. return err;
  1383. __mlx4_counter_free(dev, index);
  1384. return err;
  1385. }
  1386. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1387. u64 in_param, u64 *out_param)
  1388. {
  1389. int xrcdn;
  1390. int err;
  1391. if (op != RES_OP_RESERVE)
  1392. return -EINVAL;
  1393. xrcdn = get_param_l(&in_param);
  1394. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1395. if (err)
  1396. return err;
  1397. __mlx4_xrcd_free(dev, xrcdn);
  1398. return err;
  1399. }
  1400. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1401. struct mlx4_vhcr *vhcr,
  1402. struct mlx4_cmd_mailbox *inbox,
  1403. struct mlx4_cmd_mailbox *outbox,
  1404. struct mlx4_cmd_info *cmd)
  1405. {
  1406. int err = -EINVAL;
  1407. int alop = vhcr->op_modifier;
  1408. switch (vhcr->in_modifier) {
  1409. case RES_QP:
  1410. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1411. vhcr->in_param);
  1412. break;
  1413. case RES_MTT:
  1414. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1415. vhcr->in_param, &vhcr->out_param);
  1416. break;
  1417. case RES_MPT:
  1418. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1419. vhcr->in_param);
  1420. break;
  1421. case RES_CQ:
  1422. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1423. vhcr->in_param, &vhcr->out_param);
  1424. break;
  1425. case RES_SRQ:
  1426. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1427. vhcr->in_param, &vhcr->out_param);
  1428. break;
  1429. case RES_MAC:
  1430. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1431. vhcr->in_param, &vhcr->out_param);
  1432. break;
  1433. case RES_VLAN:
  1434. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1435. vhcr->in_param, &vhcr->out_param);
  1436. break;
  1437. case RES_COUNTER:
  1438. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1439. vhcr->in_param, &vhcr->out_param);
  1440. break;
  1441. case RES_XRCD:
  1442. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1443. vhcr->in_param, &vhcr->out_param);
  1444. default:
  1445. break;
  1446. }
  1447. return err;
  1448. }
  1449. /* ugly but other choices are uglier */
  1450. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1451. {
  1452. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1453. }
  1454. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1455. {
  1456. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1457. }
  1458. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1459. {
  1460. return be32_to_cpu(mpt->mtt_sz);
  1461. }
  1462. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1463. {
  1464. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1465. }
  1466. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1467. {
  1468. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1469. }
  1470. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1471. {
  1472. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1473. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1474. int log_sq_sride = qpc->sq_size_stride & 7;
  1475. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1476. int log_rq_stride = qpc->rq_size_stride & 7;
  1477. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1478. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1479. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1480. int sq_size;
  1481. int rq_size;
  1482. int total_pages;
  1483. int total_mem;
  1484. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1485. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1486. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1487. total_mem = sq_size + rq_size;
  1488. total_pages =
  1489. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1490. page_shift);
  1491. return total_pages;
  1492. }
  1493. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1494. int size, struct res_mtt *mtt)
  1495. {
  1496. int res_start = mtt->com.res_id;
  1497. int res_size = (1 << mtt->order);
  1498. if (start < res_start || start + size > res_start + res_size)
  1499. return -EPERM;
  1500. return 0;
  1501. }
  1502. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1503. struct mlx4_vhcr *vhcr,
  1504. struct mlx4_cmd_mailbox *inbox,
  1505. struct mlx4_cmd_mailbox *outbox,
  1506. struct mlx4_cmd_info *cmd)
  1507. {
  1508. int err;
  1509. int index = vhcr->in_modifier;
  1510. struct res_mtt *mtt;
  1511. struct res_mpt *mpt;
  1512. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1513. int phys;
  1514. int id;
  1515. id = index & mpt_mask(dev);
  1516. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1517. if (err)
  1518. return err;
  1519. phys = mr_phys_mpt(inbox->buf);
  1520. if (!phys) {
  1521. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1522. if (err)
  1523. goto ex_abort;
  1524. err = check_mtt_range(dev, slave, mtt_base,
  1525. mr_get_mtt_size(inbox->buf), mtt);
  1526. if (err)
  1527. goto ex_put;
  1528. mpt->mtt = mtt;
  1529. }
  1530. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1531. if (err)
  1532. goto ex_put;
  1533. if (!phys) {
  1534. atomic_inc(&mtt->ref_count);
  1535. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1536. }
  1537. res_end_move(dev, slave, RES_MPT, id);
  1538. return 0;
  1539. ex_put:
  1540. if (!phys)
  1541. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1542. ex_abort:
  1543. res_abort_move(dev, slave, RES_MPT, id);
  1544. return err;
  1545. }
  1546. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1547. struct mlx4_vhcr *vhcr,
  1548. struct mlx4_cmd_mailbox *inbox,
  1549. struct mlx4_cmd_mailbox *outbox,
  1550. struct mlx4_cmd_info *cmd)
  1551. {
  1552. int err;
  1553. int index = vhcr->in_modifier;
  1554. struct res_mpt *mpt;
  1555. int id;
  1556. id = index & mpt_mask(dev);
  1557. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1558. if (err)
  1559. return err;
  1560. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1561. if (err)
  1562. goto ex_abort;
  1563. if (mpt->mtt)
  1564. atomic_dec(&mpt->mtt->ref_count);
  1565. res_end_move(dev, slave, RES_MPT, id);
  1566. return 0;
  1567. ex_abort:
  1568. res_abort_move(dev, slave, RES_MPT, id);
  1569. return err;
  1570. }
  1571. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1572. struct mlx4_vhcr *vhcr,
  1573. struct mlx4_cmd_mailbox *inbox,
  1574. struct mlx4_cmd_mailbox *outbox,
  1575. struct mlx4_cmd_info *cmd)
  1576. {
  1577. int err;
  1578. int index = vhcr->in_modifier;
  1579. struct res_mpt *mpt;
  1580. int id;
  1581. id = index & mpt_mask(dev);
  1582. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1583. if (err)
  1584. return err;
  1585. if (mpt->com.from_state != RES_MPT_HW) {
  1586. err = -EBUSY;
  1587. goto out;
  1588. }
  1589. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1590. out:
  1591. put_res(dev, slave, id, RES_MPT);
  1592. return err;
  1593. }
  1594. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1595. {
  1596. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1597. }
  1598. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1599. {
  1600. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1601. }
  1602. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1603. {
  1604. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1605. }
  1606. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1607. struct mlx4_vhcr *vhcr,
  1608. struct mlx4_cmd_mailbox *inbox,
  1609. struct mlx4_cmd_mailbox *outbox,
  1610. struct mlx4_cmd_info *cmd)
  1611. {
  1612. int err;
  1613. int qpn = vhcr->in_modifier & 0x7fffff;
  1614. struct res_mtt *mtt;
  1615. struct res_qp *qp;
  1616. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1617. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1618. int mtt_size = qp_get_mtt_size(qpc);
  1619. struct res_cq *rcq;
  1620. struct res_cq *scq;
  1621. int rcqn = qp_get_rcqn(qpc);
  1622. int scqn = qp_get_scqn(qpc);
  1623. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1624. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1625. struct res_srq *srq;
  1626. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1627. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1628. if (err)
  1629. return err;
  1630. qp->local_qpn = local_qpn;
  1631. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1632. if (err)
  1633. goto ex_abort;
  1634. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1635. if (err)
  1636. goto ex_put_mtt;
  1637. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1638. if (err)
  1639. goto ex_put_mtt;
  1640. if (scqn != rcqn) {
  1641. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1642. if (err)
  1643. goto ex_put_rcq;
  1644. } else
  1645. scq = rcq;
  1646. if (use_srq) {
  1647. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1648. if (err)
  1649. goto ex_put_scq;
  1650. }
  1651. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1652. if (err)
  1653. goto ex_put_srq;
  1654. atomic_inc(&mtt->ref_count);
  1655. qp->mtt = mtt;
  1656. atomic_inc(&rcq->ref_count);
  1657. qp->rcq = rcq;
  1658. atomic_inc(&scq->ref_count);
  1659. qp->scq = scq;
  1660. if (scqn != rcqn)
  1661. put_res(dev, slave, scqn, RES_CQ);
  1662. if (use_srq) {
  1663. atomic_inc(&srq->ref_count);
  1664. put_res(dev, slave, srqn, RES_SRQ);
  1665. qp->srq = srq;
  1666. }
  1667. put_res(dev, slave, rcqn, RES_CQ);
  1668. put_res(dev, slave, mtt_base, RES_MTT);
  1669. res_end_move(dev, slave, RES_QP, qpn);
  1670. return 0;
  1671. ex_put_srq:
  1672. if (use_srq)
  1673. put_res(dev, slave, srqn, RES_SRQ);
  1674. ex_put_scq:
  1675. if (scqn != rcqn)
  1676. put_res(dev, slave, scqn, RES_CQ);
  1677. ex_put_rcq:
  1678. put_res(dev, slave, rcqn, RES_CQ);
  1679. ex_put_mtt:
  1680. put_res(dev, slave, mtt_base, RES_MTT);
  1681. ex_abort:
  1682. res_abort_move(dev, slave, RES_QP, qpn);
  1683. return err;
  1684. }
  1685. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1686. {
  1687. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1688. }
  1689. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1690. {
  1691. int log_eq_size = eqc->log_eq_size & 0x1f;
  1692. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1693. if (log_eq_size + 5 < page_shift)
  1694. return 1;
  1695. return 1 << (log_eq_size + 5 - page_shift);
  1696. }
  1697. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1698. {
  1699. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1700. }
  1701. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1702. {
  1703. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1704. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1705. if (log_cq_size + 5 < page_shift)
  1706. return 1;
  1707. return 1 << (log_cq_size + 5 - page_shift);
  1708. }
  1709. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1710. struct mlx4_vhcr *vhcr,
  1711. struct mlx4_cmd_mailbox *inbox,
  1712. struct mlx4_cmd_mailbox *outbox,
  1713. struct mlx4_cmd_info *cmd)
  1714. {
  1715. int err;
  1716. int eqn = vhcr->in_modifier;
  1717. int res_id = (slave << 8) | eqn;
  1718. struct mlx4_eq_context *eqc = inbox->buf;
  1719. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1720. int mtt_size = eq_get_mtt_size(eqc);
  1721. struct res_eq *eq;
  1722. struct res_mtt *mtt;
  1723. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1724. if (err)
  1725. return err;
  1726. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1727. if (err)
  1728. goto out_add;
  1729. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1730. if (err)
  1731. goto out_move;
  1732. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1733. if (err)
  1734. goto out_put;
  1735. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1736. if (err)
  1737. goto out_put;
  1738. atomic_inc(&mtt->ref_count);
  1739. eq->mtt = mtt;
  1740. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1741. res_end_move(dev, slave, RES_EQ, res_id);
  1742. return 0;
  1743. out_put:
  1744. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1745. out_move:
  1746. res_abort_move(dev, slave, RES_EQ, res_id);
  1747. out_add:
  1748. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1749. return err;
  1750. }
  1751. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1752. int len, struct res_mtt **res)
  1753. {
  1754. struct mlx4_priv *priv = mlx4_priv(dev);
  1755. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1756. struct res_mtt *mtt;
  1757. int err = -EINVAL;
  1758. spin_lock_irq(mlx4_tlock(dev));
  1759. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1760. com.list) {
  1761. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1762. *res = mtt;
  1763. mtt->com.from_state = mtt->com.state;
  1764. mtt->com.state = RES_MTT_BUSY;
  1765. err = 0;
  1766. break;
  1767. }
  1768. }
  1769. spin_unlock_irq(mlx4_tlock(dev));
  1770. return err;
  1771. }
  1772. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1773. struct mlx4_vhcr *vhcr,
  1774. struct mlx4_cmd_mailbox *inbox,
  1775. struct mlx4_cmd_mailbox *outbox,
  1776. struct mlx4_cmd_info *cmd)
  1777. {
  1778. struct mlx4_mtt mtt;
  1779. __be64 *page_list = inbox->buf;
  1780. u64 *pg_list = (u64 *)page_list;
  1781. int i;
  1782. struct res_mtt *rmtt = NULL;
  1783. int start = be64_to_cpu(page_list[0]);
  1784. int npages = vhcr->in_modifier;
  1785. int err;
  1786. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1787. if (err)
  1788. return err;
  1789. /* Call the SW implementation of write_mtt:
  1790. * - Prepare a dummy mtt struct
  1791. * - Translate inbox contents to simple addresses in host endianess */
  1792. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1793. we don't really use it */
  1794. mtt.order = 0;
  1795. mtt.page_shift = 0;
  1796. for (i = 0; i < npages; ++i)
  1797. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1798. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1799. ((u64 *)page_list + 2));
  1800. if (rmtt)
  1801. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1802. return err;
  1803. }
  1804. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1805. struct mlx4_vhcr *vhcr,
  1806. struct mlx4_cmd_mailbox *inbox,
  1807. struct mlx4_cmd_mailbox *outbox,
  1808. struct mlx4_cmd_info *cmd)
  1809. {
  1810. int eqn = vhcr->in_modifier;
  1811. int res_id = eqn | (slave << 8);
  1812. struct res_eq *eq;
  1813. int err;
  1814. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1815. if (err)
  1816. return err;
  1817. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1818. if (err)
  1819. goto ex_abort;
  1820. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1821. if (err)
  1822. goto ex_put;
  1823. atomic_dec(&eq->mtt->ref_count);
  1824. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1825. res_end_move(dev, slave, RES_EQ, res_id);
  1826. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1827. return 0;
  1828. ex_put:
  1829. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1830. ex_abort:
  1831. res_abort_move(dev, slave, RES_EQ, res_id);
  1832. return err;
  1833. }
  1834. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1835. {
  1836. struct mlx4_priv *priv = mlx4_priv(dev);
  1837. struct mlx4_slave_event_eq_info *event_eq;
  1838. struct mlx4_cmd_mailbox *mailbox;
  1839. u32 in_modifier = 0;
  1840. int err;
  1841. int res_id;
  1842. struct res_eq *req;
  1843. if (!priv->mfunc.master.slave_state)
  1844. return -EINVAL;
  1845. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1846. /* Create the event only if the slave is registered */
  1847. if (event_eq->eqn < 0)
  1848. return 0;
  1849. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1850. res_id = (slave << 8) | event_eq->eqn;
  1851. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1852. if (err)
  1853. goto unlock;
  1854. if (req->com.from_state != RES_EQ_HW) {
  1855. err = -EINVAL;
  1856. goto put;
  1857. }
  1858. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1859. if (IS_ERR(mailbox)) {
  1860. err = PTR_ERR(mailbox);
  1861. goto put;
  1862. }
  1863. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1864. ++event_eq->token;
  1865. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1866. }
  1867. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1868. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1869. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1870. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1871. MLX4_CMD_NATIVE);
  1872. put_res(dev, slave, res_id, RES_EQ);
  1873. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1874. mlx4_free_cmd_mailbox(dev, mailbox);
  1875. return err;
  1876. put:
  1877. put_res(dev, slave, res_id, RES_EQ);
  1878. unlock:
  1879. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1880. return err;
  1881. }
  1882. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1883. struct mlx4_vhcr *vhcr,
  1884. struct mlx4_cmd_mailbox *inbox,
  1885. struct mlx4_cmd_mailbox *outbox,
  1886. struct mlx4_cmd_info *cmd)
  1887. {
  1888. int eqn = vhcr->in_modifier;
  1889. int res_id = eqn | (slave << 8);
  1890. struct res_eq *eq;
  1891. int err;
  1892. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1893. if (err)
  1894. return err;
  1895. if (eq->com.from_state != RES_EQ_HW) {
  1896. err = -EINVAL;
  1897. goto ex_put;
  1898. }
  1899. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1900. ex_put:
  1901. put_res(dev, slave, res_id, RES_EQ);
  1902. return err;
  1903. }
  1904. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1905. struct mlx4_vhcr *vhcr,
  1906. struct mlx4_cmd_mailbox *inbox,
  1907. struct mlx4_cmd_mailbox *outbox,
  1908. struct mlx4_cmd_info *cmd)
  1909. {
  1910. int err;
  1911. int cqn = vhcr->in_modifier;
  1912. struct mlx4_cq_context *cqc = inbox->buf;
  1913. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1914. struct res_cq *cq;
  1915. struct res_mtt *mtt;
  1916. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1917. if (err)
  1918. return err;
  1919. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1920. if (err)
  1921. goto out_move;
  1922. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1923. if (err)
  1924. goto out_put;
  1925. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1926. if (err)
  1927. goto out_put;
  1928. atomic_inc(&mtt->ref_count);
  1929. cq->mtt = mtt;
  1930. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1931. res_end_move(dev, slave, RES_CQ, cqn);
  1932. return 0;
  1933. out_put:
  1934. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1935. out_move:
  1936. res_abort_move(dev, slave, RES_CQ, cqn);
  1937. return err;
  1938. }
  1939. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1940. struct mlx4_vhcr *vhcr,
  1941. struct mlx4_cmd_mailbox *inbox,
  1942. struct mlx4_cmd_mailbox *outbox,
  1943. struct mlx4_cmd_info *cmd)
  1944. {
  1945. int err;
  1946. int cqn = vhcr->in_modifier;
  1947. struct res_cq *cq;
  1948. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1949. if (err)
  1950. return err;
  1951. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1952. if (err)
  1953. goto out_move;
  1954. atomic_dec(&cq->mtt->ref_count);
  1955. res_end_move(dev, slave, RES_CQ, cqn);
  1956. return 0;
  1957. out_move:
  1958. res_abort_move(dev, slave, RES_CQ, cqn);
  1959. return err;
  1960. }
  1961. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1962. struct mlx4_vhcr *vhcr,
  1963. struct mlx4_cmd_mailbox *inbox,
  1964. struct mlx4_cmd_mailbox *outbox,
  1965. struct mlx4_cmd_info *cmd)
  1966. {
  1967. int cqn = vhcr->in_modifier;
  1968. struct res_cq *cq;
  1969. int err;
  1970. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1971. if (err)
  1972. return err;
  1973. if (cq->com.from_state != RES_CQ_HW)
  1974. goto ex_put;
  1975. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1976. ex_put:
  1977. put_res(dev, slave, cqn, RES_CQ);
  1978. return err;
  1979. }
  1980. static int handle_resize(struct mlx4_dev *dev, int slave,
  1981. struct mlx4_vhcr *vhcr,
  1982. struct mlx4_cmd_mailbox *inbox,
  1983. struct mlx4_cmd_mailbox *outbox,
  1984. struct mlx4_cmd_info *cmd,
  1985. struct res_cq *cq)
  1986. {
  1987. int err;
  1988. struct res_mtt *orig_mtt;
  1989. struct res_mtt *mtt;
  1990. struct mlx4_cq_context *cqc = inbox->buf;
  1991. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1992. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1993. if (err)
  1994. return err;
  1995. if (orig_mtt != cq->mtt) {
  1996. err = -EINVAL;
  1997. goto ex_put;
  1998. }
  1999. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2000. if (err)
  2001. goto ex_put;
  2002. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2003. if (err)
  2004. goto ex_put1;
  2005. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2006. if (err)
  2007. goto ex_put1;
  2008. atomic_dec(&orig_mtt->ref_count);
  2009. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2010. atomic_inc(&mtt->ref_count);
  2011. cq->mtt = mtt;
  2012. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2013. return 0;
  2014. ex_put1:
  2015. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2016. ex_put:
  2017. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2018. return err;
  2019. }
  2020. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2021. struct mlx4_vhcr *vhcr,
  2022. struct mlx4_cmd_mailbox *inbox,
  2023. struct mlx4_cmd_mailbox *outbox,
  2024. struct mlx4_cmd_info *cmd)
  2025. {
  2026. int cqn = vhcr->in_modifier;
  2027. struct res_cq *cq;
  2028. int err;
  2029. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2030. if (err)
  2031. return err;
  2032. if (cq->com.from_state != RES_CQ_HW)
  2033. goto ex_put;
  2034. if (vhcr->op_modifier == 0) {
  2035. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2036. goto ex_put;
  2037. }
  2038. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2039. ex_put:
  2040. put_res(dev, slave, cqn, RES_CQ);
  2041. return err;
  2042. }
  2043. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2044. {
  2045. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2046. int log_rq_stride = srqc->logstride & 7;
  2047. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2048. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2049. return 1;
  2050. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2051. }
  2052. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2053. struct mlx4_vhcr *vhcr,
  2054. struct mlx4_cmd_mailbox *inbox,
  2055. struct mlx4_cmd_mailbox *outbox,
  2056. struct mlx4_cmd_info *cmd)
  2057. {
  2058. int err;
  2059. int srqn = vhcr->in_modifier;
  2060. struct res_mtt *mtt;
  2061. struct res_srq *srq;
  2062. struct mlx4_srq_context *srqc = inbox->buf;
  2063. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2064. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2065. return -EINVAL;
  2066. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2067. if (err)
  2068. return err;
  2069. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2070. if (err)
  2071. goto ex_abort;
  2072. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2073. mtt);
  2074. if (err)
  2075. goto ex_put_mtt;
  2076. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2077. if (err)
  2078. goto ex_put_mtt;
  2079. atomic_inc(&mtt->ref_count);
  2080. srq->mtt = mtt;
  2081. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2082. res_end_move(dev, slave, RES_SRQ, srqn);
  2083. return 0;
  2084. ex_put_mtt:
  2085. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2086. ex_abort:
  2087. res_abort_move(dev, slave, RES_SRQ, srqn);
  2088. return err;
  2089. }
  2090. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2091. struct mlx4_vhcr *vhcr,
  2092. struct mlx4_cmd_mailbox *inbox,
  2093. struct mlx4_cmd_mailbox *outbox,
  2094. struct mlx4_cmd_info *cmd)
  2095. {
  2096. int err;
  2097. int srqn = vhcr->in_modifier;
  2098. struct res_srq *srq;
  2099. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2100. if (err)
  2101. return err;
  2102. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2103. if (err)
  2104. goto ex_abort;
  2105. atomic_dec(&srq->mtt->ref_count);
  2106. if (srq->cq)
  2107. atomic_dec(&srq->cq->ref_count);
  2108. res_end_move(dev, slave, RES_SRQ, srqn);
  2109. return 0;
  2110. ex_abort:
  2111. res_abort_move(dev, slave, RES_SRQ, srqn);
  2112. return err;
  2113. }
  2114. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2115. struct mlx4_vhcr *vhcr,
  2116. struct mlx4_cmd_mailbox *inbox,
  2117. struct mlx4_cmd_mailbox *outbox,
  2118. struct mlx4_cmd_info *cmd)
  2119. {
  2120. int err;
  2121. int srqn = vhcr->in_modifier;
  2122. struct res_srq *srq;
  2123. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2124. if (err)
  2125. return err;
  2126. if (srq->com.from_state != RES_SRQ_HW) {
  2127. err = -EBUSY;
  2128. goto out;
  2129. }
  2130. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2131. out:
  2132. put_res(dev, slave, srqn, RES_SRQ);
  2133. return err;
  2134. }
  2135. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2136. struct mlx4_vhcr *vhcr,
  2137. struct mlx4_cmd_mailbox *inbox,
  2138. struct mlx4_cmd_mailbox *outbox,
  2139. struct mlx4_cmd_info *cmd)
  2140. {
  2141. int err;
  2142. int srqn = vhcr->in_modifier;
  2143. struct res_srq *srq;
  2144. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2145. if (err)
  2146. return err;
  2147. if (srq->com.from_state != RES_SRQ_HW) {
  2148. err = -EBUSY;
  2149. goto out;
  2150. }
  2151. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2152. out:
  2153. put_res(dev, slave, srqn, RES_SRQ);
  2154. return err;
  2155. }
  2156. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2157. struct mlx4_vhcr *vhcr,
  2158. struct mlx4_cmd_mailbox *inbox,
  2159. struct mlx4_cmd_mailbox *outbox,
  2160. struct mlx4_cmd_info *cmd)
  2161. {
  2162. int err;
  2163. int qpn = vhcr->in_modifier & 0x7fffff;
  2164. struct res_qp *qp;
  2165. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2166. if (err)
  2167. return err;
  2168. if (qp->com.from_state != RES_QP_HW) {
  2169. err = -EBUSY;
  2170. goto out;
  2171. }
  2172. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2173. out:
  2174. put_res(dev, slave, qpn, RES_QP);
  2175. return err;
  2176. }
  2177. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2178. struct mlx4_vhcr *vhcr,
  2179. struct mlx4_cmd_mailbox *inbox,
  2180. struct mlx4_cmd_mailbox *outbox,
  2181. struct mlx4_cmd_info *cmd)
  2182. {
  2183. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2184. update_ud_gid(dev, qpc, (u8)slave);
  2185. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2186. }
  2187. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2188. struct mlx4_vhcr *vhcr,
  2189. struct mlx4_cmd_mailbox *inbox,
  2190. struct mlx4_cmd_mailbox *outbox,
  2191. struct mlx4_cmd_info *cmd)
  2192. {
  2193. int err;
  2194. int qpn = vhcr->in_modifier & 0x7fffff;
  2195. struct res_qp *qp;
  2196. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2197. if (err)
  2198. return err;
  2199. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2200. if (err)
  2201. goto ex_abort;
  2202. atomic_dec(&qp->mtt->ref_count);
  2203. atomic_dec(&qp->rcq->ref_count);
  2204. atomic_dec(&qp->scq->ref_count);
  2205. if (qp->srq)
  2206. atomic_dec(&qp->srq->ref_count);
  2207. res_end_move(dev, slave, RES_QP, qpn);
  2208. return 0;
  2209. ex_abort:
  2210. res_abort_move(dev, slave, RES_QP, qpn);
  2211. return err;
  2212. }
  2213. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2214. struct res_qp *rqp, u8 *gid)
  2215. {
  2216. struct res_gid *res;
  2217. list_for_each_entry(res, &rqp->mcg_list, list) {
  2218. if (!memcmp(res->gid, gid, 16))
  2219. return res;
  2220. }
  2221. return NULL;
  2222. }
  2223. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2224. u8 *gid, enum mlx4_protocol prot,
  2225. enum mlx4_steer_type steer)
  2226. {
  2227. struct res_gid *res;
  2228. int err;
  2229. res = kzalloc(sizeof *res, GFP_KERNEL);
  2230. if (!res)
  2231. return -ENOMEM;
  2232. spin_lock_irq(&rqp->mcg_spl);
  2233. if (find_gid(dev, slave, rqp, gid)) {
  2234. kfree(res);
  2235. err = -EEXIST;
  2236. } else {
  2237. memcpy(res->gid, gid, 16);
  2238. res->prot = prot;
  2239. res->steer = steer;
  2240. list_add_tail(&res->list, &rqp->mcg_list);
  2241. err = 0;
  2242. }
  2243. spin_unlock_irq(&rqp->mcg_spl);
  2244. return err;
  2245. }
  2246. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2247. u8 *gid, enum mlx4_protocol prot,
  2248. enum mlx4_steer_type steer)
  2249. {
  2250. struct res_gid *res;
  2251. int err;
  2252. spin_lock_irq(&rqp->mcg_spl);
  2253. res = find_gid(dev, slave, rqp, gid);
  2254. if (!res || res->prot != prot || res->steer != steer)
  2255. err = -EINVAL;
  2256. else {
  2257. list_del(&res->list);
  2258. kfree(res);
  2259. err = 0;
  2260. }
  2261. spin_unlock_irq(&rqp->mcg_spl);
  2262. return err;
  2263. }
  2264. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2265. struct mlx4_vhcr *vhcr,
  2266. struct mlx4_cmd_mailbox *inbox,
  2267. struct mlx4_cmd_mailbox *outbox,
  2268. struct mlx4_cmd_info *cmd)
  2269. {
  2270. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2271. u8 *gid = inbox->buf;
  2272. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2273. int err;
  2274. int qpn;
  2275. struct res_qp *rqp;
  2276. int attach = vhcr->op_modifier;
  2277. int block_loopback = vhcr->in_modifier >> 31;
  2278. u8 steer_type_mask = 2;
  2279. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2280. qpn = vhcr->in_modifier & 0xffffff;
  2281. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2282. if (err)
  2283. return err;
  2284. qp.qpn = qpn;
  2285. if (attach) {
  2286. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2287. if (err)
  2288. goto ex_put;
  2289. err = mlx4_qp_attach_common(dev, &qp, gid,
  2290. block_loopback, prot, type);
  2291. if (err)
  2292. goto ex_rem;
  2293. } else {
  2294. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2295. if (err)
  2296. goto ex_put;
  2297. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2298. }
  2299. put_res(dev, slave, qpn, RES_QP);
  2300. return 0;
  2301. ex_rem:
  2302. /* ignore error return below, already in error */
  2303. (void) rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2304. ex_put:
  2305. put_res(dev, slave, qpn, RES_QP);
  2306. return err;
  2307. }
  2308. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2309. struct mlx4_vhcr *vhcr,
  2310. struct mlx4_cmd_mailbox *inbox,
  2311. struct mlx4_cmd_mailbox *outbox,
  2312. struct mlx4_cmd_info *cmd)
  2313. {
  2314. int err;
  2315. if (dev->caps.steering_mode !=
  2316. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2317. return -EOPNOTSUPP;
  2318. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2319. vhcr->in_modifier, 0,
  2320. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2321. MLX4_CMD_NATIVE);
  2322. if (err)
  2323. return err;
  2324. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, 0);
  2325. if (err) {
  2326. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  2327. /* detach rule*/
  2328. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  2329. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2330. MLX4_CMD_NATIVE);
  2331. }
  2332. return err;
  2333. }
  2334. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2335. struct mlx4_vhcr *vhcr,
  2336. struct mlx4_cmd_mailbox *inbox,
  2337. struct mlx4_cmd_mailbox *outbox,
  2338. struct mlx4_cmd_info *cmd)
  2339. {
  2340. int err;
  2341. if (dev->caps.steering_mode !=
  2342. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2343. return -EOPNOTSUPP;
  2344. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  2345. if (err) {
  2346. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  2347. return err;
  2348. }
  2349. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2350. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2351. MLX4_CMD_NATIVE);
  2352. return err;
  2353. }
  2354. enum {
  2355. BUSY_MAX_RETRIES = 10
  2356. };
  2357. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2358. struct mlx4_vhcr *vhcr,
  2359. struct mlx4_cmd_mailbox *inbox,
  2360. struct mlx4_cmd_mailbox *outbox,
  2361. struct mlx4_cmd_info *cmd)
  2362. {
  2363. int err;
  2364. int index = vhcr->in_modifier & 0xffff;
  2365. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2366. if (err)
  2367. return err;
  2368. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2369. put_res(dev, slave, index, RES_COUNTER);
  2370. return err;
  2371. }
  2372. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2373. {
  2374. struct res_gid *rgid;
  2375. struct res_gid *tmp;
  2376. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2377. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2378. qp.qpn = rqp->local_qpn;
  2379. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2380. rgid->steer);
  2381. list_del(&rgid->list);
  2382. kfree(rgid);
  2383. }
  2384. }
  2385. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2386. enum mlx4_resource type, int print)
  2387. {
  2388. struct mlx4_priv *priv = mlx4_priv(dev);
  2389. struct mlx4_resource_tracker *tracker =
  2390. &priv->mfunc.master.res_tracker;
  2391. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2392. struct res_common *r;
  2393. struct res_common *tmp;
  2394. int busy;
  2395. busy = 0;
  2396. spin_lock_irq(mlx4_tlock(dev));
  2397. list_for_each_entry_safe(r, tmp, rlist, list) {
  2398. if (r->owner == slave) {
  2399. if (!r->removing) {
  2400. if (r->state == RES_ANY_BUSY) {
  2401. if (print)
  2402. mlx4_dbg(dev,
  2403. "%s id 0x%llx is busy\n",
  2404. ResourceType(type),
  2405. r->res_id);
  2406. ++busy;
  2407. } else {
  2408. r->from_state = r->state;
  2409. r->state = RES_ANY_BUSY;
  2410. r->removing = 1;
  2411. }
  2412. }
  2413. }
  2414. }
  2415. spin_unlock_irq(mlx4_tlock(dev));
  2416. return busy;
  2417. }
  2418. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2419. enum mlx4_resource type)
  2420. {
  2421. unsigned long begin;
  2422. int busy;
  2423. begin = jiffies;
  2424. do {
  2425. busy = _move_all_busy(dev, slave, type, 0);
  2426. if (time_after(jiffies, begin + 5 * HZ))
  2427. break;
  2428. if (busy)
  2429. cond_resched();
  2430. } while (busy);
  2431. if (busy)
  2432. busy = _move_all_busy(dev, slave, type, 1);
  2433. return busy;
  2434. }
  2435. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2436. {
  2437. struct mlx4_priv *priv = mlx4_priv(dev);
  2438. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2439. struct list_head *qp_list =
  2440. &tracker->slave_list[slave].res_list[RES_QP];
  2441. struct res_qp *qp;
  2442. struct res_qp *tmp;
  2443. int state;
  2444. u64 in_param;
  2445. int qpn;
  2446. int err;
  2447. err = move_all_busy(dev, slave, RES_QP);
  2448. if (err)
  2449. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2450. "for slave %d\n", slave);
  2451. spin_lock_irq(mlx4_tlock(dev));
  2452. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2453. spin_unlock_irq(mlx4_tlock(dev));
  2454. if (qp->com.owner == slave) {
  2455. qpn = qp->com.res_id;
  2456. detach_qp(dev, slave, qp);
  2457. state = qp->com.from_state;
  2458. while (state != 0) {
  2459. switch (state) {
  2460. case RES_QP_RESERVED:
  2461. spin_lock_irq(mlx4_tlock(dev));
  2462. rb_erase(&qp->com.node,
  2463. &tracker->res_tree[RES_QP]);
  2464. list_del(&qp->com.list);
  2465. spin_unlock_irq(mlx4_tlock(dev));
  2466. kfree(qp);
  2467. state = 0;
  2468. break;
  2469. case RES_QP_MAPPED:
  2470. if (!valid_reserved(dev, slave, qpn))
  2471. __mlx4_qp_free_icm(dev, qpn);
  2472. state = RES_QP_RESERVED;
  2473. break;
  2474. case RES_QP_HW:
  2475. in_param = slave;
  2476. err = mlx4_cmd(dev, in_param,
  2477. qp->local_qpn, 2,
  2478. MLX4_CMD_2RST_QP,
  2479. MLX4_CMD_TIME_CLASS_A,
  2480. MLX4_CMD_NATIVE);
  2481. if (err)
  2482. mlx4_dbg(dev, "rem_slave_qps: failed"
  2483. " to move slave %d qpn %d to"
  2484. " reset\n", slave,
  2485. qp->local_qpn);
  2486. atomic_dec(&qp->rcq->ref_count);
  2487. atomic_dec(&qp->scq->ref_count);
  2488. atomic_dec(&qp->mtt->ref_count);
  2489. if (qp->srq)
  2490. atomic_dec(&qp->srq->ref_count);
  2491. state = RES_QP_MAPPED;
  2492. break;
  2493. default:
  2494. state = 0;
  2495. }
  2496. }
  2497. }
  2498. spin_lock_irq(mlx4_tlock(dev));
  2499. }
  2500. spin_unlock_irq(mlx4_tlock(dev));
  2501. }
  2502. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2503. {
  2504. struct mlx4_priv *priv = mlx4_priv(dev);
  2505. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2506. struct list_head *srq_list =
  2507. &tracker->slave_list[slave].res_list[RES_SRQ];
  2508. struct res_srq *srq;
  2509. struct res_srq *tmp;
  2510. int state;
  2511. u64 in_param;
  2512. LIST_HEAD(tlist);
  2513. int srqn;
  2514. int err;
  2515. err = move_all_busy(dev, slave, RES_SRQ);
  2516. if (err)
  2517. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2518. "busy for slave %d\n", slave);
  2519. spin_lock_irq(mlx4_tlock(dev));
  2520. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2521. spin_unlock_irq(mlx4_tlock(dev));
  2522. if (srq->com.owner == slave) {
  2523. srqn = srq->com.res_id;
  2524. state = srq->com.from_state;
  2525. while (state != 0) {
  2526. switch (state) {
  2527. case RES_SRQ_ALLOCATED:
  2528. __mlx4_srq_free_icm(dev, srqn);
  2529. spin_lock_irq(mlx4_tlock(dev));
  2530. rb_erase(&srq->com.node,
  2531. &tracker->res_tree[RES_SRQ]);
  2532. list_del(&srq->com.list);
  2533. spin_unlock_irq(mlx4_tlock(dev));
  2534. kfree(srq);
  2535. state = 0;
  2536. break;
  2537. case RES_SRQ_HW:
  2538. in_param = slave;
  2539. err = mlx4_cmd(dev, in_param, srqn, 1,
  2540. MLX4_CMD_HW2SW_SRQ,
  2541. MLX4_CMD_TIME_CLASS_A,
  2542. MLX4_CMD_NATIVE);
  2543. if (err)
  2544. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2545. " to move slave %d srq %d to"
  2546. " SW ownership\n",
  2547. slave, srqn);
  2548. atomic_dec(&srq->mtt->ref_count);
  2549. if (srq->cq)
  2550. atomic_dec(&srq->cq->ref_count);
  2551. state = RES_SRQ_ALLOCATED;
  2552. break;
  2553. default:
  2554. state = 0;
  2555. }
  2556. }
  2557. }
  2558. spin_lock_irq(mlx4_tlock(dev));
  2559. }
  2560. spin_unlock_irq(mlx4_tlock(dev));
  2561. }
  2562. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2563. {
  2564. struct mlx4_priv *priv = mlx4_priv(dev);
  2565. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2566. struct list_head *cq_list =
  2567. &tracker->slave_list[slave].res_list[RES_CQ];
  2568. struct res_cq *cq;
  2569. struct res_cq *tmp;
  2570. int state;
  2571. u64 in_param;
  2572. LIST_HEAD(tlist);
  2573. int cqn;
  2574. int err;
  2575. err = move_all_busy(dev, slave, RES_CQ);
  2576. if (err)
  2577. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2578. "busy for slave %d\n", slave);
  2579. spin_lock_irq(mlx4_tlock(dev));
  2580. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2581. spin_unlock_irq(mlx4_tlock(dev));
  2582. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2583. cqn = cq->com.res_id;
  2584. state = cq->com.from_state;
  2585. while (state != 0) {
  2586. switch (state) {
  2587. case RES_CQ_ALLOCATED:
  2588. __mlx4_cq_free_icm(dev, cqn);
  2589. spin_lock_irq(mlx4_tlock(dev));
  2590. rb_erase(&cq->com.node,
  2591. &tracker->res_tree[RES_CQ]);
  2592. list_del(&cq->com.list);
  2593. spin_unlock_irq(mlx4_tlock(dev));
  2594. kfree(cq);
  2595. state = 0;
  2596. break;
  2597. case RES_CQ_HW:
  2598. in_param = slave;
  2599. err = mlx4_cmd(dev, in_param, cqn, 1,
  2600. MLX4_CMD_HW2SW_CQ,
  2601. MLX4_CMD_TIME_CLASS_A,
  2602. MLX4_CMD_NATIVE);
  2603. if (err)
  2604. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2605. " to move slave %d cq %d to"
  2606. " SW ownership\n",
  2607. slave, cqn);
  2608. atomic_dec(&cq->mtt->ref_count);
  2609. state = RES_CQ_ALLOCATED;
  2610. break;
  2611. default:
  2612. state = 0;
  2613. }
  2614. }
  2615. }
  2616. spin_lock_irq(mlx4_tlock(dev));
  2617. }
  2618. spin_unlock_irq(mlx4_tlock(dev));
  2619. }
  2620. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2621. {
  2622. struct mlx4_priv *priv = mlx4_priv(dev);
  2623. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2624. struct list_head *mpt_list =
  2625. &tracker->slave_list[slave].res_list[RES_MPT];
  2626. struct res_mpt *mpt;
  2627. struct res_mpt *tmp;
  2628. int state;
  2629. u64 in_param;
  2630. LIST_HEAD(tlist);
  2631. int mptn;
  2632. int err;
  2633. err = move_all_busy(dev, slave, RES_MPT);
  2634. if (err)
  2635. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2636. "busy for slave %d\n", slave);
  2637. spin_lock_irq(mlx4_tlock(dev));
  2638. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2639. spin_unlock_irq(mlx4_tlock(dev));
  2640. if (mpt->com.owner == slave) {
  2641. mptn = mpt->com.res_id;
  2642. state = mpt->com.from_state;
  2643. while (state != 0) {
  2644. switch (state) {
  2645. case RES_MPT_RESERVED:
  2646. __mlx4_mr_release(dev, mpt->key);
  2647. spin_lock_irq(mlx4_tlock(dev));
  2648. rb_erase(&mpt->com.node,
  2649. &tracker->res_tree[RES_MPT]);
  2650. list_del(&mpt->com.list);
  2651. spin_unlock_irq(mlx4_tlock(dev));
  2652. kfree(mpt);
  2653. state = 0;
  2654. break;
  2655. case RES_MPT_MAPPED:
  2656. __mlx4_mr_free_icm(dev, mpt->key);
  2657. state = RES_MPT_RESERVED;
  2658. break;
  2659. case RES_MPT_HW:
  2660. in_param = slave;
  2661. err = mlx4_cmd(dev, in_param, mptn, 0,
  2662. MLX4_CMD_HW2SW_MPT,
  2663. MLX4_CMD_TIME_CLASS_A,
  2664. MLX4_CMD_NATIVE);
  2665. if (err)
  2666. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2667. " to move slave %d mpt %d to"
  2668. " SW ownership\n",
  2669. slave, mptn);
  2670. if (mpt->mtt)
  2671. atomic_dec(&mpt->mtt->ref_count);
  2672. state = RES_MPT_MAPPED;
  2673. break;
  2674. default:
  2675. state = 0;
  2676. }
  2677. }
  2678. }
  2679. spin_lock_irq(mlx4_tlock(dev));
  2680. }
  2681. spin_unlock_irq(mlx4_tlock(dev));
  2682. }
  2683. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2684. {
  2685. struct mlx4_priv *priv = mlx4_priv(dev);
  2686. struct mlx4_resource_tracker *tracker =
  2687. &priv->mfunc.master.res_tracker;
  2688. struct list_head *mtt_list =
  2689. &tracker->slave_list[slave].res_list[RES_MTT];
  2690. struct res_mtt *mtt;
  2691. struct res_mtt *tmp;
  2692. int state;
  2693. LIST_HEAD(tlist);
  2694. int base;
  2695. int err;
  2696. err = move_all_busy(dev, slave, RES_MTT);
  2697. if (err)
  2698. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2699. "busy for slave %d\n", slave);
  2700. spin_lock_irq(mlx4_tlock(dev));
  2701. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2702. spin_unlock_irq(mlx4_tlock(dev));
  2703. if (mtt->com.owner == slave) {
  2704. base = mtt->com.res_id;
  2705. state = mtt->com.from_state;
  2706. while (state != 0) {
  2707. switch (state) {
  2708. case RES_MTT_ALLOCATED:
  2709. __mlx4_free_mtt_range(dev, base,
  2710. mtt->order);
  2711. spin_lock_irq(mlx4_tlock(dev));
  2712. rb_erase(&mtt->com.node,
  2713. &tracker->res_tree[RES_MTT]);
  2714. list_del(&mtt->com.list);
  2715. spin_unlock_irq(mlx4_tlock(dev));
  2716. kfree(mtt);
  2717. state = 0;
  2718. break;
  2719. default:
  2720. state = 0;
  2721. }
  2722. }
  2723. }
  2724. spin_lock_irq(mlx4_tlock(dev));
  2725. }
  2726. spin_unlock_irq(mlx4_tlock(dev));
  2727. }
  2728. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  2729. {
  2730. struct mlx4_priv *priv = mlx4_priv(dev);
  2731. struct mlx4_resource_tracker *tracker =
  2732. &priv->mfunc.master.res_tracker;
  2733. struct list_head *fs_rule_list =
  2734. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  2735. struct res_fs_rule *fs_rule;
  2736. struct res_fs_rule *tmp;
  2737. int state;
  2738. u64 base;
  2739. int err;
  2740. err = move_all_busy(dev, slave, RES_FS_RULE);
  2741. if (err)
  2742. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  2743. slave);
  2744. spin_lock_irq(mlx4_tlock(dev));
  2745. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  2746. spin_unlock_irq(mlx4_tlock(dev));
  2747. if (fs_rule->com.owner == slave) {
  2748. base = fs_rule->com.res_id;
  2749. state = fs_rule->com.from_state;
  2750. while (state != 0) {
  2751. switch (state) {
  2752. case RES_FS_RULE_ALLOCATED:
  2753. /* detach rule */
  2754. err = mlx4_cmd(dev, base, 0, 0,
  2755. MLX4_QP_FLOW_STEERING_DETACH,
  2756. MLX4_CMD_TIME_CLASS_A,
  2757. MLX4_CMD_NATIVE);
  2758. spin_lock_irq(mlx4_tlock(dev));
  2759. rb_erase(&fs_rule->com.node,
  2760. &tracker->res_tree[RES_FS_RULE]);
  2761. list_del(&fs_rule->com.list);
  2762. spin_unlock_irq(mlx4_tlock(dev));
  2763. kfree(fs_rule);
  2764. state = 0;
  2765. break;
  2766. default:
  2767. state = 0;
  2768. }
  2769. }
  2770. }
  2771. spin_lock_irq(mlx4_tlock(dev));
  2772. }
  2773. spin_unlock_irq(mlx4_tlock(dev));
  2774. }
  2775. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2776. {
  2777. struct mlx4_priv *priv = mlx4_priv(dev);
  2778. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2779. struct list_head *eq_list =
  2780. &tracker->slave_list[slave].res_list[RES_EQ];
  2781. struct res_eq *eq;
  2782. struct res_eq *tmp;
  2783. int err;
  2784. int state;
  2785. LIST_HEAD(tlist);
  2786. int eqn;
  2787. struct mlx4_cmd_mailbox *mailbox;
  2788. err = move_all_busy(dev, slave, RES_EQ);
  2789. if (err)
  2790. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2791. "busy for slave %d\n", slave);
  2792. spin_lock_irq(mlx4_tlock(dev));
  2793. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2794. spin_unlock_irq(mlx4_tlock(dev));
  2795. if (eq->com.owner == slave) {
  2796. eqn = eq->com.res_id;
  2797. state = eq->com.from_state;
  2798. while (state != 0) {
  2799. switch (state) {
  2800. case RES_EQ_RESERVED:
  2801. spin_lock_irq(mlx4_tlock(dev));
  2802. rb_erase(&eq->com.node,
  2803. &tracker->res_tree[RES_EQ]);
  2804. list_del(&eq->com.list);
  2805. spin_unlock_irq(mlx4_tlock(dev));
  2806. kfree(eq);
  2807. state = 0;
  2808. break;
  2809. case RES_EQ_HW:
  2810. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2811. if (IS_ERR(mailbox)) {
  2812. cond_resched();
  2813. continue;
  2814. }
  2815. err = mlx4_cmd_box(dev, slave, 0,
  2816. eqn & 0xff, 0,
  2817. MLX4_CMD_HW2SW_EQ,
  2818. MLX4_CMD_TIME_CLASS_A,
  2819. MLX4_CMD_NATIVE);
  2820. if (err)
  2821. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2822. " to move slave %d eqs %d to"
  2823. " SW ownership\n", slave, eqn);
  2824. mlx4_free_cmd_mailbox(dev, mailbox);
  2825. atomic_dec(&eq->mtt->ref_count);
  2826. state = RES_EQ_RESERVED;
  2827. break;
  2828. default:
  2829. state = 0;
  2830. }
  2831. }
  2832. }
  2833. spin_lock_irq(mlx4_tlock(dev));
  2834. }
  2835. spin_unlock_irq(mlx4_tlock(dev));
  2836. }
  2837. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  2838. {
  2839. struct mlx4_priv *priv = mlx4_priv(dev);
  2840. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2841. struct list_head *counter_list =
  2842. &tracker->slave_list[slave].res_list[RES_COUNTER];
  2843. struct res_counter *counter;
  2844. struct res_counter *tmp;
  2845. int err;
  2846. int index;
  2847. err = move_all_busy(dev, slave, RES_COUNTER);
  2848. if (err)
  2849. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  2850. "busy for slave %d\n", slave);
  2851. spin_lock_irq(mlx4_tlock(dev));
  2852. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  2853. if (counter->com.owner == slave) {
  2854. index = counter->com.res_id;
  2855. rb_erase(&counter->com.node,
  2856. &tracker->res_tree[RES_COUNTER]);
  2857. list_del(&counter->com.list);
  2858. kfree(counter);
  2859. __mlx4_counter_free(dev, index);
  2860. }
  2861. }
  2862. spin_unlock_irq(mlx4_tlock(dev));
  2863. }
  2864. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  2865. {
  2866. struct mlx4_priv *priv = mlx4_priv(dev);
  2867. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2868. struct list_head *xrcdn_list =
  2869. &tracker->slave_list[slave].res_list[RES_XRCD];
  2870. struct res_xrcdn *xrcd;
  2871. struct res_xrcdn *tmp;
  2872. int err;
  2873. int xrcdn;
  2874. err = move_all_busy(dev, slave, RES_XRCD);
  2875. if (err)
  2876. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  2877. "busy for slave %d\n", slave);
  2878. spin_lock_irq(mlx4_tlock(dev));
  2879. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  2880. if (xrcd->com.owner == slave) {
  2881. xrcdn = xrcd->com.res_id;
  2882. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  2883. list_del(&xrcd->com.list);
  2884. kfree(xrcd);
  2885. __mlx4_xrcd_free(dev, xrcdn);
  2886. }
  2887. }
  2888. spin_unlock_irq(mlx4_tlock(dev));
  2889. }
  2890. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2891. {
  2892. struct mlx4_priv *priv = mlx4_priv(dev);
  2893. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2894. /*VLAN*/
  2895. rem_slave_macs(dev, slave);
  2896. rem_slave_qps(dev, slave);
  2897. rem_slave_srqs(dev, slave);
  2898. rem_slave_cqs(dev, slave);
  2899. rem_slave_mrs(dev, slave);
  2900. rem_slave_eqs(dev, slave);
  2901. rem_slave_mtts(dev, slave);
  2902. rem_slave_counters(dev, slave);
  2903. rem_slave_xrcdns(dev, slave);
  2904. rem_slave_fs_rule(dev, slave);
  2905. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2906. }