cnic.c 145 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  47. #include "cnic.h"
  48. #include "cnic_defs.h"
  49. #define DRV_MODULE_NAME "cnic"
  50. static char version[] __devinitdata =
  51. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  52. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  53. "Chen (zongxi@broadcom.com");
  54. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(CNIC_MODULE_VERSION);
  57. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  58. static LIST_HEAD(cnic_dev_list);
  59. static LIST_HEAD(cnic_udev_list);
  60. static DEFINE_RWLOCK(cnic_dev_lock);
  61. static DEFINE_MUTEX(cnic_lock);
  62. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  63. /* helper function, assuming cnic_lock is held */
  64. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  65. {
  66. return rcu_dereference_protected(cnic_ulp_tbl[type],
  67. lockdep_is_held(&cnic_lock));
  68. }
  69. static int cnic_service_bnx2(void *, void *);
  70. static int cnic_service_bnx2x(void *, void *);
  71. static int cnic_ctl(void *, struct cnic_ctl_info *);
  72. static struct cnic_ops cnic_bnx2_ops = {
  73. .cnic_owner = THIS_MODULE,
  74. .cnic_handler = cnic_service_bnx2,
  75. .cnic_ctl = cnic_ctl,
  76. };
  77. static struct cnic_ops cnic_bnx2x_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2x,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct workqueue_struct *cnic_wq;
  83. static void cnic_shutdown_rings(struct cnic_dev *);
  84. static void cnic_init_rings(struct cnic_dev *);
  85. static int cnic_cm_set_pg(struct cnic_sock *);
  86. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  87. {
  88. struct cnic_uio_dev *udev = uinfo->priv;
  89. struct cnic_dev *dev;
  90. if (!capable(CAP_NET_ADMIN))
  91. return -EPERM;
  92. if (udev->uio_dev != -1)
  93. return -EBUSY;
  94. rtnl_lock();
  95. dev = udev->dev;
  96. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  97. rtnl_unlock();
  98. return -ENODEV;
  99. }
  100. udev->uio_dev = iminor(inode);
  101. cnic_shutdown_rings(dev);
  102. cnic_init_rings(dev);
  103. rtnl_unlock();
  104. return 0;
  105. }
  106. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  107. {
  108. struct cnic_uio_dev *udev = uinfo->priv;
  109. udev->uio_dev = -1;
  110. return 0;
  111. }
  112. static inline void cnic_hold(struct cnic_dev *dev)
  113. {
  114. atomic_inc(&dev->ref_count);
  115. }
  116. static inline void cnic_put(struct cnic_dev *dev)
  117. {
  118. atomic_dec(&dev->ref_count);
  119. }
  120. static inline void csk_hold(struct cnic_sock *csk)
  121. {
  122. atomic_inc(&csk->ref_count);
  123. }
  124. static inline void csk_put(struct cnic_sock *csk)
  125. {
  126. atomic_dec(&csk->ref_count);
  127. }
  128. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  129. {
  130. struct cnic_dev *cdev;
  131. read_lock(&cnic_dev_lock);
  132. list_for_each_entry(cdev, &cnic_dev_list, list) {
  133. if (netdev == cdev->netdev) {
  134. cnic_hold(cdev);
  135. read_unlock(&cnic_dev_lock);
  136. return cdev;
  137. }
  138. }
  139. read_unlock(&cnic_dev_lock);
  140. return NULL;
  141. }
  142. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  143. {
  144. atomic_inc(&ulp_ops->ref_count);
  145. }
  146. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_dec(&ulp_ops->ref_count);
  149. }
  150. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTX_WR_CMD;
  157. io->cid_addr = cid_addr;
  158. io->offset = off;
  159. io->data = val;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_io *io = &info.data.io;
  168. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  169. io->offset = off;
  170. io->dma_addr = addr;
  171. ethdev->drv_ctl(dev->netdev, &info);
  172. }
  173. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  174. {
  175. struct cnic_local *cp = dev->cnic_priv;
  176. struct cnic_eth_dev *ethdev = cp->ethdev;
  177. struct drv_ctl_info info;
  178. struct drv_ctl_l2_ring *ring = &info.data.ring;
  179. if (start)
  180. info.cmd = DRV_CTL_START_L2_CMD;
  181. else
  182. info.cmd = DRV_CTL_STOP_L2_CMD;
  183. ring->cid = cid;
  184. ring->client_id = cl_id;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_WR_CMD;
  194. io->offset = off;
  195. io->data = val;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. }
  198. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  199. {
  200. struct cnic_local *cp = dev->cnic_priv;
  201. struct cnic_eth_dev *ethdev = cp->ethdev;
  202. struct drv_ctl_info info;
  203. struct drv_ctl_io *io = &info.data.io;
  204. info.cmd = DRV_CTL_IO_RD_CMD;
  205. io->offset = off;
  206. ethdev->drv_ctl(dev->netdev, &info);
  207. return io->data;
  208. }
  209. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  210. {
  211. struct cnic_local *cp = dev->cnic_priv;
  212. struct cnic_eth_dev *ethdev = cp->ethdev;
  213. struct drv_ctl_info info;
  214. struct fcoe_capabilities *fcoe_cap =
  215. &info.data.register_data.fcoe_features;
  216. if (reg) {
  217. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  218. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  219. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  220. } else {
  221. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  222. }
  223. info.data.ulp_type = ulp_type;
  224. ethdev->drv_ctl(dev->netdev, &info);
  225. }
  226. static int cnic_in_use(struct cnic_sock *csk)
  227. {
  228. return test_bit(SK_F_INUSE, &csk->flags);
  229. }
  230. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  231. {
  232. struct cnic_local *cp = dev->cnic_priv;
  233. struct cnic_eth_dev *ethdev = cp->ethdev;
  234. struct drv_ctl_info info;
  235. info.cmd = cmd;
  236. info.data.credit.credit_count = count;
  237. ethdev->drv_ctl(dev->netdev, &info);
  238. }
  239. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  240. {
  241. u32 i;
  242. if (!cp->ctx_tbl)
  243. return -EINVAL;
  244. for (i = 0; i < cp->max_cid_space; i++) {
  245. if (cp->ctx_tbl[i].cid == cid) {
  246. *l5_cid = i;
  247. return 0;
  248. }
  249. }
  250. return -EINVAL;
  251. }
  252. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  253. struct cnic_sock *csk)
  254. {
  255. struct iscsi_path path_req;
  256. char *buf = NULL;
  257. u16 len = 0;
  258. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  259. struct cnic_ulp_ops *ulp_ops;
  260. struct cnic_uio_dev *udev = cp->udev;
  261. int rc = 0, retry = 0;
  262. if (!udev || udev->uio_dev == -1)
  263. return -ENODEV;
  264. if (csk) {
  265. len = sizeof(path_req);
  266. buf = (char *) &path_req;
  267. memset(&path_req, 0, len);
  268. msg_type = ISCSI_KEVENT_PATH_REQ;
  269. path_req.handle = (u64) csk->l5_cid;
  270. if (test_bit(SK_F_IPV6, &csk->flags)) {
  271. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  272. sizeof(struct in6_addr));
  273. path_req.ip_addr_len = 16;
  274. } else {
  275. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  276. sizeof(struct in_addr));
  277. path_req.ip_addr_len = 4;
  278. }
  279. path_req.vlan_id = csk->vlan_id;
  280. path_req.pmtu = csk->mtu;
  281. }
  282. while (retry < 3) {
  283. rc = 0;
  284. rcu_read_lock();
  285. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  286. if (ulp_ops)
  287. rc = ulp_ops->iscsi_nl_send_msg(
  288. cp->ulp_handle[CNIC_ULP_ISCSI],
  289. msg_type, buf, len);
  290. rcu_read_unlock();
  291. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  292. break;
  293. msleep(100);
  294. retry++;
  295. }
  296. return rc;
  297. }
  298. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  299. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  300. char *buf, u16 len)
  301. {
  302. int rc = -EINVAL;
  303. switch (msg_type) {
  304. case ISCSI_UEVENT_PATH_UPDATE: {
  305. struct cnic_local *cp;
  306. u32 l5_cid;
  307. struct cnic_sock *csk;
  308. struct iscsi_path *path_resp;
  309. if (len < sizeof(*path_resp))
  310. break;
  311. path_resp = (struct iscsi_path *) buf;
  312. cp = dev->cnic_priv;
  313. l5_cid = (u32) path_resp->handle;
  314. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  315. break;
  316. rcu_read_lock();
  317. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  318. rc = -ENODEV;
  319. rcu_read_unlock();
  320. break;
  321. }
  322. csk = &cp->csk_tbl[l5_cid];
  323. csk_hold(csk);
  324. if (cnic_in_use(csk) &&
  325. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  326. csk->vlan_id = path_resp->vlan_id;
  327. memcpy(csk->ha, path_resp->mac_addr, 6);
  328. if (test_bit(SK_F_IPV6, &csk->flags))
  329. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  330. sizeof(struct in6_addr));
  331. else
  332. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  333. sizeof(struct in_addr));
  334. if (is_valid_ether_addr(csk->ha)) {
  335. cnic_cm_set_pg(csk);
  336. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  337. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  338. cnic_cm_upcall(cp, csk,
  339. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. }
  342. }
  343. csk_put(csk);
  344. rcu_read_unlock();
  345. rc = 0;
  346. }
  347. }
  348. return rc;
  349. }
  350. static int cnic_offld_prep(struct cnic_sock *csk)
  351. {
  352. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  353. return 0;
  354. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  355. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  356. return 0;
  357. }
  358. return 1;
  359. }
  360. static int cnic_close_prep(struct cnic_sock *csk)
  361. {
  362. clear_bit(SK_F_CONNECT_START, &csk->flags);
  363. smp_mb__after_clear_bit();
  364. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  365. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  366. msleep(1);
  367. return 1;
  368. }
  369. return 0;
  370. }
  371. static int cnic_abort_prep(struct cnic_sock *csk)
  372. {
  373. clear_bit(SK_F_CONNECT_START, &csk->flags);
  374. smp_mb__after_clear_bit();
  375. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  376. msleep(1);
  377. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  378. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  379. return 1;
  380. }
  381. return 0;
  382. }
  383. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  384. {
  385. struct cnic_dev *dev;
  386. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  387. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  388. return -EINVAL;
  389. }
  390. mutex_lock(&cnic_lock);
  391. if (cnic_ulp_tbl_prot(ulp_type)) {
  392. pr_err("%s: Type %d has already been registered\n",
  393. __func__, ulp_type);
  394. mutex_unlock(&cnic_lock);
  395. return -EBUSY;
  396. }
  397. read_lock(&cnic_dev_lock);
  398. list_for_each_entry(dev, &cnic_dev_list, list) {
  399. struct cnic_local *cp = dev->cnic_priv;
  400. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  401. }
  402. read_unlock(&cnic_dev_lock);
  403. atomic_set(&ulp_ops->ref_count, 0);
  404. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  405. mutex_unlock(&cnic_lock);
  406. /* Prevent race conditions with netdev_event */
  407. rtnl_lock();
  408. list_for_each_entry(dev, &cnic_dev_list, list) {
  409. struct cnic_local *cp = dev->cnic_priv;
  410. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  411. ulp_ops->cnic_init(dev);
  412. }
  413. rtnl_unlock();
  414. return 0;
  415. }
  416. int cnic_unregister_driver(int ulp_type)
  417. {
  418. struct cnic_dev *dev;
  419. struct cnic_ulp_ops *ulp_ops;
  420. int i = 0;
  421. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  422. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  423. return -EINVAL;
  424. }
  425. mutex_lock(&cnic_lock);
  426. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  427. if (!ulp_ops) {
  428. pr_err("%s: Type %d has not been registered\n",
  429. __func__, ulp_type);
  430. goto out_unlock;
  431. }
  432. read_lock(&cnic_dev_lock);
  433. list_for_each_entry(dev, &cnic_dev_list, list) {
  434. struct cnic_local *cp = dev->cnic_priv;
  435. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  436. pr_err("%s: Type %d still has devices registered\n",
  437. __func__, ulp_type);
  438. read_unlock(&cnic_dev_lock);
  439. goto out_unlock;
  440. }
  441. }
  442. read_unlock(&cnic_dev_lock);
  443. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  444. mutex_unlock(&cnic_lock);
  445. synchronize_rcu();
  446. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  447. msleep(100);
  448. i++;
  449. }
  450. if (atomic_read(&ulp_ops->ref_count) != 0)
  451. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  452. __func__);
  453. return 0;
  454. out_unlock:
  455. mutex_unlock(&cnic_lock);
  456. return -EINVAL;
  457. }
  458. static int cnic_start_hw(struct cnic_dev *);
  459. static void cnic_stop_hw(struct cnic_dev *);
  460. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  461. void *ulp_ctx)
  462. {
  463. struct cnic_local *cp = dev->cnic_priv;
  464. struct cnic_ulp_ops *ulp_ops;
  465. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  466. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  467. return -EINVAL;
  468. }
  469. mutex_lock(&cnic_lock);
  470. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  471. pr_err("%s: Driver with type %d has not been registered\n",
  472. __func__, ulp_type);
  473. mutex_unlock(&cnic_lock);
  474. return -EAGAIN;
  475. }
  476. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  477. pr_err("%s: Type %d has already been registered to this device\n",
  478. __func__, ulp_type);
  479. mutex_unlock(&cnic_lock);
  480. return -EBUSY;
  481. }
  482. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  483. cp->ulp_handle[ulp_type] = ulp_ctx;
  484. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  485. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  486. cnic_hold(dev);
  487. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  488. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  489. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  490. mutex_unlock(&cnic_lock);
  491. cnic_ulp_ctl(dev, ulp_type, true);
  492. return 0;
  493. }
  494. EXPORT_SYMBOL(cnic_register_driver);
  495. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  496. {
  497. struct cnic_local *cp = dev->cnic_priv;
  498. int i = 0;
  499. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  500. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  501. return -EINVAL;
  502. }
  503. mutex_lock(&cnic_lock);
  504. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  505. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  506. cnic_put(dev);
  507. } else {
  508. pr_err("%s: device not registered to this ulp type %d\n",
  509. __func__, ulp_type);
  510. mutex_unlock(&cnic_lock);
  511. return -EINVAL;
  512. }
  513. mutex_unlock(&cnic_lock);
  514. if (ulp_type == CNIC_ULP_ISCSI)
  515. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  516. else if (ulp_type == CNIC_ULP_FCOE)
  517. dev->fcoe_cap = NULL;
  518. synchronize_rcu();
  519. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  520. i < 20) {
  521. msleep(100);
  522. i++;
  523. }
  524. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  525. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  526. cnic_ulp_ctl(dev, ulp_type, false);
  527. return 0;
  528. }
  529. EXPORT_SYMBOL(cnic_unregister_driver);
  530. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  531. u32 next)
  532. {
  533. id_tbl->start = start_id;
  534. id_tbl->max = size;
  535. id_tbl->next = next;
  536. spin_lock_init(&id_tbl->lock);
  537. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  538. if (!id_tbl->table)
  539. return -ENOMEM;
  540. return 0;
  541. }
  542. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  543. {
  544. kfree(id_tbl->table);
  545. id_tbl->table = NULL;
  546. }
  547. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  548. {
  549. int ret = -1;
  550. id -= id_tbl->start;
  551. if (id >= id_tbl->max)
  552. return ret;
  553. spin_lock(&id_tbl->lock);
  554. if (!test_bit(id, id_tbl->table)) {
  555. set_bit(id, id_tbl->table);
  556. ret = 0;
  557. }
  558. spin_unlock(&id_tbl->lock);
  559. return ret;
  560. }
  561. /* Returns -1 if not successful */
  562. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  563. {
  564. u32 id;
  565. spin_lock(&id_tbl->lock);
  566. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  567. if (id >= id_tbl->max) {
  568. id = -1;
  569. if (id_tbl->next != 0) {
  570. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  571. if (id >= id_tbl->next)
  572. id = -1;
  573. }
  574. }
  575. if (id < id_tbl->max) {
  576. set_bit(id, id_tbl->table);
  577. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  578. id += id_tbl->start;
  579. }
  580. spin_unlock(&id_tbl->lock);
  581. return id;
  582. }
  583. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  584. {
  585. if (id == -1)
  586. return;
  587. id -= id_tbl->start;
  588. if (id >= id_tbl->max)
  589. return;
  590. clear_bit(id, id_tbl->table);
  591. }
  592. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  593. {
  594. int i;
  595. if (!dma->pg_arr)
  596. return;
  597. for (i = 0; i < dma->num_pages; i++) {
  598. if (dma->pg_arr[i]) {
  599. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  600. dma->pg_arr[i], dma->pg_map_arr[i]);
  601. dma->pg_arr[i] = NULL;
  602. }
  603. }
  604. if (dma->pgtbl) {
  605. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  606. dma->pgtbl, dma->pgtbl_map);
  607. dma->pgtbl = NULL;
  608. }
  609. kfree(dma->pg_arr);
  610. dma->pg_arr = NULL;
  611. dma->num_pages = 0;
  612. }
  613. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  614. {
  615. int i;
  616. __le32 *page_table = (__le32 *) dma->pgtbl;
  617. for (i = 0; i < dma->num_pages; i++) {
  618. /* Each entry needs to be in big endian format. */
  619. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  620. page_table++;
  621. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  622. page_table++;
  623. }
  624. }
  625. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  626. {
  627. int i;
  628. __le32 *page_table = (__le32 *) dma->pgtbl;
  629. for (i = 0; i < dma->num_pages; i++) {
  630. /* Each entry needs to be in little endian format. */
  631. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  632. page_table++;
  633. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  634. page_table++;
  635. }
  636. }
  637. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  638. int pages, int use_pg_tbl)
  639. {
  640. int i, size;
  641. struct cnic_local *cp = dev->cnic_priv;
  642. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  643. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  644. if (dma->pg_arr == NULL)
  645. return -ENOMEM;
  646. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  647. dma->num_pages = pages;
  648. for (i = 0; i < pages; i++) {
  649. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  650. BCM_PAGE_SIZE,
  651. &dma->pg_map_arr[i],
  652. GFP_ATOMIC);
  653. if (dma->pg_arr[i] == NULL)
  654. goto error;
  655. }
  656. if (!use_pg_tbl)
  657. return 0;
  658. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  659. ~(BCM_PAGE_SIZE - 1);
  660. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  661. &dma->pgtbl_map, GFP_ATOMIC);
  662. if (dma->pgtbl == NULL)
  663. goto error;
  664. cp->setup_pgtbl(dev, dma);
  665. return 0;
  666. error:
  667. cnic_free_dma(dev, dma);
  668. return -ENOMEM;
  669. }
  670. static void cnic_free_context(struct cnic_dev *dev)
  671. {
  672. struct cnic_local *cp = dev->cnic_priv;
  673. int i;
  674. for (i = 0; i < cp->ctx_blks; i++) {
  675. if (cp->ctx_arr[i].ctx) {
  676. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  677. cp->ctx_arr[i].ctx,
  678. cp->ctx_arr[i].mapping);
  679. cp->ctx_arr[i].ctx = NULL;
  680. }
  681. }
  682. }
  683. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  684. {
  685. uio_unregister_device(&udev->cnic_uinfo);
  686. if (udev->l2_buf) {
  687. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  688. udev->l2_buf, udev->l2_buf_map);
  689. udev->l2_buf = NULL;
  690. }
  691. if (udev->l2_ring) {
  692. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  693. udev->l2_ring, udev->l2_ring_map);
  694. udev->l2_ring = NULL;
  695. }
  696. pci_dev_put(udev->pdev);
  697. kfree(udev);
  698. }
  699. static void cnic_free_uio(struct cnic_uio_dev *udev)
  700. {
  701. if (!udev)
  702. return;
  703. write_lock(&cnic_dev_lock);
  704. list_del_init(&udev->list);
  705. write_unlock(&cnic_dev_lock);
  706. __cnic_free_uio(udev);
  707. }
  708. static void cnic_free_resc(struct cnic_dev *dev)
  709. {
  710. struct cnic_local *cp = dev->cnic_priv;
  711. struct cnic_uio_dev *udev = cp->udev;
  712. if (udev) {
  713. udev->dev = NULL;
  714. cp->udev = NULL;
  715. }
  716. cnic_free_context(dev);
  717. kfree(cp->ctx_arr);
  718. cp->ctx_arr = NULL;
  719. cp->ctx_blks = 0;
  720. cnic_free_dma(dev, &cp->gbl_buf_info);
  721. cnic_free_dma(dev, &cp->kwq_info);
  722. cnic_free_dma(dev, &cp->kwq_16_data_info);
  723. cnic_free_dma(dev, &cp->kcq2.dma);
  724. cnic_free_dma(dev, &cp->kcq1.dma);
  725. kfree(cp->iscsi_tbl);
  726. cp->iscsi_tbl = NULL;
  727. kfree(cp->ctx_tbl);
  728. cp->ctx_tbl = NULL;
  729. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  730. cnic_free_id_tbl(&cp->cid_tbl);
  731. }
  732. static int cnic_alloc_context(struct cnic_dev *dev)
  733. {
  734. struct cnic_local *cp = dev->cnic_priv;
  735. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  736. int i, k, arr_size;
  737. cp->ctx_blk_size = BCM_PAGE_SIZE;
  738. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  739. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  740. sizeof(struct cnic_ctx);
  741. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  742. if (cp->ctx_arr == NULL)
  743. return -ENOMEM;
  744. k = 0;
  745. for (i = 0; i < 2; i++) {
  746. u32 j, reg, off, lo, hi;
  747. if (i == 0)
  748. off = BNX2_PG_CTX_MAP;
  749. else
  750. off = BNX2_ISCSI_CTX_MAP;
  751. reg = cnic_reg_rd_ind(dev, off);
  752. lo = reg >> 16;
  753. hi = reg & 0xffff;
  754. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  755. cp->ctx_arr[k].cid = j;
  756. }
  757. cp->ctx_blks = k;
  758. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  759. cp->ctx_blks = 0;
  760. return -ENOMEM;
  761. }
  762. for (i = 0; i < cp->ctx_blks; i++) {
  763. cp->ctx_arr[i].ctx =
  764. dma_alloc_coherent(&dev->pcidev->dev,
  765. BCM_PAGE_SIZE,
  766. &cp->ctx_arr[i].mapping,
  767. GFP_KERNEL);
  768. if (cp->ctx_arr[i].ctx == NULL)
  769. return -ENOMEM;
  770. }
  771. }
  772. return 0;
  773. }
  774. static u16 cnic_bnx2_next_idx(u16 idx)
  775. {
  776. return idx + 1;
  777. }
  778. static u16 cnic_bnx2_hw_idx(u16 idx)
  779. {
  780. return idx;
  781. }
  782. static u16 cnic_bnx2x_next_idx(u16 idx)
  783. {
  784. idx++;
  785. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  786. idx++;
  787. return idx;
  788. }
  789. static u16 cnic_bnx2x_hw_idx(u16 idx)
  790. {
  791. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  792. idx++;
  793. return idx;
  794. }
  795. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  796. bool use_pg_tbl)
  797. {
  798. int err, i, use_page_tbl = 0;
  799. struct kcqe **kcq;
  800. if (use_pg_tbl)
  801. use_page_tbl = 1;
  802. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  803. if (err)
  804. return err;
  805. kcq = (struct kcqe **) info->dma.pg_arr;
  806. info->kcq = kcq;
  807. info->next_idx = cnic_bnx2_next_idx;
  808. info->hw_idx = cnic_bnx2_hw_idx;
  809. if (use_pg_tbl)
  810. return 0;
  811. info->next_idx = cnic_bnx2x_next_idx;
  812. info->hw_idx = cnic_bnx2x_hw_idx;
  813. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  814. struct bnx2x_bd_chain_next *next =
  815. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  816. int j = i + 1;
  817. if (j >= KCQ_PAGE_CNT)
  818. j = 0;
  819. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  820. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  821. }
  822. return 0;
  823. }
  824. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  825. {
  826. struct cnic_local *cp = dev->cnic_priv;
  827. struct cnic_uio_dev *udev;
  828. read_lock(&cnic_dev_lock);
  829. list_for_each_entry(udev, &cnic_udev_list, list) {
  830. if (udev->pdev == dev->pcidev) {
  831. udev->dev = dev;
  832. cp->udev = udev;
  833. read_unlock(&cnic_dev_lock);
  834. return 0;
  835. }
  836. }
  837. read_unlock(&cnic_dev_lock);
  838. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  839. if (!udev)
  840. return -ENOMEM;
  841. udev->uio_dev = -1;
  842. udev->dev = dev;
  843. udev->pdev = dev->pcidev;
  844. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  845. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  846. &udev->l2_ring_map,
  847. GFP_KERNEL | __GFP_COMP);
  848. if (!udev->l2_ring)
  849. goto err_udev;
  850. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  851. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  852. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  853. &udev->l2_buf_map,
  854. GFP_KERNEL | __GFP_COMP);
  855. if (!udev->l2_buf)
  856. goto err_dma;
  857. write_lock(&cnic_dev_lock);
  858. list_add(&udev->list, &cnic_udev_list);
  859. write_unlock(&cnic_dev_lock);
  860. pci_dev_get(udev->pdev);
  861. cp->udev = udev;
  862. return 0;
  863. err_dma:
  864. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  865. udev->l2_ring, udev->l2_ring_map);
  866. err_udev:
  867. kfree(udev);
  868. return -ENOMEM;
  869. }
  870. static int cnic_init_uio(struct cnic_dev *dev)
  871. {
  872. struct cnic_local *cp = dev->cnic_priv;
  873. struct cnic_uio_dev *udev = cp->udev;
  874. struct uio_info *uinfo;
  875. int ret = 0;
  876. if (!udev)
  877. return -ENOMEM;
  878. uinfo = &udev->cnic_uinfo;
  879. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  880. uinfo->mem[0].internal_addr = dev->regview;
  881. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  882. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  883. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  884. TX_MAX_TSS_RINGS + 1);
  885. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  886. PAGE_MASK;
  887. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  888. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  889. else
  890. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  891. uinfo->name = "bnx2_cnic";
  892. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  893. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  894. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  895. PAGE_MASK;
  896. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  897. uinfo->name = "bnx2x_cnic";
  898. }
  899. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  900. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  901. uinfo->mem[2].size = udev->l2_ring_size;
  902. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  903. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  904. uinfo->mem[3].size = udev->l2_buf_size;
  905. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  906. uinfo->version = CNIC_MODULE_VERSION;
  907. uinfo->irq = UIO_IRQ_CUSTOM;
  908. uinfo->open = cnic_uio_open;
  909. uinfo->release = cnic_uio_close;
  910. if (udev->uio_dev == -1) {
  911. if (!uinfo->priv) {
  912. uinfo->priv = udev;
  913. ret = uio_register_device(&udev->pdev->dev, uinfo);
  914. }
  915. } else {
  916. cnic_init_rings(dev);
  917. }
  918. return ret;
  919. }
  920. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  921. {
  922. struct cnic_local *cp = dev->cnic_priv;
  923. int ret;
  924. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  925. if (ret)
  926. goto error;
  927. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  928. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  929. if (ret)
  930. goto error;
  931. ret = cnic_alloc_context(dev);
  932. if (ret)
  933. goto error;
  934. ret = cnic_alloc_uio_rings(dev, 2);
  935. if (ret)
  936. goto error;
  937. ret = cnic_init_uio(dev);
  938. if (ret)
  939. goto error;
  940. return 0;
  941. error:
  942. cnic_free_resc(dev);
  943. return ret;
  944. }
  945. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  946. {
  947. struct cnic_local *cp = dev->cnic_priv;
  948. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  949. int total_mem, blks, i;
  950. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  951. blks = total_mem / ctx_blk_size;
  952. if (total_mem % ctx_blk_size)
  953. blks++;
  954. if (blks > cp->ethdev->ctx_tbl_len)
  955. return -ENOMEM;
  956. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  957. if (cp->ctx_arr == NULL)
  958. return -ENOMEM;
  959. cp->ctx_blks = blks;
  960. cp->ctx_blk_size = ctx_blk_size;
  961. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  962. cp->ctx_align = 0;
  963. else
  964. cp->ctx_align = ctx_blk_size;
  965. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  966. for (i = 0; i < blks; i++) {
  967. cp->ctx_arr[i].ctx =
  968. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  969. &cp->ctx_arr[i].mapping,
  970. GFP_KERNEL);
  971. if (cp->ctx_arr[i].ctx == NULL)
  972. return -ENOMEM;
  973. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  974. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  975. cnic_free_context(dev);
  976. cp->ctx_blk_size += cp->ctx_align;
  977. i = -1;
  978. continue;
  979. }
  980. }
  981. }
  982. return 0;
  983. }
  984. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  985. {
  986. struct cnic_local *cp = dev->cnic_priv;
  987. struct cnic_eth_dev *ethdev = cp->ethdev;
  988. u32 start_cid = ethdev->starting_cid;
  989. int i, j, n, ret, pages;
  990. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  991. cp->iro_arr = ethdev->iro_arr;
  992. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  993. cp->iscsi_start_cid = start_cid;
  994. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  995. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  996. cp->max_cid_space += dev->max_fcoe_conn;
  997. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  998. if (!cp->fcoe_init_cid)
  999. cp->fcoe_init_cid = 0x10;
  1000. }
  1001. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1002. GFP_KERNEL);
  1003. if (!cp->iscsi_tbl)
  1004. goto error;
  1005. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1006. cp->max_cid_space, GFP_KERNEL);
  1007. if (!cp->ctx_tbl)
  1008. goto error;
  1009. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1010. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1011. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1012. }
  1013. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1014. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1015. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1016. PAGE_SIZE;
  1017. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1018. if (ret)
  1019. return -ENOMEM;
  1020. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1021. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1022. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1023. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1024. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1025. off;
  1026. if ((i % n) == (n - 1))
  1027. j++;
  1028. }
  1029. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1030. if (ret)
  1031. goto error;
  1032. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1033. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1034. if (ret)
  1035. goto error;
  1036. }
  1037. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1038. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1039. if (ret)
  1040. goto error;
  1041. ret = cnic_alloc_bnx2x_context(dev);
  1042. if (ret)
  1043. goto error;
  1044. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1045. cp->l2_rx_ring_size = 15;
  1046. ret = cnic_alloc_uio_rings(dev, 4);
  1047. if (ret)
  1048. goto error;
  1049. ret = cnic_init_uio(dev);
  1050. if (ret)
  1051. goto error;
  1052. return 0;
  1053. error:
  1054. cnic_free_resc(dev);
  1055. return -ENOMEM;
  1056. }
  1057. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1058. {
  1059. return cp->max_kwq_idx -
  1060. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1061. }
  1062. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1063. u32 num_wqes)
  1064. {
  1065. struct cnic_local *cp = dev->cnic_priv;
  1066. struct kwqe *prod_qe;
  1067. u16 prod, sw_prod, i;
  1068. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1069. return -EAGAIN; /* bnx2 is down */
  1070. spin_lock_bh(&cp->cnic_ulp_lock);
  1071. if (num_wqes > cnic_kwq_avail(cp) &&
  1072. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1073. spin_unlock_bh(&cp->cnic_ulp_lock);
  1074. return -EAGAIN;
  1075. }
  1076. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1077. prod = cp->kwq_prod_idx;
  1078. sw_prod = prod & MAX_KWQ_IDX;
  1079. for (i = 0; i < num_wqes; i++) {
  1080. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1081. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1082. prod++;
  1083. sw_prod = prod & MAX_KWQ_IDX;
  1084. }
  1085. cp->kwq_prod_idx = prod;
  1086. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1087. spin_unlock_bh(&cp->cnic_ulp_lock);
  1088. return 0;
  1089. }
  1090. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1091. union l5cm_specific_data *l5_data)
  1092. {
  1093. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1094. dma_addr_t map;
  1095. map = ctx->kwqe_data_mapping;
  1096. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1097. l5_data->phy_address.hi = (u64) map >> 32;
  1098. return ctx->kwqe_data;
  1099. }
  1100. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1101. u32 type, union l5cm_specific_data *l5_data)
  1102. {
  1103. struct cnic_local *cp = dev->cnic_priv;
  1104. struct l5cm_spe kwqe;
  1105. struct kwqe_16 *kwq[1];
  1106. u16 type_16;
  1107. int ret;
  1108. kwqe.hdr.conn_and_cmd_data =
  1109. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1110. BNX2X_HW_CID(cp, cid)));
  1111. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1112. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1113. SPE_HDR_FUNCTION_ID;
  1114. kwqe.hdr.type = cpu_to_le16(type_16);
  1115. kwqe.hdr.reserved1 = 0;
  1116. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1117. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1118. kwq[0] = (struct kwqe_16 *) &kwqe;
  1119. spin_lock_bh(&cp->cnic_ulp_lock);
  1120. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1121. spin_unlock_bh(&cp->cnic_ulp_lock);
  1122. if (ret == 1)
  1123. return 0;
  1124. return ret;
  1125. }
  1126. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1127. struct kcqe *cqes[], u32 num_cqes)
  1128. {
  1129. struct cnic_local *cp = dev->cnic_priv;
  1130. struct cnic_ulp_ops *ulp_ops;
  1131. rcu_read_lock();
  1132. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1133. if (likely(ulp_ops)) {
  1134. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1135. cqes, num_cqes);
  1136. }
  1137. rcu_read_unlock();
  1138. }
  1139. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1140. {
  1141. struct cnic_local *cp = dev->cnic_priv;
  1142. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1143. int hq_bds, pages;
  1144. u32 pfid = cp->pfid;
  1145. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1146. cp->num_ccells = req1->num_ccells_per_conn;
  1147. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1148. cp->num_iscsi_tasks;
  1149. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1150. BNX2X_ISCSI_R2TQE_SIZE;
  1151. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1152. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1153. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1154. cp->num_cqs = req1->num_cqs;
  1155. if (!dev->max_iscsi_conn)
  1156. return 0;
  1157. /* init Tstorm RAM */
  1158. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1159. req1->rq_num_wqes);
  1160. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1161. PAGE_SIZE);
  1162. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1163. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1164. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1165. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1166. req1->num_tasks_per_conn);
  1167. /* init Ustorm RAM */
  1168. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1169. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1170. req1->rq_buffer_size);
  1171. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1172. PAGE_SIZE);
  1173. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1174. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1175. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1176. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1177. req1->num_tasks_per_conn);
  1178. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1179. req1->rq_num_wqes);
  1180. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1181. req1->cq_num_wqes);
  1182. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1183. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1184. /* init Xstorm RAM */
  1185. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1186. PAGE_SIZE);
  1187. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1188. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1189. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1190. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1191. req1->num_tasks_per_conn);
  1192. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1193. hq_bds);
  1194. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1195. req1->num_tasks_per_conn);
  1196. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1197. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1198. /* init Cstorm RAM */
  1199. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1200. PAGE_SIZE);
  1201. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1202. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1203. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1204. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1205. req1->num_tasks_per_conn);
  1206. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1207. req1->cq_num_wqes);
  1208. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1209. hq_bds);
  1210. return 0;
  1211. }
  1212. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1213. {
  1214. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1215. struct cnic_local *cp = dev->cnic_priv;
  1216. u32 pfid = cp->pfid;
  1217. struct iscsi_kcqe kcqe;
  1218. struct kcqe *cqes[1];
  1219. memset(&kcqe, 0, sizeof(kcqe));
  1220. if (!dev->max_iscsi_conn) {
  1221. kcqe.completion_status =
  1222. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1223. goto done;
  1224. }
  1225. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1226. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1227. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1228. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1229. req2->error_bit_map[1]);
  1230. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1231. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1232. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1233. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1234. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1235. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1236. req2->error_bit_map[1]);
  1237. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1238. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1239. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1240. done:
  1241. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1242. cqes[0] = (struct kcqe *) &kcqe;
  1243. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1244. return 0;
  1245. }
  1246. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1247. {
  1248. struct cnic_local *cp = dev->cnic_priv;
  1249. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1250. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1251. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1252. cnic_free_dma(dev, &iscsi->hq_info);
  1253. cnic_free_dma(dev, &iscsi->r2tq_info);
  1254. cnic_free_dma(dev, &iscsi->task_array_info);
  1255. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1256. } else {
  1257. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1258. }
  1259. ctx->cid = 0;
  1260. }
  1261. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1262. {
  1263. u32 cid;
  1264. int ret, pages;
  1265. struct cnic_local *cp = dev->cnic_priv;
  1266. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1267. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1268. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1269. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1270. if (cid == -1) {
  1271. ret = -ENOMEM;
  1272. goto error;
  1273. }
  1274. ctx->cid = cid;
  1275. return 0;
  1276. }
  1277. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1278. if (cid == -1) {
  1279. ret = -ENOMEM;
  1280. goto error;
  1281. }
  1282. ctx->cid = cid;
  1283. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1284. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1285. if (ret)
  1286. goto error;
  1287. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1288. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1289. if (ret)
  1290. goto error;
  1291. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1292. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1293. if (ret)
  1294. goto error;
  1295. return 0;
  1296. error:
  1297. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1298. return ret;
  1299. }
  1300. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1301. struct regpair *ctx_addr)
  1302. {
  1303. struct cnic_local *cp = dev->cnic_priv;
  1304. struct cnic_eth_dev *ethdev = cp->ethdev;
  1305. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1306. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1307. unsigned long align_off = 0;
  1308. dma_addr_t ctx_map;
  1309. void *ctx;
  1310. if (cp->ctx_align) {
  1311. unsigned long mask = cp->ctx_align - 1;
  1312. if (cp->ctx_arr[blk].mapping & mask)
  1313. align_off = cp->ctx_align -
  1314. (cp->ctx_arr[blk].mapping & mask);
  1315. }
  1316. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1317. (off * BNX2X_CONTEXT_MEM_SIZE);
  1318. ctx = cp->ctx_arr[blk].ctx + align_off +
  1319. (off * BNX2X_CONTEXT_MEM_SIZE);
  1320. if (init)
  1321. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1322. ctx_addr->lo = ctx_map & 0xffffffff;
  1323. ctx_addr->hi = (u64) ctx_map >> 32;
  1324. return ctx;
  1325. }
  1326. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1327. u32 num)
  1328. {
  1329. struct cnic_local *cp = dev->cnic_priv;
  1330. struct iscsi_kwqe_conn_offload1 *req1 =
  1331. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1332. struct iscsi_kwqe_conn_offload2 *req2 =
  1333. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1334. struct iscsi_kwqe_conn_offload3 *req3;
  1335. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1336. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1337. u32 cid = ctx->cid;
  1338. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1339. struct iscsi_context *ictx;
  1340. struct regpair context_addr;
  1341. int i, j, n = 2, n_max;
  1342. u8 port = CNIC_PORT(cp);
  1343. ctx->ctx_flags = 0;
  1344. if (!req2->num_additional_wqes)
  1345. return -EINVAL;
  1346. n_max = req2->num_additional_wqes + 2;
  1347. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1348. if (ictx == NULL)
  1349. return -ENOMEM;
  1350. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1351. ictx->xstorm_ag_context.hq_prod = 1;
  1352. ictx->xstorm_st_context.iscsi.first_burst_length =
  1353. ISCSI_DEF_FIRST_BURST_LEN;
  1354. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1355. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1356. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1357. req1->sq_page_table_addr_lo;
  1358. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1359. req1->sq_page_table_addr_hi;
  1360. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1361. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1362. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1363. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1364. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1365. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1366. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1367. iscsi->hq_info.pgtbl[0];
  1368. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1369. iscsi->hq_info.pgtbl[1];
  1370. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1371. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1372. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1373. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1374. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1375. iscsi->r2tq_info.pgtbl[0];
  1376. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1377. iscsi->r2tq_info.pgtbl[1];
  1378. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1379. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1380. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1381. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1382. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1383. BNX2X_ISCSI_PBL_NOT_CACHED;
  1384. ictx->xstorm_st_context.iscsi.flags.flags |=
  1385. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1386. ictx->xstorm_st_context.iscsi.flags.flags |=
  1387. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1388. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1389. ETH_P_8021Q;
  1390. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1391. cp->port_mode == CHIP_2_PORT_MODE) {
  1392. port = 0;
  1393. }
  1394. ictx->xstorm_st_context.common.flags =
  1395. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1396. ictx->xstorm_st_context.common.flags =
  1397. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1398. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1399. /* TSTORM requires the base address of RQ DB & not PTE */
  1400. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1401. req2->rq_page_table_addr_lo & PAGE_MASK;
  1402. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1403. req2->rq_page_table_addr_hi;
  1404. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1405. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1406. ictx->tstorm_st_context.tcp.flags2 |=
  1407. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1408. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1409. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1410. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1411. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1412. req2->rq_page_table_addr_lo;
  1413. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1414. req2->rq_page_table_addr_hi;
  1415. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1416. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1417. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1418. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1419. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1420. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1421. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1422. iscsi->r2tq_info.pgtbl[0];
  1423. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1424. iscsi->r2tq_info.pgtbl[1];
  1425. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1426. req1->cq_page_table_addr_lo;
  1427. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1428. req1->cq_page_table_addr_hi;
  1429. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1430. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1431. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1432. ictx->ustorm_st_context.task_pbe_cache_index =
  1433. BNX2X_ISCSI_PBL_NOT_CACHED;
  1434. ictx->ustorm_st_context.task_pdu_cache_index =
  1435. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1436. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1437. if (j == 3) {
  1438. if (n >= n_max)
  1439. break;
  1440. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1441. j = 0;
  1442. }
  1443. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1444. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1445. req3->qp_first_pte[j].hi;
  1446. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1447. req3->qp_first_pte[j].lo;
  1448. }
  1449. ictx->ustorm_st_context.task_pbl_base.lo =
  1450. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1451. ictx->ustorm_st_context.task_pbl_base.hi =
  1452. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1453. ictx->ustorm_st_context.tce_phy_addr.lo =
  1454. iscsi->task_array_info.pgtbl[0];
  1455. ictx->ustorm_st_context.tce_phy_addr.hi =
  1456. iscsi->task_array_info.pgtbl[1];
  1457. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1458. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1459. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1460. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1461. ISCSI_DEF_MAX_BURST_LEN;
  1462. ictx->ustorm_st_context.negotiated_rx |=
  1463. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1464. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1465. ictx->cstorm_st_context.hq_pbl_base.lo =
  1466. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1467. ictx->cstorm_st_context.hq_pbl_base.hi =
  1468. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1469. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1470. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1471. ictx->cstorm_st_context.task_pbl_base.lo =
  1472. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1473. ictx->cstorm_st_context.task_pbl_base.hi =
  1474. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1475. /* CSTORM and USTORM initialization is different, CSTORM requires
  1476. * CQ DB base & not PTE addr */
  1477. ictx->cstorm_st_context.cq_db_base.lo =
  1478. req1->cq_page_table_addr_lo & PAGE_MASK;
  1479. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1480. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1481. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1482. for (i = 0; i < cp->num_cqs; i++) {
  1483. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1484. ISCSI_INITIAL_SN;
  1485. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1486. ISCSI_INITIAL_SN;
  1487. }
  1488. ictx->xstorm_ag_context.cdu_reserved =
  1489. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1490. ISCSI_CONNECTION_TYPE);
  1491. ictx->ustorm_ag_context.cdu_usage =
  1492. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1493. ISCSI_CONNECTION_TYPE);
  1494. return 0;
  1495. }
  1496. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1497. u32 num, int *work)
  1498. {
  1499. struct iscsi_kwqe_conn_offload1 *req1;
  1500. struct iscsi_kwqe_conn_offload2 *req2;
  1501. struct cnic_local *cp = dev->cnic_priv;
  1502. struct cnic_context *ctx;
  1503. struct iscsi_kcqe kcqe;
  1504. struct kcqe *cqes[1];
  1505. u32 l5_cid;
  1506. int ret = 0;
  1507. if (num < 2) {
  1508. *work = num;
  1509. return -EINVAL;
  1510. }
  1511. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1512. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1513. if ((num - 2) < req2->num_additional_wqes) {
  1514. *work = num;
  1515. return -EINVAL;
  1516. }
  1517. *work = 2 + req2->num_additional_wqes;
  1518. l5_cid = req1->iscsi_conn_id;
  1519. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1520. return -EINVAL;
  1521. memset(&kcqe, 0, sizeof(kcqe));
  1522. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1523. kcqe.iscsi_conn_id = l5_cid;
  1524. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1525. ctx = &cp->ctx_tbl[l5_cid];
  1526. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1527. kcqe.completion_status =
  1528. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1529. goto done;
  1530. }
  1531. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1532. atomic_dec(&cp->iscsi_conn);
  1533. goto done;
  1534. }
  1535. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1536. if (ret) {
  1537. atomic_dec(&cp->iscsi_conn);
  1538. ret = 0;
  1539. goto done;
  1540. }
  1541. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1542. if (ret < 0) {
  1543. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1544. atomic_dec(&cp->iscsi_conn);
  1545. goto done;
  1546. }
  1547. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1548. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1549. done:
  1550. cqes[0] = (struct kcqe *) &kcqe;
  1551. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1552. return 0;
  1553. }
  1554. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1555. {
  1556. struct cnic_local *cp = dev->cnic_priv;
  1557. struct iscsi_kwqe_conn_update *req =
  1558. (struct iscsi_kwqe_conn_update *) kwqe;
  1559. void *data;
  1560. union l5cm_specific_data l5_data;
  1561. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1562. int ret;
  1563. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1564. return -EINVAL;
  1565. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1566. if (!data)
  1567. return -ENOMEM;
  1568. memcpy(data, kwqe, sizeof(struct kwqe));
  1569. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1570. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1571. return ret;
  1572. }
  1573. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1574. {
  1575. struct cnic_local *cp = dev->cnic_priv;
  1576. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1577. union l5cm_specific_data l5_data;
  1578. int ret;
  1579. u32 hw_cid;
  1580. init_waitqueue_head(&ctx->waitq);
  1581. ctx->wait_cond = 0;
  1582. memset(&l5_data, 0, sizeof(l5_data));
  1583. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1584. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1585. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1586. if (ret == 0) {
  1587. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1588. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1589. return -EBUSY;
  1590. }
  1591. return 0;
  1592. }
  1593. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1594. {
  1595. struct cnic_local *cp = dev->cnic_priv;
  1596. struct iscsi_kwqe_conn_destroy *req =
  1597. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1598. u32 l5_cid = req->reserved0;
  1599. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1600. int ret = 0;
  1601. struct iscsi_kcqe kcqe;
  1602. struct kcqe *cqes[1];
  1603. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1604. goto skip_cfc_delete;
  1605. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1606. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1607. if (delta > (2 * HZ))
  1608. delta = 0;
  1609. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1610. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1611. goto destroy_reply;
  1612. }
  1613. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1614. skip_cfc_delete:
  1615. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1616. if (!ret) {
  1617. atomic_dec(&cp->iscsi_conn);
  1618. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1619. }
  1620. destroy_reply:
  1621. memset(&kcqe, 0, sizeof(kcqe));
  1622. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1623. kcqe.iscsi_conn_id = l5_cid;
  1624. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1625. kcqe.iscsi_conn_context_id = req->context_id;
  1626. cqes[0] = (struct kcqe *) &kcqe;
  1627. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1628. return 0;
  1629. }
  1630. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1631. struct l4_kwq_connect_req1 *kwqe1,
  1632. struct l4_kwq_connect_req3 *kwqe3,
  1633. struct l5cm_active_conn_buffer *conn_buf)
  1634. {
  1635. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1636. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1637. &conn_buf->xstorm_conn_buffer;
  1638. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1639. &conn_buf->tstorm_conn_buffer;
  1640. struct regpair context_addr;
  1641. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1642. struct in6_addr src_ip, dst_ip;
  1643. int i;
  1644. u32 *addrp;
  1645. addrp = (u32 *) &conn_addr->local_ip_addr;
  1646. for (i = 0; i < 4; i++, addrp++)
  1647. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1648. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1649. for (i = 0; i < 4; i++, addrp++)
  1650. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1651. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1652. xstorm_buf->context_addr.hi = context_addr.hi;
  1653. xstorm_buf->context_addr.lo = context_addr.lo;
  1654. xstorm_buf->mss = 0xffff;
  1655. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1656. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1657. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1658. xstorm_buf->pseudo_header_checksum =
  1659. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1660. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1661. tstorm_buf->params |=
  1662. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1663. if (kwqe3->ka_timeout) {
  1664. tstorm_buf->ka_enable = 1;
  1665. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1666. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1667. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1668. }
  1669. tstorm_buf->max_rt_time = 0xffffffff;
  1670. }
  1671. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1672. {
  1673. struct cnic_local *cp = dev->cnic_priv;
  1674. u32 pfid = cp->pfid;
  1675. u8 *mac = dev->mac_addr;
  1676. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1677. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1678. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1679. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1680. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1681. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1682. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1683. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1684. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1685. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1686. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1687. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1688. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1689. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1690. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1691. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1692. mac[4]);
  1693. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1694. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1695. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1696. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1697. mac[2]);
  1698. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1699. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1700. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1701. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1702. mac[0]);
  1703. }
  1704. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1705. {
  1706. struct cnic_local *cp = dev->cnic_priv;
  1707. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1708. u16 tstorm_flags = 0;
  1709. if (tcp_ts) {
  1710. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1711. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1712. }
  1713. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1714. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1715. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1716. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1717. }
  1718. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1719. u32 num, int *work)
  1720. {
  1721. struct cnic_local *cp = dev->cnic_priv;
  1722. struct l4_kwq_connect_req1 *kwqe1 =
  1723. (struct l4_kwq_connect_req1 *) wqes[0];
  1724. struct l4_kwq_connect_req3 *kwqe3;
  1725. struct l5cm_active_conn_buffer *conn_buf;
  1726. struct l5cm_conn_addr_params *conn_addr;
  1727. union l5cm_specific_data l5_data;
  1728. u32 l5_cid = kwqe1->pg_cid;
  1729. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1730. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1731. int ret;
  1732. if (num < 2) {
  1733. *work = num;
  1734. return -EINVAL;
  1735. }
  1736. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1737. *work = 3;
  1738. else
  1739. *work = 2;
  1740. if (num < *work) {
  1741. *work = num;
  1742. return -EINVAL;
  1743. }
  1744. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1745. netdev_err(dev->netdev, "conn_buf size too big\n");
  1746. return -ENOMEM;
  1747. }
  1748. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1749. if (!conn_buf)
  1750. return -ENOMEM;
  1751. memset(conn_buf, 0, sizeof(*conn_buf));
  1752. conn_addr = &conn_buf->conn_addr_buf;
  1753. conn_addr->remote_addr_0 = csk->ha[0];
  1754. conn_addr->remote_addr_1 = csk->ha[1];
  1755. conn_addr->remote_addr_2 = csk->ha[2];
  1756. conn_addr->remote_addr_3 = csk->ha[3];
  1757. conn_addr->remote_addr_4 = csk->ha[4];
  1758. conn_addr->remote_addr_5 = csk->ha[5];
  1759. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1760. struct l4_kwq_connect_req2 *kwqe2 =
  1761. (struct l4_kwq_connect_req2 *) wqes[1];
  1762. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1763. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1764. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1765. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1766. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1767. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1768. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1769. }
  1770. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1771. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1772. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1773. conn_addr->local_tcp_port = kwqe1->src_port;
  1774. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1775. conn_addr->pmtu = kwqe3->pmtu;
  1776. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1777. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1778. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1779. cnic_bnx2x_set_tcp_timestamp(dev,
  1780. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1781. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1782. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1783. if (!ret)
  1784. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1785. return ret;
  1786. }
  1787. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1788. {
  1789. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1790. union l5cm_specific_data l5_data;
  1791. int ret;
  1792. memset(&l5_data, 0, sizeof(l5_data));
  1793. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1794. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1795. return ret;
  1796. }
  1797. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1798. {
  1799. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1800. union l5cm_specific_data l5_data;
  1801. int ret;
  1802. memset(&l5_data, 0, sizeof(l5_data));
  1803. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1804. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1805. return ret;
  1806. }
  1807. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1808. {
  1809. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1810. struct l4_kcq kcqe;
  1811. struct kcqe *cqes[1];
  1812. memset(&kcqe, 0, sizeof(kcqe));
  1813. kcqe.pg_host_opaque = req->host_opaque;
  1814. kcqe.pg_cid = req->host_opaque;
  1815. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1816. cqes[0] = (struct kcqe *) &kcqe;
  1817. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1818. return 0;
  1819. }
  1820. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1821. {
  1822. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1823. struct l4_kcq kcqe;
  1824. struct kcqe *cqes[1];
  1825. memset(&kcqe, 0, sizeof(kcqe));
  1826. kcqe.pg_host_opaque = req->pg_host_opaque;
  1827. kcqe.pg_cid = req->pg_cid;
  1828. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1829. cqes[0] = (struct kcqe *) &kcqe;
  1830. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1831. return 0;
  1832. }
  1833. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1834. {
  1835. struct fcoe_kwqe_stat *req;
  1836. struct fcoe_stat_ramrod_params *fcoe_stat;
  1837. union l5cm_specific_data l5_data;
  1838. struct cnic_local *cp = dev->cnic_priv;
  1839. int ret;
  1840. u32 cid;
  1841. req = (struct fcoe_kwqe_stat *) kwqe;
  1842. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1843. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1844. if (!fcoe_stat)
  1845. return -ENOMEM;
  1846. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1847. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1848. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1849. FCOE_CONNECTION_TYPE, &l5_data);
  1850. return ret;
  1851. }
  1852. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1853. u32 num, int *work)
  1854. {
  1855. int ret;
  1856. struct cnic_local *cp = dev->cnic_priv;
  1857. u32 cid;
  1858. struct fcoe_init_ramrod_params *fcoe_init;
  1859. struct fcoe_kwqe_init1 *req1;
  1860. struct fcoe_kwqe_init2 *req2;
  1861. struct fcoe_kwqe_init3 *req3;
  1862. union l5cm_specific_data l5_data;
  1863. if (num < 3) {
  1864. *work = num;
  1865. return -EINVAL;
  1866. }
  1867. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1868. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1869. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1870. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1871. *work = 1;
  1872. return -EINVAL;
  1873. }
  1874. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1875. *work = 2;
  1876. return -EINVAL;
  1877. }
  1878. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1879. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1880. return -ENOMEM;
  1881. }
  1882. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1883. if (!fcoe_init)
  1884. return -ENOMEM;
  1885. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1886. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1887. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1888. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1889. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1890. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1891. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1892. fcoe_init->sb_num = cp->status_blk_num;
  1893. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1894. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1895. cp->kcq2.sw_prod_idx = 0;
  1896. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1897. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1898. FCOE_CONNECTION_TYPE, &l5_data);
  1899. *work = 3;
  1900. return ret;
  1901. }
  1902. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1903. u32 num, int *work)
  1904. {
  1905. int ret = 0;
  1906. u32 cid = -1, l5_cid;
  1907. struct cnic_local *cp = dev->cnic_priv;
  1908. struct fcoe_kwqe_conn_offload1 *req1;
  1909. struct fcoe_kwqe_conn_offload2 *req2;
  1910. struct fcoe_kwqe_conn_offload3 *req3;
  1911. struct fcoe_kwqe_conn_offload4 *req4;
  1912. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1913. struct cnic_context *ctx;
  1914. struct fcoe_context *fctx;
  1915. struct regpair ctx_addr;
  1916. union l5cm_specific_data l5_data;
  1917. struct fcoe_kcqe kcqe;
  1918. struct kcqe *cqes[1];
  1919. if (num < 4) {
  1920. *work = num;
  1921. return -EINVAL;
  1922. }
  1923. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1924. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1925. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1926. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1927. *work = 4;
  1928. l5_cid = req1->fcoe_conn_id;
  1929. if (l5_cid >= dev->max_fcoe_conn)
  1930. goto err_reply;
  1931. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1932. ctx = &cp->ctx_tbl[l5_cid];
  1933. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1934. goto err_reply;
  1935. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1936. if (ret) {
  1937. ret = 0;
  1938. goto err_reply;
  1939. }
  1940. cid = ctx->cid;
  1941. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1942. if (fctx) {
  1943. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1944. u32 val;
  1945. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1946. FCOE_CONNECTION_TYPE);
  1947. fctx->xstorm_ag_context.cdu_reserved = val;
  1948. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1949. FCOE_CONNECTION_TYPE);
  1950. fctx->ustorm_ag_context.cdu_usage = val;
  1951. }
  1952. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1953. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1954. goto err_reply;
  1955. }
  1956. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1957. if (!fcoe_offload)
  1958. goto err_reply;
  1959. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1960. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1961. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1962. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1963. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1964. cid = BNX2X_HW_CID(cp, cid);
  1965. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1966. FCOE_CONNECTION_TYPE, &l5_data);
  1967. if (!ret)
  1968. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1969. return ret;
  1970. err_reply:
  1971. if (cid != -1)
  1972. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1973. memset(&kcqe, 0, sizeof(kcqe));
  1974. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1975. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1976. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1977. cqes[0] = (struct kcqe *) &kcqe;
  1978. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1979. return ret;
  1980. }
  1981. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1982. {
  1983. struct fcoe_kwqe_conn_enable_disable *req;
  1984. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1985. union l5cm_specific_data l5_data;
  1986. int ret;
  1987. u32 cid, l5_cid;
  1988. struct cnic_local *cp = dev->cnic_priv;
  1989. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1990. cid = req->context_id;
  1991. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1992. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1993. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1994. return -ENOMEM;
  1995. }
  1996. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1997. if (!fcoe_enable)
  1998. return -ENOMEM;
  1999. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2000. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2001. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2002. FCOE_CONNECTION_TYPE, &l5_data);
  2003. return ret;
  2004. }
  2005. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2006. {
  2007. struct fcoe_kwqe_conn_enable_disable *req;
  2008. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2009. union l5cm_specific_data l5_data;
  2010. int ret;
  2011. u32 cid, l5_cid;
  2012. struct cnic_local *cp = dev->cnic_priv;
  2013. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2014. cid = req->context_id;
  2015. l5_cid = req->conn_id;
  2016. if (l5_cid >= dev->max_fcoe_conn)
  2017. return -EINVAL;
  2018. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2019. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2020. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2021. return -ENOMEM;
  2022. }
  2023. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2024. if (!fcoe_disable)
  2025. return -ENOMEM;
  2026. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2027. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2028. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2029. FCOE_CONNECTION_TYPE, &l5_data);
  2030. return ret;
  2031. }
  2032. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2033. {
  2034. struct fcoe_kwqe_conn_destroy *req;
  2035. union l5cm_specific_data l5_data;
  2036. int ret;
  2037. u32 cid, l5_cid;
  2038. struct cnic_local *cp = dev->cnic_priv;
  2039. struct cnic_context *ctx;
  2040. struct fcoe_kcqe kcqe;
  2041. struct kcqe *cqes[1];
  2042. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2043. cid = req->context_id;
  2044. l5_cid = req->conn_id;
  2045. if (l5_cid >= dev->max_fcoe_conn)
  2046. return -EINVAL;
  2047. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2048. ctx = &cp->ctx_tbl[l5_cid];
  2049. init_waitqueue_head(&ctx->waitq);
  2050. ctx->wait_cond = 0;
  2051. memset(&kcqe, 0, sizeof(kcqe));
  2052. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2053. memset(&l5_data, 0, sizeof(l5_data));
  2054. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2055. FCOE_CONNECTION_TYPE, &l5_data);
  2056. if (ret == 0) {
  2057. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2058. if (ctx->wait_cond)
  2059. kcqe.completion_status = 0;
  2060. }
  2061. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2062. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2063. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2064. kcqe.fcoe_conn_id = req->conn_id;
  2065. kcqe.fcoe_conn_context_id = cid;
  2066. cqes[0] = (struct kcqe *) &kcqe;
  2067. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2068. return ret;
  2069. }
  2070. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2071. {
  2072. struct cnic_local *cp = dev->cnic_priv;
  2073. u32 i;
  2074. for (i = start_cid; i < cp->max_cid_space; i++) {
  2075. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2076. int j;
  2077. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2078. msleep(10);
  2079. for (j = 0; j < 5; j++) {
  2080. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2081. break;
  2082. msleep(20);
  2083. }
  2084. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2085. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2086. ctx->cid);
  2087. }
  2088. }
  2089. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2090. {
  2091. struct fcoe_kwqe_destroy *req;
  2092. union l5cm_specific_data l5_data;
  2093. struct cnic_local *cp = dev->cnic_priv;
  2094. int ret;
  2095. u32 cid;
  2096. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2097. req = (struct fcoe_kwqe_destroy *) kwqe;
  2098. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2099. memset(&l5_data, 0, sizeof(l5_data));
  2100. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2101. FCOE_CONNECTION_TYPE, &l5_data);
  2102. return ret;
  2103. }
  2104. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2105. {
  2106. struct cnic_local *cp = dev->cnic_priv;
  2107. struct kcqe kcqe;
  2108. struct kcqe *cqes[1];
  2109. u32 cid;
  2110. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2111. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2112. u32 kcqe_op;
  2113. int ulp_type;
  2114. cid = kwqe->kwqe_info0;
  2115. memset(&kcqe, 0, sizeof(kcqe));
  2116. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2117. u32 l5_cid = 0;
  2118. ulp_type = CNIC_ULP_FCOE;
  2119. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2120. struct fcoe_kwqe_conn_enable_disable *req;
  2121. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2122. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2123. cid = req->context_id;
  2124. l5_cid = req->conn_id;
  2125. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2126. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2127. } else {
  2128. return;
  2129. }
  2130. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2131. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2132. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2133. kcqe.kcqe_info2 = cid;
  2134. kcqe.kcqe_info0 = l5_cid;
  2135. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2136. ulp_type = CNIC_ULP_ISCSI;
  2137. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2138. cid = kwqe->kwqe_info1;
  2139. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2140. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2141. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2142. kcqe.kcqe_info2 = cid;
  2143. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2144. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2145. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2146. ulp_type = CNIC_ULP_L4;
  2147. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2148. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2149. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2150. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2151. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2152. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2153. else
  2154. return;
  2155. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2156. KCQE_FLAGS_LAYER_MASK_L4;
  2157. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2158. l4kcqe->cid = cid;
  2159. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2160. } else {
  2161. return;
  2162. }
  2163. cqes[0] = &kcqe;
  2164. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2165. }
  2166. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2167. struct kwqe *wqes[], u32 num_wqes)
  2168. {
  2169. int i, work, ret;
  2170. u32 opcode;
  2171. struct kwqe *kwqe;
  2172. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2173. return -EAGAIN; /* bnx2 is down */
  2174. for (i = 0; i < num_wqes; ) {
  2175. kwqe = wqes[i];
  2176. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2177. work = 1;
  2178. switch (opcode) {
  2179. case ISCSI_KWQE_OPCODE_INIT1:
  2180. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2181. break;
  2182. case ISCSI_KWQE_OPCODE_INIT2:
  2183. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2184. break;
  2185. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2186. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2187. num_wqes - i, &work);
  2188. break;
  2189. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2190. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2191. break;
  2192. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2193. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2194. break;
  2195. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2196. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2197. &work);
  2198. break;
  2199. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2200. ret = cnic_bnx2x_close(dev, kwqe);
  2201. break;
  2202. case L4_KWQE_OPCODE_VALUE_RESET:
  2203. ret = cnic_bnx2x_reset(dev, kwqe);
  2204. break;
  2205. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2206. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2207. break;
  2208. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2209. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2210. break;
  2211. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2212. ret = 0;
  2213. break;
  2214. default:
  2215. ret = 0;
  2216. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2217. opcode);
  2218. break;
  2219. }
  2220. if (ret < 0) {
  2221. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2222. opcode);
  2223. /* Possibly bnx2x parity error, send completion
  2224. * to ulp drivers with error code to speed up
  2225. * cleanup and reset recovery.
  2226. */
  2227. if (ret == -EIO || ret == -EAGAIN)
  2228. cnic_bnx2x_kwqe_err(dev, kwqe);
  2229. }
  2230. i += work;
  2231. }
  2232. return 0;
  2233. }
  2234. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2235. struct kwqe *wqes[], u32 num_wqes)
  2236. {
  2237. struct cnic_local *cp = dev->cnic_priv;
  2238. int i, work, ret;
  2239. u32 opcode;
  2240. struct kwqe *kwqe;
  2241. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2242. return -EAGAIN; /* bnx2 is down */
  2243. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2244. return -EINVAL;
  2245. for (i = 0; i < num_wqes; ) {
  2246. kwqe = wqes[i];
  2247. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2248. work = 1;
  2249. switch (opcode) {
  2250. case FCOE_KWQE_OPCODE_INIT1:
  2251. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2252. num_wqes - i, &work);
  2253. break;
  2254. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2255. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2256. num_wqes - i, &work);
  2257. break;
  2258. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2259. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2260. break;
  2261. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2262. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2263. break;
  2264. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2265. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2266. break;
  2267. case FCOE_KWQE_OPCODE_DESTROY:
  2268. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2269. break;
  2270. case FCOE_KWQE_OPCODE_STAT:
  2271. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2272. break;
  2273. default:
  2274. ret = 0;
  2275. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2276. opcode);
  2277. break;
  2278. }
  2279. if (ret < 0) {
  2280. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2281. opcode);
  2282. /* Possibly bnx2x parity error, send completion
  2283. * to ulp drivers with error code to speed up
  2284. * cleanup and reset recovery.
  2285. */
  2286. if (ret == -EIO || ret == -EAGAIN)
  2287. cnic_bnx2x_kwqe_err(dev, kwqe);
  2288. }
  2289. i += work;
  2290. }
  2291. return 0;
  2292. }
  2293. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2294. u32 num_wqes)
  2295. {
  2296. int ret = -EINVAL;
  2297. u32 layer_code;
  2298. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2299. return -EAGAIN; /* bnx2x is down */
  2300. if (!num_wqes)
  2301. return 0;
  2302. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2303. switch (layer_code) {
  2304. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2305. case KWQE_FLAGS_LAYER_MASK_L4:
  2306. case KWQE_FLAGS_LAYER_MASK_L2:
  2307. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2308. break;
  2309. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2310. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2311. break;
  2312. }
  2313. return ret;
  2314. }
  2315. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2316. {
  2317. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2318. return KCQE_FLAGS_LAYER_MASK_L4;
  2319. return opflag & KCQE_FLAGS_LAYER_MASK;
  2320. }
  2321. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2322. {
  2323. struct cnic_local *cp = dev->cnic_priv;
  2324. int i, j, comp = 0;
  2325. i = 0;
  2326. j = 1;
  2327. while (num_cqes) {
  2328. struct cnic_ulp_ops *ulp_ops;
  2329. int ulp_type;
  2330. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2331. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2332. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2333. comp++;
  2334. while (j < num_cqes) {
  2335. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2336. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2337. break;
  2338. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2339. comp++;
  2340. j++;
  2341. }
  2342. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2343. ulp_type = CNIC_ULP_RDMA;
  2344. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2345. ulp_type = CNIC_ULP_ISCSI;
  2346. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2347. ulp_type = CNIC_ULP_FCOE;
  2348. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2349. ulp_type = CNIC_ULP_L4;
  2350. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2351. goto end;
  2352. else {
  2353. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2354. kcqe_op_flag);
  2355. goto end;
  2356. }
  2357. rcu_read_lock();
  2358. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2359. if (likely(ulp_ops)) {
  2360. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2361. cp->completed_kcq + i, j);
  2362. }
  2363. rcu_read_unlock();
  2364. end:
  2365. num_cqes -= j;
  2366. i += j;
  2367. j = 1;
  2368. }
  2369. if (unlikely(comp))
  2370. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2371. }
  2372. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2373. {
  2374. struct cnic_local *cp = dev->cnic_priv;
  2375. u16 i, ri, hw_prod, last;
  2376. struct kcqe *kcqe;
  2377. int kcqe_cnt = 0, last_cnt = 0;
  2378. i = ri = last = info->sw_prod_idx;
  2379. ri &= MAX_KCQ_IDX;
  2380. hw_prod = *info->hw_prod_idx_ptr;
  2381. hw_prod = info->hw_idx(hw_prod);
  2382. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2383. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2384. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2385. i = info->next_idx(i);
  2386. ri = i & MAX_KCQ_IDX;
  2387. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2388. last_cnt = kcqe_cnt;
  2389. last = i;
  2390. }
  2391. }
  2392. info->sw_prod_idx = last;
  2393. return last_cnt;
  2394. }
  2395. static int cnic_l2_completion(struct cnic_local *cp)
  2396. {
  2397. u16 hw_cons, sw_cons;
  2398. struct cnic_uio_dev *udev = cp->udev;
  2399. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2400. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2401. u32 cmd;
  2402. int comp = 0;
  2403. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2404. return 0;
  2405. hw_cons = *cp->rx_cons_ptr;
  2406. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2407. hw_cons++;
  2408. sw_cons = cp->rx_cons;
  2409. while (sw_cons != hw_cons) {
  2410. u8 cqe_fp_flags;
  2411. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2412. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2413. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2414. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2415. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2416. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2417. cmd == RAMROD_CMD_ID_ETH_HALT)
  2418. comp++;
  2419. }
  2420. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2421. }
  2422. return comp;
  2423. }
  2424. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2425. {
  2426. u16 rx_cons, tx_cons;
  2427. int comp = 0;
  2428. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2429. return;
  2430. rx_cons = *cp->rx_cons_ptr;
  2431. tx_cons = *cp->tx_cons_ptr;
  2432. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2433. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2434. comp = cnic_l2_completion(cp);
  2435. cp->tx_cons = tx_cons;
  2436. cp->rx_cons = rx_cons;
  2437. if (cp->udev)
  2438. uio_event_notify(&cp->udev->cnic_uinfo);
  2439. }
  2440. if (comp)
  2441. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2442. }
  2443. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2444. {
  2445. struct cnic_local *cp = dev->cnic_priv;
  2446. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2447. int kcqe_cnt;
  2448. /* status block index must be read before reading other fields */
  2449. rmb();
  2450. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2451. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2452. service_kcqes(dev, kcqe_cnt);
  2453. /* Tell compiler that status_blk fields can change. */
  2454. barrier();
  2455. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2456. /* status block index must be read first */
  2457. rmb();
  2458. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2459. }
  2460. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2461. cnic_chk_pkt_rings(cp);
  2462. return status_idx;
  2463. }
  2464. static int cnic_service_bnx2(void *data, void *status_blk)
  2465. {
  2466. struct cnic_dev *dev = data;
  2467. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2468. struct status_block *sblk = status_blk;
  2469. return sblk->status_idx;
  2470. }
  2471. return cnic_service_bnx2_queues(dev);
  2472. }
  2473. static void cnic_service_bnx2_msix(unsigned long data)
  2474. {
  2475. struct cnic_dev *dev = (struct cnic_dev *) data;
  2476. struct cnic_local *cp = dev->cnic_priv;
  2477. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2478. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2479. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2480. }
  2481. static void cnic_doirq(struct cnic_dev *dev)
  2482. {
  2483. struct cnic_local *cp = dev->cnic_priv;
  2484. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2485. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2486. prefetch(cp->status_blk.gen);
  2487. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2488. tasklet_schedule(&cp->cnic_irq_task);
  2489. }
  2490. }
  2491. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2492. {
  2493. struct cnic_dev *dev = dev_instance;
  2494. struct cnic_local *cp = dev->cnic_priv;
  2495. if (cp->ack_int)
  2496. cp->ack_int(dev);
  2497. cnic_doirq(dev);
  2498. return IRQ_HANDLED;
  2499. }
  2500. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2501. u16 index, u8 op, u8 update)
  2502. {
  2503. struct cnic_local *cp = dev->cnic_priv;
  2504. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2505. COMMAND_REG_INT_ACK);
  2506. struct igu_ack_register igu_ack;
  2507. igu_ack.status_block_index = index;
  2508. igu_ack.sb_id_and_flags =
  2509. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2510. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2511. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2512. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2513. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2514. }
  2515. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2516. u16 index, u8 op, u8 update)
  2517. {
  2518. struct igu_regular cmd_data;
  2519. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2520. cmd_data.sb_id_and_flags =
  2521. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2522. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2523. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2524. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2525. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2526. }
  2527. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2528. {
  2529. struct cnic_local *cp = dev->cnic_priv;
  2530. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2531. IGU_INT_DISABLE, 0);
  2532. }
  2533. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2534. {
  2535. struct cnic_local *cp = dev->cnic_priv;
  2536. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2537. IGU_INT_DISABLE, 0);
  2538. }
  2539. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2540. {
  2541. u32 last_status = *info->status_idx_ptr;
  2542. int kcqe_cnt;
  2543. /* status block index must be read before reading the KCQ */
  2544. rmb();
  2545. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2546. service_kcqes(dev, kcqe_cnt);
  2547. /* Tell compiler that sblk fields can change. */
  2548. barrier();
  2549. last_status = *info->status_idx_ptr;
  2550. /* status block index must be read before reading the KCQ */
  2551. rmb();
  2552. }
  2553. return last_status;
  2554. }
  2555. static void cnic_service_bnx2x_bh(unsigned long data)
  2556. {
  2557. struct cnic_dev *dev = (struct cnic_dev *) data;
  2558. struct cnic_local *cp = dev->cnic_priv;
  2559. u32 status_idx, new_status_idx;
  2560. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2561. return;
  2562. while (1) {
  2563. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2564. CNIC_WR16(dev, cp->kcq1.io_addr,
  2565. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2566. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2567. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2568. status_idx, IGU_INT_ENABLE, 1);
  2569. break;
  2570. }
  2571. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2572. if (new_status_idx != status_idx)
  2573. continue;
  2574. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2575. MAX_KCQ_IDX);
  2576. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2577. status_idx, IGU_INT_ENABLE, 1);
  2578. break;
  2579. }
  2580. }
  2581. static int cnic_service_bnx2x(void *data, void *status_blk)
  2582. {
  2583. struct cnic_dev *dev = data;
  2584. struct cnic_local *cp = dev->cnic_priv;
  2585. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2586. cnic_doirq(dev);
  2587. cnic_chk_pkt_rings(cp);
  2588. return 0;
  2589. }
  2590. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2591. {
  2592. struct cnic_ulp_ops *ulp_ops;
  2593. if (if_type == CNIC_ULP_ISCSI)
  2594. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2595. mutex_lock(&cnic_lock);
  2596. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2597. lockdep_is_held(&cnic_lock));
  2598. if (!ulp_ops) {
  2599. mutex_unlock(&cnic_lock);
  2600. return;
  2601. }
  2602. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2603. mutex_unlock(&cnic_lock);
  2604. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2605. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2606. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2607. }
  2608. static void cnic_ulp_stop(struct cnic_dev *dev)
  2609. {
  2610. struct cnic_local *cp = dev->cnic_priv;
  2611. int if_type;
  2612. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2613. cnic_ulp_stop_one(cp, if_type);
  2614. }
  2615. static void cnic_ulp_start(struct cnic_dev *dev)
  2616. {
  2617. struct cnic_local *cp = dev->cnic_priv;
  2618. int if_type;
  2619. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2620. struct cnic_ulp_ops *ulp_ops;
  2621. mutex_lock(&cnic_lock);
  2622. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2623. lockdep_is_held(&cnic_lock));
  2624. if (!ulp_ops || !ulp_ops->cnic_start) {
  2625. mutex_unlock(&cnic_lock);
  2626. continue;
  2627. }
  2628. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2629. mutex_unlock(&cnic_lock);
  2630. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2631. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2632. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2633. }
  2634. }
  2635. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2636. {
  2637. struct cnic_local *cp = dev->cnic_priv;
  2638. struct cnic_ulp_ops *ulp_ops;
  2639. int rc;
  2640. mutex_lock(&cnic_lock);
  2641. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2642. if (ulp_ops && ulp_ops->cnic_get_stats)
  2643. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2644. else
  2645. rc = -ENODEV;
  2646. mutex_unlock(&cnic_lock);
  2647. return rc;
  2648. }
  2649. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2650. {
  2651. struct cnic_dev *dev = data;
  2652. int ulp_type = CNIC_ULP_ISCSI;
  2653. switch (info->cmd) {
  2654. case CNIC_CTL_STOP_CMD:
  2655. cnic_hold(dev);
  2656. cnic_ulp_stop(dev);
  2657. cnic_stop_hw(dev);
  2658. cnic_put(dev);
  2659. break;
  2660. case CNIC_CTL_START_CMD:
  2661. cnic_hold(dev);
  2662. if (!cnic_start_hw(dev))
  2663. cnic_ulp_start(dev);
  2664. cnic_put(dev);
  2665. break;
  2666. case CNIC_CTL_STOP_ISCSI_CMD: {
  2667. struct cnic_local *cp = dev->cnic_priv;
  2668. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2669. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2670. break;
  2671. }
  2672. case CNIC_CTL_COMPLETION_CMD: {
  2673. struct cnic_ctl_completion *comp = &info->data.comp;
  2674. u32 cid = BNX2X_SW_CID(comp->cid);
  2675. u32 l5_cid;
  2676. struct cnic_local *cp = dev->cnic_priv;
  2677. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2678. break;
  2679. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2680. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2681. if (unlikely(comp->error)) {
  2682. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2683. netdev_err(dev->netdev,
  2684. "CID %x CFC delete comp error %x\n",
  2685. cid, comp->error);
  2686. }
  2687. ctx->wait_cond = 1;
  2688. wake_up(&ctx->waitq);
  2689. }
  2690. break;
  2691. }
  2692. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2693. ulp_type = CNIC_ULP_FCOE;
  2694. /* fall through */
  2695. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2696. cnic_hold(dev);
  2697. cnic_copy_ulp_stats(dev, ulp_type);
  2698. cnic_put(dev);
  2699. break;
  2700. default:
  2701. return -EINVAL;
  2702. }
  2703. return 0;
  2704. }
  2705. static void cnic_ulp_init(struct cnic_dev *dev)
  2706. {
  2707. int i;
  2708. struct cnic_local *cp = dev->cnic_priv;
  2709. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2710. struct cnic_ulp_ops *ulp_ops;
  2711. mutex_lock(&cnic_lock);
  2712. ulp_ops = cnic_ulp_tbl_prot(i);
  2713. if (!ulp_ops || !ulp_ops->cnic_init) {
  2714. mutex_unlock(&cnic_lock);
  2715. continue;
  2716. }
  2717. ulp_get(ulp_ops);
  2718. mutex_unlock(&cnic_lock);
  2719. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2720. ulp_ops->cnic_init(dev);
  2721. ulp_put(ulp_ops);
  2722. }
  2723. }
  2724. static void cnic_ulp_exit(struct cnic_dev *dev)
  2725. {
  2726. int i;
  2727. struct cnic_local *cp = dev->cnic_priv;
  2728. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2729. struct cnic_ulp_ops *ulp_ops;
  2730. mutex_lock(&cnic_lock);
  2731. ulp_ops = cnic_ulp_tbl_prot(i);
  2732. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2733. mutex_unlock(&cnic_lock);
  2734. continue;
  2735. }
  2736. ulp_get(ulp_ops);
  2737. mutex_unlock(&cnic_lock);
  2738. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2739. ulp_ops->cnic_exit(dev);
  2740. ulp_put(ulp_ops);
  2741. }
  2742. }
  2743. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2744. {
  2745. struct cnic_dev *dev = csk->dev;
  2746. struct l4_kwq_offload_pg *l4kwqe;
  2747. struct kwqe *wqes[1];
  2748. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2749. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2750. wqes[0] = (struct kwqe *) l4kwqe;
  2751. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2752. l4kwqe->flags =
  2753. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2754. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2755. l4kwqe->da0 = csk->ha[0];
  2756. l4kwqe->da1 = csk->ha[1];
  2757. l4kwqe->da2 = csk->ha[2];
  2758. l4kwqe->da3 = csk->ha[3];
  2759. l4kwqe->da4 = csk->ha[4];
  2760. l4kwqe->da5 = csk->ha[5];
  2761. l4kwqe->sa0 = dev->mac_addr[0];
  2762. l4kwqe->sa1 = dev->mac_addr[1];
  2763. l4kwqe->sa2 = dev->mac_addr[2];
  2764. l4kwqe->sa3 = dev->mac_addr[3];
  2765. l4kwqe->sa4 = dev->mac_addr[4];
  2766. l4kwqe->sa5 = dev->mac_addr[5];
  2767. l4kwqe->etype = ETH_P_IP;
  2768. l4kwqe->ipid_start = DEF_IPID_START;
  2769. l4kwqe->host_opaque = csk->l5_cid;
  2770. if (csk->vlan_id) {
  2771. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2772. l4kwqe->vlan_tag = csk->vlan_id;
  2773. l4kwqe->l2hdr_nbytes += 4;
  2774. }
  2775. return dev->submit_kwqes(dev, wqes, 1);
  2776. }
  2777. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2778. {
  2779. struct cnic_dev *dev = csk->dev;
  2780. struct l4_kwq_update_pg *l4kwqe;
  2781. struct kwqe *wqes[1];
  2782. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2783. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2784. wqes[0] = (struct kwqe *) l4kwqe;
  2785. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2786. l4kwqe->flags =
  2787. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2788. l4kwqe->pg_cid = csk->pg_cid;
  2789. l4kwqe->da0 = csk->ha[0];
  2790. l4kwqe->da1 = csk->ha[1];
  2791. l4kwqe->da2 = csk->ha[2];
  2792. l4kwqe->da3 = csk->ha[3];
  2793. l4kwqe->da4 = csk->ha[4];
  2794. l4kwqe->da5 = csk->ha[5];
  2795. l4kwqe->pg_host_opaque = csk->l5_cid;
  2796. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2797. return dev->submit_kwqes(dev, wqes, 1);
  2798. }
  2799. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2800. {
  2801. struct cnic_dev *dev = csk->dev;
  2802. struct l4_kwq_upload *l4kwqe;
  2803. struct kwqe *wqes[1];
  2804. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2805. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2806. wqes[0] = (struct kwqe *) l4kwqe;
  2807. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2808. l4kwqe->flags =
  2809. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2810. l4kwqe->cid = csk->pg_cid;
  2811. return dev->submit_kwqes(dev, wqes, 1);
  2812. }
  2813. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2814. {
  2815. struct cnic_dev *dev = csk->dev;
  2816. struct l4_kwq_connect_req1 *l4kwqe1;
  2817. struct l4_kwq_connect_req2 *l4kwqe2;
  2818. struct l4_kwq_connect_req3 *l4kwqe3;
  2819. struct kwqe *wqes[3];
  2820. u8 tcp_flags = 0;
  2821. int num_wqes = 2;
  2822. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2823. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2824. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2825. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2826. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2827. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2828. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2829. l4kwqe3->flags =
  2830. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2831. l4kwqe3->ka_timeout = csk->ka_timeout;
  2832. l4kwqe3->ka_interval = csk->ka_interval;
  2833. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2834. l4kwqe3->tos = csk->tos;
  2835. l4kwqe3->ttl = csk->ttl;
  2836. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2837. l4kwqe3->pmtu = csk->mtu;
  2838. l4kwqe3->rcv_buf = csk->rcv_buf;
  2839. l4kwqe3->snd_buf = csk->snd_buf;
  2840. l4kwqe3->seed = csk->seed;
  2841. wqes[0] = (struct kwqe *) l4kwqe1;
  2842. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2843. wqes[1] = (struct kwqe *) l4kwqe2;
  2844. wqes[2] = (struct kwqe *) l4kwqe3;
  2845. num_wqes = 3;
  2846. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2847. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2848. l4kwqe2->flags =
  2849. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2850. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2851. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2852. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2853. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2854. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2855. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2856. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2857. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2858. sizeof(struct tcphdr);
  2859. } else {
  2860. wqes[1] = (struct kwqe *) l4kwqe3;
  2861. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2862. sizeof(struct tcphdr);
  2863. }
  2864. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2865. l4kwqe1->flags =
  2866. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2867. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2868. l4kwqe1->cid = csk->cid;
  2869. l4kwqe1->pg_cid = csk->pg_cid;
  2870. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2871. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2872. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2873. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2874. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2875. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2876. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2877. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2878. if (csk->tcp_flags & SK_TCP_NAGLE)
  2879. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2880. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2881. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2882. if (csk->tcp_flags & SK_TCP_SACK)
  2883. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2884. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2885. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2886. l4kwqe1->tcp_flags = tcp_flags;
  2887. return dev->submit_kwqes(dev, wqes, num_wqes);
  2888. }
  2889. static int cnic_cm_close_req(struct cnic_sock *csk)
  2890. {
  2891. struct cnic_dev *dev = csk->dev;
  2892. struct l4_kwq_close_req *l4kwqe;
  2893. struct kwqe *wqes[1];
  2894. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2895. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2896. wqes[0] = (struct kwqe *) l4kwqe;
  2897. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2898. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2899. l4kwqe->cid = csk->cid;
  2900. return dev->submit_kwqes(dev, wqes, 1);
  2901. }
  2902. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2903. {
  2904. struct cnic_dev *dev = csk->dev;
  2905. struct l4_kwq_reset_req *l4kwqe;
  2906. struct kwqe *wqes[1];
  2907. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2908. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2909. wqes[0] = (struct kwqe *) l4kwqe;
  2910. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2911. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2912. l4kwqe->cid = csk->cid;
  2913. return dev->submit_kwqes(dev, wqes, 1);
  2914. }
  2915. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2916. u32 l5_cid, struct cnic_sock **csk, void *context)
  2917. {
  2918. struct cnic_local *cp = dev->cnic_priv;
  2919. struct cnic_sock *csk1;
  2920. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2921. return -EINVAL;
  2922. if (cp->ctx_tbl) {
  2923. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2924. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2925. return -EAGAIN;
  2926. }
  2927. csk1 = &cp->csk_tbl[l5_cid];
  2928. if (atomic_read(&csk1->ref_count))
  2929. return -EAGAIN;
  2930. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2931. return -EBUSY;
  2932. csk1->dev = dev;
  2933. csk1->cid = cid;
  2934. csk1->l5_cid = l5_cid;
  2935. csk1->ulp_type = ulp_type;
  2936. csk1->context = context;
  2937. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2938. csk1->ka_interval = DEF_KA_INTERVAL;
  2939. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2940. csk1->tos = DEF_TOS;
  2941. csk1->ttl = DEF_TTL;
  2942. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2943. csk1->rcv_buf = DEF_RCV_BUF;
  2944. csk1->snd_buf = DEF_SND_BUF;
  2945. csk1->seed = DEF_SEED;
  2946. *csk = csk1;
  2947. return 0;
  2948. }
  2949. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2950. {
  2951. if (csk->src_port) {
  2952. struct cnic_dev *dev = csk->dev;
  2953. struct cnic_local *cp = dev->cnic_priv;
  2954. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2955. csk->src_port = 0;
  2956. }
  2957. }
  2958. static void cnic_close_conn(struct cnic_sock *csk)
  2959. {
  2960. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2961. cnic_cm_upload_pg(csk);
  2962. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2963. }
  2964. cnic_cm_cleanup(csk);
  2965. }
  2966. static int cnic_cm_destroy(struct cnic_sock *csk)
  2967. {
  2968. if (!cnic_in_use(csk))
  2969. return -EINVAL;
  2970. csk_hold(csk);
  2971. clear_bit(SK_F_INUSE, &csk->flags);
  2972. smp_mb__after_clear_bit();
  2973. while (atomic_read(&csk->ref_count) != 1)
  2974. msleep(1);
  2975. cnic_cm_cleanup(csk);
  2976. csk->flags = 0;
  2977. csk_put(csk);
  2978. return 0;
  2979. }
  2980. static inline u16 cnic_get_vlan(struct net_device *dev,
  2981. struct net_device **vlan_dev)
  2982. {
  2983. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2984. *vlan_dev = vlan_dev_real_dev(dev);
  2985. return vlan_dev_vlan_id(dev);
  2986. }
  2987. *vlan_dev = dev;
  2988. return 0;
  2989. }
  2990. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2991. struct dst_entry **dst)
  2992. {
  2993. #if defined(CONFIG_INET)
  2994. struct rtable *rt;
  2995. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2996. if (!IS_ERR(rt)) {
  2997. *dst = &rt->dst;
  2998. return 0;
  2999. }
  3000. return PTR_ERR(rt);
  3001. #else
  3002. return -ENETUNREACH;
  3003. #endif
  3004. }
  3005. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3006. struct dst_entry **dst)
  3007. {
  3008. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  3009. struct flowi6 fl6;
  3010. memset(&fl6, 0, sizeof(fl6));
  3011. fl6.daddr = dst_addr->sin6_addr;
  3012. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3013. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3014. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3015. if ((*dst)->error) {
  3016. dst_release(*dst);
  3017. *dst = NULL;
  3018. return -ENETUNREACH;
  3019. } else
  3020. return 0;
  3021. #endif
  3022. return -ENETUNREACH;
  3023. }
  3024. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3025. int ulp_type)
  3026. {
  3027. struct cnic_dev *dev = NULL;
  3028. struct dst_entry *dst;
  3029. struct net_device *netdev = NULL;
  3030. int err = -ENETUNREACH;
  3031. if (dst_addr->sin_family == AF_INET)
  3032. err = cnic_get_v4_route(dst_addr, &dst);
  3033. else if (dst_addr->sin_family == AF_INET6) {
  3034. struct sockaddr_in6 *dst_addr6 =
  3035. (struct sockaddr_in6 *) dst_addr;
  3036. err = cnic_get_v6_route(dst_addr6, &dst);
  3037. } else
  3038. return NULL;
  3039. if (err)
  3040. return NULL;
  3041. if (!dst->dev)
  3042. goto done;
  3043. cnic_get_vlan(dst->dev, &netdev);
  3044. dev = cnic_from_netdev(netdev);
  3045. done:
  3046. dst_release(dst);
  3047. if (dev)
  3048. cnic_put(dev);
  3049. return dev;
  3050. }
  3051. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3052. {
  3053. struct cnic_dev *dev = csk->dev;
  3054. struct cnic_local *cp = dev->cnic_priv;
  3055. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3056. }
  3057. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3058. {
  3059. struct cnic_dev *dev = csk->dev;
  3060. struct cnic_local *cp = dev->cnic_priv;
  3061. int is_v6, rc = 0;
  3062. struct dst_entry *dst = NULL;
  3063. struct net_device *realdev;
  3064. __be16 local_port;
  3065. u32 port_id;
  3066. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3067. saddr->remote.v6.sin6_family == AF_INET6)
  3068. is_v6 = 1;
  3069. else if (saddr->local.v4.sin_family == AF_INET &&
  3070. saddr->remote.v4.sin_family == AF_INET)
  3071. is_v6 = 0;
  3072. else
  3073. return -EINVAL;
  3074. clear_bit(SK_F_IPV6, &csk->flags);
  3075. if (is_v6) {
  3076. set_bit(SK_F_IPV6, &csk->flags);
  3077. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3078. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3079. sizeof(struct in6_addr));
  3080. csk->dst_port = saddr->remote.v6.sin6_port;
  3081. local_port = saddr->local.v6.sin6_port;
  3082. } else {
  3083. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3084. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3085. csk->dst_port = saddr->remote.v4.sin_port;
  3086. local_port = saddr->local.v4.sin_port;
  3087. }
  3088. csk->vlan_id = 0;
  3089. csk->mtu = dev->netdev->mtu;
  3090. if (dst && dst->dev) {
  3091. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3092. if (realdev == dev->netdev) {
  3093. csk->vlan_id = vlan;
  3094. csk->mtu = dst_mtu(dst);
  3095. }
  3096. }
  3097. port_id = be16_to_cpu(local_port);
  3098. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3099. port_id < CNIC_LOCAL_PORT_MAX) {
  3100. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3101. port_id = 0;
  3102. } else
  3103. port_id = 0;
  3104. if (!port_id) {
  3105. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3106. if (port_id == -1) {
  3107. rc = -ENOMEM;
  3108. goto err_out;
  3109. }
  3110. local_port = cpu_to_be16(port_id);
  3111. }
  3112. csk->src_port = local_port;
  3113. err_out:
  3114. dst_release(dst);
  3115. return rc;
  3116. }
  3117. static void cnic_init_csk_state(struct cnic_sock *csk)
  3118. {
  3119. csk->state = 0;
  3120. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3121. clear_bit(SK_F_CLOSING, &csk->flags);
  3122. }
  3123. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3124. {
  3125. struct cnic_local *cp = csk->dev->cnic_priv;
  3126. int err = 0;
  3127. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3128. return -EOPNOTSUPP;
  3129. if (!cnic_in_use(csk))
  3130. return -EINVAL;
  3131. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3132. return -EINVAL;
  3133. cnic_init_csk_state(csk);
  3134. err = cnic_get_route(csk, saddr);
  3135. if (err)
  3136. goto err_out;
  3137. err = cnic_resolve_addr(csk, saddr);
  3138. if (!err)
  3139. return 0;
  3140. err_out:
  3141. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3142. return err;
  3143. }
  3144. static int cnic_cm_abort(struct cnic_sock *csk)
  3145. {
  3146. struct cnic_local *cp = csk->dev->cnic_priv;
  3147. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3148. if (!cnic_in_use(csk))
  3149. return -EINVAL;
  3150. if (cnic_abort_prep(csk))
  3151. return cnic_cm_abort_req(csk);
  3152. /* Getting here means that we haven't started connect, or
  3153. * connect was not successful.
  3154. */
  3155. cp->close_conn(csk, opcode);
  3156. if (csk->state != opcode)
  3157. return -EALREADY;
  3158. return 0;
  3159. }
  3160. static int cnic_cm_close(struct cnic_sock *csk)
  3161. {
  3162. if (!cnic_in_use(csk))
  3163. return -EINVAL;
  3164. if (cnic_close_prep(csk)) {
  3165. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3166. return cnic_cm_close_req(csk);
  3167. } else {
  3168. return -EALREADY;
  3169. }
  3170. return 0;
  3171. }
  3172. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3173. u8 opcode)
  3174. {
  3175. struct cnic_ulp_ops *ulp_ops;
  3176. int ulp_type = csk->ulp_type;
  3177. rcu_read_lock();
  3178. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3179. if (ulp_ops) {
  3180. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3181. ulp_ops->cm_connect_complete(csk);
  3182. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3183. ulp_ops->cm_close_complete(csk);
  3184. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3185. ulp_ops->cm_remote_abort(csk);
  3186. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3187. ulp_ops->cm_abort_complete(csk);
  3188. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3189. ulp_ops->cm_remote_close(csk);
  3190. }
  3191. rcu_read_unlock();
  3192. }
  3193. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3194. {
  3195. if (cnic_offld_prep(csk)) {
  3196. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3197. cnic_cm_update_pg(csk);
  3198. else
  3199. cnic_cm_offload_pg(csk);
  3200. }
  3201. return 0;
  3202. }
  3203. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3204. {
  3205. struct cnic_local *cp = dev->cnic_priv;
  3206. u32 l5_cid = kcqe->pg_host_opaque;
  3207. u8 opcode = kcqe->op_code;
  3208. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3209. csk_hold(csk);
  3210. if (!cnic_in_use(csk))
  3211. goto done;
  3212. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3213. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3214. goto done;
  3215. }
  3216. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3217. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3218. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3219. cnic_cm_upcall(cp, csk,
  3220. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3221. goto done;
  3222. }
  3223. csk->pg_cid = kcqe->pg_cid;
  3224. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3225. cnic_cm_conn_req(csk);
  3226. done:
  3227. csk_put(csk);
  3228. }
  3229. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3230. {
  3231. struct cnic_local *cp = dev->cnic_priv;
  3232. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3233. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3234. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3235. ctx->timestamp = jiffies;
  3236. ctx->wait_cond = 1;
  3237. wake_up(&ctx->waitq);
  3238. }
  3239. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3240. {
  3241. struct cnic_local *cp = dev->cnic_priv;
  3242. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3243. u8 opcode = l4kcqe->op_code;
  3244. u32 l5_cid;
  3245. struct cnic_sock *csk;
  3246. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3247. cnic_process_fcoe_term_conn(dev, kcqe);
  3248. return;
  3249. }
  3250. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3251. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3252. cnic_cm_process_offld_pg(dev, l4kcqe);
  3253. return;
  3254. }
  3255. l5_cid = l4kcqe->conn_id;
  3256. if (opcode & 0x80)
  3257. l5_cid = l4kcqe->cid;
  3258. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3259. return;
  3260. csk = &cp->csk_tbl[l5_cid];
  3261. csk_hold(csk);
  3262. if (!cnic_in_use(csk)) {
  3263. csk_put(csk);
  3264. return;
  3265. }
  3266. switch (opcode) {
  3267. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3268. if (l4kcqe->status != 0) {
  3269. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3270. cnic_cm_upcall(cp, csk,
  3271. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3272. }
  3273. break;
  3274. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3275. if (l4kcqe->status == 0)
  3276. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3277. else if (l4kcqe->status ==
  3278. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3279. set_bit(SK_F_HW_ERR, &csk->flags);
  3280. smp_mb__before_clear_bit();
  3281. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3282. cnic_cm_upcall(cp, csk, opcode);
  3283. break;
  3284. case L5CM_RAMROD_CMD_ID_CLOSE:
  3285. if (l4kcqe->status != 0) {
  3286. netdev_warn(dev->netdev, "RAMROD CLOSE compl with "
  3287. "status 0x%x\n", l4kcqe->status);
  3288. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3289. /* Fall through */
  3290. } else {
  3291. break;
  3292. }
  3293. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3294. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3295. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3296. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3297. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3298. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3299. set_bit(SK_F_HW_ERR, &csk->flags);
  3300. cp->close_conn(csk, opcode);
  3301. break;
  3302. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3303. /* after we already sent CLOSE_REQ */
  3304. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3305. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3306. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3307. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3308. else
  3309. cnic_cm_upcall(cp, csk, opcode);
  3310. break;
  3311. }
  3312. csk_put(csk);
  3313. }
  3314. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3315. {
  3316. struct cnic_dev *dev = data;
  3317. int i;
  3318. for (i = 0; i < num; i++)
  3319. cnic_cm_process_kcqe(dev, kcqe[i]);
  3320. }
  3321. static struct cnic_ulp_ops cm_ulp_ops = {
  3322. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3323. };
  3324. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3325. {
  3326. struct cnic_local *cp = dev->cnic_priv;
  3327. kfree(cp->csk_tbl);
  3328. cp->csk_tbl = NULL;
  3329. cnic_free_id_tbl(&cp->csk_port_tbl);
  3330. }
  3331. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3332. {
  3333. struct cnic_local *cp = dev->cnic_priv;
  3334. u32 port_id;
  3335. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3336. GFP_KERNEL);
  3337. if (!cp->csk_tbl)
  3338. return -ENOMEM;
  3339. port_id = random32();
  3340. port_id %= CNIC_LOCAL_PORT_RANGE;
  3341. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3342. CNIC_LOCAL_PORT_MIN, port_id)) {
  3343. cnic_cm_free_mem(dev);
  3344. return -ENOMEM;
  3345. }
  3346. return 0;
  3347. }
  3348. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3349. {
  3350. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3351. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3352. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3353. csk->state = opcode;
  3354. }
  3355. /* 1. If event opcode matches the expected event in csk->state
  3356. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3357. * event
  3358. * 3. If the expected event is 0, meaning the connection was never
  3359. * never established, we accept the opcode from cm_abort.
  3360. */
  3361. if (opcode == csk->state || csk->state == 0 ||
  3362. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3363. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3364. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3365. if (csk->state == 0)
  3366. csk->state = opcode;
  3367. return 1;
  3368. }
  3369. }
  3370. return 0;
  3371. }
  3372. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3373. {
  3374. struct cnic_dev *dev = csk->dev;
  3375. struct cnic_local *cp = dev->cnic_priv;
  3376. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3377. cnic_cm_upcall(cp, csk, opcode);
  3378. return;
  3379. }
  3380. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3381. cnic_close_conn(csk);
  3382. csk->state = opcode;
  3383. cnic_cm_upcall(cp, csk, opcode);
  3384. }
  3385. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3386. {
  3387. }
  3388. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3389. {
  3390. u32 seed;
  3391. seed = random32();
  3392. cnic_ctx_wr(dev, 45, 0, seed);
  3393. return 0;
  3394. }
  3395. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3396. {
  3397. struct cnic_dev *dev = csk->dev;
  3398. struct cnic_local *cp = dev->cnic_priv;
  3399. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3400. union l5cm_specific_data l5_data;
  3401. u32 cmd = 0;
  3402. int close_complete = 0;
  3403. switch (opcode) {
  3404. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3405. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3406. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3407. if (cnic_ready_to_close(csk, opcode)) {
  3408. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3409. close_complete = 1;
  3410. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3411. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3412. else
  3413. close_complete = 1;
  3414. }
  3415. break;
  3416. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3417. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3418. break;
  3419. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3420. close_complete = 1;
  3421. break;
  3422. }
  3423. if (cmd) {
  3424. memset(&l5_data, 0, sizeof(l5_data));
  3425. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3426. &l5_data);
  3427. } else if (close_complete) {
  3428. ctx->timestamp = jiffies;
  3429. cnic_close_conn(csk);
  3430. cnic_cm_upcall(cp, csk, csk->state);
  3431. }
  3432. }
  3433. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3434. {
  3435. struct cnic_local *cp = dev->cnic_priv;
  3436. if (!cp->ctx_tbl)
  3437. return;
  3438. if (!netif_running(dev->netdev))
  3439. return;
  3440. cnic_bnx2x_delete_wait(dev, 0);
  3441. cancel_delayed_work(&cp->delete_task);
  3442. flush_workqueue(cnic_wq);
  3443. if (atomic_read(&cp->iscsi_conn) != 0)
  3444. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3445. atomic_read(&cp->iscsi_conn));
  3446. }
  3447. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3448. {
  3449. struct cnic_local *cp = dev->cnic_priv;
  3450. u32 pfid = cp->pfid;
  3451. u32 port = CNIC_PORT(cp);
  3452. cnic_init_bnx2x_mac(dev);
  3453. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3454. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3455. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3456. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3457. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3458. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3459. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3460. DEF_MAX_DA_COUNT);
  3461. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3462. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3463. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3464. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3465. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3466. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3467. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3468. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3469. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3470. DEF_MAX_CWND);
  3471. return 0;
  3472. }
  3473. static void cnic_delete_task(struct work_struct *work)
  3474. {
  3475. struct cnic_local *cp;
  3476. struct cnic_dev *dev;
  3477. u32 i;
  3478. int need_resched = 0;
  3479. cp = container_of(work, struct cnic_local, delete_task.work);
  3480. dev = cp->dev;
  3481. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3482. struct drv_ctl_info info;
  3483. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3484. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3485. cp->ethdev->drv_ctl(dev->netdev, &info);
  3486. }
  3487. for (i = 0; i < cp->max_cid_space; i++) {
  3488. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3489. int err;
  3490. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3491. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3492. continue;
  3493. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3494. need_resched = 1;
  3495. continue;
  3496. }
  3497. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3498. continue;
  3499. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3500. cnic_free_bnx2x_conn_resc(dev, i);
  3501. if (!err) {
  3502. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3503. atomic_dec(&cp->iscsi_conn);
  3504. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3505. }
  3506. }
  3507. if (need_resched)
  3508. queue_delayed_work(cnic_wq, &cp->delete_task,
  3509. msecs_to_jiffies(10));
  3510. }
  3511. static int cnic_cm_open(struct cnic_dev *dev)
  3512. {
  3513. struct cnic_local *cp = dev->cnic_priv;
  3514. int err;
  3515. err = cnic_cm_alloc_mem(dev);
  3516. if (err)
  3517. return err;
  3518. err = cp->start_cm(dev);
  3519. if (err)
  3520. goto err_out;
  3521. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3522. dev->cm_create = cnic_cm_create;
  3523. dev->cm_destroy = cnic_cm_destroy;
  3524. dev->cm_connect = cnic_cm_connect;
  3525. dev->cm_abort = cnic_cm_abort;
  3526. dev->cm_close = cnic_cm_close;
  3527. dev->cm_select_dev = cnic_cm_select_dev;
  3528. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3529. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3530. return 0;
  3531. err_out:
  3532. cnic_cm_free_mem(dev);
  3533. return err;
  3534. }
  3535. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3536. {
  3537. struct cnic_local *cp = dev->cnic_priv;
  3538. int i;
  3539. if (!cp->csk_tbl)
  3540. return 0;
  3541. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3542. struct cnic_sock *csk = &cp->csk_tbl[i];
  3543. clear_bit(SK_F_INUSE, &csk->flags);
  3544. cnic_cm_cleanup(csk);
  3545. }
  3546. cnic_cm_free_mem(dev);
  3547. return 0;
  3548. }
  3549. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3550. {
  3551. u32 cid_addr;
  3552. int i;
  3553. cid_addr = GET_CID_ADDR(cid);
  3554. for (i = 0; i < CTX_SIZE; i += 4)
  3555. cnic_ctx_wr(dev, cid_addr, i, 0);
  3556. }
  3557. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3558. {
  3559. struct cnic_local *cp = dev->cnic_priv;
  3560. int ret = 0, i;
  3561. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3562. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3563. return 0;
  3564. for (i = 0; i < cp->ctx_blks; i++) {
  3565. int j;
  3566. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3567. u32 val;
  3568. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3569. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3570. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3571. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3572. (u64) cp->ctx_arr[i].mapping >> 32);
  3573. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3574. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3575. for (j = 0; j < 10; j++) {
  3576. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3577. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3578. break;
  3579. udelay(5);
  3580. }
  3581. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3582. ret = -EBUSY;
  3583. break;
  3584. }
  3585. }
  3586. return ret;
  3587. }
  3588. static void cnic_free_irq(struct cnic_dev *dev)
  3589. {
  3590. struct cnic_local *cp = dev->cnic_priv;
  3591. struct cnic_eth_dev *ethdev = cp->ethdev;
  3592. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3593. cp->disable_int_sync(dev);
  3594. tasklet_kill(&cp->cnic_irq_task);
  3595. free_irq(ethdev->irq_arr[0].vector, dev);
  3596. }
  3597. }
  3598. static int cnic_request_irq(struct cnic_dev *dev)
  3599. {
  3600. struct cnic_local *cp = dev->cnic_priv;
  3601. struct cnic_eth_dev *ethdev = cp->ethdev;
  3602. int err;
  3603. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3604. if (err)
  3605. tasklet_disable(&cp->cnic_irq_task);
  3606. return err;
  3607. }
  3608. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3609. {
  3610. struct cnic_local *cp = dev->cnic_priv;
  3611. struct cnic_eth_dev *ethdev = cp->ethdev;
  3612. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3613. int err, i = 0;
  3614. int sblk_num = cp->status_blk_num;
  3615. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3616. BNX2_HC_SB_CONFIG_1;
  3617. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3618. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3619. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3620. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3621. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3622. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3623. (unsigned long) dev);
  3624. err = cnic_request_irq(dev);
  3625. if (err)
  3626. return err;
  3627. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3628. i < 10) {
  3629. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3630. 1 << (11 + sblk_num));
  3631. udelay(10);
  3632. i++;
  3633. barrier();
  3634. }
  3635. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3636. cnic_free_irq(dev);
  3637. goto failed;
  3638. }
  3639. } else {
  3640. struct status_block *sblk = cp->status_blk.gen;
  3641. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3642. int i = 0;
  3643. while (sblk->status_completion_producer_index && i < 10) {
  3644. CNIC_WR(dev, BNX2_HC_COMMAND,
  3645. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3646. udelay(10);
  3647. i++;
  3648. barrier();
  3649. }
  3650. if (sblk->status_completion_producer_index)
  3651. goto failed;
  3652. }
  3653. return 0;
  3654. failed:
  3655. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3656. return -EBUSY;
  3657. }
  3658. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3659. {
  3660. struct cnic_local *cp = dev->cnic_priv;
  3661. struct cnic_eth_dev *ethdev = cp->ethdev;
  3662. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3663. return;
  3664. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3665. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3666. }
  3667. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3668. {
  3669. struct cnic_local *cp = dev->cnic_priv;
  3670. struct cnic_eth_dev *ethdev = cp->ethdev;
  3671. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3672. return;
  3673. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3674. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3675. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3676. synchronize_irq(ethdev->irq_arr[0].vector);
  3677. }
  3678. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3679. {
  3680. struct cnic_local *cp = dev->cnic_priv;
  3681. struct cnic_eth_dev *ethdev = cp->ethdev;
  3682. struct cnic_uio_dev *udev = cp->udev;
  3683. u32 cid_addr, tx_cid, sb_id;
  3684. u32 val, offset0, offset1, offset2, offset3;
  3685. int i;
  3686. struct tx_bd *txbd;
  3687. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3688. struct status_block *s_blk = cp->status_blk.gen;
  3689. sb_id = cp->status_blk_num;
  3690. tx_cid = 20;
  3691. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3692. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3693. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3694. tx_cid = TX_TSS_CID + sb_id - 1;
  3695. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3696. (TX_TSS_CID << 7));
  3697. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3698. }
  3699. cp->tx_cons = *cp->tx_cons_ptr;
  3700. cid_addr = GET_CID_ADDR(tx_cid);
  3701. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3702. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3703. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3704. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3705. offset0 = BNX2_L2CTX_TYPE_XI;
  3706. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3707. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3708. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3709. } else {
  3710. cnic_init_context(dev, tx_cid);
  3711. cnic_init_context(dev, tx_cid + 1);
  3712. offset0 = BNX2_L2CTX_TYPE;
  3713. offset1 = BNX2_L2CTX_CMD_TYPE;
  3714. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3715. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3716. }
  3717. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3718. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3719. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3720. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3721. txbd = udev->l2_ring;
  3722. buf_map = udev->l2_buf_map;
  3723. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3724. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3725. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3726. }
  3727. val = (u64) ring_map >> 32;
  3728. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3729. txbd->tx_bd_haddr_hi = val;
  3730. val = (u64) ring_map & 0xffffffff;
  3731. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3732. txbd->tx_bd_haddr_lo = val;
  3733. }
  3734. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3735. {
  3736. struct cnic_local *cp = dev->cnic_priv;
  3737. struct cnic_eth_dev *ethdev = cp->ethdev;
  3738. struct cnic_uio_dev *udev = cp->udev;
  3739. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3740. int i;
  3741. struct rx_bd *rxbd;
  3742. struct status_block *s_blk = cp->status_blk.gen;
  3743. dma_addr_t ring_map = udev->l2_ring_map;
  3744. sb_id = cp->status_blk_num;
  3745. cnic_init_context(dev, 2);
  3746. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3747. coal_reg = BNX2_HC_COMMAND;
  3748. coal_val = CNIC_RD(dev, coal_reg);
  3749. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3750. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3751. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3752. coal_reg = BNX2_HC_COALESCE_NOW;
  3753. coal_val = 1 << (11 + sb_id);
  3754. }
  3755. i = 0;
  3756. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3757. CNIC_WR(dev, coal_reg, coal_val);
  3758. udelay(10);
  3759. i++;
  3760. barrier();
  3761. }
  3762. cp->rx_cons = *cp->rx_cons_ptr;
  3763. cid_addr = GET_CID_ADDR(2);
  3764. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3765. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3766. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3767. if (sb_id == 0)
  3768. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3769. else
  3770. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3771. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3772. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3773. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3774. dma_addr_t buf_map;
  3775. int n = (i % cp->l2_rx_ring_size) + 1;
  3776. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3777. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3778. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3779. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3780. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3781. }
  3782. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3783. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3784. rxbd->rx_bd_haddr_hi = val;
  3785. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3786. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3787. rxbd->rx_bd_haddr_lo = val;
  3788. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3789. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3790. }
  3791. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3792. {
  3793. struct kwqe *wqes[1], l2kwqe;
  3794. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3795. wqes[0] = &l2kwqe;
  3796. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3797. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3798. KWQE_OPCODE_SHIFT) | 2;
  3799. dev->submit_kwqes(dev, wqes, 1);
  3800. }
  3801. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3802. {
  3803. struct cnic_local *cp = dev->cnic_priv;
  3804. u32 val;
  3805. val = cp->func << 2;
  3806. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3807. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3808. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3809. dev->mac_addr[0] = (u8) (val >> 8);
  3810. dev->mac_addr[1] = (u8) val;
  3811. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3812. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3813. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3814. dev->mac_addr[2] = (u8) (val >> 24);
  3815. dev->mac_addr[3] = (u8) (val >> 16);
  3816. dev->mac_addr[4] = (u8) (val >> 8);
  3817. dev->mac_addr[5] = (u8) val;
  3818. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3819. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3820. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3821. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3822. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3823. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3824. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3825. }
  3826. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3827. {
  3828. struct cnic_local *cp = dev->cnic_priv;
  3829. struct cnic_eth_dev *ethdev = cp->ethdev;
  3830. struct status_block *sblk = cp->status_blk.gen;
  3831. u32 val, kcq_cid_addr, kwq_cid_addr;
  3832. int err;
  3833. cnic_set_bnx2_mac(dev);
  3834. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3835. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3836. if (BCM_PAGE_BITS > 12)
  3837. val |= (12 - 8) << 4;
  3838. else
  3839. val |= (BCM_PAGE_BITS - 8) << 4;
  3840. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3841. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3842. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3843. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3844. err = cnic_setup_5709_context(dev, 1);
  3845. if (err)
  3846. return err;
  3847. cnic_init_context(dev, KWQ_CID);
  3848. cnic_init_context(dev, KCQ_CID);
  3849. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3850. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3851. cp->max_kwq_idx = MAX_KWQ_IDX;
  3852. cp->kwq_prod_idx = 0;
  3853. cp->kwq_con_idx = 0;
  3854. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3855. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3856. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3857. else
  3858. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3859. /* Initialize the kernel work queue context. */
  3860. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3861. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3862. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3863. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3864. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3865. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3866. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3867. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3868. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3869. val = (u32) cp->kwq_info.pgtbl_map;
  3870. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3871. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3872. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3873. cp->kcq1.sw_prod_idx = 0;
  3874. cp->kcq1.hw_prod_idx_ptr =
  3875. &sblk->status_completion_producer_index;
  3876. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3877. /* Initialize the kernel complete queue context. */
  3878. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3879. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3880. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3881. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3882. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3883. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3884. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3885. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3886. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3887. val = (u32) cp->kcq1.dma.pgtbl_map;
  3888. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3889. cp->int_num = 0;
  3890. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3891. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3892. u32 sb_id = cp->status_blk_num;
  3893. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3894. cp->kcq1.hw_prod_idx_ptr =
  3895. &msblk->status_completion_producer_index;
  3896. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3897. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3898. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3899. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3900. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3901. }
  3902. /* Enable Commnad Scheduler notification when we write to the
  3903. * host producer index of the kernel contexts. */
  3904. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3905. /* Enable Command Scheduler notification when we write to either
  3906. * the Send Queue or Receive Queue producer indexes of the kernel
  3907. * bypass contexts. */
  3908. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3909. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3910. /* Notify COM when the driver post an application buffer. */
  3911. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3912. /* Set the CP and COM doorbells. These two processors polls the
  3913. * doorbell for a non zero value before running. This must be done
  3914. * after setting up the kernel queue contexts. */
  3915. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3916. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3917. cnic_init_bnx2_tx_ring(dev);
  3918. cnic_init_bnx2_rx_ring(dev);
  3919. err = cnic_init_bnx2_irq(dev);
  3920. if (err) {
  3921. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3922. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3923. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3924. return err;
  3925. }
  3926. return 0;
  3927. }
  3928. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3929. {
  3930. struct cnic_local *cp = dev->cnic_priv;
  3931. struct cnic_eth_dev *ethdev = cp->ethdev;
  3932. u32 start_offset = ethdev->ctx_tbl_offset;
  3933. int i;
  3934. for (i = 0; i < cp->ctx_blks; i++) {
  3935. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3936. dma_addr_t map = ctx->mapping;
  3937. if (cp->ctx_align) {
  3938. unsigned long mask = cp->ctx_align - 1;
  3939. map = (map + mask) & ~mask;
  3940. }
  3941. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3942. }
  3943. }
  3944. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3945. {
  3946. struct cnic_local *cp = dev->cnic_priv;
  3947. struct cnic_eth_dev *ethdev = cp->ethdev;
  3948. int err = 0;
  3949. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3950. (unsigned long) dev);
  3951. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3952. err = cnic_request_irq(dev);
  3953. return err;
  3954. }
  3955. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3956. u16 sb_id, u8 sb_index,
  3957. u8 disable)
  3958. {
  3959. u32 addr = BAR_CSTRORM_INTMEM +
  3960. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3961. offsetof(struct hc_status_block_data_e1x, index_data) +
  3962. sizeof(struct hc_index_data)*sb_index +
  3963. offsetof(struct hc_index_data, flags);
  3964. u16 flags = CNIC_RD16(dev, addr);
  3965. /* clear and set */
  3966. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3967. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3968. HC_INDEX_DATA_HC_ENABLED);
  3969. CNIC_WR16(dev, addr, flags);
  3970. }
  3971. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3972. {
  3973. struct cnic_local *cp = dev->cnic_priv;
  3974. u8 sb_id = cp->status_blk_num;
  3975. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3976. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3977. offsetof(struct hc_status_block_data_e1x, index_data) +
  3978. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3979. offsetof(struct hc_index_data, timeout), 64 / 4);
  3980. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3981. }
  3982. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3983. {
  3984. }
  3985. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3986. struct client_init_ramrod_data *data)
  3987. {
  3988. struct cnic_local *cp = dev->cnic_priv;
  3989. struct cnic_uio_dev *udev = cp->udev;
  3990. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3991. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3992. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3993. int i;
  3994. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3995. u32 val;
  3996. memset(txbd, 0, BCM_PAGE_SIZE);
  3997. buf_map = udev->l2_buf_map;
  3998. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3999. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4000. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4001. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4002. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4003. reg_bd->addr_hi = start_bd->addr_hi;
  4004. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4005. start_bd->nbytes = cpu_to_le16(0x10);
  4006. start_bd->nbd = cpu_to_le16(3);
  4007. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4008. start_bd->general_data = (UNICAST_ADDRESS <<
  4009. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  4010. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4011. }
  4012. val = (u64) ring_map >> 32;
  4013. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4014. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4015. val = (u64) ring_map & 0xffffffff;
  4016. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4017. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4018. /* Other ramrod params */
  4019. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4020. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4021. /* reset xstorm per client statistics */
  4022. if (cli < MAX_STAT_COUNTER_ID) {
  4023. data->general.statistics_zero_flg = 1;
  4024. data->general.statistics_en_flg = 1;
  4025. data->general.statistics_counter_id = cli;
  4026. }
  4027. cp->tx_cons_ptr =
  4028. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4029. }
  4030. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4031. struct client_init_ramrod_data *data)
  4032. {
  4033. struct cnic_local *cp = dev->cnic_priv;
  4034. struct cnic_uio_dev *udev = cp->udev;
  4035. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4036. BCM_PAGE_SIZE);
  4037. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4038. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4039. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4040. int i;
  4041. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4042. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4043. u32 val;
  4044. dma_addr_t ring_map = udev->l2_ring_map;
  4045. /* General data */
  4046. data->general.client_id = cli;
  4047. data->general.activate_flg = 1;
  4048. data->general.sp_client_id = cli;
  4049. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4050. data->general.func_id = cp->pfid;
  4051. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4052. dma_addr_t buf_map;
  4053. int n = (i % cp->l2_rx_ring_size) + 1;
  4054. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4055. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4056. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4057. }
  4058. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4059. rxbd->addr_hi = cpu_to_le32(val);
  4060. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4061. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4062. rxbd->addr_lo = cpu_to_le32(val);
  4063. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4064. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4065. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4066. rxcqe->addr_hi = cpu_to_le32(val);
  4067. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4068. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4069. rxcqe->addr_lo = cpu_to_le32(val);
  4070. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4071. /* Other ramrod params */
  4072. data->rx.client_qzone_id = cl_qzone_id;
  4073. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4074. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4075. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4076. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4077. data->rx.outer_vlan_removal_enable_flg = 1;
  4078. data->rx.silent_vlan_removal_flg = 1;
  4079. data->rx.silent_vlan_value = 0;
  4080. data->rx.silent_vlan_mask = 0xffff;
  4081. cp->rx_cons_ptr =
  4082. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4083. cp->rx_cons = *cp->rx_cons_ptr;
  4084. }
  4085. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4086. {
  4087. struct cnic_local *cp = dev->cnic_priv;
  4088. u32 pfid = cp->pfid;
  4089. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4090. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4091. cp->kcq1.sw_prod_idx = 0;
  4092. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4093. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4094. cp->kcq1.hw_prod_idx_ptr =
  4095. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4096. cp->kcq1.status_idx_ptr =
  4097. &sb->sb.running_index[SM_RX_ID];
  4098. } else {
  4099. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4100. cp->kcq1.hw_prod_idx_ptr =
  4101. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4102. cp->kcq1.status_idx_ptr =
  4103. &sb->sb.running_index[SM_RX_ID];
  4104. }
  4105. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4106. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4107. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4108. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4109. cp->kcq2.sw_prod_idx = 0;
  4110. cp->kcq2.hw_prod_idx_ptr =
  4111. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4112. cp->kcq2.status_idx_ptr =
  4113. &sb->sb.running_index[SM_RX_ID];
  4114. }
  4115. }
  4116. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4117. {
  4118. struct cnic_local *cp = dev->cnic_priv;
  4119. struct cnic_eth_dev *ethdev = cp->ethdev;
  4120. int func = CNIC_FUNC(cp), ret;
  4121. u32 pfid;
  4122. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4123. cp->port_mode = CHIP_PORT_MODE_NONE;
  4124. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4125. u32 val;
  4126. pci_read_config_dword(dev->pcidev, PCICFG_ME_REGISTER, &val);
  4127. cp->func = (u8) ((val & ME_REG_ABS_PF_NUM) >>
  4128. ME_REG_ABS_PF_NUM_SHIFT);
  4129. func = CNIC_FUNC(cp);
  4130. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4131. if (!(val & 1))
  4132. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4133. else
  4134. val = (val >> 1) & 1;
  4135. if (val) {
  4136. cp->port_mode = CHIP_4_PORT_MODE;
  4137. cp->pfid = func >> 1;
  4138. } else {
  4139. cp->port_mode = CHIP_2_PORT_MODE;
  4140. cp->pfid = func & 0x6;
  4141. }
  4142. } else {
  4143. cp->pfid = func;
  4144. }
  4145. pfid = cp->pfid;
  4146. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4147. cp->iscsi_start_cid, 0);
  4148. if (ret)
  4149. return -ENOMEM;
  4150. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4151. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4152. cp->fcoe_start_cid, 0);
  4153. if (ret)
  4154. return -ENOMEM;
  4155. }
  4156. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4157. cnic_init_bnx2x_kcq(dev);
  4158. /* Only 1 EQ */
  4159. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4160. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4161. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4162. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4163. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4164. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4165. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4166. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4167. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4168. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4169. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4170. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4171. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4172. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4173. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4174. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4175. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4176. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4177. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4178. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4179. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4180. HC_INDEX_ISCSI_EQ_CONS);
  4181. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4182. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4183. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4184. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4185. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4186. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4187. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4188. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4189. cnic_setup_bnx2x_context(dev);
  4190. ret = cnic_init_bnx2x_irq(dev);
  4191. if (ret)
  4192. return ret;
  4193. return 0;
  4194. }
  4195. static void cnic_init_rings(struct cnic_dev *dev)
  4196. {
  4197. struct cnic_local *cp = dev->cnic_priv;
  4198. struct cnic_uio_dev *udev = cp->udev;
  4199. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4200. return;
  4201. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4202. cnic_init_bnx2_tx_ring(dev);
  4203. cnic_init_bnx2_rx_ring(dev);
  4204. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4205. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4206. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4207. u32 cid = cp->ethdev->iscsi_l2_cid;
  4208. u32 cl_qzone_id;
  4209. struct client_init_ramrod_data *data;
  4210. union l5cm_specific_data l5_data;
  4211. struct ustorm_eth_rx_producers rx_prods = {0};
  4212. u32 off, i, *cid_ptr;
  4213. rx_prods.bd_prod = 0;
  4214. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4215. barrier();
  4216. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4217. off = BAR_USTRORM_INTMEM +
  4218. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4219. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4220. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4221. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4222. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4223. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4224. data = udev->l2_buf;
  4225. cid_ptr = udev->l2_buf + 12;
  4226. memset(data, 0, sizeof(*data));
  4227. cnic_init_bnx2x_tx_ring(dev, data);
  4228. cnic_init_bnx2x_rx_ring(dev, data);
  4229. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4230. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4231. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4232. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4233. cid, ETH_CONNECTION_TYPE, &l5_data);
  4234. i = 0;
  4235. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4236. ++i < 10)
  4237. msleep(1);
  4238. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4239. netdev_err(dev->netdev,
  4240. "iSCSI CLIENT_SETUP did not complete\n");
  4241. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4242. cnic_ring_ctl(dev, cid, cli, 1);
  4243. *cid_ptr = cid;
  4244. }
  4245. }
  4246. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4247. {
  4248. struct cnic_local *cp = dev->cnic_priv;
  4249. struct cnic_uio_dev *udev = cp->udev;
  4250. void *rx_ring;
  4251. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4252. return;
  4253. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4254. cnic_shutdown_bnx2_rx_ring(dev);
  4255. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4256. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4257. u32 cid = cp->ethdev->iscsi_l2_cid;
  4258. union l5cm_specific_data l5_data;
  4259. int i;
  4260. cnic_ring_ctl(dev, cid, cli, 0);
  4261. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4262. l5_data.phy_address.lo = cli;
  4263. l5_data.phy_address.hi = 0;
  4264. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4265. cid, ETH_CONNECTION_TYPE, &l5_data);
  4266. i = 0;
  4267. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4268. ++i < 10)
  4269. msleep(1);
  4270. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4271. netdev_err(dev->netdev,
  4272. "iSCSI CLIENT_HALT did not complete\n");
  4273. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4274. memset(&l5_data, 0, sizeof(l5_data));
  4275. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4276. cid, NONE_CONNECTION_TYPE, &l5_data);
  4277. msleep(10);
  4278. }
  4279. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4280. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4281. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4282. }
  4283. static int cnic_register_netdev(struct cnic_dev *dev)
  4284. {
  4285. struct cnic_local *cp = dev->cnic_priv;
  4286. struct cnic_eth_dev *ethdev = cp->ethdev;
  4287. int err;
  4288. if (!ethdev)
  4289. return -ENODEV;
  4290. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4291. return 0;
  4292. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4293. if (err)
  4294. netdev_err(dev->netdev, "register_cnic failed\n");
  4295. return err;
  4296. }
  4297. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4298. {
  4299. struct cnic_local *cp = dev->cnic_priv;
  4300. struct cnic_eth_dev *ethdev = cp->ethdev;
  4301. if (!ethdev)
  4302. return;
  4303. ethdev->drv_unregister_cnic(dev->netdev);
  4304. }
  4305. static int cnic_start_hw(struct cnic_dev *dev)
  4306. {
  4307. struct cnic_local *cp = dev->cnic_priv;
  4308. struct cnic_eth_dev *ethdev = cp->ethdev;
  4309. int err;
  4310. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4311. return -EALREADY;
  4312. dev->regview = ethdev->io_base;
  4313. pci_dev_get(dev->pcidev);
  4314. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4315. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4316. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4317. err = cp->alloc_resc(dev);
  4318. if (err) {
  4319. netdev_err(dev->netdev, "allocate resource failure\n");
  4320. goto err1;
  4321. }
  4322. err = cp->start_hw(dev);
  4323. if (err)
  4324. goto err1;
  4325. err = cnic_cm_open(dev);
  4326. if (err)
  4327. goto err1;
  4328. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4329. cp->enable_int(dev);
  4330. return 0;
  4331. err1:
  4332. cp->free_resc(dev);
  4333. pci_dev_put(dev->pcidev);
  4334. return err;
  4335. }
  4336. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4337. {
  4338. cnic_disable_bnx2_int_sync(dev);
  4339. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4340. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4341. cnic_init_context(dev, KWQ_CID);
  4342. cnic_init_context(dev, KCQ_CID);
  4343. cnic_setup_5709_context(dev, 0);
  4344. cnic_free_irq(dev);
  4345. cnic_free_resc(dev);
  4346. }
  4347. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4348. {
  4349. struct cnic_local *cp = dev->cnic_priv;
  4350. cnic_free_irq(dev);
  4351. *cp->kcq1.hw_prod_idx_ptr = 0;
  4352. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4353. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4354. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4355. cnic_free_resc(dev);
  4356. }
  4357. static void cnic_stop_hw(struct cnic_dev *dev)
  4358. {
  4359. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4360. struct cnic_local *cp = dev->cnic_priv;
  4361. int i = 0;
  4362. /* Need to wait for the ring shutdown event to complete
  4363. * before clearing the CNIC_UP flag.
  4364. */
  4365. while (cp->udev->uio_dev != -1 && i < 15) {
  4366. msleep(100);
  4367. i++;
  4368. }
  4369. cnic_shutdown_rings(dev);
  4370. cp->stop_cm(dev);
  4371. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4372. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4373. synchronize_rcu();
  4374. cnic_cm_shutdown(dev);
  4375. cp->stop_hw(dev);
  4376. pci_dev_put(dev->pcidev);
  4377. }
  4378. }
  4379. static void cnic_free_dev(struct cnic_dev *dev)
  4380. {
  4381. int i = 0;
  4382. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4383. msleep(100);
  4384. i++;
  4385. }
  4386. if (atomic_read(&dev->ref_count) != 0)
  4387. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4388. netdev_info(dev->netdev, "Removed CNIC device\n");
  4389. dev_put(dev->netdev);
  4390. kfree(dev);
  4391. }
  4392. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4393. struct pci_dev *pdev)
  4394. {
  4395. struct cnic_dev *cdev;
  4396. struct cnic_local *cp;
  4397. int alloc_size;
  4398. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4399. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4400. if (cdev == NULL) {
  4401. netdev_err(dev, "allocate dev struct failure\n");
  4402. return NULL;
  4403. }
  4404. cdev->netdev = dev;
  4405. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4406. cdev->register_device = cnic_register_device;
  4407. cdev->unregister_device = cnic_unregister_device;
  4408. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4409. cp = cdev->cnic_priv;
  4410. cp->dev = cdev;
  4411. cp->l2_single_buf_size = 0x400;
  4412. cp->l2_rx_ring_size = 3;
  4413. spin_lock_init(&cp->cnic_ulp_lock);
  4414. netdev_info(dev, "Added CNIC device\n");
  4415. return cdev;
  4416. }
  4417. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4418. {
  4419. struct pci_dev *pdev;
  4420. struct cnic_dev *cdev;
  4421. struct cnic_local *cp;
  4422. struct cnic_eth_dev *ethdev = NULL;
  4423. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4424. probe = symbol_get(bnx2_cnic_probe);
  4425. if (probe) {
  4426. ethdev = (*probe)(dev);
  4427. symbol_put(bnx2_cnic_probe);
  4428. }
  4429. if (!ethdev)
  4430. return NULL;
  4431. pdev = ethdev->pdev;
  4432. if (!pdev)
  4433. return NULL;
  4434. dev_hold(dev);
  4435. pci_dev_get(pdev);
  4436. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4437. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4438. (pdev->revision < 0x10)) {
  4439. pci_dev_put(pdev);
  4440. goto cnic_err;
  4441. }
  4442. pci_dev_put(pdev);
  4443. cdev = cnic_alloc_dev(dev, pdev);
  4444. if (cdev == NULL)
  4445. goto cnic_err;
  4446. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4447. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4448. cp = cdev->cnic_priv;
  4449. cp->ethdev = ethdev;
  4450. cdev->pcidev = pdev;
  4451. cp->chip_id = ethdev->chip_id;
  4452. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4453. cp->cnic_ops = &cnic_bnx2_ops;
  4454. cp->start_hw = cnic_start_bnx2_hw;
  4455. cp->stop_hw = cnic_stop_bnx2_hw;
  4456. cp->setup_pgtbl = cnic_setup_page_tbl;
  4457. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4458. cp->free_resc = cnic_free_resc;
  4459. cp->start_cm = cnic_cm_init_bnx2_hw;
  4460. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4461. cp->enable_int = cnic_enable_bnx2_int;
  4462. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4463. cp->close_conn = cnic_close_bnx2_conn;
  4464. return cdev;
  4465. cnic_err:
  4466. dev_put(dev);
  4467. return NULL;
  4468. }
  4469. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4470. {
  4471. struct pci_dev *pdev;
  4472. struct cnic_dev *cdev;
  4473. struct cnic_local *cp;
  4474. struct cnic_eth_dev *ethdev = NULL;
  4475. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4476. probe = symbol_get(bnx2x_cnic_probe);
  4477. if (probe) {
  4478. ethdev = (*probe)(dev);
  4479. symbol_put(bnx2x_cnic_probe);
  4480. }
  4481. if (!ethdev)
  4482. return NULL;
  4483. pdev = ethdev->pdev;
  4484. if (!pdev)
  4485. return NULL;
  4486. dev_hold(dev);
  4487. cdev = cnic_alloc_dev(dev, pdev);
  4488. if (cdev == NULL) {
  4489. dev_put(dev);
  4490. return NULL;
  4491. }
  4492. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4493. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4494. cp = cdev->cnic_priv;
  4495. cp->ethdev = ethdev;
  4496. cdev->pcidev = pdev;
  4497. cp->chip_id = ethdev->chip_id;
  4498. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4499. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4500. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4501. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4502. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4503. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4504. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4505. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4506. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4507. cp->cnic_ops = &cnic_bnx2x_ops;
  4508. cp->start_hw = cnic_start_bnx2x_hw;
  4509. cp->stop_hw = cnic_stop_bnx2x_hw;
  4510. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4511. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4512. cp->free_resc = cnic_free_resc;
  4513. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4514. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4515. cp->enable_int = cnic_enable_bnx2x_int;
  4516. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4517. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4518. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4519. else
  4520. cp->ack_int = cnic_ack_bnx2x_msix;
  4521. cp->close_conn = cnic_close_bnx2x_conn;
  4522. return cdev;
  4523. }
  4524. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4525. {
  4526. struct ethtool_drvinfo drvinfo;
  4527. struct cnic_dev *cdev = NULL;
  4528. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4529. memset(&drvinfo, 0, sizeof(drvinfo));
  4530. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4531. if (!strcmp(drvinfo.driver, "bnx2"))
  4532. cdev = init_bnx2_cnic(dev);
  4533. if (!strcmp(drvinfo.driver, "bnx2x"))
  4534. cdev = init_bnx2x_cnic(dev);
  4535. if (cdev) {
  4536. write_lock(&cnic_dev_lock);
  4537. list_add(&cdev->list, &cnic_dev_list);
  4538. write_unlock(&cnic_dev_lock);
  4539. }
  4540. }
  4541. return cdev;
  4542. }
  4543. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4544. u16 vlan_id)
  4545. {
  4546. int if_type;
  4547. rcu_read_lock();
  4548. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4549. struct cnic_ulp_ops *ulp_ops;
  4550. void *ctx;
  4551. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4552. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4553. continue;
  4554. ctx = cp->ulp_handle[if_type];
  4555. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4556. }
  4557. rcu_read_unlock();
  4558. }
  4559. /* netdev event handler */
  4560. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4561. void *ptr)
  4562. {
  4563. struct net_device *netdev = ptr;
  4564. struct cnic_dev *dev;
  4565. int new_dev = 0;
  4566. dev = cnic_from_netdev(netdev);
  4567. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4568. /* Check for the hot-plug device */
  4569. dev = is_cnic_dev(netdev);
  4570. if (dev) {
  4571. new_dev = 1;
  4572. cnic_hold(dev);
  4573. }
  4574. }
  4575. if (dev) {
  4576. struct cnic_local *cp = dev->cnic_priv;
  4577. if (new_dev)
  4578. cnic_ulp_init(dev);
  4579. else if (event == NETDEV_UNREGISTER)
  4580. cnic_ulp_exit(dev);
  4581. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4582. if (cnic_register_netdev(dev) != 0) {
  4583. cnic_put(dev);
  4584. goto done;
  4585. }
  4586. if (!cnic_start_hw(dev))
  4587. cnic_ulp_start(dev);
  4588. }
  4589. cnic_rcv_netevent(cp, event, 0);
  4590. if (event == NETDEV_GOING_DOWN) {
  4591. cnic_ulp_stop(dev);
  4592. cnic_stop_hw(dev);
  4593. cnic_unregister_netdev(dev);
  4594. } else if (event == NETDEV_UNREGISTER) {
  4595. write_lock(&cnic_dev_lock);
  4596. list_del_init(&dev->list);
  4597. write_unlock(&cnic_dev_lock);
  4598. cnic_put(dev);
  4599. cnic_free_dev(dev);
  4600. goto done;
  4601. }
  4602. cnic_put(dev);
  4603. } else {
  4604. struct net_device *realdev;
  4605. u16 vid;
  4606. vid = cnic_get_vlan(netdev, &realdev);
  4607. if (realdev) {
  4608. dev = cnic_from_netdev(realdev);
  4609. if (dev) {
  4610. vid |= VLAN_TAG_PRESENT;
  4611. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4612. cnic_put(dev);
  4613. }
  4614. }
  4615. }
  4616. done:
  4617. return NOTIFY_DONE;
  4618. }
  4619. static struct notifier_block cnic_netdev_notifier = {
  4620. .notifier_call = cnic_netdev_event
  4621. };
  4622. static void cnic_release(void)
  4623. {
  4624. struct cnic_dev *dev;
  4625. struct cnic_uio_dev *udev;
  4626. while (!list_empty(&cnic_dev_list)) {
  4627. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4628. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4629. cnic_ulp_stop(dev);
  4630. cnic_stop_hw(dev);
  4631. }
  4632. cnic_ulp_exit(dev);
  4633. cnic_unregister_netdev(dev);
  4634. list_del_init(&dev->list);
  4635. cnic_free_dev(dev);
  4636. }
  4637. while (!list_empty(&cnic_udev_list)) {
  4638. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4639. list);
  4640. cnic_free_uio(udev);
  4641. }
  4642. }
  4643. static int __init cnic_init(void)
  4644. {
  4645. int rc = 0;
  4646. pr_info("%s", version);
  4647. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4648. if (rc) {
  4649. cnic_release();
  4650. return rc;
  4651. }
  4652. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4653. if (!cnic_wq) {
  4654. cnic_release();
  4655. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4656. return -ENOMEM;
  4657. }
  4658. return 0;
  4659. }
  4660. static void __exit cnic_exit(void)
  4661. {
  4662. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4663. cnic_release();
  4664. destroy_workqueue(cnic_wq);
  4665. }
  4666. module_init(cnic_init);
  4667. module_exit(cnic_exit);