janz-ican3.c 47 KB

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  1. /*
  2. * Janz MODULbus VMOD-ICAN3 CAN Interface Driver
  3. *
  4. * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/delay.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/netdevice.h>
  18. #include <linux/can.h>
  19. #include <linux/can/dev.h>
  20. #include <linux/can/error.h>
  21. #include <linux/mfd/janz.h>
  22. #include <asm/io.h>
  23. /* the DPM has 64k of memory, organized into 256x 256 byte pages */
  24. #define DPM_NUM_PAGES 256
  25. #define DPM_PAGE_SIZE 256
  26. #define DPM_PAGE_ADDR(p) ((p) * DPM_PAGE_SIZE)
  27. /* JANZ ICAN3 "old-style" host interface queue page numbers */
  28. #define QUEUE_OLD_CONTROL 0
  29. #define QUEUE_OLD_RB0 1
  30. #define QUEUE_OLD_RB1 2
  31. #define QUEUE_OLD_WB0 3
  32. #define QUEUE_OLD_WB1 4
  33. /* Janz ICAN3 "old-style" host interface control registers */
  34. #define MSYNC_PEER 0x00 /* ICAN only */
  35. #define MSYNC_LOCL 0x01 /* host only */
  36. #define TARGET_RUNNING 0x02
  37. #define MSYNC_RB0 0x01
  38. #define MSYNC_RB1 0x02
  39. #define MSYNC_RBLW 0x04
  40. #define MSYNC_RB_MASK (MSYNC_RB0 | MSYNC_RB1)
  41. #define MSYNC_WB0 0x10
  42. #define MSYNC_WB1 0x20
  43. #define MSYNC_WBLW 0x40
  44. #define MSYNC_WB_MASK (MSYNC_WB0 | MSYNC_WB1)
  45. /* Janz ICAN3 "new-style" host interface queue page numbers */
  46. #define QUEUE_TOHOST 5
  47. #define QUEUE_FROMHOST_MID 6
  48. #define QUEUE_FROMHOST_HIGH 7
  49. #define QUEUE_FROMHOST_LOW 8
  50. /* The first free page in the DPM is #9 */
  51. #define DPM_FREE_START 9
  52. /* Janz ICAN3 "new-style" and "fast" host interface descriptor flags */
  53. #define DESC_VALID 0x80
  54. #define DESC_WRAP 0x40
  55. #define DESC_INTERRUPT 0x20
  56. #define DESC_IVALID 0x10
  57. #define DESC_LEN(len) (len)
  58. /* Janz ICAN3 Firmware Messages */
  59. #define MSG_CONNECTI 0x02
  60. #define MSG_DISCONNECT 0x03
  61. #define MSG_IDVERS 0x04
  62. #define MSG_MSGLOST 0x05
  63. #define MSG_NEWHOSTIF 0x08
  64. #define MSG_INQUIRY 0x0a
  65. #define MSG_SETAFILMASK 0x10
  66. #define MSG_INITFDPMQUEUE 0x11
  67. #define MSG_HWCONF 0x12
  68. #define MSG_FMSGLOST 0x15
  69. #define MSG_CEVTIND 0x37
  70. #define MSG_CBTRREQ 0x41
  71. #define MSG_COFFREQ 0x42
  72. #define MSG_CONREQ 0x43
  73. #define MSG_CCONFREQ 0x47
  74. /*
  75. * Janz ICAN3 CAN Inquiry Message Types
  76. *
  77. * NOTE: there appears to be a firmware bug here. You must send
  78. * NOTE: INQUIRY_STATUS and expect to receive an INQUIRY_EXTENDED
  79. * NOTE: response. The controller never responds to a message with
  80. * NOTE: the INQUIRY_EXTENDED subspec :(
  81. */
  82. #define INQUIRY_STATUS 0x00
  83. #define INQUIRY_TERMINATION 0x01
  84. #define INQUIRY_EXTENDED 0x04
  85. /* Janz ICAN3 CAN Set Acceptance Filter Mask Message Types */
  86. #define SETAFILMASK_REJECT 0x00
  87. #define SETAFILMASK_FASTIF 0x02
  88. /* Janz ICAN3 CAN Hardware Configuration Message Types */
  89. #define HWCONF_TERMINATE_ON 0x01
  90. #define HWCONF_TERMINATE_OFF 0x00
  91. /* Janz ICAN3 CAN Event Indication Message Types */
  92. #define CEVTIND_EI 0x01
  93. #define CEVTIND_DOI 0x02
  94. #define CEVTIND_LOST 0x04
  95. #define CEVTIND_FULL 0x08
  96. #define CEVTIND_BEI 0x10
  97. #define CEVTIND_CHIP_SJA1000 0x02
  98. #define ICAN3_BUSERR_QUOTA_MAX 255
  99. /* Janz ICAN3 CAN Frame Conversion */
  100. #define ICAN3_SNGL 0x02
  101. #define ICAN3_ECHO 0x10
  102. #define ICAN3_EFF_RTR 0x40
  103. #define ICAN3_SFF_RTR 0x10
  104. #define ICAN3_EFF 0x80
  105. #define ICAN3_CAN_TYPE_MASK 0x0f
  106. #define ICAN3_CAN_TYPE_SFF 0x00
  107. #define ICAN3_CAN_TYPE_EFF 0x01
  108. #define ICAN3_CAN_DLC_MASK 0x0f
  109. /*
  110. * SJA1000 Status and Error Register Definitions
  111. *
  112. * Copied from drivers/net/can/sja1000/sja1000.h
  113. */
  114. /* status register content */
  115. #define SR_BS 0x80
  116. #define SR_ES 0x40
  117. #define SR_TS 0x20
  118. #define SR_RS 0x10
  119. #define SR_TCS 0x08
  120. #define SR_TBS 0x04
  121. #define SR_DOS 0x02
  122. #define SR_RBS 0x01
  123. #define SR_CRIT (SR_BS|SR_ES)
  124. /* ECC register */
  125. #define ECC_SEG 0x1F
  126. #define ECC_DIR 0x20
  127. #define ECC_ERR 6
  128. #define ECC_BIT 0x00
  129. #define ECC_FORM 0x40
  130. #define ECC_STUFF 0x80
  131. #define ECC_MASK 0xc0
  132. /* Number of buffers for use in the "new-style" host interface */
  133. #define ICAN3_NEW_BUFFERS 16
  134. /* Number of buffers for use in the "fast" host interface */
  135. #define ICAN3_TX_BUFFERS 512
  136. #define ICAN3_RX_BUFFERS 1024
  137. /* SJA1000 Clock Input */
  138. #define ICAN3_CAN_CLOCK 8000000
  139. /* Driver Name */
  140. #define DRV_NAME "janz-ican3"
  141. /* DPM Control Registers -- starts at offset 0x100 in the MODULbus registers */
  142. struct ican3_dpm_control {
  143. /* window address register */
  144. u8 window_address;
  145. u8 unused1;
  146. /*
  147. * Read access: clear interrupt from microcontroller
  148. * Write access: send interrupt to microcontroller
  149. */
  150. u8 interrupt;
  151. u8 unused2;
  152. /* write-only: reset all hardware on the module */
  153. u8 hwreset;
  154. u8 unused3;
  155. /* write-only: generate an interrupt to the TPU */
  156. u8 tpuinterrupt;
  157. };
  158. struct ican3_dev {
  159. /* must be the first member */
  160. struct can_priv can;
  161. /* CAN network device */
  162. struct net_device *ndev;
  163. struct napi_struct napi;
  164. /* Device for printing */
  165. struct device *dev;
  166. /* module number */
  167. unsigned int num;
  168. /* base address of registers and IRQ */
  169. struct janz_cmodio_onboard_regs __iomem *ctrl;
  170. struct ican3_dpm_control __iomem *dpmctrl;
  171. void __iomem *dpm;
  172. int irq;
  173. /* CAN bus termination status */
  174. struct completion termination_comp;
  175. bool termination_enabled;
  176. /* CAN bus error status registers */
  177. struct completion buserror_comp;
  178. struct can_berr_counter bec;
  179. /* old and new style host interface */
  180. unsigned int iftype;
  181. /* queue for echo packets */
  182. struct sk_buff_head echoq;
  183. /*
  184. * Any function which changes the current DPM page must hold this
  185. * lock while it is performing data accesses. This ensures that the
  186. * function will not be preempted and end up reading data from a
  187. * different DPM page than it expects.
  188. */
  189. spinlock_t lock;
  190. /* new host interface */
  191. unsigned int rx_int;
  192. unsigned int rx_num;
  193. unsigned int tx_num;
  194. /* fast host interface */
  195. unsigned int fastrx_start;
  196. unsigned int fastrx_num;
  197. unsigned int fasttx_start;
  198. unsigned int fasttx_num;
  199. /* first free DPM page */
  200. unsigned int free_page;
  201. };
  202. struct ican3_msg {
  203. u8 control;
  204. u8 spec;
  205. __le16 len;
  206. u8 data[252];
  207. };
  208. struct ican3_new_desc {
  209. u8 control;
  210. u8 pointer;
  211. };
  212. struct ican3_fast_desc {
  213. u8 control;
  214. u8 command;
  215. u8 data[14];
  216. };
  217. /* write to the window basic address register */
  218. static inline void ican3_set_page(struct ican3_dev *mod, unsigned int page)
  219. {
  220. BUG_ON(page >= DPM_NUM_PAGES);
  221. iowrite8(page, &mod->dpmctrl->window_address);
  222. }
  223. /*
  224. * ICAN3 "old-style" host interface
  225. */
  226. /*
  227. * Receive a message from the ICAN3 "old-style" firmware interface
  228. *
  229. * LOCKING: must hold mod->lock
  230. *
  231. * returns 0 on success, -ENOMEM when no message exists
  232. */
  233. static int ican3_old_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  234. {
  235. unsigned int mbox, mbox_page;
  236. u8 locl, peer, xord;
  237. /* get the MSYNC registers */
  238. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  239. peer = ioread8(mod->dpm + MSYNC_PEER);
  240. locl = ioread8(mod->dpm + MSYNC_LOCL);
  241. xord = locl ^ peer;
  242. if ((xord & MSYNC_RB_MASK) == 0x00) {
  243. dev_dbg(mod->dev, "no mbox for reading\n");
  244. return -ENOMEM;
  245. }
  246. /* find the first free mbox to read */
  247. if ((xord & MSYNC_RB_MASK) == MSYNC_RB_MASK)
  248. mbox = (xord & MSYNC_RBLW) ? MSYNC_RB0 : MSYNC_RB1;
  249. else
  250. mbox = (xord & MSYNC_RB0) ? MSYNC_RB0 : MSYNC_RB1;
  251. /* copy the message */
  252. mbox_page = (mbox == MSYNC_RB0) ? QUEUE_OLD_RB0 : QUEUE_OLD_RB1;
  253. ican3_set_page(mod, mbox_page);
  254. memcpy_fromio(msg, mod->dpm, sizeof(*msg));
  255. /*
  256. * notify the firmware that the read buffer is available
  257. * for it to fill again
  258. */
  259. locl ^= mbox;
  260. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  261. iowrite8(locl, mod->dpm + MSYNC_LOCL);
  262. return 0;
  263. }
  264. /*
  265. * Send a message through the "old-style" firmware interface
  266. *
  267. * LOCKING: must hold mod->lock
  268. *
  269. * returns 0 on success, -ENOMEM when no free space exists
  270. */
  271. static int ican3_old_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  272. {
  273. unsigned int mbox, mbox_page;
  274. u8 locl, peer, xord;
  275. /* get the MSYNC registers */
  276. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  277. peer = ioread8(mod->dpm + MSYNC_PEER);
  278. locl = ioread8(mod->dpm + MSYNC_LOCL);
  279. xord = locl ^ peer;
  280. if ((xord & MSYNC_WB_MASK) == MSYNC_WB_MASK) {
  281. dev_err(mod->dev, "no mbox for writing\n");
  282. return -ENOMEM;
  283. }
  284. /* calculate a free mbox to use */
  285. mbox = (xord & MSYNC_WB0) ? MSYNC_WB1 : MSYNC_WB0;
  286. /* copy the message to the DPM */
  287. mbox_page = (mbox == MSYNC_WB0) ? QUEUE_OLD_WB0 : QUEUE_OLD_WB1;
  288. ican3_set_page(mod, mbox_page);
  289. memcpy_toio(mod->dpm, msg, sizeof(*msg));
  290. locl ^= mbox;
  291. if (mbox == MSYNC_WB1)
  292. locl |= MSYNC_WBLW;
  293. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  294. iowrite8(locl, mod->dpm + MSYNC_LOCL);
  295. return 0;
  296. }
  297. /*
  298. * ICAN3 "new-style" Host Interface Setup
  299. */
  300. static void __devinit ican3_init_new_host_interface(struct ican3_dev *mod)
  301. {
  302. struct ican3_new_desc desc;
  303. unsigned long flags;
  304. void __iomem *dst;
  305. int i;
  306. spin_lock_irqsave(&mod->lock, flags);
  307. /* setup the internal datastructures for RX */
  308. mod->rx_num = 0;
  309. mod->rx_int = 0;
  310. /* tohost queue descriptors are in page 5 */
  311. ican3_set_page(mod, QUEUE_TOHOST);
  312. dst = mod->dpm;
  313. /* initialize the tohost (rx) queue descriptors: pages 9-24 */
  314. for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
  315. desc.control = DESC_INTERRUPT | DESC_LEN(1); /* I L=1 */
  316. desc.pointer = mod->free_page;
  317. /* set wrap flag on last buffer */
  318. if (i == ICAN3_NEW_BUFFERS - 1)
  319. desc.control |= DESC_WRAP;
  320. memcpy_toio(dst, &desc, sizeof(desc));
  321. dst += sizeof(desc);
  322. mod->free_page++;
  323. }
  324. /* fromhost (tx) mid queue descriptors are in page 6 */
  325. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  326. dst = mod->dpm;
  327. /* setup the internal datastructures for TX */
  328. mod->tx_num = 0;
  329. /* initialize the fromhost mid queue descriptors: pages 25-40 */
  330. for (i = 0; i < ICAN3_NEW_BUFFERS; i++) {
  331. desc.control = DESC_VALID | DESC_LEN(1); /* V L=1 */
  332. desc.pointer = mod->free_page;
  333. /* set wrap flag on last buffer */
  334. if (i == ICAN3_NEW_BUFFERS - 1)
  335. desc.control |= DESC_WRAP;
  336. memcpy_toio(dst, &desc, sizeof(desc));
  337. dst += sizeof(desc);
  338. mod->free_page++;
  339. }
  340. /* fromhost hi queue descriptors are in page 7 */
  341. ican3_set_page(mod, QUEUE_FROMHOST_HIGH);
  342. dst = mod->dpm;
  343. /* initialize only a single buffer in the fromhost hi queue (unused) */
  344. desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
  345. desc.pointer = mod->free_page;
  346. memcpy_toio(dst, &desc, sizeof(desc));
  347. mod->free_page++;
  348. /* fromhost low queue descriptors are in page 8 */
  349. ican3_set_page(mod, QUEUE_FROMHOST_LOW);
  350. dst = mod->dpm;
  351. /* initialize only a single buffer in the fromhost low queue (unused) */
  352. desc.control = DESC_VALID | DESC_WRAP | DESC_LEN(1); /* VW L=1 */
  353. desc.pointer = mod->free_page;
  354. memcpy_toio(dst, &desc, sizeof(desc));
  355. mod->free_page++;
  356. spin_unlock_irqrestore(&mod->lock, flags);
  357. }
  358. /*
  359. * ICAN3 Fast Host Interface Setup
  360. */
  361. static void __devinit ican3_init_fast_host_interface(struct ican3_dev *mod)
  362. {
  363. struct ican3_fast_desc desc;
  364. unsigned long flags;
  365. unsigned int addr;
  366. void __iomem *dst;
  367. int i;
  368. spin_lock_irqsave(&mod->lock, flags);
  369. /* save the start recv page */
  370. mod->fastrx_start = mod->free_page;
  371. mod->fastrx_num = 0;
  372. /* build a single fast tohost queue descriptor */
  373. memset(&desc, 0, sizeof(desc));
  374. desc.control = 0x00;
  375. desc.command = 1;
  376. /* build the tohost queue descriptor ring in memory */
  377. addr = 0;
  378. for (i = 0; i < ICAN3_RX_BUFFERS; i++) {
  379. /* set the wrap bit on the last buffer */
  380. if (i == ICAN3_RX_BUFFERS - 1)
  381. desc.control |= DESC_WRAP;
  382. /* switch to the correct page */
  383. ican3_set_page(mod, mod->free_page);
  384. /* copy the descriptor to the DPM */
  385. dst = mod->dpm + addr;
  386. memcpy_toio(dst, &desc, sizeof(desc));
  387. addr += sizeof(desc);
  388. /* move to the next page if necessary */
  389. if (addr >= DPM_PAGE_SIZE) {
  390. addr = 0;
  391. mod->free_page++;
  392. }
  393. }
  394. /* make sure we page-align the next queue */
  395. if (addr != 0)
  396. mod->free_page++;
  397. /* save the start xmit page */
  398. mod->fasttx_start = mod->free_page;
  399. mod->fasttx_num = 0;
  400. /* build a single fast fromhost queue descriptor */
  401. memset(&desc, 0, sizeof(desc));
  402. desc.control = DESC_VALID;
  403. desc.command = 1;
  404. /* build the fromhost queue descriptor ring in memory */
  405. addr = 0;
  406. for (i = 0; i < ICAN3_TX_BUFFERS; i++) {
  407. /* set the wrap bit on the last buffer */
  408. if (i == ICAN3_TX_BUFFERS - 1)
  409. desc.control |= DESC_WRAP;
  410. /* switch to the correct page */
  411. ican3_set_page(mod, mod->free_page);
  412. /* copy the descriptor to the DPM */
  413. dst = mod->dpm + addr;
  414. memcpy_toio(dst, &desc, sizeof(desc));
  415. addr += sizeof(desc);
  416. /* move to the next page if necessary */
  417. if (addr >= DPM_PAGE_SIZE) {
  418. addr = 0;
  419. mod->free_page++;
  420. }
  421. }
  422. spin_unlock_irqrestore(&mod->lock, flags);
  423. }
  424. /*
  425. * ICAN3 "new-style" Host Interface Message Helpers
  426. */
  427. /*
  428. * LOCKING: must hold mod->lock
  429. */
  430. static int ican3_new_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  431. {
  432. struct ican3_new_desc desc;
  433. void __iomem *desc_addr = mod->dpm + (mod->tx_num * sizeof(desc));
  434. /* switch to the fromhost mid queue, and read the buffer descriptor */
  435. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  436. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  437. if (!(desc.control & DESC_VALID)) {
  438. dev_dbg(mod->dev, "%s: no free buffers\n", __func__);
  439. return -ENOMEM;
  440. }
  441. /* switch to the data page, copy the data */
  442. ican3_set_page(mod, desc.pointer);
  443. memcpy_toio(mod->dpm, msg, sizeof(*msg));
  444. /* switch back to the descriptor, set the valid bit, write it back */
  445. ican3_set_page(mod, QUEUE_FROMHOST_MID);
  446. desc.control ^= DESC_VALID;
  447. memcpy_toio(desc_addr, &desc, sizeof(desc));
  448. /* update the tx number */
  449. mod->tx_num = (desc.control & DESC_WRAP) ? 0 : (mod->tx_num + 1);
  450. return 0;
  451. }
  452. /*
  453. * LOCKING: must hold mod->lock
  454. */
  455. static int ican3_new_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  456. {
  457. struct ican3_new_desc desc;
  458. void __iomem *desc_addr = mod->dpm + (mod->rx_num * sizeof(desc));
  459. /* switch to the tohost queue, and read the buffer descriptor */
  460. ican3_set_page(mod, QUEUE_TOHOST);
  461. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  462. if (!(desc.control & DESC_VALID)) {
  463. dev_dbg(mod->dev, "%s: no buffers to recv\n", __func__);
  464. return -ENOMEM;
  465. }
  466. /* switch to the data page, copy the data */
  467. ican3_set_page(mod, desc.pointer);
  468. memcpy_fromio(msg, mod->dpm, sizeof(*msg));
  469. /* switch back to the descriptor, toggle the valid bit, write it back */
  470. ican3_set_page(mod, QUEUE_TOHOST);
  471. desc.control ^= DESC_VALID;
  472. memcpy_toio(desc_addr, &desc, sizeof(desc));
  473. /* update the rx number */
  474. mod->rx_num = (desc.control & DESC_WRAP) ? 0 : (mod->rx_num + 1);
  475. return 0;
  476. }
  477. /*
  478. * Message Send / Recv Helpers
  479. */
  480. static int ican3_send_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  481. {
  482. unsigned long flags;
  483. int ret;
  484. spin_lock_irqsave(&mod->lock, flags);
  485. if (mod->iftype == 0)
  486. ret = ican3_old_send_msg(mod, msg);
  487. else
  488. ret = ican3_new_send_msg(mod, msg);
  489. spin_unlock_irqrestore(&mod->lock, flags);
  490. return ret;
  491. }
  492. static int ican3_recv_msg(struct ican3_dev *mod, struct ican3_msg *msg)
  493. {
  494. unsigned long flags;
  495. int ret;
  496. spin_lock_irqsave(&mod->lock, flags);
  497. if (mod->iftype == 0)
  498. ret = ican3_old_recv_msg(mod, msg);
  499. else
  500. ret = ican3_new_recv_msg(mod, msg);
  501. spin_unlock_irqrestore(&mod->lock, flags);
  502. return ret;
  503. }
  504. /*
  505. * Quick Pre-constructed Messages
  506. */
  507. static int __devinit ican3_msg_connect(struct ican3_dev *mod)
  508. {
  509. struct ican3_msg msg;
  510. memset(&msg, 0, sizeof(msg));
  511. msg.spec = MSG_CONNECTI;
  512. msg.len = cpu_to_le16(0);
  513. return ican3_send_msg(mod, &msg);
  514. }
  515. static int __devexit ican3_msg_disconnect(struct ican3_dev *mod)
  516. {
  517. struct ican3_msg msg;
  518. memset(&msg, 0, sizeof(msg));
  519. msg.spec = MSG_DISCONNECT;
  520. msg.len = cpu_to_le16(0);
  521. return ican3_send_msg(mod, &msg);
  522. }
  523. static int __devinit ican3_msg_newhostif(struct ican3_dev *mod)
  524. {
  525. struct ican3_msg msg;
  526. int ret;
  527. memset(&msg, 0, sizeof(msg));
  528. msg.spec = MSG_NEWHOSTIF;
  529. msg.len = cpu_to_le16(0);
  530. /* If we're not using the old interface, switching seems bogus */
  531. WARN_ON(mod->iftype != 0);
  532. ret = ican3_send_msg(mod, &msg);
  533. if (ret)
  534. return ret;
  535. /* mark the module as using the new host interface */
  536. mod->iftype = 1;
  537. return 0;
  538. }
  539. static int __devinit ican3_msg_fasthostif(struct ican3_dev *mod)
  540. {
  541. struct ican3_msg msg;
  542. unsigned int addr;
  543. memset(&msg, 0, sizeof(msg));
  544. msg.spec = MSG_INITFDPMQUEUE;
  545. msg.len = cpu_to_le16(8);
  546. /* write the tohost queue start address */
  547. addr = DPM_PAGE_ADDR(mod->fastrx_start);
  548. msg.data[0] = addr & 0xff;
  549. msg.data[1] = (addr >> 8) & 0xff;
  550. msg.data[2] = (addr >> 16) & 0xff;
  551. msg.data[3] = (addr >> 24) & 0xff;
  552. /* write the fromhost queue start address */
  553. addr = DPM_PAGE_ADDR(mod->fasttx_start);
  554. msg.data[4] = addr & 0xff;
  555. msg.data[5] = (addr >> 8) & 0xff;
  556. msg.data[6] = (addr >> 16) & 0xff;
  557. msg.data[7] = (addr >> 24) & 0xff;
  558. /* If we're not using the new interface yet, we cannot do this */
  559. WARN_ON(mod->iftype != 1);
  560. return ican3_send_msg(mod, &msg);
  561. }
  562. /*
  563. * Setup the CAN filter to either accept or reject all
  564. * messages from the CAN bus.
  565. */
  566. static int __devinit ican3_set_id_filter(struct ican3_dev *mod, bool accept)
  567. {
  568. struct ican3_msg msg;
  569. int ret;
  570. /* Standard Frame Format */
  571. memset(&msg, 0, sizeof(msg));
  572. msg.spec = MSG_SETAFILMASK;
  573. msg.len = cpu_to_le16(5);
  574. msg.data[0] = 0x00; /* IDLo LSB */
  575. msg.data[1] = 0x00; /* IDLo MSB */
  576. msg.data[2] = 0xff; /* IDHi LSB */
  577. msg.data[3] = 0x07; /* IDHi MSB */
  578. /* accept all frames for fast host if, or reject all frames */
  579. msg.data[4] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
  580. ret = ican3_send_msg(mod, &msg);
  581. if (ret)
  582. return ret;
  583. /* Extended Frame Format */
  584. memset(&msg, 0, sizeof(msg));
  585. msg.spec = MSG_SETAFILMASK;
  586. msg.len = cpu_to_le16(13);
  587. msg.data[0] = 0; /* MUX = 0 */
  588. msg.data[1] = 0x00; /* IDLo LSB */
  589. msg.data[2] = 0x00;
  590. msg.data[3] = 0x00;
  591. msg.data[4] = 0x20; /* IDLo MSB */
  592. msg.data[5] = 0xff; /* IDHi LSB */
  593. msg.data[6] = 0xff;
  594. msg.data[7] = 0xff;
  595. msg.data[8] = 0x3f; /* IDHi MSB */
  596. /* accept all frames for fast host if, or reject all frames */
  597. msg.data[9] = accept ? SETAFILMASK_FASTIF : SETAFILMASK_REJECT;
  598. return ican3_send_msg(mod, &msg);
  599. }
  600. /*
  601. * Bring the CAN bus online or offline
  602. */
  603. static int ican3_set_bus_state(struct ican3_dev *mod, bool on)
  604. {
  605. struct ican3_msg msg;
  606. memset(&msg, 0, sizeof(msg));
  607. msg.spec = on ? MSG_CONREQ : MSG_COFFREQ;
  608. msg.len = cpu_to_le16(0);
  609. return ican3_send_msg(mod, &msg);
  610. }
  611. static int ican3_set_termination(struct ican3_dev *mod, bool on)
  612. {
  613. struct ican3_msg msg;
  614. memset(&msg, 0, sizeof(msg));
  615. msg.spec = MSG_HWCONF;
  616. msg.len = cpu_to_le16(2);
  617. msg.data[0] = 0x00;
  618. msg.data[1] = on ? HWCONF_TERMINATE_ON : HWCONF_TERMINATE_OFF;
  619. return ican3_send_msg(mod, &msg);
  620. }
  621. static int ican3_send_inquiry(struct ican3_dev *mod, u8 subspec)
  622. {
  623. struct ican3_msg msg;
  624. memset(&msg, 0, sizeof(msg));
  625. msg.spec = MSG_INQUIRY;
  626. msg.len = cpu_to_le16(2);
  627. msg.data[0] = subspec;
  628. msg.data[1] = 0x00;
  629. return ican3_send_msg(mod, &msg);
  630. }
  631. static int ican3_set_buserror(struct ican3_dev *mod, u8 quota)
  632. {
  633. struct ican3_msg msg;
  634. memset(&msg, 0, sizeof(msg));
  635. msg.spec = MSG_CCONFREQ;
  636. msg.len = cpu_to_le16(2);
  637. msg.data[0] = 0x00;
  638. msg.data[1] = quota;
  639. return ican3_send_msg(mod, &msg);
  640. }
  641. /*
  642. * ICAN3 to Linux CAN Frame Conversion
  643. */
  644. static void ican3_to_can_frame(struct ican3_dev *mod,
  645. struct ican3_fast_desc *desc,
  646. struct can_frame *cf)
  647. {
  648. if ((desc->command & ICAN3_CAN_TYPE_MASK) == ICAN3_CAN_TYPE_SFF) {
  649. if (desc->data[1] & ICAN3_SFF_RTR)
  650. cf->can_id |= CAN_RTR_FLAG;
  651. cf->can_id |= desc->data[0] << 3;
  652. cf->can_id |= (desc->data[1] & 0xe0) >> 5;
  653. cf->can_dlc = get_can_dlc(desc->data[1] & ICAN3_CAN_DLC_MASK);
  654. memcpy(cf->data, &desc->data[2], cf->can_dlc);
  655. } else {
  656. cf->can_dlc = get_can_dlc(desc->data[0] & ICAN3_CAN_DLC_MASK);
  657. if (desc->data[0] & ICAN3_EFF_RTR)
  658. cf->can_id |= CAN_RTR_FLAG;
  659. if (desc->data[0] & ICAN3_EFF) {
  660. cf->can_id |= CAN_EFF_FLAG;
  661. cf->can_id |= desc->data[2] << 21; /* 28-21 */
  662. cf->can_id |= desc->data[3] << 13; /* 20-13 */
  663. cf->can_id |= desc->data[4] << 5; /* 12-5 */
  664. cf->can_id |= (desc->data[5] & 0xf8) >> 3;
  665. } else {
  666. cf->can_id |= desc->data[2] << 3; /* 10-3 */
  667. cf->can_id |= desc->data[3] >> 5; /* 2-0 */
  668. }
  669. memcpy(cf->data, &desc->data[6], cf->can_dlc);
  670. }
  671. }
  672. static void can_frame_to_ican3(struct ican3_dev *mod,
  673. struct can_frame *cf,
  674. struct ican3_fast_desc *desc)
  675. {
  676. /* clear out any stale data in the descriptor */
  677. memset(desc->data, 0, sizeof(desc->data));
  678. /* we always use the extended format, with the ECHO flag set */
  679. desc->command = ICAN3_CAN_TYPE_EFF;
  680. desc->data[0] |= cf->can_dlc;
  681. desc->data[1] |= ICAN3_ECHO;
  682. /* support single transmission (no retries) mode */
  683. if (mod->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
  684. desc->data[1] |= ICAN3_SNGL;
  685. if (cf->can_id & CAN_RTR_FLAG)
  686. desc->data[0] |= ICAN3_EFF_RTR;
  687. /* pack the id into the correct places */
  688. if (cf->can_id & CAN_EFF_FLAG) {
  689. desc->data[0] |= ICAN3_EFF;
  690. desc->data[2] = (cf->can_id & 0x1fe00000) >> 21; /* 28-21 */
  691. desc->data[3] = (cf->can_id & 0x001fe000) >> 13; /* 20-13 */
  692. desc->data[4] = (cf->can_id & 0x00001fe0) >> 5; /* 12-5 */
  693. desc->data[5] = (cf->can_id & 0x0000001f) << 3; /* 4-0 */
  694. } else {
  695. desc->data[2] = (cf->can_id & 0x7F8) >> 3; /* bits 10-3 */
  696. desc->data[3] = (cf->can_id & 0x007) << 5; /* bits 2-0 */
  697. }
  698. /* copy the data bits into the descriptor */
  699. memcpy(&desc->data[6], cf->data, cf->can_dlc);
  700. }
  701. /*
  702. * Interrupt Handling
  703. */
  704. /*
  705. * Handle an ID + Version message response from the firmware. We never generate
  706. * this message in production code, but it is very useful when debugging to be
  707. * able to display this message.
  708. */
  709. static void ican3_handle_idvers(struct ican3_dev *mod, struct ican3_msg *msg)
  710. {
  711. dev_dbg(mod->dev, "IDVERS response: %s\n", msg->data);
  712. }
  713. static void ican3_handle_msglost(struct ican3_dev *mod, struct ican3_msg *msg)
  714. {
  715. struct net_device *dev = mod->ndev;
  716. struct net_device_stats *stats = &dev->stats;
  717. struct can_frame *cf;
  718. struct sk_buff *skb;
  719. /*
  720. * Report that communication messages with the microcontroller firmware
  721. * are being lost. These are never CAN frames, so we do not generate an
  722. * error frame for userspace
  723. */
  724. if (msg->spec == MSG_MSGLOST) {
  725. dev_err(mod->dev, "lost %d control messages\n", msg->data[0]);
  726. return;
  727. }
  728. /*
  729. * Oops, this indicates that we have lost messages in the fast queue,
  730. * which are exclusively CAN messages. Our driver isn't reading CAN
  731. * frames fast enough.
  732. *
  733. * We'll pretend that the SJA1000 told us that it ran out of buffer
  734. * space, because there is not a better message for this.
  735. */
  736. skb = alloc_can_err_skb(dev, &cf);
  737. if (skb) {
  738. cf->can_id |= CAN_ERR_CRTL;
  739. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  740. stats->rx_over_errors++;
  741. stats->rx_errors++;
  742. netif_rx(skb);
  743. }
  744. }
  745. /*
  746. * Handle CAN Event Indication Messages from the firmware
  747. *
  748. * The ICAN3 firmware provides the values of some SJA1000 registers when it
  749. * generates this message. The code below is largely copied from the
  750. * drivers/net/can/sja1000/sja1000.c file, and adapted as necessary
  751. */
  752. static int ican3_handle_cevtind(struct ican3_dev *mod, struct ican3_msg *msg)
  753. {
  754. struct net_device *dev = mod->ndev;
  755. struct net_device_stats *stats = &dev->stats;
  756. enum can_state state = mod->can.state;
  757. u8 isrc, ecc, status, rxerr, txerr;
  758. struct can_frame *cf;
  759. struct sk_buff *skb;
  760. /* we can only handle the SJA1000 part */
  761. if (msg->data[1] != CEVTIND_CHIP_SJA1000) {
  762. dev_err(mod->dev, "unable to handle errors on non-SJA1000\n");
  763. return -ENODEV;
  764. }
  765. /* check the message length for sanity */
  766. if (le16_to_cpu(msg->len) < 6) {
  767. dev_err(mod->dev, "error message too short\n");
  768. return -EINVAL;
  769. }
  770. isrc = msg->data[0];
  771. ecc = msg->data[2];
  772. status = msg->data[3];
  773. rxerr = msg->data[4];
  774. txerr = msg->data[5];
  775. /*
  776. * This hardware lacks any support other than bus error messages to
  777. * determine if packet transmission has failed.
  778. *
  779. * When TX errors happen, one echo skb needs to be dropped from the
  780. * front of the queue.
  781. *
  782. * A small bit of code is duplicated here and below, to avoid error
  783. * skb allocation when it will just be freed immediately.
  784. */
  785. if (isrc == CEVTIND_BEI) {
  786. int ret;
  787. dev_dbg(mod->dev, "bus error interrupt\n");
  788. /* TX error */
  789. if (!(ecc & ECC_DIR)) {
  790. kfree_skb(skb_dequeue(&mod->echoq));
  791. stats->tx_errors++;
  792. } else {
  793. stats->rx_errors++;
  794. }
  795. /*
  796. * The controller automatically disables bus-error interrupts
  797. * and therefore we must re-enable them.
  798. */
  799. ret = ican3_set_buserror(mod, 1);
  800. if (ret) {
  801. dev_err(mod->dev, "unable to re-enable bus-error\n");
  802. return ret;
  803. }
  804. /* bus error reporting is off, return immediately */
  805. if (!(mod->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
  806. return 0;
  807. }
  808. skb = alloc_can_err_skb(dev, &cf);
  809. if (skb == NULL)
  810. return -ENOMEM;
  811. /* data overrun interrupt */
  812. if (isrc == CEVTIND_DOI || isrc == CEVTIND_LOST) {
  813. dev_dbg(mod->dev, "data overrun interrupt\n");
  814. cf->can_id |= CAN_ERR_CRTL;
  815. cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
  816. stats->rx_over_errors++;
  817. stats->rx_errors++;
  818. }
  819. /* error warning + passive interrupt */
  820. if (isrc == CEVTIND_EI) {
  821. dev_dbg(mod->dev, "error warning + passive interrupt\n");
  822. if (status & SR_BS) {
  823. state = CAN_STATE_BUS_OFF;
  824. cf->can_id |= CAN_ERR_BUSOFF;
  825. can_bus_off(dev);
  826. } else if (status & SR_ES) {
  827. if (rxerr >= 128 || txerr >= 128)
  828. state = CAN_STATE_ERROR_PASSIVE;
  829. else
  830. state = CAN_STATE_ERROR_WARNING;
  831. } else {
  832. state = CAN_STATE_ERROR_ACTIVE;
  833. }
  834. }
  835. /* bus error interrupt */
  836. if (isrc == CEVTIND_BEI) {
  837. mod->can.can_stats.bus_error++;
  838. cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
  839. switch (ecc & ECC_MASK) {
  840. case ECC_BIT:
  841. cf->data[2] |= CAN_ERR_PROT_BIT;
  842. break;
  843. case ECC_FORM:
  844. cf->data[2] |= CAN_ERR_PROT_FORM;
  845. break;
  846. case ECC_STUFF:
  847. cf->data[2] |= CAN_ERR_PROT_STUFF;
  848. break;
  849. default:
  850. cf->data[2] |= CAN_ERR_PROT_UNSPEC;
  851. cf->data[3] = ecc & ECC_SEG;
  852. break;
  853. }
  854. if (!(ecc & ECC_DIR))
  855. cf->data[2] |= CAN_ERR_PROT_TX;
  856. cf->data[6] = txerr;
  857. cf->data[7] = rxerr;
  858. }
  859. if (state != mod->can.state && (state == CAN_STATE_ERROR_WARNING ||
  860. state == CAN_STATE_ERROR_PASSIVE)) {
  861. cf->can_id |= CAN_ERR_CRTL;
  862. if (state == CAN_STATE_ERROR_WARNING) {
  863. mod->can.can_stats.error_warning++;
  864. cf->data[1] = (txerr > rxerr) ?
  865. CAN_ERR_CRTL_TX_WARNING :
  866. CAN_ERR_CRTL_RX_WARNING;
  867. } else {
  868. mod->can.can_stats.error_passive++;
  869. cf->data[1] = (txerr > rxerr) ?
  870. CAN_ERR_CRTL_TX_PASSIVE :
  871. CAN_ERR_CRTL_RX_PASSIVE;
  872. }
  873. cf->data[6] = txerr;
  874. cf->data[7] = rxerr;
  875. }
  876. mod->can.state = state;
  877. netif_rx(skb);
  878. return 0;
  879. }
  880. static void ican3_handle_inquiry(struct ican3_dev *mod, struct ican3_msg *msg)
  881. {
  882. switch (msg->data[0]) {
  883. case INQUIRY_STATUS:
  884. case INQUIRY_EXTENDED:
  885. mod->bec.rxerr = msg->data[5];
  886. mod->bec.txerr = msg->data[6];
  887. complete(&mod->buserror_comp);
  888. break;
  889. case INQUIRY_TERMINATION:
  890. mod->termination_enabled = msg->data[6] & HWCONF_TERMINATE_ON;
  891. complete(&mod->termination_comp);
  892. break;
  893. default:
  894. dev_err(mod->dev, "received an unknown inquiry response\n");
  895. break;
  896. }
  897. }
  898. static void ican3_handle_unknown_message(struct ican3_dev *mod,
  899. struct ican3_msg *msg)
  900. {
  901. dev_warn(mod->dev, "received unknown message: spec 0x%.2x length %d\n",
  902. msg->spec, le16_to_cpu(msg->len));
  903. }
  904. /*
  905. * Handle a control message from the firmware
  906. */
  907. static void ican3_handle_message(struct ican3_dev *mod, struct ican3_msg *msg)
  908. {
  909. dev_dbg(mod->dev, "%s: modno %d spec 0x%.2x len %d bytes\n", __func__,
  910. mod->num, msg->spec, le16_to_cpu(msg->len));
  911. switch (msg->spec) {
  912. case MSG_IDVERS:
  913. ican3_handle_idvers(mod, msg);
  914. break;
  915. case MSG_MSGLOST:
  916. case MSG_FMSGLOST:
  917. ican3_handle_msglost(mod, msg);
  918. break;
  919. case MSG_CEVTIND:
  920. ican3_handle_cevtind(mod, msg);
  921. break;
  922. case MSG_INQUIRY:
  923. ican3_handle_inquiry(mod, msg);
  924. break;
  925. default:
  926. ican3_handle_unknown_message(mod, msg);
  927. break;
  928. }
  929. }
  930. /*
  931. * The ican3 needs to store all echo skbs, and therefore cannot
  932. * use the generic infrastructure for this.
  933. */
  934. static void ican3_put_echo_skb(struct ican3_dev *mod, struct sk_buff *skb)
  935. {
  936. struct sock *srcsk = skb->sk;
  937. if (atomic_read(&skb->users) != 1) {
  938. struct sk_buff *old_skb = skb;
  939. skb = skb_clone(old_skb, GFP_ATOMIC);
  940. kfree_skb(old_skb);
  941. if (!skb)
  942. return;
  943. } else {
  944. skb_orphan(skb);
  945. }
  946. skb->sk = srcsk;
  947. /* save this skb for tx interrupt echo handling */
  948. skb_queue_tail(&mod->echoq, skb);
  949. }
  950. static unsigned int ican3_get_echo_skb(struct ican3_dev *mod)
  951. {
  952. struct sk_buff *skb = skb_dequeue(&mod->echoq);
  953. struct can_frame *cf;
  954. u8 dlc;
  955. /* this should never trigger unless there is a driver bug */
  956. if (!skb) {
  957. netdev_err(mod->ndev, "BUG: echo skb not occupied\n");
  958. return 0;
  959. }
  960. cf = (struct can_frame *)skb->data;
  961. dlc = cf->can_dlc;
  962. /* check flag whether this packet has to be looped back */
  963. if (skb->pkt_type != PACKET_LOOPBACK) {
  964. kfree_skb(skb);
  965. return dlc;
  966. }
  967. skb->protocol = htons(ETH_P_CAN);
  968. skb->pkt_type = PACKET_BROADCAST;
  969. skb->ip_summed = CHECKSUM_UNNECESSARY;
  970. skb->dev = mod->ndev;
  971. netif_receive_skb(skb);
  972. return dlc;
  973. }
  974. /*
  975. * Compare an skb with an existing echo skb
  976. *
  977. * This function will be used on devices which have a hardware loopback.
  978. * On these devices, this function can be used to compare a received skb
  979. * with the saved echo skbs so that the hardware echo skb can be dropped.
  980. *
  981. * Returns true if the skb's are identical, false otherwise.
  982. */
  983. static bool ican3_echo_skb_matches(struct ican3_dev *mod, struct sk_buff *skb)
  984. {
  985. struct can_frame *cf = (struct can_frame *)skb->data;
  986. struct sk_buff *echo_skb = skb_peek(&mod->echoq);
  987. struct can_frame *echo_cf;
  988. if (!echo_skb)
  989. return false;
  990. echo_cf = (struct can_frame *)echo_skb->data;
  991. if (cf->can_id != echo_cf->can_id)
  992. return false;
  993. if (cf->can_dlc != echo_cf->can_dlc)
  994. return false;
  995. return memcmp(cf->data, echo_cf->data, cf->can_dlc) == 0;
  996. }
  997. /*
  998. * Check that there is room in the TX ring to transmit another skb
  999. *
  1000. * LOCKING: must hold mod->lock
  1001. */
  1002. static bool ican3_txok(struct ican3_dev *mod)
  1003. {
  1004. struct ican3_fast_desc __iomem *desc;
  1005. u8 control;
  1006. /* check that we have echo queue space */
  1007. if (skb_queue_len(&mod->echoq) >= ICAN3_TX_BUFFERS)
  1008. return false;
  1009. /* copy the control bits of the descriptor */
  1010. ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
  1011. desc = mod->dpm + ((mod->fasttx_num % 16) * sizeof(*desc));
  1012. control = ioread8(&desc->control);
  1013. /* if the control bits are not valid, then we have no more space */
  1014. if (!(control & DESC_VALID))
  1015. return false;
  1016. return true;
  1017. }
  1018. /*
  1019. * Receive one CAN frame from the hardware
  1020. *
  1021. * CONTEXT: must be called from user context
  1022. */
  1023. static int ican3_recv_skb(struct ican3_dev *mod)
  1024. {
  1025. struct net_device *ndev = mod->ndev;
  1026. struct net_device_stats *stats = &ndev->stats;
  1027. struct ican3_fast_desc desc;
  1028. void __iomem *desc_addr;
  1029. struct can_frame *cf;
  1030. struct sk_buff *skb;
  1031. unsigned long flags;
  1032. spin_lock_irqsave(&mod->lock, flags);
  1033. /* copy the whole descriptor */
  1034. ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
  1035. desc_addr = mod->dpm + ((mod->fastrx_num % 16) * sizeof(desc));
  1036. memcpy_fromio(&desc, desc_addr, sizeof(desc));
  1037. spin_unlock_irqrestore(&mod->lock, flags);
  1038. /* check that we actually have a CAN frame */
  1039. if (!(desc.control & DESC_VALID))
  1040. return -ENOBUFS;
  1041. /* allocate an skb */
  1042. skb = alloc_can_skb(ndev, &cf);
  1043. if (unlikely(skb == NULL)) {
  1044. stats->rx_dropped++;
  1045. goto err_noalloc;
  1046. }
  1047. /* convert the ICAN3 frame into Linux CAN format */
  1048. ican3_to_can_frame(mod, &desc, cf);
  1049. /*
  1050. * If this is an ECHO frame received from the hardware loopback
  1051. * feature, use the skb saved in the ECHO stack instead. This allows
  1052. * the Linux CAN core to support CAN_RAW_RECV_OWN_MSGS correctly.
  1053. *
  1054. * Since this is a confirmation of a successfully transmitted packet
  1055. * sent from this host, update the transmit statistics.
  1056. *
  1057. * Also, the netdevice queue needs to be allowed to send packets again.
  1058. */
  1059. if (ican3_echo_skb_matches(mod, skb)) {
  1060. stats->tx_packets++;
  1061. stats->tx_bytes += ican3_get_echo_skb(mod);
  1062. kfree_skb(skb);
  1063. goto err_noalloc;
  1064. }
  1065. /* update statistics, receive the skb */
  1066. stats->rx_packets++;
  1067. stats->rx_bytes += cf->can_dlc;
  1068. netif_receive_skb(skb);
  1069. err_noalloc:
  1070. /* toggle the valid bit and return the descriptor to the ring */
  1071. desc.control ^= DESC_VALID;
  1072. spin_lock_irqsave(&mod->lock, flags);
  1073. ican3_set_page(mod, mod->fastrx_start + (mod->fastrx_num / 16));
  1074. memcpy_toio(desc_addr, &desc, 1);
  1075. /* update the next buffer pointer */
  1076. mod->fastrx_num = (desc.control & DESC_WRAP) ? 0
  1077. : (mod->fastrx_num + 1);
  1078. /* there are still more buffers to process */
  1079. spin_unlock_irqrestore(&mod->lock, flags);
  1080. return 0;
  1081. }
  1082. static int ican3_napi(struct napi_struct *napi, int budget)
  1083. {
  1084. struct ican3_dev *mod = container_of(napi, struct ican3_dev, napi);
  1085. unsigned long flags;
  1086. int received = 0;
  1087. int ret;
  1088. /* process all communication messages */
  1089. while (true) {
  1090. struct ican3_msg msg;
  1091. ret = ican3_recv_msg(mod, &msg);
  1092. if (ret)
  1093. break;
  1094. ican3_handle_message(mod, &msg);
  1095. }
  1096. /* process all CAN frames from the fast interface */
  1097. while (received < budget) {
  1098. ret = ican3_recv_skb(mod);
  1099. if (ret)
  1100. break;
  1101. received++;
  1102. }
  1103. /* We have processed all packets that the adapter had, but it
  1104. * was less than our budget, stop polling */
  1105. if (received < budget)
  1106. napi_complete(napi);
  1107. spin_lock_irqsave(&mod->lock, flags);
  1108. /* Wake up the transmit queue if necessary */
  1109. if (netif_queue_stopped(mod->ndev) && ican3_txok(mod))
  1110. netif_wake_queue(mod->ndev);
  1111. spin_unlock_irqrestore(&mod->lock, flags);
  1112. /* re-enable interrupt generation */
  1113. iowrite8(1 << mod->num, &mod->ctrl->int_enable);
  1114. return received;
  1115. }
  1116. static irqreturn_t ican3_irq(int irq, void *dev_id)
  1117. {
  1118. struct ican3_dev *mod = dev_id;
  1119. u8 stat;
  1120. /*
  1121. * The interrupt status register on this device reports interrupts
  1122. * as zeroes instead of using ones like most other devices
  1123. */
  1124. stat = ioread8(&mod->ctrl->int_disable) & (1 << mod->num);
  1125. if (stat == (1 << mod->num))
  1126. return IRQ_NONE;
  1127. /* clear the MODULbus interrupt from the microcontroller */
  1128. ioread8(&mod->dpmctrl->interrupt);
  1129. /* disable interrupt generation, schedule the NAPI poller */
  1130. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1131. napi_schedule(&mod->napi);
  1132. return IRQ_HANDLED;
  1133. }
  1134. /*
  1135. * Firmware reset, startup, and shutdown
  1136. */
  1137. /*
  1138. * Reset an ICAN module to its power-on state
  1139. *
  1140. * CONTEXT: no network device registered
  1141. */
  1142. static int ican3_reset_module(struct ican3_dev *mod)
  1143. {
  1144. u8 val = 1 << mod->num;
  1145. unsigned long start;
  1146. u8 runold, runnew;
  1147. /* disable interrupts so no more work is scheduled */
  1148. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1149. /* the first unallocated page in the DPM is #9 */
  1150. mod->free_page = DPM_FREE_START;
  1151. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  1152. runold = ioread8(mod->dpm + TARGET_RUNNING);
  1153. /* reset the module */
  1154. iowrite8(val, &mod->ctrl->reset_assert);
  1155. iowrite8(val, &mod->ctrl->reset_deassert);
  1156. /* wait until the module has finished resetting and is running */
  1157. start = jiffies;
  1158. do {
  1159. ican3_set_page(mod, QUEUE_OLD_CONTROL);
  1160. runnew = ioread8(mod->dpm + TARGET_RUNNING);
  1161. if (runnew == (runold ^ 0xff))
  1162. return 0;
  1163. msleep(10);
  1164. } while (time_before(jiffies, start + HZ / 4));
  1165. dev_err(mod->dev, "failed to reset CAN module\n");
  1166. return -ETIMEDOUT;
  1167. }
  1168. static void __devexit ican3_shutdown_module(struct ican3_dev *mod)
  1169. {
  1170. ican3_msg_disconnect(mod);
  1171. ican3_reset_module(mod);
  1172. }
  1173. /*
  1174. * Startup an ICAN module, bringing it into fast mode
  1175. */
  1176. static int __devinit ican3_startup_module(struct ican3_dev *mod)
  1177. {
  1178. int ret;
  1179. ret = ican3_reset_module(mod);
  1180. if (ret) {
  1181. dev_err(mod->dev, "unable to reset module\n");
  1182. return ret;
  1183. }
  1184. /* re-enable interrupts so we can send messages */
  1185. iowrite8(1 << mod->num, &mod->ctrl->int_enable);
  1186. ret = ican3_msg_connect(mod);
  1187. if (ret) {
  1188. dev_err(mod->dev, "unable to connect to module\n");
  1189. return ret;
  1190. }
  1191. ican3_init_new_host_interface(mod);
  1192. ret = ican3_msg_newhostif(mod);
  1193. if (ret) {
  1194. dev_err(mod->dev, "unable to switch to new-style interface\n");
  1195. return ret;
  1196. }
  1197. /* default to "termination on" */
  1198. ret = ican3_set_termination(mod, true);
  1199. if (ret) {
  1200. dev_err(mod->dev, "unable to enable termination\n");
  1201. return ret;
  1202. }
  1203. /* default to "bus errors enabled" */
  1204. ret = ican3_set_buserror(mod, 1);
  1205. if (ret) {
  1206. dev_err(mod->dev, "unable to set bus-error\n");
  1207. return ret;
  1208. }
  1209. ican3_init_fast_host_interface(mod);
  1210. ret = ican3_msg_fasthostif(mod);
  1211. if (ret) {
  1212. dev_err(mod->dev, "unable to switch to fast host interface\n");
  1213. return ret;
  1214. }
  1215. ret = ican3_set_id_filter(mod, true);
  1216. if (ret) {
  1217. dev_err(mod->dev, "unable to set acceptance filter\n");
  1218. return ret;
  1219. }
  1220. return 0;
  1221. }
  1222. /*
  1223. * CAN Network Device
  1224. */
  1225. static int ican3_open(struct net_device *ndev)
  1226. {
  1227. struct ican3_dev *mod = netdev_priv(ndev);
  1228. int ret;
  1229. /* open the CAN layer */
  1230. ret = open_candev(ndev);
  1231. if (ret) {
  1232. dev_err(mod->dev, "unable to start CAN layer\n");
  1233. return ret;
  1234. }
  1235. /* bring the bus online */
  1236. ret = ican3_set_bus_state(mod, true);
  1237. if (ret) {
  1238. dev_err(mod->dev, "unable to set bus-on\n");
  1239. close_candev(ndev);
  1240. return ret;
  1241. }
  1242. /* start up the network device */
  1243. mod->can.state = CAN_STATE_ERROR_ACTIVE;
  1244. netif_start_queue(ndev);
  1245. return 0;
  1246. }
  1247. static int ican3_stop(struct net_device *ndev)
  1248. {
  1249. struct ican3_dev *mod = netdev_priv(ndev);
  1250. int ret;
  1251. /* stop the network device xmit routine */
  1252. netif_stop_queue(ndev);
  1253. mod->can.state = CAN_STATE_STOPPED;
  1254. /* bring the bus offline, stop receiving packets */
  1255. ret = ican3_set_bus_state(mod, false);
  1256. if (ret) {
  1257. dev_err(mod->dev, "unable to set bus-off\n");
  1258. return ret;
  1259. }
  1260. /* drop all outstanding echo skbs */
  1261. skb_queue_purge(&mod->echoq);
  1262. /* close the CAN layer */
  1263. close_candev(ndev);
  1264. return 0;
  1265. }
  1266. static int ican3_xmit(struct sk_buff *skb, struct net_device *ndev)
  1267. {
  1268. struct ican3_dev *mod = netdev_priv(ndev);
  1269. struct can_frame *cf = (struct can_frame *)skb->data;
  1270. struct ican3_fast_desc desc;
  1271. void __iomem *desc_addr;
  1272. unsigned long flags;
  1273. if (can_dropped_invalid_skb(ndev, skb))
  1274. return NETDEV_TX_OK;
  1275. spin_lock_irqsave(&mod->lock, flags);
  1276. /* check that we can actually transmit */
  1277. if (!ican3_txok(mod)) {
  1278. dev_err(mod->dev, "BUG: no free descriptors\n");
  1279. spin_unlock_irqrestore(&mod->lock, flags);
  1280. return NETDEV_TX_BUSY;
  1281. }
  1282. /* copy the control bits of the descriptor */
  1283. ican3_set_page(mod, mod->fasttx_start + (mod->fasttx_num / 16));
  1284. desc_addr = mod->dpm + ((mod->fasttx_num % 16) * sizeof(desc));
  1285. memset(&desc, 0, sizeof(desc));
  1286. memcpy_fromio(&desc, desc_addr, 1);
  1287. /* convert the Linux CAN frame into ICAN3 format */
  1288. can_frame_to_ican3(mod, cf, &desc);
  1289. /*
  1290. * This hardware doesn't have TX-done notifications, so we'll try and
  1291. * emulate it the best we can using ECHO skbs. Add the skb to the ECHO
  1292. * stack. Upon packet reception, check if the ECHO skb and received
  1293. * skb match, and use that to wake the queue.
  1294. */
  1295. ican3_put_echo_skb(mod, skb);
  1296. /*
  1297. * the programming manual says that you must set the IVALID bit, then
  1298. * interrupt, then set the valid bit. Quite weird, but it seems to be
  1299. * required for this to work
  1300. */
  1301. desc.control |= DESC_IVALID;
  1302. memcpy_toio(desc_addr, &desc, sizeof(desc));
  1303. /* generate a MODULbus interrupt to the microcontroller */
  1304. iowrite8(0x01, &mod->dpmctrl->interrupt);
  1305. desc.control ^= DESC_VALID;
  1306. memcpy_toio(desc_addr, &desc, sizeof(desc));
  1307. /* update the next buffer pointer */
  1308. mod->fasttx_num = (desc.control & DESC_WRAP) ? 0
  1309. : (mod->fasttx_num + 1);
  1310. /* if there is no free descriptor space, stop the transmit queue */
  1311. if (!ican3_txok(mod))
  1312. netif_stop_queue(ndev);
  1313. spin_unlock_irqrestore(&mod->lock, flags);
  1314. return NETDEV_TX_OK;
  1315. }
  1316. static const struct net_device_ops ican3_netdev_ops = {
  1317. .ndo_open = ican3_open,
  1318. .ndo_stop = ican3_stop,
  1319. .ndo_start_xmit = ican3_xmit,
  1320. };
  1321. /*
  1322. * Low-level CAN Device
  1323. */
  1324. /* This structure was stolen from drivers/net/can/sja1000/sja1000.c */
  1325. static const struct can_bittiming_const ican3_bittiming_const = {
  1326. .name = DRV_NAME,
  1327. .tseg1_min = 1,
  1328. .tseg1_max = 16,
  1329. .tseg2_min = 1,
  1330. .tseg2_max = 8,
  1331. .sjw_max = 4,
  1332. .brp_min = 1,
  1333. .brp_max = 64,
  1334. .brp_inc = 1,
  1335. };
  1336. /*
  1337. * This routine was stolen from drivers/net/can/sja1000/sja1000.c
  1338. *
  1339. * The bittiming register command for the ICAN3 just sets the bit timing
  1340. * registers on the SJA1000 chip directly
  1341. */
  1342. static int ican3_set_bittiming(struct net_device *ndev)
  1343. {
  1344. struct ican3_dev *mod = netdev_priv(ndev);
  1345. struct can_bittiming *bt = &mod->can.bittiming;
  1346. struct ican3_msg msg;
  1347. u8 btr0, btr1;
  1348. btr0 = ((bt->brp - 1) & 0x3f) | (((bt->sjw - 1) & 0x3) << 6);
  1349. btr1 = ((bt->prop_seg + bt->phase_seg1 - 1) & 0xf) |
  1350. (((bt->phase_seg2 - 1) & 0x7) << 4);
  1351. if (mod->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
  1352. btr1 |= 0x80;
  1353. memset(&msg, 0, sizeof(msg));
  1354. msg.spec = MSG_CBTRREQ;
  1355. msg.len = cpu_to_le16(4);
  1356. msg.data[0] = 0x00;
  1357. msg.data[1] = 0x00;
  1358. msg.data[2] = btr0;
  1359. msg.data[3] = btr1;
  1360. return ican3_send_msg(mod, &msg);
  1361. }
  1362. static int ican3_set_mode(struct net_device *ndev, enum can_mode mode)
  1363. {
  1364. struct ican3_dev *mod = netdev_priv(ndev);
  1365. int ret;
  1366. if (mode != CAN_MODE_START)
  1367. return -ENOTSUPP;
  1368. /* bring the bus online */
  1369. ret = ican3_set_bus_state(mod, true);
  1370. if (ret) {
  1371. dev_err(mod->dev, "unable to set bus-on\n");
  1372. return ret;
  1373. }
  1374. /* start up the network device */
  1375. mod->can.state = CAN_STATE_ERROR_ACTIVE;
  1376. if (netif_queue_stopped(ndev))
  1377. netif_wake_queue(ndev);
  1378. return 0;
  1379. }
  1380. static int ican3_get_berr_counter(const struct net_device *ndev,
  1381. struct can_berr_counter *bec)
  1382. {
  1383. struct ican3_dev *mod = netdev_priv(ndev);
  1384. int ret;
  1385. ret = ican3_send_inquiry(mod, INQUIRY_STATUS);
  1386. if (ret)
  1387. return ret;
  1388. ret = wait_for_completion_timeout(&mod->buserror_comp, HZ);
  1389. if (ret <= 0) {
  1390. dev_info(mod->dev, "%s timed out\n", __func__);
  1391. return -ETIMEDOUT;
  1392. }
  1393. bec->rxerr = mod->bec.rxerr;
  1394. bec->txerr = mod->bec.txerr;
  1395. return 0;
  1396. }
  1397. /*
  1398. * Sysfs Attributes
  1399. */
  1400. static ssize_t ican3_sysfs_show_term(struct device *dev,
  1401. struct device_attribute *attr,
  1402. char *buf)
  1403. {
  1404. struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
  1405. int ret;
  1406. ret = ican3_send_inquiry(mod, INQUIRY_TERMINATION);
  1407. if (ret)
  1408. return ret;
  1409. ret = wait_for_completion_timeout(&mod->termination_comp, HZ);
  1410. if (ret <= 0) {
  1411. dev_info(mod->dev, "%s timed out\n", __func__);
  1412. return -ETIMEDOUT;
  1413. }
  1414. return snprintf(buf, PAGE_SIZE, "%u\n", mod->termination_enabled);
  1415. }
  1416. static ssize_t ican3_sysfs_set_term(struct device *dev,
  1417. struct device_attribute *attr,
  1418. const char *buf, size_t count)
  1419. {
  1420. struct ican3_dev *mod = netdev_priv(to_net_dev(dev));
  1421. unsigned long enable;
  1422. int ret;
  1423. if (strict_strtoul(buf, 0, &enable))
  1424. return -EINVAL;
  1425. ret = ican3_set_termination(mod, enable);
  1426. if (ret)
  1427. return ret;
  1428. return count;
  1429. }
  1430. static DEVICE_ATTR(termination, S_IWUSR | S_IRUGO, ican3_sysfs_show_term,
  1431. ican3_sysfs_set_term);
  1432. static struct attribute *ican3_sysfs_attrs[] = {
  1433. &dev_attr_termination.attr,
  1434. NULL,
  1435. };
  1436. static struct attribute_group ican3_sysfs_attr_group = {
  1437. .attrs = ican3_sysfs_attrs,
  1438. };
  1439. /*
  1440. * PCI Subsystem
  1441. */
  1442. static int __devinit ican3_probe(struct platform_device *pdev)
  1443. {
  1444. struct janz_platform_data *pdata;
  1445. struct net_device *ndev;
  1446. struct ican3_dev *mod;
  1447. struct resource *res;
  1448. struct device *dev;
  1449. int ret;
  1450. pdata = pdev->dev.platform_data;
  1451. if (!pdata)
  1452. return -ENXIO;
  1453. dev_dbg(&pdev->dev, "probe: module number %d\n", pdata->modno);
  1454. /* save the struct device for printing */
  1455. dev = &pdev->dev;
  1456. /* allocate the CAN device and private data */
  1457. ndev = alloc_candev(sizeof(*mod), 0);
  1458. if (!ndev) {
  1459. dev_err(dev, "unable to allocate CANdev\n");
  1460. ret = -ENOMEM;
  1461. goto out_return;
  1462. }
  1463. platform_set_drvdata(pdev, ndev);
  1464. mod = netdev_priv(ndev);
  1465. mod->ndev = ndev;
  1466. mod->dev = &pdev->dev;
  1467. mod->num = pdata->modno;
  1468. netif_napi_add(ndev, &mod->napi, ican3_napi, ICAN3_RX_BUFFERS);
  1469. skb_queue_head_init(&mod->echoq);
  1470. spin_lock_init(&mod->lock);
  1471. init_completion(&mod->termination_comp);
  1472. init_completion(&mod->buserror_comp);
  1473. /* setup device-specific sysfs attributes */
  1474. ndev->sysfs_groups[0] = &ican3_sysfs_attr_group;
  1475. /* the first unallocated page in the DPM is 9 */
  1476. mod->free_page = DPM_FREE_START;
  1477. ndev->netdev_ops = &ican3_netdev_ops;
  1478. ndev->flags |= IFF_ECHO;
  1479. SET_NETDEV_DEV(ndev, &pdev->dev);
  1480. mod->can.clock.freq = ICAN3_CAN_CLOCK;
  1481. mod->can.bittiming_const = &ican3_bittiming_const;
  1482. mod->can.do_set_bittiming = ican3_set_bittiming;
  1483. mod->can.do_set_mode = ican3_set_mode;
  1484. mod->can.do_get_berr_counter = ican3_get_berr_counter;
  1485. mod->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES
  1486. | CAN_CTRLMODE_BERR_REPORTING
  1487. | CAN_CTRLMODE_ONE_SHOT;
  1488. /* find our IRQ number */
  1489. mod->irq = platform_get_irq(pdev, 0);
  1490. if (mod->irq < 0) {
  1491. dev_err(dev, "IRQ line not found\n");
  1492. ret = -ENODEV;
  1493. goto out_free_ndev;
  1494. }
  1495. ndev->irq = mod->irq;
  1496. /* get access to the MODULbus registers for this module */
  1497. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1498. if (!res) {
  1499. dev_err(dev, "MODULbus registers not found\n");
  1500. ret = -ENODEV;
  1501. goto out_free_ndev;
  1502. }
  1503. mod->dpm = ioremap(res->start, resource_size(res));
  1504. if (!mod->dpm) {
  1505. dev_err(dev, "MODULbus registers not ioremap\n");
  1506. ret = -ENOMEM;
  1507. goto out_free_ndev;
  1508. }
  1509. mod->dpmctrl = mod->dpm + DPM_PAGE_SIZE;
  1510. /* get access to the control registers for this module */
  1511. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1512. if (!res) {
  1513. dev_err(dev, "CONTROL registers not found\n");
  1514. ret = -ENODEV;
  1515. goto out_iounmap_dpm;
  1516. }
  1517. mod->ctrl = ioremap(res->start, resource_size(res));
  1518. if (!mod->ctrl) {
  1519. dev_err(dev, "CONTROL registers not ioremap\n");
  1520. ret = -ENOMEM;
  1521. goto out_iounmap_dpm;
  1522. }
  1523. /* disable our IRQ, then hookup the IRQ handler */
  1524. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1525. ret = request_irq(mod->irq, ican3_irq, IRQF_SHARED, DRV_NAME, mod);
  1526. if (ret) {
  1527. dev_err(dev, "unable to request IRQ\n");
  1528. goto out_iounmap_ctrl;
  1529. }
  1530. /* reset and initialize the CAN controller into fast mode */
  1531. napi_enable(&mod->napi);
  1532. ret = ican3_startup_module(mod);
  1533. if (ret) {
  1534. dev_err(dev, "%s: unable to start CANdev\n", __func__);
  1535. goto out_free_irq;
  1536. }
  1537. /* register with the Linux CAN layer */
  1538. ret = register_candev(ndev);
  1539. if (ret) {
  1540. dev_err(dev, "%s: unable to register CANdev\n", __func__);
  1541. goto out_free_irq;
  1542. }
  1543. dev_info(dev, "module %d: registered CAN device\n", pdata->modno);
  1544. return 0;
  1545. out_free_irq:
  1546. napi_disable(&mod->napi);
  1547. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1548. free_irq(mod->irq, mod);
  1549. out_iounmap_ctrl:
  1550. iounmap(mod->ctrl);
  1551. out_iounmap_dpm:
  1552. iounmap(mod->dpm);
  1553. out_free_ndev:
  1554. free_candev(ndev);
  1555. out_return:
  1556. return ret;
  1557. }
  1558. static int __devexit ican3_remove(struct platform_device *pdev)
  1559. {
  1560. struct net_device *ndev = platform_get_drvdata(pdev);
  1561. struct ican3_dev *mod = netdev_priv(ndev);
  1562. /* unregister the netdevice, stop interrupts */
  1563. unregister_netdev(ndev);
  1564. napi_disable(&mod->napi);
  1565. iowrite8(1 << mod->num, &mod->ctrl->int_disable);
  1566. free_irq(mod->irq, mod);
  1567. /* put the module into reset */
  1568. ican3_shutdown_module(mod);
  1569. /* unmap all registers */
  1570. iounmap(mod->ctrl);
  1571. iounmap(mod->dpm);
  1572. free_candev(ndev);
  1573. return 0;
  1574. }
  1575. static struct platform_driver ican3_driver = {
  1576. .driver = {
  1577. .name = DRV_NAME,
  1578. .owner = THIS_MODULE,
  1579. },
  1580. .probe = ican3_probe,
  1581. .remove = __devexit_p(ican3_remove),
  1582. };
  1583. module_platform_driver(ican3_driver);
  1584. MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>");
  1585. MODULE_DESCRIPTION("Janz MODULbus VMOD-ICAN3 Driver");
  1586. MODULE_LICENSE("GPL");
  1587. MODULE_ALIAS("platform:janz-ican3");