tmio_mmc_pio.c 29 KB

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  1. /*
  2. * linux/drivers/mmc/host/tmio_mmc_pio.c
  3. *
  4. * Copyright (C) 2011 Guennadi Liakhovetski
  5. * Copyright (C) 2007 Ian Molton
  6. * Copyright (C) 2004 Ian Molton
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * Driver for the MMC / SD / SDIO IP found in:
  13. *
  14. * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
  15. *
  16. * This driver draws mainly on scattered spec sheets, Reverse engineering
  17. * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
  18. * support). (Further 4 bit support from a later datasheet).
  19. *
  20. * TODO:
  21. * Investigate using a workqueue for PIO transfers
  22. * Eliminate FIXMEs
  23. * SDIO support
  24. * Better Power management
  25. * Handle MMC errors better
  26. * double buffer support
  27. *
  28. */
  29. #include <linux/delay.h>
  30. #include <linux/device.h>
  31. #include <linux/highmem.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/io.h>
  34. #include <linux/irq.h>
  35. #include <linux/mfd/tmio.h>
  36. #include <linux/mmc/host.h>
  37. #include <linux/mmc/mmc.h>
  38. #include <linux/mmc/slot-gpio.h>
  39. #include <linux/mmc/tmio.h>
  40. #include <linux/module.h>
  41. #include <linux/pagemap.h>
  42. #include <linux/platform_device.h>
  43. #include <linux/pm_qos.h>
  44. #include <linux/pm_runtime.h>
  45. #include <linux/scatterlist.h>
  46. #include <linux/spinlock.h>
  47. #include <linux/workqueue.h>
  48. #include "tmio_mmc.h"
  49. void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
  50. {
  51. host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
  52. sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
  53. }
  54. void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
  55. {
  56. host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
  57. sd_ctrl_write32(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
  58. }
  59. static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
  60. {
  61. sd_ctrl_write32(host, CTL_STATUS, ~i);
  62. }
  63. static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
  64. {
  65. host->sg_len = data->sg_len;
  66. host->sg_ptr = data->sg;
  67. host->sg_orig = data->sg;
  68. host->sg_off = 0;
  69. }
  70. static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
  71. {
  72. host->sg_ptr = sg_next(host->sg_ptr);
  73. host->sg_off = 0;
  74. return --host->sg_len;
  75. }
  76. #ifdef CONFIG_MMC_DEBUG
  77. #define STATUS_TO_TEXT(a, status, i) \
  78. do { \
  79. if (status & TMIO_STAT_##a) { \
  80. if (i++) \
  81. printk(" | "); \
  82. printk(#a); \
  83. } \
  84. } while (0)
  85. static void pr_debug_status(u32 status)
  86. {
  87. int i = 0;
  88. pr_debug("status: %08x = ", status);
  89. STATUS_TO_TEXT(CARD_REMOVE, status, i);
  90. STATUS_TO_TEXT(CARD_INSERT, status, i);
  91. STATUS_TO_TEXT(SIGSTATE, status, i);
  92. STATUS_TO_TEXT(WRPROTECT, status, i);
  93. STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
  94. STATUS_TO_TEXT(CARD_INSERT_A, status, i);
  95. STATUS_TO_TEXT(SIGSTATE_A, status, i);
  96. STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
  97. STATUS_TO_TEXT(STOPBIT_ERR, status, i);
  98. STATUS_TO_TEXT(ILL_FUNC, status, i);
  99. STATUS_TO_TEXT(CMD_BUSY, status, i);
  100. STATUS_TO_TEXT(CMDRESPEND, status, i);
  101. STATUS_TO_TEXT(DATAEND, status, i);
  102. STATUS_TO_TEXT(CRCFAIL, status, i);
  103. STATUS_TO_TEXT(DATATIMEOUT, status, i);
  104. STATUS_TO_TEXT(CMDTIMEOUT, status, i);
  105. STATUS_TO_TEXT(RXOVERFLOW, status, i);
  106. STATUS_TO_TEXT(TXUNDERRUN, status, i);
  107. STATUS_TO_TEXT(RXRDY, status, i);
  108. STATUS_TO_TEXT(TXRQ, status, i);
  109. STATUS_TO_TEXT(ILL_ACCESS, status, i);
  110. printk("\n");
  111. }
  112. #else
  113. #define pr_debug_status(s) do { } while (0)
  114. #endif
  115. static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  116. {
  117. struct tmio_mmc_host *host = mmc_priv(mmc);
  118. if (enable) {
  119. host->sdio_irq_mask = TMIO_SDIO_MASK_ALL &
  120. ~TMIO_SDIO_STAT_IOIRQ;
  121. sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
  122. sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
  123. } else {
  124. host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
  125. sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
  126. sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
  127. }
  128. }
  129. static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
  130. {
  131. u32 clk = 0, clock;
  132. if (new_clock) {
  133. for (clock = host->mmc->f_min, clk = 0x80000080;
  134. new_clock >= (clock<<1); clk >>= 1)
  135. clock <<= 1;
  136. clk |= 0x100;
  137. }
  138. if (host->set_clk_div)
  139. host->set_clk_div(host->pdev, (clk>>22) & 1);
  140. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
  141. }
  142. static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
  143. {
  144. struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
  145. /* implicit BUG_ON(!res) */
  146. if (resource_size(res) > 0x100) {
  147. sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
  148. msleep(10);
  149. }
  150. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
  151. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  152. msleep(10);
  153. }
  154. static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
  155. {
  156. struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
  157. sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
  158. sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
  159. msleep(10);
  160. /* implicit BUG_ON(!res) */
  161. if (resource_size(res) > 0x100) {
  162. sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
  163. msleep(10);
  164. }
  165. }
  166. static void tmio_mmc_reset(struct tmio_mmc_host *host)
  167. {
  168. struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
  169. /* FIXME - should we set stop clock reg here */
  170. sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
  171. /* implicit BUG_ON(!res) */
  172. if (resource_size(res) > 0x100)
  173. sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
  174. msleep(10);
  175. sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
  176. if (resource_size(res) > 0x100)
  177. sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
  178. msleep(10);
  179. }
  180. static void tmio_mmc_reset_work(struct work_struct *work)
  181. {
  182. struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
  183. delayed_reset_work.work);
  184. struct mmc_request *mrq;
  185. unsigned long flags;
  186. spin_lock_irqsave(&host->lock, flags);
  187. mrq = host->mrq;
  188. /*
  189. * is request already finished? Since we use a non-blocking
  190. * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
  191. * us, so, have to check for IS_ERR(host->mrq)
  192. */
  193. if (IS_ERR_OR_NULL(mrq)
  194. || time_is_after_jiffies(host->last_req_ts +
  195. msecs_to_jiffies(2000))) {
  196. spin_unlock_irqrestore(&host->lock, flags);
  197. return;
  198. }
  199. dev_warn(&host->pdev->dev,
  200. "timeout waiting for hardware interrupt (CMD%u)\n",
  201. mrq->cmd->opcode);
  202. if (host->data)
  203. host->data->error = -ETIMEDOUT;
  204. else if (host->cmd)
  205. host->cmd->error = -ETIMEDOUT;
  206. else
  207. mrq->cmd->error = -ETIMEDOUT;
  208. host->cmd = NULL;
  209. host->data = NULL;
  210. host->force_pio = false;
  211. spin_unlock_irqrestore(&host->lock, flags);
  212. tmio_mmc_reset(host);
  213. /* Ready for new calls */
  214. host->mrq = NULL;
  215. tmio_mmc_abort_dma(host);
  216. mmc_request_done(host->mmc, mrq);
  217. }
  218. /* called with host->lock held, interrupts disabled */
  219. static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
  220. {
  221. struct mmc_request *mrq;
  222. unsigned long flags;
  223. spin_lock_irqsave(&host->lock, flags);
  224. mrq = host->mrq;
  225. if (IS_ERR_OR_NULL(mrq)) {
  226. spin_unlock_irqrestore(&host->lock, flags);
  227. return;
  228. }
  229. host->cmd = NULL;
  230. host->data = NULL;
  231. host->force_pio = false;
  232. cancel_delayed_work(&host->delayed_reset_work);
  233. host->mrq = NULL;
  234. spin_unlock_irqrestore(&host->lock, flags);
  235. if (mrq->cmd->error || (mrq->data && mrq->data->error))
  236. tmio_mmc_abort_dma(host);
  237. mmc_request_done(host->mmc, mrq);
  238. }
  239. static void tmio_mmc_done_work(struct work_struct *work)
  240. {
  241. struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
  242. done);
  243. tmio_mmc_finish_request(host);
  244. }
  245. /* These are the bitmasks the tmio chip requires to implement the MMC response
  246. * types. Note that R1 and R6 are the same in this scheme. */
  247. #define APP_CMD 0x0040
  248. #define RESP_NONE 0x0300
  249. #define RESP_R1 0x0400
  250. #define RESP_R1B 0x0500
  251. #define RESP_R2 0x0600
  252. #define RESP_R3 0x0700
  253. #define DATA_PRESENT 0x0800
  254. #define TRANSFER_READ 0x1000
  255. #define TRANSFER_MULTI 0x2000
  256. #define SECURITY_CMD 0x4000
  257. static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
  258. {
  259. struct mmc_data *data = host->data;
  260. int c = cmd->opcode;
  261. u32 irq_mask = TMIO_MASK_CMD;
  262. /* CMD12 is handled by hardware */
  263. if (cmd->opcode == MMC_STOP_TRANSMISSION && !cmd->arg) {
  264. sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
  265. return 0;
  266. }
  267. switch (mmc_resp_type(cmd)) {
  268. case MMC_RSP_NONE: c |= RESP_NONE; break;
  269. case MMC_RSP_R1: c |= RESP_R1; break;
  270. case MMC_RSP_R1B: c |= RESP_R1B; break;
  271. case MMC_RSP_R2: c |= RESP_R2; break;
  272. case MMC_RSP_R3: c |= RESP_R3; break;
  273. default:
  274. pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
  275. return -EINVAL;
  276. }
  277. host->cmd = cmd;
  278. /* FIXME - this seems to be ok commented out but the spec suggest this bit
  279. * should be set when issuing app commands.
  280. * if(cmd->flags & MMC_FLAG_ACMD)
  281. * c |= APP_CMD;
  282. */
  283. if (data) {
  284. c |= DATA_PRESENT;
  285. if (data->blocks > 1) {
  286. sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
  287. c |= TRANSFER_MULTI;
  288. }
  289. if (data->flags & MMC_DATA_READ)
  290. c |= TRANSFER_READ;
  291. }
  292. if (!host->native_hotplug)
  293. irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
  294. tmio_mmc_enable_mmc_irqs(host, irq_mask);
  295. /* Fire off the command */
  296. sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
  297. sd_ctrl_write16(host, CTL_SD_CMD, c);
  298. return 0;
  299. }
  300. /*
  301. * This chip always returns (at least?) as much data as you ask for.
  302. * I'm unsure what happens if you ask for less than a block. This should be
  303. * looked into to ensure that a funny length read doesn't hose the controller.
  304. */
  305. static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
  306. {
  307. struct mmc_data *data = host->data;
  308. void *sg_virt;
  309. unsigned short *buf;
  310. unsigned int count;
  311. unsigned long flags;
  312. if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
  313. pr_err("PIO IRQ in DMA mode!\n");
  314. return;
  315. } else if (!data) {
  316. pr_debug("Spurious PIO IRQ\n");
  317. return;
  318. }
  319. sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
  320. buf = (unsigned short *)(sg_virt + host->sg_off);
  321. count = host->sg_ptr->length - host->sg_off;
  322. if (count > data->blksz)
  323. count = data->blksz;
  324. pr_debug("count: %08x offset: %08x flags %08x\n",
  325. count, host->sg_off, data->flags);
  326. /* Transfer the data */
  327. if (data->flags & MMC_DATA_READ)
  328. sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
  329. else
  330. sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
  331. host->sg_off += count;
  332. tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
  333. if (host->sg_off == host->sg_ptr->length)
  334. tmio_mmc_next_sg(host);
  335. return;
  336. }
  337. static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
  338. {
  339. if (host->sg_ptr == &host->bounce_sg) {
  340. unsigned long flags;
  341. void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
  342. memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
  343. tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
  344. }
  345. }
  346. /* needs to be called with host->lock held */
  347. void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
  348. {
  349. struct mmc_data *data = host->data;
  350. struct mmc_command *stop;
  351. host->data = NULL;
  352. if (!data) {
  353. dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
  354. return;
  355. }
  356. stop = data->stop;
  357. /* FIXME - return correct transfer count on errors */
  358. if (!data->error)
  359. data->bytes_xfered = data->blocks * data->blksz;
  360. else
  361. data->bytes_xfered = 0;
  362. pr_debug("Completed data request\n");
  363. /*
  364. * FIXME: other drivers allow an optional stop command of any given type
  365. * which we dont do, as the chip can auto generate them.
  366. * Perhaps we can be smarter about when to use auto CMD12 and
  367. * only issue the auto request when we know this is the desired
  368. * stop command, allowing fallback to the stop command the
  369. * upper layers expect. For now, we do what works.
  370. */
  371. if (data->flags & MMC_DATA_READ) {
  372. if (host->chan_rx && !host->force_pio)
  373. tmio_mmc_check_bounce_buffer(host);
  374. dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
  375. host->mrq);
  376. } else {
  377. dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
  378. host->mrq);
  379. }
  380. if (stop) {
  381. if (stop->opcode == MMC_STOP_TRANSMISSION && !stop->arg)
  382. sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
  383. else
  384. BUG();
  385. }
  386. schedule_work(&host->done);
  387. }
  388. static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
  389. {
  390. struct mmc_data *data;
  391. spin_lock(&host->lock);
  392. data = host->data;
  393. if (!data)
  394. goto out;
  395. if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
  396. /*
  397. * Has all data been written out yet? Testing on SuperH showed,
  398. * that in most cases the first interrupt comes already with the
  399. * BUSY status bit clear, but on some operations, like mount or
  400. * in the beginning of a write / sync / umount, there is one
  401. * DATAEND interrupt with the BUSY bit set, in this cases
  402. * waiting for one more interrupt fixes the problem.
  403. */
  404. if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
  405. tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
  406. tasklet_schedule(&host->dma_complete);
  407. }
  408. } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
  409. tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
  410. tasklet_schedule(&host->dma_complete);
  411. } else {
  412. tmio_mmc_do_data_irq(host);
  413. tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
  414. }
  415. out:
  416. spin_unlock(&host->lock);
  417. }
  418. static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
  419. unsigned int stat)
  420. {
  421. struct mmc_command *cmd = host->cmd;
  422. int i, addr;
  423. spin_lock(&host->lock);
  424. if (!host->cmd) {
  425. pr_debug("Spurious CMD irq\n");
  426. goto out;
  427. }
  428. host->cmd = NULL;
  429. /* This controller is sicker than the PXA one. Not only do we need to
  430. * drop the top 8 bits of the first response word, we also need to
  431. * modify the order of the response for short response command types.
  432. */
  433. for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
  434. cmd->resp[i] = sd_ctrl_read32(host, addr);
  435. if (cmd->flags & MMC_RSP_136) {
  436. cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
  437. cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
  438. cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
  439. cmd->resp[3] <<= 8;
  440. } else if (cmd->flags & MMC_RSP_R3) {
  441. cmd->resp[0] = cmd->resp[3];
  442. }
  443. if (stat & TMIO_STAT_CMDTIMEOUT)
  444. cmd->error = -ETIMEDOUT;
  445. else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
  446. cmd->error = -EILSEQ;
  447. /* If there is data to handle we enable data IRQs here, and
  448. * we will ultimatley finish the request in the data_end handler.
  449. * If theres no data or we encountered an error, finish now.
  450. */
  451. if (host->data && !cmd->error) {
  452. if (host->data->flags & MMC_DATA_READ) {
  453. if (host->force_pio || !host->chan_rx)
  454. tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
  455. else
  456. tasklet_schedule(&host->dma_issue);
  457. } else {
  458. if (host->force_pio || !host->chan_tx)
  459. tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
  460. else
  461. tasklet_schedule(&host->dma_issue);
  462. }
  463. } else {
  464. schedule_work(&host->done);
  465. }
  466. out:
  467. spin_unlock(&host->lock);
  468. }
  469. static void tmio_mmc_card_irq_status(struct tmio_mmc_host *host,
  470. int *ireg, int *status)
  471. {
  472. *status = sd_ctrl_read32(host, CTL_STATUS);
  473. *ireg = *status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
  474. pr_debug_status(*status);
  475. pr_debug_status(*ireg);
  476. }
  477. static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
  478. int ireg, int status)
  479. {
  480. struct mmc_host *mmc = host->mmc;
  481. /* Card insert / remove attempts */
  482. if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
  483. tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
  484. TMIO_STAT_CARD_REMOVE);
  485. if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
  486. ((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
  487. !work_pending(&mmc->detect.work))
  488. mmc_detect_change(host->mmc, msecs_to_jiffies(100));
  489. return true;
  490. }
  491. return false;
  492. }
  493. irqreturn_t tmio_mmc_card_detect_irq(int irq, void *devid)
  494. {
  495. unsigned int ireg, status;
  496. struct tmio_mmc_host *host = devid;
  497. tmio_mmc_card_irq_status(host, &ireg, &status);
  498. __tmio_mmc_card_detect_irq(host, ireg, status);
  499. return IRQ_HANDLED;
  500. }
  501. EXPORT_SYMBOL(tmio_mmc_card_detect_irq);
  502. static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host,
  503. int ireg, int status)
  504. {
  505. /* Command completion */
  506. if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
  507. tmio_mmc_ack_mmc_irqs(host,
  508. TMIO_STAT_CMDRESPEND |
  509. TMIO_STAT_CMDTIMEOUT);
  510. tmio_mmc_cmd_irq(host, status);
  511. return true;
  512. }
  513. /* Data transfer */
  514. if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
  515. tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
  516. tmio_mmc_pio_irq(host);
  517. return true;
  518. }
  519. /* Data transfer completion */
  520. if (ireg & TMIO_STAT_DATAEND) {
  521. tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
  522. tmio_mmc_data_irq(host);
  523. return true;
  524. }
  525. return false;
  526. }
  527. irqreturn_t tmio_mmc_sdcard_irq(int irq, void *devid)
  528. {
  529. unsigned int ireg, status;
  530. struct tmio_mmc_host *host = devid;
  531. tmio_mmc_card_irq_status(host, &ireg, &status);
  532. __tmio_mmc_sdcard_irq(host, ireg, status);
  533. return IRQ_HANDLED;
  534. }
  535. EXPORT_SYMBOL(tmio_mmc_sdcard_irq);
  536. irqreturn_t tmio_mmc_sdio_irq(int irq, void *devid)
  537. {
  538. struct tmio_mmc_host *host = devid;
  539. struct mmc_host *mmc = host->mmc;
  540. struct tmio_mmc_data *pdata = host->pdata;
  541. unsigned int ireg, status;
  542. if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
  543. return IRQ_HANDLED;
  544. status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
  545. ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdcard_irq_mask;
  546. sd_ctrl_write16(host, CTL_SDIO_STATUS, status & ~TMIO_SDIO_MASK_ALL);
  547. if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
  548. mmc_signal_sdio_irq(mmc);
  549. return IRQ_HANDLED;
  550. }
  551. EXPORT_SYMBOL(tmio_mmc_sdio_irq);
  552. irqreturn_t tmio_mmc_irq(int irq, void *devid)
  553. {
  554. struct tmio_mmc_host *host = devid;
  555. unsigned int ireg, status;
  556. pr_debug("MMC IRQ begin\n");
  557. tmio_mmc_card_irq_status(host, &ireg, &status);
  558. if (__tmio_mmc_card_detect_irq(host, ireg, status))
  559. return IRQ_HANDLED;
  560. if (__tmio_mmc_sdcard_irq(host, ireg, status))
  561. return IRQ_HANDLED;
  562. tmio_mmc_sdio_irq(irq, devid);
  563. return IRQ_HANDLED;
  564. }
  565. EXPORT_SYMBOL(tmio_mmc_irq);
  566. static int tmio_mmc_start_data(struct tmio_mmc_host *host,
  567. struct mmc_data *data)
  568. {
  569. struct tmio_mmc_data *pdata = host->pdata;
  570. pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
  571. data->blksz, data->blocks);
  572. /* Some hardware cannot perform 2 byte requests in 4 bit mode */
  573. if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
  574. int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
  575. if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
  576. pr_err("%s: %d byte block unsupported in 4 bit mode\n",
  577. mmc_hostname(host->mmc), data->blksz);
  578. return -EINVAL;
  579. }
  580. }
  581. tmio_mmc_init_sg(host, data);
  582. host->data = data;
  583. /* Set transfer length / blocksize */
  584. sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
  585. sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
  586. tmio_mmc_start_dma(host, data);
  587. return 0;
  588. }
  589. /* Process requests from the MMC layer */
  590. static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  591. {
  592. struct tmio_mmc_host *host = mmc_priv(mmc);
  593. unsigned long flags;
  594. int ret;
  595. spin_lock_irqsave(&host->lock, flags);
  596. if (host->mrq) {
  597. pr_debug("request not null\n");
  598. if (IS_ERR(host->mrq)) {
  599. spin_unlock_irqrestore(&host->lock, flags);
  600. mrq->cmd->error = -EAGAIN;
  601. mmc_request_done(mmc, mrq);
  602. return;
  603. }
  604. }
  605. host->last_req_ts = jiffies;
  606. wmb();
  607. host->mrq = mrq;
  608. spin_unlock_irqrestore(&host->lock, flags);
  609. if (mrq->data) {
  610. ret = tmio_mmc_start_data(host, mrq->data);
  611. if (ret)
  612. goto fail;
  613. }
  614. ret = tmio_mmc_start_command(host, mrq->cmd);
  615. if (!ret) {
  616. schedule_delayed_work(&host->delayed_reset_work,
  617. msecs_to_jiffies(2000));
  618. return;
  619. }
  620. fail:
  621. host->force_pio = false;
  622. host->mrq = NULL;
  623. mrq->cmd->error = ret;
  624. mmc_request_done(mmc, mrq);
  625. }
  626. static int tmio_mmc_clk_update(struct mmc_host *mmc)
  627. {
  628. struct tmio_mmc_host *host = mmc_priv(mmc);
  629. struct tmio_mmc_data *pdata = host->pdata;
  630. int ret;
  631. if (!pdata->clk_enable)
  632. return -ENOTSUPP;
  633. ret = pdata->clk_enable(host->pdev, &mmc->f_max);
  634. if (!ret)
  635. mmc->f_min = mmc->f_max / 512;
  636. return ret;
  637. }
  638. static void tmio_mmc_set_power(struct tmio_mmc_host *host, struct mmc_ios *ios)
  639. {
  640. struct mmc_host *mmc = host->mmc;
  641. if (host->set_pwr)
  642. host->set_pwr(host->pdev, ios->power_mode != MMC_POWER_OFF);
  643. if (!IS_ERR(mmc->supply.vmmc))
  644. /* Errors ignored... */
  645. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
  646. ios->power_mode ? ios->vdd : 0);
  647. }
  648. /* Set MMC clock / power.
  649. * Note: This controller uses a simple divider scheme therefore it cannot
  650. * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
  651. * MMC wont run that fast, it has to be clocked at 12MHz which is the next
  652. * slowest setting.
  653. */
  654. static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  655. {
  656. struct tmio_mmc_host *host = mmc_priv(mmc);
  657. struct device *dev = &host->pdev->dev;
  658. unsigned long flags;
  659. mutex_lock(&host->ios_lock);
  660. spin_lock_irqsave(&host->lock, flags);
  661. if (host->mrq) {
  662. if (IS_ERR(host->mrq)) {
  663. dev_dbg(dev,
  664. "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
  665. current->comm, task_pid_nr(current),
  666. ios->clock, ios->power_mode);
  667. host->mrq = ERR_PTR(-EINTR);
  668. } else {
  669. dev_dbg(dev,
  670. "%s.%d: CMD%u active since %lu, now %lu!\n",
  671. current->comm, task_pid_nr(current),
  672. host->mrq->cmd->opcode, host->last_req_ts, jiffies);
  673. }
  674. spin_unlock_irqrestore(&host->lock, flags);
  675. mutex_unlock(&host->ios_lock);
  676. return;
  677. }
  678. host->mrq = ERR_PTR(-EBUSY);
  679. spin_unlock_irqrestore(&host->lock, flags);
  680. /*
  681. * host->power toggles between false and true in both cases - either
  682. * or not the controller can be runtime-suspended during inactivity.
  683. * But if the controller has to be kept on, the runtime-pm usage_count
  684. * is kept positive, so no suspending actually takes place.
  685. */
  686. if (ios->power_mode == MMC_POWER_ON && ios->clock) {
  687. if (!host->power) {
  688. tmio_mmc_clk_update(mmc);
  689. pm_runtime_get_sync(dev);
  690. host->power = true;
  691. }
  692. tmio_mmc_set_clock(host, ios->clock);
  693. /* power up SD bus */
  694. tmio_mmc_set_power(host, ios);
  695. /* start bus clock */
  696. tmio_mmc_clk_start(host);
  697. } else if (ios->power_mode != MMC_POWER_UP) {
  698. if (ios->power_mode == MMC_POWER_OFF)
  699. tmio_mmc_set_power(host, ios);
  700. if (host->power) {
  701. struct tmio_mmc_data *pdata = host->pdata;
  702. tmio_mmc_clk_stop(host);
  703. host->power = false;
  704. pm_runtime_put(dev);
  705. if (pdata->clk_disable)
  706. pdata->clk_disable(host->pdev);
  707. }
  708. }
  709. if (host->power) {
  710. switch (ios->bus_width) {
  711. case MMC_BUS_WIDTH_1:
  712. sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
  713. break;
  714. case MMC_BUS_WIDTH_4:
  715. sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
  716. break;
  717. }
  718. }
  719. /* Let things settle. delay taken from winCE driver */
  720. udelay(140);
  721. if (PTR_ERR(host->mrq) == -EINTR)
  722. dev_dbg(&host->pdev->dev,
  723. "%s.%d: IOS interrupted: clk %u, mode %u",
  724. current->comm, task_pid_nr(current),
  725. ios->clock, ios->power_mode);
  726. host->mrq = NULL;
  727. mutex_unlock(&host->ios_lock);
  728. }
  729. static int tmio_mmc_get_ro(struct mmc_host *mmc)
  730. {
  731. struct tmio_mmc_host *host = mmc_priv(mmc);
  732. struct tmio_mmc_data *pdata = host->pdata;
  733. int ret = mmc_gpio_get_ro(mmc);
  734. if (ret >= 0)
  735. return ret;
  736. return !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
  737. (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
  738. }
  739. static int tmio_mmc_get_cd(struct mmc_host *mmc)
  740. {
  741. struct tmio_mmc_host *host = mmc_priv(mmc);
  742. struct tmio_mmc_data *pdata = host->pdata;
  743. int ret = mmc_gpio_get_cd(mmc);
  744. if (ret >= 0)
  745. return ret;
  746. if (!pdata->get_cd)
  747. return -ENOSYS;
  748. else
  749. return pdata->get_cd(host->pdev);
  750. }
  751. static const struct mmc_host_ops tmio_mmc_ops = {
  752. .request = tmio_mmc_request,
  753. .set_ios = tmio_mmc_set_ios,
  754. .get_ro = tmio_mmc_get_ro,
  755. .get_cd = tmio_mmc_get_cd,
  756. .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
  757. };
  758. static void tmio_mmc_init_ocr(struct tmio_mmc_host *host)
  759. {
  760. struct tmio_mmc_data *pdata = host->pdata;
  761. struct mmc_host *mmc = host->mmc;
  762. mmc_regulator_get_supply(mmc);
  763. if (!mmc->ocr_avail)
  764. mmc->ocr_avail = pdata->ocr_mask ? : MMC_VDD_32_33 | MMC_VDD_33_34;
  765. else if (pdata->ocr_mask)
  766. dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
  767. }
  768. int __devinit tmio_mmc_host_probe(struct tmio_mmc_host **host,
  769. struct platform_device *pdev,
  770. struct tmio_mmc_data *pdata)
  771. {
  772. struct tmio_mmc_host *_host;
  773. struct mmc_host *mmc;
  774. struct resource *res_ctl;
  775. int ret;
  776. u32 irq_mask = TMIO_MASK_CMD;
  777. res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  778. if (!res_ctl)
  779. return -EINVAL;
  780. mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
  781. if (!mmc)
  782. return -ENOMEM;
  783. pdata->dev = &pdev->dev;
  784. _host = mmc_priv(mmc);
  785. _host->pdata = pdata;
  786. _host->mmc = mmc;
  787. _host->pdev = pdev;
  788. platform_set_drvdata(pdev, mmc);
  789. _host->set_pwr = pdata->set_pwr;
  790. _host->set_clk_div = pdata->set_clk_div;
  791. /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
  792. _host->bus_shift = resource_size(res_ctl) >> 10;
  793. _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
  794. if (!_host->ctl) {
  795. ret = -ENOMEM;
  796. goto host_free;
  797. }
  798. mmc->ops = &tmio_mmc_ops;
  799. mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
  800. mmc->caps2 = pdata->capabilities2;
  801. mmc->max_segs = 32;
  802. mmc->max_blk_size = 512;
  803. mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
  804. mmc->max_segs;
  805. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  806. mmc->max_seg_size = mmc->max_req_size;
  807. tmio_mmc_init_ocr(_host);
  808. _host->native_hotplug = !(pdata->flags & TMIO_MMC_USE_GPIO_CD ||
  809. mmc->caps & MMC_CAP_NEEDS_POLL ||
  810. mmc->caps & MMC_CAP_NONREMOVABLE);
  811. _host->power = false;
  812. pm_runtime_enable(&pdev->dev);
  813. ret = pm_runtime_resume(&pdev->dev);
  814. if (ret < 0)
  815. goto pm_disable;
  816. if (tmio_mmc_clk_update(mmc) < 0) {
  817. mmc->f_max = pdata->hclk;
  818. mmc->f_min = mmc->f_max / 512;
  819. }
  820. /*
  821. * There are 4 different scenarios for the card detection:
  822. * 1) an external gpio irq handles the cd (best for power savings)
  823. * 2) internal sdhi irq handles the cd
  824. * 3) a worker thread polls the sdhi - indicated by MMC_CAP_NEEDS_POLL
  825. * 4) the medium is non-removable - indicated by MMC_CAP_NONREMOVABLE
  826. *
  827. * While we increment the runtime PM counter for all scenarios when
  828. * the mmc core activates us by calling an appropriate set_ios(), we
  829. * must additionally ensure that in case 2) the tmio mmc hardware stays
  830. * powered on during runtime for the card detection to work.
  831. */
  832. if (_host->native_hotplug)
  833. pm_runtime_get_noresume(&pdev->dev);
  834. tmio_mmc_clk_stop(_host);
  835. tmio_mmc_reset(_host);
  836. _host->sdcard_irq_mask = sd_ctrl_read32(_host, CTL_IRQ_MASK);
  837. tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
  838. /* Unmask the IRQs we want to know about */
  839. if (!_host->chan_rx)
  840. irq_mask |= TMIO_MASK_READOP;
  841. if (!_host->chan_tx)
  842. irq_mask |= TMIO_MASK_WRITEOP;
  843. if (!_host->native_hotplug)
  844. irq_mask &= ~(TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
  845. _host->sdcard_irq_mask &= ~irq_mask;
  846. if (pdata->flags & TMIO_MMC_SDIO_IRQ)
  847. tmio_mmc_enable_sdio_irq(mmc, 0);
  848. spin_lock_init(&_host->lock);
  849. mutex_init(&_host->ios_lock);
  850. /* Init delayed work for request timeouts */
  851. INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
  852. INIT_WORK(&_host->done, tmio_mmc_done_work);
  853. /* See if we also get DMA */
  854. tmio_mmc_request_dma(_host, pdata);
  855. ret = mmc_add_host(mmc);
  856. if (pdata->clk_disable)
  857. pdata->clk_disable(pdev);
  858. if (ret < 0) {
  859. tmio_mmc_host_remove(_host);
  860. return ret;
  861. }
  862. dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
  863. if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
  864. ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio);
  865. if (ret < 0) {
  866. tmio_mmc_host_remove(_host);
  867. return ret;
  868. }
  869. }
  870. *host = _host;
  871. return 0;
  872. pm_disable:
  873. pm_runtime_disable(&pdev->dev);
  874. iounmap(_host->ctl);
  875. host_free:
  876. mmc_free_host(mmc);
  877. return ret;
  878. }
  879. EXPORT_SYMBOL(tmio_mmc_host_probe);
  880. void tmio_mmc_host_remove(struct tmio_mmc_host *host)
  881. {
  882. struct platform_device *pdev = host->pdev;
  883. struct tmio_mmc_data *pdata = host->pdata;
  884. struct mmc_host *mmc = host->mmc;
  885. if (pdata->flags & TMIO_MMC_USE_GPIO_CD)
  886. /*
  887. * This means we can miss a card-eject, but this is anyway
  888. * possible, because of delayed processing of hotplug events.
  889. */
  890. mmc_gpio_free_cd(mmc);
  891. if (!host->native_hotplug)
  892. pm_runtime_get_sync(&pdev->dev);
  893. dev_pm_qos_hide_latency_limit(&pdev->dev);
  894. mmc_remove_host(mmc);
  895. cancel_work_sync(&host->done);
  896. cancel_delayed_work_sync(&host->delayed_reset_work);
  897. tmio_mmc_release_dma(host);
  898. pm_runtime_put_sync(&pdev->dev);
  899. pm_runtime_disable(&pdev->dev);
  900. iounmap(host->ctl);
  901. mmc_free_host(mmc);
  902. }
  903. EXPORT_SYMBOL(tmio_mmc_host_remove);
  904. #ifdef CONFIG_PM
  905. int tmio_mmc_host_suspend(struct device *dev)
  906. {
  907. struct mmc_host *mmc = dev_get_drvdata(dev);
  908. struct tmio_mmc_host *host = mmc_priv(mmc);
  909. int ret = mmc_suspend_host(mmc);
  910. if (!ret)
  911. tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
  912. return ret;
  913. }
  914. EXPORT_SYMBOL(tmio_mmc_host_suspend);
  915. int tmio_mmc_host_resume(struct device *dev)
  916. {
  917. struct mmc_host *mmc = dev_get_drvdata(dev);
  918. struct tmio_mmc_host *host = mmc_priv(mmc);
  919. tmio_mmc_reset(host);
  920. tmio_mmc_enable_dma(host, true);
  921. /* The MMC core will perform the complete set up */
  922. return mmc_resume_host(mmc);
  923. }
  924. EXPORT_SYMBOL(tmio_mmc_host_resume);
  925. #endif /* CONFIG_PM */
  926. int tmio_mmc_host_runtime_suspend(struct device *dev)
  927. {
  928. return 0;
  929. }
  930. EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
  931. int tmio_mmc_host_runtime_resume(struct device *dev)
  932. {
  933. struct mmc_host *mmc = dev_get_drvdata(dev);
  934. struct tmio_mmc_host *host = mmc_priv(mmc);
  935. tmio_mmc_reset(host);
  936. tmio_mmc_enable_dma(host, true);
  937. return 0;
  938. }
  939. EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
  940. MODULE_LICENSE("GPL v2");