at91_adc.c 18 KB

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  1. /*
  2. * Driver for the ADC present in the Atmel AT91 evaluation boards.
  3. *
  4. * Copyright 2011 Free Electrons
  5. *
  6. * Licensed under the GPLv2 or later.
  7. */
  8. #include <linux/bitmap.h>
  9. #include <linux/bitops.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/jiffies.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_device.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/sched.h>
  21. #include <linux/slab.h>
  22. #include <linux/wait.h>
  23. #include <linux/platform_data/at91_adc.h>
  24. #include <linux/iio/iio.h>
  25. #include <linux/iio/buffer.h>
  26. #include <linux/iio/trigger.h>
  27. #include <linux/iio/trigger_consumer.h>
  28. #include <linux/iio/triggered_buffer.h>
  29. #include <mach/at91_adc.h>
  30. #define AT91_ADC_CHAN(st, ch) \
  31. (st->registers->channel_base + (ch * 4))
  32. #define at91_adc_readl(st, reg) \
  33. (readl_relaxed(st->reg_base + reg))
  34. #define at91_adc_writel(st, reg, val) \
  35. (writel_relaxed(val, st->reg_base + reg))
  36. struct at91_adc_state {
  37. struct clk *adc_clk;
  38. u16 *buffer;
  39. unsigned long channels_mask;
  40. struct clk *clk;
  41. bool done;
  42. int irq;
  43. bool irq_enabled;
  44. u16 last_value;
  45. struct mutex lock;
  46. u8 num_channels;
  47. void __iomem *reg_base;
  48. struct at91_adc_reg_desc *registers;
  49. u8 startup_time;
  50. struct iio_trigger **trig;
  51. struct at91_adc_trigger *trigger_list;
  52. u32 trigger_number;
  53. bool use_external;
  54. u32 vref_mv;
  55. wait_queue_head_t wq_data_avail;
  56. };
  57. static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
  58. {
  59. struct iio_poll_func *pf = p;
  60. struct iio_dev *idev = pf->indio_dev;
  61. struct at91_adc_state *st = iio_priv(idev);
  62. struct iio_buffer *buffer = idev->buffer;
  63. int i, j = 0;
  64. for (i = 0; i < idev->masklength; i++) {
  65. if (!test_bit(i, idev->active_scan_mask))
  66. continue;
  67. st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
  68. j++;
  69. }
  70. if (idev->scan_timestamp) {
  71. s64 *timestamp = (s64 *)((u8 *)st->buffer +
  72. ALIGN(j, sizeof(s64)));
  73. *timestamp = pf->timestamp;
  74. }
  75. buffer->access->store_to(buffer, (u8 *)st->buffer, pf->timestamp);
  76. iio_trigger_notify_done(idev->trig);
  77. st->irq_enabled = true;
  78. /* Needed to ACK the DRDY interruption */
  79. at91_adc_readl(st, AT91_ADC_LCDR);
  80. enable_irq(st->irq);
  81. return IRQ_HANDLED;
  82. }
  83. static irqreturn_t at91_adc_eoc_trigger(int irq, void *private)
  84. {
  85. struct iio_dev *idev = private;
  86. struct at91_adc_state *st = iio_priv(idev);
  87. u32 status = at91_adc_readl(st, st->registers->status_register);
  88. if (!(status & st->registers->drdy_mask))
  89. return IRQ_HANDLED;
  90. if (iio_buffer_enabled(idev)) {
  91. disable_irq_nosync(irq);
  92. st->irq_enabled = false;
  93. iio_trigger_poll(idev->trig, iio_get_time_ns());
  94. } else {
  95. st->last_value = at91_adc_readl(st, AT91_ADC_LCDR);
  96. st->done = true;
  97. wake_up_interruptible(&st->wq_data_avail);
  98. }
  99. return IRQ_HANDLED;
  100. }
  101. static int at91_adc_channel_init(struct iio_dev *idev)
  102. {
  103. struct at91_adc_state *st = iio_priv(idev);
  104. struct iio_chan_spec *chan_array, *timestamp;
  105. int bit, idx = 0;
  106. idev->num_channels = bitmap_weight(&st->channels_mask,
  107. st->num_channels) + 1;
  108. chan_array = devm_kzalloc(&idev->dev,
  109. ((idev->num_channels + 1) *
  110. sizeof(struct iio_chan_spec)),
  111. GFP_KERNEL);
  112. if (!chan_array)
  113. return -ENOMEM;
  114. for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
  115. struct iio_chan_spec *chan = chan_array + idx;
  116. chan->type = IIO_VOLTAGE;
  117. chan->indexed = 1;
  118. chan->channel = bit;
  119. chan->scan_index = idx;
  120. chan->scan_type.sign = 'u';
  121. chan->scan_type.realbits = 10;
  122. chan->scan_type.storagebits = 16;
  123. chan->info_mask = IIO_CHAN_INFO_SCALE_SHARED_BIT |
  124. IIO_CHAN_INFO_RAW_SEPARATE_BIT;
  125. idx++;
  126. }
  127. timestamp = chan_array + idx;
  128. timestamp->type = IIO_TIMESTAMP;
  129. timestamp->channel = -1;
  130. timestamp->scan_index = idx;
  131. timestamp->scan_type.sign = 's';
  132. timestamp->scan_type.realbits = 64;
  133. timestamp->scan_type.storagebits = 64;
  134. idev->channels = chan_array;
  135. return idev->num_channels;
  136. }
  137. static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
  138. struct at91_adc_trigger *triggers,
  139. const char *trigger_name)
  140. {
  141. struct at91_adc_state *st = iio_priv(idev);
  142. u8 value = 0;
  143. int i;
  144. for (i = 0; i < st->trigger_number; i++) {
  145. char *name = kasprintf(GFP_KERNEL,
  146. "%s-dev%d-%s",
  147. idev->name,
  148. idev->id,
  149. triggers[i].name);
  150. if (!name)
  151. return -ENOMEM;
  152. if (strcmp(trigger_name, name) == 0) {
  153. value = triggers[i].value;
  154. kfree(name);
  155. break;
  156. }
  157. kfree(name);
  158. }
  159. return value;
  160. }
  161. static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
  162. {
  163. struct iio_dev *idev = trig->private_data;
  164. struct at91_adc_state *st = iio_priv(idev);
  165. struct iio_buffer *buffer = idev->buffer;
  166. struct at91_adc_reg_desc *reg = st->registers;
  167. u32 status = at91_adc_readl(st, reg->trigger_register);
  168. u8 value;
  169. u8 bit;
  170. value = at91_adc_get_trigger_value_by_name(idev,
  171. st->trigger_list,
  172. idev->trig->name);
  173. if (value == 0)
  174. return -EINVAL;
  175. if (state) {
  176. st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
  177. if (st->buffer == NULL)
  178. return -ENOMEM;
  179. at91_adc_writel(st, reg->trigger_register,
  180. status | value);
  181. for_each_set_bit(bit, buffer->scan_mask,
  182. st->num_channels) {
  183. struct iio_chan_spec const *chan = idev->channels + bit;
  184. at91_adc_writel(st, AT91_ADC_CHER,
  185. AT91_ADC_CH(chan->channel));
  186. }
  187. at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
  188. } else {
  189. at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
  190. at91_adc_writel(st, reg->trigger_register,
  191. status & ~value);
  192. for_each_set_bit(bit, buffer->scan_mask,
  193. st->num_channels) {
  194. struct iio_chan_spec const *chan = idev->channels + bit;
  195. at91_adc_writel(st, AT91_ADC_CHDR,
  196. AT91_ADC_CH(chan->channel));
  197. }
  198. kfree(st->buffer);
  199. }
  200. return 0;
  201. }
  202. static const struct iio_trigger_ops at91_adc_trigger_ops = {
  203. .owner = THIS_MODULE,
  204. .set_trigger_state = &at91_adc_configure_trigger,
  205. };
  206. static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
  207. struct at91_adc_trigger *trigger)
  208. {
  209. struct iio_trigger *trig;
  210. int ret;
  211. trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
  212. idev->id, trigger->name);
  213. if (trig == NULL)
  214. return NULL;
  215. trig->dev.parent = idev->dev.parent;
  216. trig->private_data = idev;
  217. trig->ops = &at91_adc_trigger_ops;
  218. ret = iio_trigger_register(trig);
  219. if (ret)
  220. return NULL;
  221. return trig;
  222. }
  223. static int at91_adc_trigger_init(struct iio_dev *idev)
  224. {
  225. struct at91_adc_state *st = iio_priv(idev);
  226. int i, ret;
  227. st->trig = devm_kzalloc(&idev->dev,
  228. st->trigger_number * sizeof(st->trig),
  229. GFP_KERNEL);
  230. if (st->trig == NULL) {
  231. ret = -ENOMEM;
  232. goto error_ret;
  233. }
  234. for (i = 0; i < st->trigger_number; i++) {
  235. if (st->trigger_list[i].is_external && !(st->use_external))
  236. continue;
  237. st->trig[i] = at91_adc_allocate_trigger(idev,
  238. st->trigger_list + i);
  239. if (st->trig[i] == NULL) {
  240. dev_err(&idev->dev,
  241. "Could not allocate trigger %d\n", i);
  242. ret = -ENOMEM;
  243. goto error_trigger;
  244. }
  245. }
  246. return 0;
  247. error_trigger:
  248. for (i--; i >= 0; i--) {
  249. iio_trigger_unregister(st->trig[i]);
  250. iio_trigger_free(st->trig[i]);
  251. }
  252. error_ret:
  253. return ret;
  254. }
  255. static void at91_adc_trigger_remove(struct iio_dev *idev)
  256. {
  257. struct at91_adc_state *st = iio_priv(idev);
  258. int i;
  259. for (i = 0; i < st->trigger_number; i++) {
  260. iio_trigger_unregister(st->trig[i]);
  261. iio_trigger_free(st->trig[i]);
  262. }
  263. }
  264. static int at91_adc_buffer_init(struct iio_dev *idev)
  265. {
  266. return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
  267. &at91_adc_trigger_handler, NULL);
  268. }
  269. static void at91_adc_buffer_remove(struct iio_dev *idev)
  270. {
  271. iio_triggered_buffer_cleanup(idev);
  272. }
  273. static int at91_adc_read_raw(struct iio_dev *idev,
  274. struct iio_chan_spec const *chan,
  275. int *val, int *val2, long mask)
  276. {
  277. struct at91_adc_state *st = iio_priv(idev);
  278. int ret;
  279. switch (mask) {
  280. case IIO_CHAN_INFO_RAW:
  281. mutex_lock(&st->lock);
  282. at91_adc_writel(st, AT91_ADC_CHER,
  283. AT91_ADC_CH(chan->channel));
  284. at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask);
  285. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
  286. ret = wait_event_interruptible_timeout(st->wq_data_avail,
  287. st->done,
  288. msecs_to_jiffies(1000));
  289. if (ret == 0)
  290. ret = -ETIMEDOUT;
  291. if (ret < 0) {
  292. mutex_unlock(&st->lock);
  293. return ret;
  294. }
  295. *val = st->last_value;
  296. at91_adc_writel(st, AT91_ADC_CHDR,
  297. AT91_ADC_CH(chan->channel));
  298. at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask);
  299. st->last_value = 0;
  300. st->done = false;
  301. mutex_unlock(&st->lock);
  302. return IIO_VAL_INT;
  303. case IIO_CHAN_INFO_SCALE:
  304. *val = (st->vref_mv * 1000) >> chan->scan_type.realbits;
  305. *val2 = 0;
  306. return IIO_VAL_INT_PLUS_MICRO;
  307. default:
  308. break;
  309. }
  310. return -EINVAL;
  311. }
  312. static int at91_adc_probe_dt(struct at91_adc_state *st,
  313. struct platform_device *pdev)
  314. {
  315. struct iio_dev *idev = iio_priv_to_dev(st);
  316. struct device_node *node = pdev->dev.of_node;
  317. struct device_node *trig_node;
  318. int i = 0, ret;
  319. u32 prop;
  320. if (!node)
  321. return -EINVAL;
  322. st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
  323. if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
  324. dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
  325. ret = -EINVAL;
  326. goto error_ret;
  327. }
  328. st->channels_mask = prop;
  329. if (of_property_read_u32(node, "atmel,adc-num-channels", &prop)) {
  330. dev_err(&idev->dev, "Missing adc-num-channels property in the DT.\n");
  331. ret = -EINVAL;
  332. goto error_ret;
  333. }
  334. st->num_channels = prop;
  335. if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
  336. dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
  337. ret = -EINVAL;
  338. goto error_ret;
  339. }
  340. st->startup_time = prop;
  341. if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
  342. dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
  343. ret = -EINVAL;
  344. goto error_ret;
  345. }
  346. st->vref_mv = prop;
  347. st->registers = devm_kzalloc(&idev->dev,
  348. sizeof(struct at91_adc_reg_desc),
  349. GFP_KERNEL);
  350. if (!st->registers) {
  351. dev_err(&idev->dev, "Could not allocate register memory.\n");
  352. ret = -ENOMEM;
  353. goto error_ret;
  354. }
  355. if (of_property_read_u32(node, "atmel,adc-channel-base", &prop)) {
  356. dev_err(&idev->dev, "Missing adc-channel-base property in the DT.\n");
  357. ret = -EINVAL;
  358. goto error_ret;
  359. }
  360. st->registers->channel_base = prop;
  361. if (of_property_read_u32(node, "atmel,adc-drdy-mask", &prop)) {
  362. dev_err(&idev->dev, "Missing adc-drdy-mask property in the DT.\n");
  363. ret = -EINVAL;
  364. goto error_ret;
  365. }
  366. st->registers->drdy_mask = prop;
  367. if (of_property_read_u32(node, "atmel,adc-status-register", &prop)) {
  368. dev_err(&idev->dev, "Missing adc-status-register property in the DT.\n");
  369. ret = -EINVAL;
  370. goto error_ret;
  371. }
  372. st->registers->status_register = prop;
  373. if (of_property_read_u32(node, "atmel,adc-trigger-register", &prop)) {
  374. dev_err(&idev->dev, "Missing adc-trigger-register property in the DT.\n");
  375. ret = -EINVAL;
  376. goto error_ret;
  377. }
  378. st->registers->trigger_register = prop;
  379. st->trigger_number = of_get_child_count(node);
  380. st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
  381. sizeof(struct at91_adc_trigger),
  382. GFP_KERNEL);
  383. if (!st->trigger_list) {
  384. dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
  385. ret = -ENOMEM;
  386. goto error_ret;
  387. }
  388. for_each_child_of_node(node, trig_node) {
  389. struct at91_adc_trigger *trig = st->trigger_list + i;
  390. const char *name;
  391. if (of_property_read_string(trig_node, "trigger-name", &name)) {
  392. dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
  393. ret = -EINVAL;
  394. goto error_ret;
  395. }
  396. trig->name = name;
  397. if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
  398. dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
  399. ret = -EINVAL;
  400. goto error_ret;
  401. }
  402. trig->value = prop;
  403. trig->is_external = of_property_read_bool(trig_node, "trigger-external");
  404. i++;
  405. }
  406. return 0;
  407. error_ret:
  408. return ret;
  409. }
  410. static int at91_adc_probe_pdata(struct at91_adc_state *st,
  411. struct platform_device *pdev)
  412. {
  413. struct at91_adc_data *pdata = pdev->dev.platform_data;
  414. if (!pdata)
  415. return -EINVAL;
  416. st->use_external = pdata->use_external_triggers;
  417. st->vref_mv = pdata->vref;
  418. st->channels_mask = pdata->channels_used;
  419. st->num_channels = pdata->num_channels;
  420. st->startup_time = pdata->startup_time;
  421. st->trigger_number = pdata->trigger_number;
  422. st->trigger_list = pdata->trigger_list;
  423. st->registers = pdata->registers;
  424. return 0;
  425. }
  426. static const struct iio_info at91_adc_info = {
  427. .driver_module = THIS_MODULE,
  428. .read_raw = &at91_adc_read_raw,
  429. };
  430. static int __devinit at91_adc_probe(struct platform_device *pdev)
  431. {
  432. unsigned int prsc, mstrclk, ticks, adc_clk;
  433. int ret;
  434. struct iio_dev *idev;
  435. struct at91_adc_state *st;
  436. struct resource *res;
  437. idev = iio_device_alloc(sizeof(struct at91_adc_state));
  438. if (idev == NULL) {
  439. ret = -ENOMEM;
  440. goto error_ret;
  441. }
  442. st = iio_priv(idev);
  443. if (pdev->dev.of_node)
  444. ret = at91_adc_probe_dt(st, pdev);
  445. else
  446. ret = at91_adc_probe_pdata(st, pdev);
  447. if (ret) {
  448. dev_err(&pdev->dev, "No platform data available.\n");
  449. ret = -EINVAL;
  450. goto error_free_device;
  451. }
  452. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  453. if (!res) {
  454. dev_err(&pdev->dev, "No resource defined\n");
  455. ret = -ENXIO;
  456. goto error_ret;
  457. }
  458. platform_set_drvdata(pdev, idev);
  459. idev->dev.parent = &pdev->dev;
  460. idev->name = dev_name(&pdev->dev);
  461. idev->modes = INDIO_DIRECT_MODE;
  462. idev->info = &at91_adc_info;
  463. st->irq = platform_get_irq(pdev, 0);
  464. if (st->irq < 0) {
  465. dev_err(&pdev->dev, "No IRQ ID is designated\n");
  466. ret = -ENODEV;
  467. goto error_free_device;
  468. }
  469. if (!request_mem_region(res->start, resource_size(res),
  470. "AT91 adc registers")) {
  471. dev_err(&pdev->dev, "Resources are unavailable.\n");
  472. ret = -EBUSY;
  473. goto error_free_device;
  474. }
  475. st->reg_base = ioremap(res->start, resource_size(res));
  476. if (!st->reg_base) {
  477. dev_err(&pdev->dev, "Failed to map registers.\n");
  478. ret = -ENOMEM;
  479. goto error_release_mem;
  480. }
  481. /*
  482. * Disable all IRQs before setting up the handler
  483. */
  484. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
  485. at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
  486. ret = request_irq(st->irq,
  487. at91_adc_eoc_trigger,
  488. 0,
  489. pdev->dev.driver->name,
  490. idev);
  491. if (ret) {
  492. dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
  493. goto error_unmap_reg;
  494. }
  495. st->clk = clk_get(&pdev->dev, "adc_clk");
  496. if (IS_ERR(st->clk)) {
  497. dev_err(&pdev->dev, "Failed to get the clock.\n");
  498. ret = PTR_ERR(st->clk);
  499. goto error_free_irq;
  500. }
  501. ret = clk_prepare(st->clk);
  502. if (ret) {
  503. dev_err(&pdev->dev, "Could not prepare the clock.\n");
  504. goto error_free_clk;
  505. }
  506. ret = clk_enable(st->clk);
  507. if (ret) {
  508. dev_err(&pdev->dev, "Could not enable the clock.\n");
  509. goto error_unprepare_clk;
  510. }
  511. st->adc_clk = clk_get(&pdev->dev, "adc_op_clk");
  512. if (IS_ERR(st->adc_clk)) {
  513. dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
  514. ret = PTR_ERR(st->clk);
  515. goto error_disable_clk;
  516. }
  517. ret = clk_prepare(st->adc_clk);
  518. if (ret) {
  519. dev_err(&pdev->dev, "Could not prepare the ADC clock.\n");
  520. goto error_free_adc_clk;
  521. }
  522. ret = clk_enable(st->adc_clk);
  523. if (ret) {
  524. dev_err(&pdev->dev, "Could not enable the ADC clock.\n");
  525. goto error_unprepare_adc_clk;
  526. }
  527. /*
  528. * Prescaler rate computation using the formula from the Atmel's
  529. * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
  530. * specified by the electrical characteristics of the board.
  531. */
  532. mstrclk = clk_get_rate(st->clk);
  533. adc_clk = clk_get_rate(st->adc_clk);
  534. prsc = (mstrclk / (2 * adc_clk)) - 1;
  535. if (!st->startup_time) {
  536. dev_err(&pdev->dev, "No startup time available.\n");
  537. ret = -EINVAL;
  538. goto error_disable_adc_clk;
  539. }
  540. /*
  541. * Number of ticks needed to cover the startup time of the ADC as
  542. * defined in the electrical characteristics of the board, divided by 8.
  543. * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
  544. */
  545. ticks = round_up((st->startup_time * adc_clk /
  546. 1000000) - 1, 8) / 8;
  547. at91_adc_writel(st, AT91_ADC_MR,
  548. (AT91_ADC_PRESCAL_(prsc) & AT91_ADC_PRESCAL) |
  549. (AT91_ADC_STARTUP_(ticks) & AT91_ADC_STARTUP));
  550. /* Setup the ADC channels available on the board */
  551. ret = at91_adc_channel_init(idev);
  552. if (ret < 0) {
  553. dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
  554. goto error_disable_adc_clk;
  555. }
  556. init_waitqueue_head(&st->wq_data_avail);
  557. mutex_init(&st->lock);
  558. ret = at91_adc_buffer_init(idev);
  559. if (ret < 0) {
  560. dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
  561. goto error_disable_adc_clk;
  562. }
  563. ret = at91_adc_trigger_init(idev);
  564. if (ret < 0) {
  565. dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
  566. goto error_unregister_buffer;
  567. }
  568. ret = iio_device_register(idev);
  569. if (ret < 0) {
  570. dev_err(&pdev->dev, "Couldn't register the device.\n");
  571. goto error_remove_triggers;
  572. }
  573. return 0;
  574. error_remove_triggers:
  575. at91_adc_trigger_remove(idev);
  576. error_unregister_buffer:
  577. at91_adc_buffer_remove(idev);
  578. error_disable_adc_clk:
  579. clk_disable(st->adc_clk);
  580. error_unprepare_adc_clk:
  581. clk_unprepare(st->adc_clk);
  582. error_free_adc_clk:
  583. clk_put(st->adc_clk);
  584. error_disable_clk:
  585. clk_disable(st->clk);
  586. error_unprepare_clk:
  587. clk_unprepare(st->clk);
  588. error_free_clk:
  589. clk_put(st->clk);
  590. error_free_irq:
  591. free_irq(st->irq, idev);
  592. error_unmap_reg:
  593. iounmap(st->reg_base);
  594. error_release_mem:
  595. release_mem_region(res->start, resource_size(res));
  596. error_free_device:
  597. iio_device_free(idev);
  598. error_ret:
  599. return ret;
  600. }
  601. static int __devexit at91_adc_remove(struct platform_device *pdev)
  602. {
  603. struct iio_dev *idev = platform_get_drvdata(pdev);
  604. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  605. struct at91_adc_state *st = iio_priv(idev);
  606. iio_device_unregister(idev);
  607. at91_adc_trigger_remove(idev);
  608. at91_adc_buffer_remove(idev);
  609. clk_disable_unprepare(st->adc_clk);
  610. clk_put(st->adc_clk);
  611. clk_disable(st->clk);
  612. clk_unprepare(st->clk);
  613. clk_put(st->clk);
  614. free_irq(st->irq, idev);
  615. iounmap(st->reg_base);
  616. release_mem_region(res->start, resource_size(res));
  617. iio_device_free(idev);
  618. return 0;
  619. }
  620. static const struct of_device_id at91_adc_dt_ids[] = {
  621. { .compatible = "atmel,at91sam9260-adc" },
  622. {},
  623. };
  624. MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
  625. static struct platform_driver at91_adc_driver = {
  626. .probe = at91_adc_probe,
  627. .remove = __devexit_p(at91_adc_remove),
  628. .driver = {
  629. .name = "at91_adc",
  630. .of_match_table = of_match_ptr(at91_adc_dt_ids),
  631. },
  632. };
  633. module_platform_driver(at91_adc_driver);
  634. MODULE_LICENSE("GPL");
  635. MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
  636. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");