i2c-imx.c 17 KB

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  1. /*
  2. * Copyright (C) 2002 Motorola GSG-China
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version 2
  7. * of the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
  17. * USA.
  18. *
  19. * Author:
  20. * Darius Augulis, Teltonika Inc.
  21. *
  22. * Desc.:
  23. * Implementation of I2C Adapter/Algorithm Driver
  24. * for I2C Bus integrated in Freescale i.MX/MXC processors
  25. *
  26. * Derived from Motorola GSG China I2C example driver
  27. *
  28. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  29. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  30. * Copyright (C) 2007 RightHand Technologies, Inc.
  31. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  32. *
  33. */
  34. /** Includes *******************************************************************
  35. *******************************************************************************/
  36. #include <linux/init.h>
  37. #include <linux/kernel.h>
  38. #include <linux/module.h>
  39. #include <linux/errno.h>
  40. #include <linux/err.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/delay.h>
  43. #include <linux/i2c.h>
  44. #include <linux/io.h>
  45. #include <linux/sched.h>
  46. #include <linux/platform_device.h>
  47. #include <linux/clk.h>
  48. #include <linux/slab.h>
  49. #include <linux/of.h>
  50. #include <linux/of_device.h>
  51. #include <linux/of_i2c.h>
  52. #include <linux/pinctrl/consumer.h>
  53. #include <mach/hardware.h>
  54. #include <mach/i2c.h>
  55. /** Defines ********************************************************************
  56. *******************************************************************************/
  57. /* This will be the driver name the kernel reports */
  58. #define DRIVER_NAME "imx-i2c"
  59. /* Default value */
  60. #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
  61. /* IMX I2C registers */
  62. #define IMX_I2C_IADR 0x00 /* i2c slave address */
  63. #define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
  64. #define IMX_I2C_I2CR 0x08 /* i2c control */
  65. #define IMX_I2C_I2SR 0x0C /* i2c status */
  66. #define IMX_I2C_I2DR 0x10 /* i2c transfer data */
  67. /* Bits of IMX I2C registers */
  68. #define I2SR_RXAK 0x01
  69. #define I2SR_IIF 0x02
  70. #define I2SR_SRW 0x04
  71. #define I2SR_IAL 0x10
  72. #define I2SR_IBB 0x20
  73. #define I2SR_IAAS 0x40
  74. #define I2SR_ICF 0x80
  75. #define I2CR_RSTA 0x04
  76. #define I2CR_TXAK 0x08
  77. #define I2CR_MTX 0x10
  78. #define I2CR_MSTA 0x20
  79. #define I2CR_IIEN 0x40
  80. #define I2CR_IEN 0x80
  81. /** Variables ******************************************************************
  82. *******************************************************************************/
  83. /*
  84. * sorted list of clock divider, register value pairs
  85. * taken from table 26-5, p.26-9, Freescale i.MX
  86. * Integrated Portable System Processor Reference Manual
  87. * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
  88. *
  89. * Duplicated divider values removed from list
  90. */
  91. static u16 __initdata i2c_clk_div[50][2] = {
  92. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  93. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  94. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  95. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  96. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  97. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  98. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  99. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  100. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  101. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  102. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  103. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  104. { 3072, 0x1E }, { 3840, 0x1F }
  105. };
  106. struct imx_i2c_struct {
  107. struct i2c_adapter adapter;
  108. struct clk *clk;
  109. void __iomem *base;
  110. wait_queue_head_t queue;
  111. unsigned long i2csr;
  112. unsigned int disable_delay;
  113. int stopped;
  114. unsigned int ifdr; /* IMX_I2C_IFDR */
  115. };
  116. static const struct of_device_id i2c_imx_dt_ids[] = {
  117. { .compatible = "fsl,imx1-i2c", },
  118. { /* sentinel */ }
  119. };
  120. /** Functions for IMX I2C adapter driver ***************************************
  121. *******************************************************************************/
  122. static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
  123. {
  124. unsigned long orig_jiffies = jiffies;
  125. unsigned int temp;
  126. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  127. while (1) {
  128. temp = readb(i2c_imx->base + IMX_I2C_I2SR);
  129. if (for_busy && (temp & I2SR_IBB))
  130. break;
  131. if (!for_busy && !(temp & I2SR_IBB))
  132. break;
  133. if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
  134. dev_dbg(&i2c_imx->adapter.dev,
  135. "<%s> I2C bus is busy\n", __func__);
  136. return -ETIMEDOUT;
  137. }
  138. schedule();
  139. }
  140. return 0;
  141. }
  142. static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
  143. {
  144. wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
  145. if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
  146. dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
  147. return -ETIMEDOUT;
  148. }
  149. dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
  150. i2c_imx->i2csr = 0;
  151. return 0;
  152. }
  153. static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
  154. {
  155. if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
  156. dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
  157. return -EIO; /* No ACK */
  158. }
  159. dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
  160. return 0;
  161. }
  162. static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
  163. {
  164. unsigned int temp = 0;
  165. int result;
  166. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  167. clk_prepare_enable(i2c_imx->clk);
  168. writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
  169. /* Enable I2C controller */
  170. writeb(0, i2c_imx->base + IMX_I2C_I2SR);
  171. writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
  172. /* Wait controller to be stable */
  173. udelay(50);
  174. /* Start I2C transaction */
  175. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  176. temp |= I2CR_MSTA;
  177. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  178. result = i2c_imx_bus_busy(i2c_imx, 1);
  179. if (result)
  180. return result;
  181. i2c_imx->stopped = 0;
  182. temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
  183. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  184. return result;
  185. }
  186. static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
  187. {
  188. unsigned int temp = 0;
  189. if (!i2c_imx->stopped) {
  190. /* Stop I2C transaction */
  191. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  192. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  193. temp &= ~(I2CR_MSTA | I2CR_MTX);
  194. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  195. }
  196. if (cpu_is_mx1()) {
  197. /*
  198. * This delay caused by an i.MXL hardware bug.
  199. * If no (or too short) delay, no "STOP" bit will be generated.
  200. */
  201. udelay(i2c_imx->disable_delay);
  202. }
  203. if (!i2c_imx->stopped) {
  204. i2c_imx_bus_busy(i2c_imx, 0);
  205. i2c_imx->stopped = 1;
  206. }
  207. /* Disable I2C controller */
  208. writeb(0, i2c_imx->base + IMX_I2C_I2CR);
  209. clk_disable_unprepare(i2c_imx->clk);
  210. }
  211. static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
  212. unsigned int rate)
  213. {
  214. unsigned int i2c_clk_rate;
  215. unsigned int div;
  216. int i;
  217. /* Divider value calculation */
  218. i2c_clk_rate = clk_get_rate(i2c_imx->clk);
  219. div = (i2c_clk_rate + rate - 1) / rate;
  220. if (div < i2c_clk_div[0][0])
  221. i = 0;
  222. else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
  223. i = ARRAY_SIZE(i2c_clk_div) - 1;
  224. else
  225. for (i = 0; i2c_clk_div[i][0] < div; i++);
  226. /* Store divider value */
  227. i2c_imx->ifdr = i2c_clk_div[i][1];
  228. /*
  229. * There dummy delay is calculated.
  230. * It should be about one I2C clock period long.
  231. * This delay is used in I2C bus disable function
  232. * to fix chip hardware bug.
  233. */
  234. i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
  235. + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
  236. /* dev_dbg() can't be used, because adapter is not yet registered */
  237. #ifdef CONFIG_I2C_DEBUG_BUS
  238. printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
  239. __func__, i2c_clk_rate, div);
  240. printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
  241. __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
  242. #endif
  243. }
  244. static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
  245. {
  246. struct imx_i2c_struct *i2c_imx = dev_id;
  247. unsigned int temp;
  248. temp = readb(i2c_imx->base + IMX_I2C_I2SR);
  249. if (temp & I2SR_IIF) {
  250. /* save status register */
  251. i2c_imx->i2csr = temp;
  252. temp &= ~I2SR_IIF;
  253. writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
  254. wake_up(&i2c_imx->queue);
  255. return IRQ_HANDLED;
  256. }
  257. return IRQ_NONE;
  258. }
  259. static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
  260. {
  261. int i, result;
  262. dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
  263. __func__, msgs->addr << 1);
  264. /* write slave address */
  265. writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
  266. result = i2c_imx_trx_complete(i2c_imx);
  267. if (result)
  268. return result;
  269. result = i2c_imx_acked(i2c_imx);
  270. if (result)
  271. return result;
  272. dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
  273. /* write data */
  274. for (i = 0; i < msgs->len; i++) {
  275. dev_dbg(&i2c_imx->adapter.dev,
  276. "<%s> write byte: B%d=0x%X\n",
  277. __func__, i, msgs->buf[i]);
  278. writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
  279. result = i2c_imx_trx_complete(i2c_imx);
  280. if (result)
  281. return result;
  282. result = i2c_imx_acked(i2c_imx);
  283. if (result)
  284. return result;
  285. }
  286. return 0;
  287. }
  288. static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
  289. {
  290. int i, result;
  291. unsigned int temp;
  292. dev_dbg(&i2c_imx->adapter.dev,
  293. "<%s> write slave address: addr=0x%x\n",
  294. __func__, (msgs->addr << 1) | 0x01);
  295. /* write slave address */
  296. writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
  297. result = i2c_imx_trx_complete(i2c_imx);
  298. if (result)
  299. return result;
  300. result = i2c_imx_acked(i2c_imx);
  301. if (result)
  302. return result;
  303. dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
  304. /* setup bus to read data */
  305. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  306. temp &= ~I2CR_MTX;
  307. if (msgs->len - 1)
  308. temp &= ~I2CR_TXAK;
  309. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  310. readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
  311. dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
  312. /* read data */
  313. for (i = 0; i < msgs->len; i++) {
  314. result = i2c_imx_trx_complete(i2c_imx);
  315. if (result)
  316. return result;
  317. if (i == (msgs->len - 1)) {
  318. /* It must generate STOP before read I2DR to prevent
  319. controller from generating another clock cycle */
  320. dev_dbg(&i2c_imx->adapter.dev,
  321. "<%s> clear MSTA\n", __func__);
  322. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  323. temp &= ~(I2CR_MSTA | I2CR_MTX);
  324. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  325. i2c_imx_bus_busy(i2c_imx, 0);
  326. i2c_imx->stopped = 1;
  327. } else if (i == (msgs->len - 2)) {
  328. dev_dbg(&i2c_imx->adapter.dev,
  329. "<%s> set TXAK\n", __func__);
  330. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  331. temp |= I2CR_TXAK;
  332. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  333. }
  334. msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
  335. dev_dbg(&i2c_imx->adapter.dev,
  336. "<%s> read byte: B%d=0x%X\n",
  337. __func__, i, msgs->buf[i]);
  338. }
  339. return 0;
  340. }
  341. static int i2c_imx_xfer(struct i2c_adapter *adapter,
  342. struct i2c_msg *msgs, int num)
  343. {
  344. unsigned int i, temp;
  345. int result;
  346. struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
  347. dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
  348. /* Start I2C transfer */
  349. result = i2c_imx_start(i2c_imx);
  350. if (result)
  351. goto fail0;
  352. /* read/write data */
  353. for (i = 0; i < num; i++) {
  354. if (i) {
  355. dev_dbg(&i2c_imx->adapter.dev,
  356. "<%s> repeated start\n", __func__);
  357. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  358. temp |= I2CR_RSTA;
  359. writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
  360. result = i2c_imx_bus_busy(i2c_imx, 1);
  361. if (result)
  362. goto fail0;
  363. }
  364. dev_dbg(&i2c_imx->adapter.dev,
  365. "<%s> transfer message: %d\n", __func__, i);
  366. /* write/read data */
  367. #ifdef CONFIG_I2C_DEBUG_BUS
  368. temp = readb(i2c_imx->base + IMX_I2C_I2CR);
  369. dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
  370. "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
  371. (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
  372. (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
  373. (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
  374. temp = readb(i2c_imx->base + IMX_I2C_I2SR);
  375. dev_dbg(&i2c_imx->adapter.dev,
  376. "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
  377. "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
  378. (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
  379. (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
  380. (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
  381. (temp & I2SR_RXAK ? 1 : 0));
  382. #endif
  383. if (msgs[i].flags & I2C_M_RD)
  384. result = i2c_imx_read(i2c_imx, &msgs[i]);
  385. else
  386. result = i2c_imx_write(i2c_imx, &msgs[i]);
  387. if (result)
  388. goto fail0;
  389. }
  390. fail0:
  391. /* Stop I2C transfer */
  392. i2c_imx_stop(i2c_imx);
  393. dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
  394. (result < 0) ? "error" : "success msg",
  395. (result < 0) ? result : num);
  396. return (result < 0) ? result : num;
  397. }
  398. static u32 i2c_imx_func(struct i2c_adapter *adapter)
  399. {
  400. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  401. }
  402. static struct i2c_algorithm i2c_imx_algo = {
  403. .master_xfer = i2c_imx_xfer,
  404. .functionality = i2c_imx_func,
  405. };
  406. static int __init i2c_imx_probe(struct platform_device *pdev)
  407. {
  408. struct imx_i2c_struct *i2c_imx;
  409. struct resource *res;
  410. struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
  411. struct pinctrl *pinctrl;
  412. void __iomem *base;
  413. int irq, ret;
  414. u32 bitrate;
  415. dev_dbg(&pdev->dev, "<%s>\n", __func__);
  416. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  417. if (!res) {
  418. dev_err(&pdev->dev, "can't get device resources\n");
  419. return -ENOENT;
  420. }
  421. irq = platform_get_irq(pdev, 0);
  422. if (irq < 0) {
  423. dev_err(&pdev->dev, "can't get irq number\n");
  424. return -ENOENT;
  425. }
  426. base = devm_request_and_ioremap(&pdev->dev, res);
  427. if (!base)
  428. return -EBUSY;
  429. i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
  430. GFP_KERNEL);
  431. if (!i2c_imx) {
  432. dev_err(&pdev->dev, "can't allocate interface\n");
  433. return -ENOMEM;
  434. }
  435. /* Setup i2c_imx driver structure */
  436. strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
  437. i2c_imx->adapter.owner = THIS_MODULE;
  438. i2c_imx->adapter.algo = &i2c_imx_algo;
  439. i2c_imx->adapter.dev.parent = &pdev->dev;
  440. i2c_imx->adapter.nr = pdev->id;
  441. i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
  442. i2c_imx->base = base;
  443. pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  444. if (IS_ERR(pinctrl)) {
  445. dev_err(&pdev->dev, "can't get/select pinctrl\n");
  446. return PTR_ERR(pinctrl);
  447. }
  448. /* Get I2C clock */
  449. i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
  450. if (IS_ERR(i2c_imx->clk)) {
  451. dev_err(&pdev->dev, "can't get I2C clock\n");
  452. return PTR_ERR(i2c_imx->clk);
  453. }
  454. /* Request IRQ */
  455. ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
  456. pdev->name, i2c_imx);
  457. if (ret) {
  458. dev_err(&pdev->dev, "can't claim irq %d\n", irq);
  459. return ret;
  460. }
  461. /* Init queue */
  462. init_waitqueue_head(&i2c_imx->queue);
  463. /* Set up adapter data */
  464. i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
  465. /* Set up clock divider */
  466. bitrate = IMX_I2C_BIT_RATE;
  467. ret = of_property_read_u32(pdev->dev.of_node,
  468. "clock-frequency", &bitrate);
  469. if (ret < 0 && pdata && pdata->bitrate)
  470. bitrate = pdata->bitrate;
  471. i2c_imx_set_clk(i2c_imx, bitrate);
  472. /* Set up chip registers to defaults */
  473. writeb(0, i2c_imx->base + IMX_I2C_I2CR);
  474. writeb(0, i2c_imx->base + IMX_I2C_I2SR);
  475. /* Add I2C adapter */
  476. ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
  477. if (ret < 0) {
  478. dev_err(&pdev->dev, "registration failed\n");
  479. return ret;
  480. }
  481. of_i2c_register_devices(&i2c_imx->adapter);
  482. /* Set up platform driver data */
  483. platform_set_drvdata(pdev, i2c_imx);
  484. dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
  485. dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
  486. res->start, res->end);
  487. dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x\n",
  488. resource_size(res), res->start);
  489. dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
  490. i2c_imx->adapter.name);
  491. dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
  492. return 0; /* Return OK */
  493. }
  494. static int __exit i2c_imx_remove(struct platform_device *pdev)
  495. {
  496. struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
  497. /* remove adapter */
  498. dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
  499. i2c_del_adapter(&i2c_imx->adapter);
  500. platform_set_drvdata(pdev, NULL);
  501. /* setup chip registers to defaults */
  502. writeb(0, i2c_imx->base + IMX_I2C_IADR);
  503. writeb(0, i2c_imx->base + IMX_I2C_IFDR);
  504. writeb(0, i2c_imx->base + IMX_I2C_I2CR);
  505. writeb(0, i2c_imx->base + IMX_I2C_I2SR);
  506. return 0;
  507. }
  508. static struct platform_driver i2c_imx_driver = {
  509. .remove = __exit_p(i2c_imx_remove),
  510. .driver = {
  511. .name = DRIVER_NAME,
  512. .owner = THIS_MODULE,
  513. .of_match_table = i2c_imx_dt_ids,
  514. }
  515. };
  516. static int __init i2c_adap_imx_init(void)
  517. {
  518. return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
  519. }
  520. subsys_initcall(i2c_adap_imx_init);
  521. static void __exit i2c_adap_imx_exit(void)
  522. {
  523. platform_driver_unregister(&i2c_imx_driver);
  524. }
  525. module_exit(i2c_adap_imx_exit);
  526. MODULE_LICENSE("GPL");
  527. MODULE_AUTHOR("Darius Augulis");
  528. MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
  529. MODULE_ALIAS("platform:" DRIVER_NAME);