nouveau_drv.c 15 KB

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  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #include <linux/console.h>
  25. #include <linux/module.h>
  26. #include "drmP.h"
  27. #include "drm.h"
  28. #include "drm_crtc_helper.h"
  29. #include "nouveau_drv.h"
  30. #include "nouveau_abi16.h"
  31. #include "nouveau_hw.h"
  32. #include "nouveau_fb.h"
  33. #include "nouveau_fbcon.h"
  34. #include "nouveau_pm.h"
  35. #include "nouveau_fifo.h"
  36. #include "nv50_display.h"
  37. #include "drm_pciids.h"
  38. MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)");
  39. int nouveau_agpmode = -1;
  40. module_param_named(agpmode, nouveau_agpmode, int, 0400);
  41. MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
  42. int nouveau_modeset = -1;
  43. module_param_named(modeset, nouveau_modeset, int, 0400);
  44. MODULE_PARM_DESC(vbios, "Override default VBIOS location");
  45. char *nouveau_vbios;
  46. module_param_named(vbios, nouveau_vbios, charp, 0400);
  47. MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM");
  48. int nouveau_vram_pushbuf;
  49. module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
  50. MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
  51. int nouveau_vram_notify = 0;
  52. module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
  53. MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
  54. char *nouveau_vram_type;
  55. module_param_named(vram_type, nouveau_vram_type, charp, 0400);
  56. MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
  57. int nouveau_duallink = 1;
  58. module_param_named(duallink, nouveau_duallink, int, 0400);
  59. MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
  60. int nouveau_uscript_lvds = -1;
  61. module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
  62. MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
  63. int nouveau_uscript_tmds = -1;
  64. module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
  65. MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
  66. int nouveau_ignorelid = 0;
  67. module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
  68. MODULE_PARM_DESC(noaccel, "Disable all acceleration");
  69. int nouveau_noaccel = -1;
  70. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  71. MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration");
  72. int nouveau_nofbaccel = 0;
  73. module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400);
  74. MODULE_PARM_DESC(force_post, "Force POST");
  75. int nouveau_force_post = 0;
  76. module_param_named(force_post, nouveau_force_post, int, 0400);
  77. MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
  78. int nouveau_override_conntype = 0;
  79. module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
  80. MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
  81. int nouveau_tv_disable = 0;
  82. module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
  83. MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
  84. "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
  85. "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
  86. "\t\tDefault: PAL\n"
  87. "\t\t*NOTE* Ignored for cards with external TV encoders.");
  88. char *nouveau_tv_norm;
  89. module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
  90. MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n"
  91. "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n"
  92. "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n"
  93. "\t\t0x100 vgaattr, 0x200 EVO (G80+)");
  94. int nouveau_reg_debug;
  95. module_param_named(reg_debug, nouveau_reg_debug, int, 0600);
  96. MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
  97. char *nouveau_perflvl;
  98. module_param_named(perflvl, nouveau_perflvl, charp, 0400);
  99. MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
  100. int nouveau_perflvl_wr;
  101. module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
  102. MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
  103. int nouveau_msi;
  104. module_param_named(msi, nouveau_msi, int, 0400);
  105. MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
  106. int nouveau_ctxfw;
  107. module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
  108. MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
  109. int nouveau_mxmdcb = 1;
  110. module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
  111. int nouveau_fbpercrtc;
  112. #if 0
  113. module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
  114. #endif
  115. static struct pci_device_id pciidlist[] = {
  116. {
  117. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  118. .class = PCI_BASE_CLASS_DISPLAY << 16,
  119. .class_mask = 0xff << 16,
  120. },
  121. {
  122. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  123. .class = PCI_BASE_CLASS_DISPLAY << 16,
  124. .class_mask = 0xff << 16,
  125. },
  126. {}
  127. };
  128. MODULE_DEVICE_TABLE(pci, pciidlist);
  129. static struct drm_driver driver;
  130. static int __devinit
  131. nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  132. {
  133. return drm_get_pci_dev(pdev, ent, &driver);
  134. }
  135. static void
  136. nouveau_pci_remove(struct pci_dev *pdev)
  137. {
  138. struct drm_device *dev = pci_get_drvdata(pdev);
  139. drm_put_dev(dev);
  140. }
  141. int
  142. nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
  143. {
  144. struct drm_device *dev = pci_get_drvdata(pdev);
  145. struct drm_nouveau_private *dev_priv = dev->dev_private;
  146. struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
  147. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  148. struct nouveau_channel *chan;
  149. struct drm_crtc *crtc;
  150. int ret, i, e;
  151. if (pm_state.event == PM_EVENT_PRETHAW)
  152. return 0;
  153. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  154. return 0;
  155. NV_INFO(dev, "Disabling display...\n");
  156. nouveau_display_fini(dev);
  157. NV_INFO(dev, "Disabling fbcon...\n");
  158. nouveau_fbcon_set_suspend(dev, 1);
  159. NV_INFO(dev, "Unpinning framebuffer(s)...\n");
  160. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  161. struct nouveau_framebuffer *nouveau_fb;
  162. nouveau_fb = nouveau_framebuffer(crtc->fb);
  163. if (!nouveau_fb || !nouveau_fb->nvbo)
  164. continue;
  165. nouveau_bo_unpin(nouveau_fb->nvbo);
  166. }
  167. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  168. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  169. nouveau_bo_unmap(nv_crtc->cursor.nvbo);
  170. nouveau_bo_unpin(nv_crtc->cursor.nvbo);
  171. }
  172. NV_INFO(dev, "Evicting buffers...\n");
  173. ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
  174. NV_INFO(dev, "Idling channels...\n");
  175. for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
  176. chan = dev_priv->channels.ptr[i];
  177. if (chan && chan->pushbuf_bo)
  178. nouveau_channel_idle(chan);
  179. }
  180. for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
  181. if (!dev_priv->eng[e])
  182. continue;
  183. ret = dev_priv->eng[e]->fini(dev, e, true);
  184. if (ret) {
  185. NV_ERROR(dev, "... engine %d failed: %d\n", e, ret);
  186. goto out_abort;
  187. }
  188. }
  189. ret = pinstmem->suspend(dev);
  190. if (ret) {
  191. NV_ERROR(dev, "... failed: %d\n", ret);
  192. goto out_abort;
  193. }
  194. NV_INFO(dev, "Suspending GPU objects...\n");
  195. ret = nouveau_gpuobj_suspend(dev);
  196. if (ret) {
  197. NV_ERROR(dev, "... failed: %d\n", ret);
  198. pinstmem->resume(dev);
  199. goto out_abort;
  200. }
  201. NV_INFO(dev, "And we're gone!\n");
  202. pci_save_state(pdev);
  203. if (pm_state.event == PM_EVENT_SUSPEND) {
  204. pci_disable_device(pdev);
  205. pci_set_power_state(pdev, PCI_D3hot);
  206. }
  207. return 0;
  208. out_abort:
  209. NV_INFO(dev, "Re-enabling acceleration..\n");
  210. for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
  211. if (dev_priv->eng[e])
  212. dev_priv->eng[e]->init(dev, e);
  213. }
  214. return ret;
  215. }
  216. int
  217. nouveau_pci_resume(struct pci_dev *pdev)
  218. {
  219. struct drm_device *dev = pci_get_drvdata(pdev);
  220. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  221. struct drm_nouveau_private *dev_priv = dev->dev_private;
  222. struct nouveau_engine *engine = &dev_priv->engine;
  223. struct drm_crtc *crtc;
  224. int ret, i;
  225. if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
  226. return 0;
  227. NV_INFO(dev, "We're back, enabling device...\n");
  228. pci_set_power_state(pdev, PCI_D0);
  229. pci_restore_state(pdev);
  230. if (pci_enable_device(pdev))
  231. return -1;
  232. pci_set_master(dev->pdev);
  233. /* Make sure the AGP controller is in a consistent state */
  234. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
  235. nouveau_mem_reset_agp(dev);
  236. /* Make the CRTCs accessible */
  237. engine->display.early_init(dev);
  238. NV_INFO(dev, "POSTing device...\n");
  239. ret = nouveau_run_vbios_init(dev);
  240. if (ret)
  241. return ret;
  242. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  243. ret = nouveau_mem_init_agp(dev);
  244. if (ret) {
  245. NV_ERROR(dev, "error reinitialising AGP: %d\n", ret);
  246. return ret;
  247. }
  248. }
  249. NV_INFO(dev, "Restoring GPU objects...\n");
  250. nouveau_gpuobj_resume(dev);
  251. NV_INFO(dev, "Reinitialising engines...\n");
  252. engine->instmem.resume(dev);
  253. engine->mc.init(dev);
  254. engine->timer.init(dev);
  255. engine->fb.init(dev);
  256. for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
  257. if (dev_priv->eng[i])
  258. dev_priv->eng[i]->init(dev, i);
  259. }
  260. nouveau_irq_postinstall(dev);
  261. /* Re-write SKIPS, they'll have been lost over the suspend */
  262. if (nouveau_vram_pushbuf) {
  263. struct nouveau_channel *chan;
  264. int j;
  265. for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
  266. chan = dev_priv->channels.ptr[i];
  267. if (!chan || !chan->pushbuf_bo)
  268. continue;
  269. for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
  270. nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
  271. }
  272. }
  273. nouveau_pm_resume(dev);
  274. NV_INFO(dev, "Restoring mode...\n");
  275. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  276. struct nouveau_framebuffer *nouveau_fb;
  277. nouveau_fb = nouveau_framebuffer(crtc->fb);
  278. if (!nouveau_fb || !nouveau_fb->nvbo)
  279. continue;
  280. nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
  281. }
  282. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  283. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  284. ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
  285. if (!ret)
  286. ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
  287. if (ret)
  288. NV_ERROR(dev, "Could not pin/map cursor.\n");
  289. }
  290. nouveau_fbcon_set_suspend(dev, 0);
  291. nouveau_fbcon_zfill_all(dev);
  292. nouveau_display_init(dev);
  293. /* Force CLUT to get re-loaded during modeset */
  294. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  295. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  296. nv_crtc->lut.depth = 0;
  297. }
  298. drm_helper_resume_force_mode(dev);
  299. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  300. struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
  301. u32 offset = nv_crtc->cursor.nvbo->bo.offset;
  302. nv_crtc->cursor.set_offset(nv_crtc, offset);
  303. nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
  304. nv_crtc->cursor_saved_y);
  305. }
  306. return 0;
  307. }
  308. static struct drm_ioctl_desc nouveau_ioctls[] = {
  309. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
  310. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  311. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
  312. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
  313. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  314. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
  315. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
  316. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
  317. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
  318. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
  319. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
  320. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
  321. };
  322. static const struct file_operations nouveau_driver_fops = {
  323. .owner = THIS_MODULE,
  324. .open = drm_open,
  325. .release = drm_release,
  326. .unlocked_ioctl = drm_ioctl,
  327. .mmap = nouveau_ttm_mmap,
  328. .poll = drm_poll,
  329. .fasync = drm_fasync,
  330. .read = drm_read,
  331. #if defined(CONFIG_COMPAT)
  332. .compat_ioctl = nouveau_compat_ioctl,
  333. #endif
  334. .llseek = noop_llseek,
  335. };
  336. static struct drm_driver driver = {
  337. .driver_features =
  338. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  339. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  340. DRIVER_MODESET | DRIVER_PRIME,
  341. .load = nouveau_load,
  342. .firstopen = nouveau_firstopen,
  343. .lastclose = nouveau_lastclose,
  344. .unload = nouveau_unload,
  345. .open = nouveau_open,
  346. .preclose = nouveau_preclose,
  347. .postclose = nouveau_postclose,
  348. #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
  349. .debugfs_init = nouveau_debugfs_init,
  350. .debugfs_cleanup = nouveau_debugfs_takedown,
  351. #endif
  352. .irq_preinstall = nouveau_irq_preinstall,
  353. .irq_postinstall = nouveau_irq_postinstall,
  354. .irq_uninstall = nouveau_irq_uninstall,
  355. .irq_handler = nouveau_irq_handler,
  356. .get_vblank_counter = drm_vblank_count,
  357. .enable_vblank = nouveau_vblank_enable,
  358. .disable_vblank = nouveau_vblank_disable,
  359. .ioctls = nouveau_ioctls,
  360. .fops = &nouveau_driver_fops,
  361. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  362. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  363. .gem_prime_export = nouveau_gem_prime_export,
  364. .gem_prime_import = nouveau_gem_prime_import,
  365. .gem_init_object = nouveau_gem_object_new,
  366. .gem_free_object = nouveau_gem_object_del,
  367. .gem_open_object = nouveau_gem_object_open,
  368. .gem_close_object = nouveau_gem_object_close,
  369. .dumb_create = nouveau_display_dumb_create,
  370. .dumb_map_offset = nouveau_display_dumb_map_offset,
  371. .dumb_destroy = nouveau_display_dumb_destroy,
  372. .name = DRIVER_NAME,
  373. .desc = DRIVER_DESC,
  374. #ifdef GIT_REVISION
  375. .date = GIT_REVISION,
  376. #else
  377. .date = DRIVER_DATE,
  378. #endif
  379. .major = DRIVER_MAJOR,
  380. .minor = DRIVER_MINOR,
  381. .patchlevel = DRIVER_PATCHLEVEL,
  382. };
  383. static struct pci_driver nouveau_pci_driver = {
  384. .name = DRIVER_NAME,
  385. .id_table = pciidlist,
  386. .probe = nouveau_pci_probe,
  387. .remove = nouveau_pci_remove,
  388. .suspend = nouveau_pci_suspend,
  389. .resume = nouveau_pci_resume
  390. };
  391. static int __init nouveau_init(void)
  392. {
  393. driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
  394. if (nouveau_modeset == -1) {
  395. #ifdef CONFIG_VGA_CONSOLE
  396. if (vgacon_text_force())
  397. nouveau_modeset = 0;
  398. else
  399. #endif
  400. nouveau_modeset = 1;
  401. }
  402. if (!nouveau_modeset)
  403. return 0;
  404. nouveau_register_dsm_handler();
  405. return drm_pci_init(&driver, &nouveau_pci_driver);
  406. }
  407. static void __exit nouveau_exit(void)
  408. {
  409. if (!nouveau_modeset)
  410. return;
  411. drm_pci_exit(&driver, &nouveau_pci_driver);
  412. nouveau_unregister_dsm_handler();
  413. }
  414. module_init(nouveau_init);
  415. module_exit(nouveau_exit);
  416. MODULE_AUTHOR(DRIVER_AUTHOR);
  417. MODULE_DESCRIPTION(DRIVER_DESC);
  418. MODULE_LICENSE("GPL and additional rights");