intel_sdvo.c 79 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include "drmP.h"
  33. #include "drm.h"
  34. #include "drm_crtc.h"
  35. #include "drm_edid.h"
  36. #include "intel_drv.h"
  37. #include "i915_drm.h"
  38. #include "i915_drv.h"
  39. #include "intel_sdvo_regs.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  51. static const char *tv_format_names[] = {
  52. "NTSC_M" , "NTSC_J" , "NTSC_443",
  53. "PAL_B" , "PAL_D" , "PAL_G" ,
  54. "PAL_H" , "PAL_I" , "PAL_M" ,
  55. "PAL_N" , "PAL_NC" , "PAL_60" ,
  56. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  57. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  58. "SECAM_60"
  59. };
  60. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  61. struct intel_sdvo {
  62. struct intel_encoder base;
  63. struct i2c_adapter *i2c;
  64. u8 slave_addr;
  65. struct i2c_adapter ddc;
  66. /* Register for the SDVO device: SDVOB or SDVOC */
  67. uint32_t sdvo_reg;
  68. /* Active outputs controlled by this SDVO output */
  69. uint16_t controlled_output;
  70. /*
  71. * Capabilities of the SDVO device returned by
  72. * i830_sdvo_get_capabilities()
  73. */
  74. struct intel_sdvo_caps caps;
  75. /* Pixel clock limitations reported by the SDVO device, in kHz */
  76. int pixel_clock_min, pixel_clock_max;
  77. /*
  78. * For multiple function SDVO device,
  79. * this is for current attached outputs.
  80. */
  81. uint16_t attached_output;
  82. /*
  83. * Hotplug activation bits for this device
  84. */
  85. uint8_t hotplug_active[2];
  86. /**
  87. * This is used to select the color range of RBG outputs in HDMI mode.
  88. * It is only valid when using TMDS encoding and 8 bit per color mode.
  89. */
  90. uint32_t color_range;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. /**
  110. * This is set if we detect output of sdvo device as LVDS and
  111. * have a valid fixed mode to use with the panel.
  112. */
  113. bool is_lvds;
  114. /**
  115. * This is sdvo fixed pannel mode pointer
  116. */
  117. struct drm_display_mode *sdvo_lvds_fixed_mode;
  118. /* DDC bus used by this SDVO encoder */
  119. uint8_t ddc_bus;
  120. };
  121. struct intel_sdvo_connector {
  122. struct intel_connector base;
  123. /* Mark the type of connector */
  124. uint16_t output_flag;
  125. enum hdmi_force_audio force_audio;
  126. /* This contains all current supported TV format */
  127. u8 tv_format_supported[TV_FORMAT_NUM];
  128. int format_supported_num;
  129. struct drm_property *tv_format;
  130. /* add the property for the SDVO-TV */
  131. struct drm_property *left;
  132. struct drm_property *right;
  133. struct drm_property *top;
  134. struct drm_property *bottom;
  135. struct drm_property *hpos;
  136. struct drm_property *vpos;
  137. struct drm_property *contrast;
  138. struct drm_property *saturation;
  139. struct drm_property *hue;
  140. struct drm_property *sharpness;
  141. struct drm_property *flicker_filter;
  142. struct drm_property *flicker_filter_adaptive;
  143. struct drm_property *flicker_filter_2d;
  144. struct drm_property *tv_chroma_filter;
  145. struct drm_property *tv_luma_filter;
  146. struct drm_property *dot_crawl;
  147. /* add the property for the SDVO-TV/LVDS */
  148. struct drm_property *brightness;
  149. /* Add variable to record current setting for the above property */
  150. u32 left_margin, right_margin, top_margin, bottom_margin;
  151. /* this is to get the range of margin.*/
  152. u32 max_hscan, max_vscan;
  153. u32 max_hpos, cur_hpos;
  154. u32 max_vpos, cur_vpos;
  155. u32 cur_brightness, max_brightness;
  156. u32 cur_contrast, max_contrast;
  157. u32 cur_saturation, max_saturation;
  158. u32 cur_hue, max_hue;
  159. u32 cur_sharpness, max_sharpness;
  160. u32 cur_flicker_filter, max_flicker_filter;
  161. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  162. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  163. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  164. u32 cur_tv_luma_filter, max_tv_luma_filter;
  165. u32 cur_dot_crawl, max_dot_crawl;
  166. };
  167. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  168. {
  169. return container_of(encoder, struct intel_sdvo, base.base);
  170. }
  171. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  172. {
  173. return container_of(intel_attached_encoder(connector),
  174. struct intel_sdvo, base);
  175. }
  176. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  177. {
  178. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  179. }
  180. static bool
  181. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  182. static bool
  183. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  184. struct intel_sdvo_connector *intel_sdvo_connector,
  185. int type);
  186. static bool
  187. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  188. struct intel_sdvo_connector *intel_sdvo_connector);
  189. /**
  190. * Writes the SDVOB or SDVOC with the given value, but always writes both
  191. * SDVOB and SDVOC to work around apparent hardware issues (according to
  192. * comments in the BIOS).
  193. */
  194. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  195. {
  196. struct drm_device *dev = intel_sdvo->base.base.dev;
  197. struct drm_i915_private *dev_priv = dev->dev_private;
  198. u32 bval = val, cval = val;
  199. int i;
  200. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  201. I915_WRITE(intel_sdvo->sdvo_reg, val);
  202. I915_READ(intel_sdvo->sdvo_reg);
  203. return;
  204. }
  205. if (intel_sdvo->sdvo_reg == SDVOB) {
  206. cval = I915_READ(SDVOC);
  207. } else {
  208. bval = I915_READ(SDVOB);
  209. }
  210. /*
  211. * Write the registers twice for luck. Sometimes,
  212. * writing them only once doesn't appear to 'stick'.
  213. * The BIOS does this too. Yay, magic
  214. */
  215. for (i = 0; i < 2; i++)
  216. {
  217. I915_WRITE(SDVOB, bval);
  218. I915_READ(SDVOB);
  219. I915_WRITE(SDVOC, cval);
  220. I915_READ(SDVOC);
  221. }
  222. }
  223. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  224. {
  225. struct i2c_msg msgs[] = {
  226. {
  227. .addr = intel_sdvo->slave_addr,
  228. .flags = 0,
  229. .len = 1,
  230. .buf = &addr,
  231. },
  232. {
  233. .addr = intel_sdvo->slave_addr,
  234. .flags = I2C_M_RD,
  235. .len = 1,
  236. .buf = ch,
  237. }
  238. };
  239. int ret;
  240. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  241. return true;
  242. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  243. return false;
  244. }
  245. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  246. /** Mapping of command numbers to names, for debug output */
  247. static const struct _sdvo_cmd_name {
  248. u8 cmd;
  249. const char *name;
  250. } sdvo_cmd_names[] = {
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  294. /* Add the op code for SDVO enhancements */
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  339. /* HDMI op code */
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  360. };
  361. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  362. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  363. const void *args, int args_len)
  364. {
  365. int i;
  366. DRM_DEBUG_KMS("%s: W: %02X ",
  367. SDVO_NAME(intel_sdvo), cmd);
  368. for (i = 0; i < args_len; i++)
  369. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  370. for (; i < 8; i++)
  371. DRM_LOG_KMS(" ");
  372. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  373. if (cmd == sdvo_cmd_names[i].cmd) {
  374. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  375. break;
  376. }
  377. }
  378. if (i == ARRAY_SIZE(sdvo_cmd_names))
  379. DRM_LOG_KMS("(%02X)", cmd);
  380. DRM_LOG_KMS("\n");
  381. }
  382. static const char *cmd_status_names[] = {
  383. "Power on",
  384. "Success",
  385. "Not supported",
  386. "Invalid arg",
  387. "Pending",
  388. "Target not specified",
  389. "Scaling not supported"
  390. };
  391. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  392. const void *args, int args_len)
  393. {
  394. u8 *buf, status;
  395. struct i2c_msg *msgs;
  396. int i, ret = true;
  397. buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
  398. if (!buf)
  399. return false;
  400. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  401. if (!msgs)
  402. return false;
  403. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  404. for (i = 0; i < args_len; i++) {
  405. msgs[i].addr = intel_sdvo->slave_addr;
  406. msgs[i].flags = 0;
  407. msgs[i].len = 2;
  408. msgs[i].buf = buf + 2 *i;
  409. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  410. buf[2*i + 1] = ((u8*)args)[i];
  411. }
  412. msgs[i].addr = intel_sdvo->slave_addr;
  413. msgs[i].flags = 0;
  414. msgs[i].len = 2;
  415. msgs[i].buf = buf + 2*i;
  416. buf[2*i + 0] = SDVO_I2C_OPCODE;
  417. buf[2*i + 1] = cmd;
  418. /* the following two are to read the response */
  419. status = SDVO_I2C_CMD_STATUS;
  420. msgs[i+1].addr = intel_sdvo->slave_addr;
  421. msgs[i+1].flags = 0;
  422. msgs[i+1].len = 1;
  423. msgs[i+1].buf = &status;
  424. msgs[i+2].addr = intel_sdvo->slave_addr;
  425. msgs[i+2].flags = I2C_M_RD;
  426. msgs[i+2].len = 1;
  427. msgs[i+2].buf = &status;
  428. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  429. if (ret < 0) {
  430. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  431. ret = false;
  432. goto out;
  433. }
  434. if (ret != i+3) {
  435. /* failure in I2C transfer */
  436. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  437. ret = false;
  438. }
  439. out:
  440. kfree(msgs);
  441. kfree(buf);
  442. return ret;
  443. }
  444. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  445. void *response, int response_len)
  446. {
  447. u8 retry = 5;
  448. u8 status;
  449. int i;
  450. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  451. /*
  452. * The documentation states that all commands will be
  453. * processed within 15µs, and that we need only poll
  454. * the status byte a maximum of 3 times in order for the
  455. * command to be complete.
  456. *
  457. * Check 5 times in case the hardware failed to read the docs.
  458. */
  459. if (!intel_sdvo_read_byte(intel_sdvo,
  460. SDVO_I2C_CMD_STATUS,
  461. &status))
  462. goto log_fail;
  463. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  464. udelay(15);
  465. if (!intel_sdvo_read_byte(intel_sdvo,
  466. SDVO_I2C_CMD_STATUS,
  467. &status))
  468. goto log_fail;
  469. }
  470. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  471. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  472. else
  473. DRM_LOG_KMS("(??? %d)", status);
  474. if (status != SDVO_CMD_STATUS_SUCCESS)
  475. goto log_fail;
  476. /* Read the command response */
  477. for (i = 0; i < response_len; i++) {
  478. if (!intel_sdvo_read_byte(intel_sdvo,
  479. SDVO_I2C_RETURN_0 + i,
  480. &((u8 *)response)[i]))
  481. goto log_fail;
  482. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  483. }
  484. DRM_LOG_KMS("\n");
  485. return true;
  486. log_fail:
  487. DRM_LOG_KMS("... failed\n");
  488. return false;
  489. }
  490. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  491. {
  492. if (mode->clock >= 100000)
  493. return 1;
  494. else if (mode->clock >= 50000)
  495. return 2;
  496. else
  497. return 4;
  498. }
  499. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  500. u8 ddc_bus)
  501. {
  502. /* This must be the immediately preceding write before the i2c xfer */
  503. return intel_sdvo_write_cmd(intel_sdvo,
  504. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  505. &ddc_bus, 1);
  506. }
  507. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  508. {
  509. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  510. return false;
  511. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  512. }
  513. static bool
  514. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  515. {
  516. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  517. return false;
  518. return intel_sdvo_read_response(intel_sdvo, value, len);
  519. }
  520. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  521. {
  522. struct intel_sdvo_set_target_input_args targets = {0};
  523. return intel_sdvo_set_value(intel_sdvo,
  524. SDVO_CMD_SET_TARGET_INPUT,
  525. &targets, sizeof(targets));
  526. }
  527. /**
  528. * Return whether each input is trained.
  529. *
  530. * This function is making an assumption about the layout of the response,
  531. * which should be checked against the docs.
  532. */
  533. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  534. {
  535. struct intel_sdvo_get_trained_inputs_response response;
  536. BUILD_BUG_ON(sizeof(response) != 1);
  537. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  538. &response, sizeof(response)))
  539. return false;
  540. *input_1 = response.input0_trained;
  541. *input_2 = response.input1_trained;
  542. return true;
  543. }
  544. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  545. u16 outputs)
  546. {
  547. return intel_sdvo_set_value(intel_sdvo,
  548. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  549. &outputs, sizeof(outputs));
  550. }
  551. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  552. int mode)
  553. {
  554. u8 state = SDVO_ENCODER_STATE_ON;
  555. switch (mode) {
  556. case DRM_MODE_DPMS_ON:
  557. state = SDVO_ENCODER_STATE_ON;
  558. break;
  559. case DRM_MODE_DPMS_STANDBY:
  560. state = SDVO_ENCODER_STATE_STANDBY;
  561. break;
  562. case DRM_MODE_DPMS_SUSPEND:
  563. state = SDVO_ENCODER_STATE_SUSPEND;
  564. break;
  565. case DRM_MODE_DPMS_OFF:
  566. state = SDVO_ENCODER_STATE_OFF;
  567. break;
  568. }
  569. return intel_sdvo_set_value(intel_sdvo,
  570. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  571. }
  572. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  573. int *clock_min,
  574. int *clock_max)
  575. {
  576. struct intel_sdvo_pixel_clock_range clocks;
  577. BUILD_BUG_ON(sizeof(clocks) != 4);
  578. if (!intel_sdvo_get_value(intel_sdvo,
  579. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  580. &clocks, sizeof(clocks)))
  581. return false;
  582. /* Convert the values from units of 10 kHz to kHz. */
  583. *clock_min = clocks.min * 10;
  584. *clock_max = clocks.max * 10;
  585. return true;
  586. }
  587. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  588. u16 outputs)
  589. {
  590. return intel_sdvo_set_value(intel_sdvo,
  591. SDVO_CMD_SET_TARGET_OUTPUT,
  592. &outputs, sizeof(outputs));
  593. }
  594. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  595. struct intel_sdvo_dtd *dtd)
  596. {
  597. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  598. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  599. }
  600. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  601. struct intel_sdvo_dtd *dtd)
  602. {
  603. return intel_sdvo_set_timing(intel_sdvo,
  604. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  605. }
  606. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  607. struct intel_sdvo_dtd *dtd)
  608. {
  609. return intel_sdvo_set_timing(intel_sdvo,
  610. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  611. }
  612. static bool
  613. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  614. uint16_t clock,
  615. uint16_t width,
  616. uint16_t height)
  617. {
  618. struct intel_sdvo_preferred_input_timing_args args;
  619. memset(&args, 0, sizeof(args));
  620. args.clock = clock;
  621. args.width = width;
  622. args.height = height;
  623. args.interlace = 0;
  624. if (intel_sdvo->is_lvds &&
  625. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  626. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  627. args.scaled = 1;
  628. return intel_sdvo_set_value(intel_sdvo,
  629. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  630. &args, sizeof(args));
  631. }
  632. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  633. struct intel_sdvo_dtd *dtd)
  634. {
  635. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  636. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  637. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  638. &dtd->part1, sizeof(dtd->part1)) &&
  639. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  640. &dtd->part2, sizeof(dtd->part2));
  641. }
  642. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  643. {
  644. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  645. }
  646. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  647. const struct drm_display_mode *mode)
  648. {
  649. uint16_t width, height;
  650. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  651. uint16_t h_sync_offset, v_sync_offset;
  652. int mode_clock;
  653. width = mode->hdisplay;
  654. height = mode->vdisplay;
  655. /* do some mode translations */
  656. h_blank_len = mode->htotal - mode->hdisplay;
  657. h_sync_len = mode->hsync_end - mode->hsync_start;
  658. v_blank_len = mode->vtotal - mode->vdisplay;
  659. v_sync_len = mode->vsync_end - mode->vsync_start;
  660. h_sync_offset = mode->hsync_start - mode->hdisplay;
  661. v_sync_offset = mode->vsync_start - mode->vdisplay;
  662. mode_clock = mode->clock;
  663. mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
  664. mode_clock /= 10;
  665. dtd->part1.clock = mode_clock;
  666. dtd->part1.h_active = width & 0xff;
  667. dtd->part1.h_blank = h_blank_len & 0xff;
  668. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  669. ((h_blank_len >> 8) & 0xf);
  670. dtd->part1.v_active = height & 0xff;
  671. dtd->part1.v_blank = v_blank_len & 0xff;
  672. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  673. ((v_blank_len >> 8) & 0xf);
  674. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  675. dtd->part2.h_sync_width = h_sync_len & 0xff;
  676. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  677. (v_sync_len & 0xf);
  678. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  679. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  680. ((v_sync_len & 0x30) >> 4);
  681. dtd->part2.dtd_flags = 0x18;
  682. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  683. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  684. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  685. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  686. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  687. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  688. dtd->part2.sdvo_flags = 0;
  689. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  690. dtd->part2.reserved = 0;
  691. }
  692. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  693. const struct intel_sdvo_dtd *dtd)
  694. {
  695. mode->hdisplay = dtd->part1.h_active;
  696. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  697. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  698. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  699. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  700. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  701. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  702. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  703. mode->vdisplay = dtd->part1.v_active;
  704. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  705. mode->vsync_start = mode->vdisplay;
  706. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  707. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  708. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  709. mode->vsync_end = mode->vsync_start +
  710. (dtd->part2.v_sync_off_width & 0xf);
  711. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  712. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  713. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  714. mode->clock = dtd->part1.clock * 10;
  715. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  716. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  717. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  718. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  719. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  720. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  721. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  722. }
  723. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  724. {
  725. struct intel_sdvo_encode encode;
  726. BUILD_BUG_ON(sizeof(encode) != 2);
  727. return intel_sdvo_get_value(intel_sdvo,
  728. SDVO_CMD_GET_SUPP_ENCODE,
  729. &encode, sizeof(encode));
  730. }
  731. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  732. uint8_t mode)
  733. {
  734. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  735. }
  736. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  737. uint8_t mode)
  738. {
  739. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  740. }
  741. #if 0
  742. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  743. {
  744. int i, j;
  745. uint8_t set_buf_index[2];
  746. uint8_t av_split;
  747. uint8_t buf_size;
  748. uint8_t buf[48];
  749. uint8_t *pos;
  750. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  751. for (i = 0; i <= av_split; i++) {
  752. set_buf_index[0] = i; set_buf_index[1] = 0;
  753. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  754. set_buf_index, 2);
  755. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  756. intel_sdvo_read_response(encoder, &buf_size, 1);
  757. pos = buf;
  758. for (j = 0; j <= buf_size; j += 8) {
  759. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  760. NULL, 0);
  761. intel_sdvo_read_response(encoder, pos, 8);
  762. pos += 8;
  763. }
  764. }
  765. }
  766. #endif
  767. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
  768. {
  769. struct dip_infoframe avi_if = {
  770. .type = DIP_TYPE_AVI,
  771. .ver = DIP_VERSION_AVI,
  772. .len = DIP_LEN_AVI,
  773. };
  774. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  775. uint8_t set_buf_index[2] = { 1, 0 };
  776. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  777. uint64_t *data = (uint64_t *)sdvo_data;
  778. unsigned i;
  779. intel_dip_infoframe_csum(&avi_if);
  780. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  781. * we must not send the ecc field, either. */
  782. memcpy(sdvo_data, &avi_if, 3);
  783. sdvo_data[3] = avi_if.checksum;
  784. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  785. if (!intel_sdvo_set_value(intel_sdvo,
  786. SDVO_CMD_SET_HBUF_INDEX,
  787. set_buf_index, 2))
  788. return false;
  789. for (i = 0; i < sizeof(sdvo_data); i += 8) {
  790. if (!intel_sdvo_set_value(intel_sdvo,
  791. SDVO_CMD_SET_HBUF_DATA,
  792. data, 8))
  793. return false;
  794. data++;
  795. }
  796. return intel_sdvo_set_value(intel_sdvo,
  797. SDVO_CMD_SET_HBUF_TXRATE,
  798. &tx_rate, 1);
  799. }
  800. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  801. {
  802. struct intel_sdvo_tv_format format;
  803. uint32_t format_map;
  804. format_map = 1 << intel_sdvo->tv_format_index;
  805. memset(&format, 0, sizeof(format));
  806. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  807. BUILD_BUG_ON(sizeof(format) != 6);
  808. return intel_sdvo_set_value(intel_sdvo,
  809. SDVO_CMD_SET_TV_FORMAT,
  810. &format, sizeof(format));
  811. }
  812. static bool
  813. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  814. const struct drm_display_mode *mode)
  815. {
  816. struct intel_sdvo_dtd output_dtd;
  817. if (!intel_sdvo_set_target_output(intel_sdvo,
  818. intel_sdvo->attached_output))
  819. return false;
  820. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  821. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  822. return false;
  823. return true;
  824. }
  825. /* Asks the sdvo controller for the preferred input mode given the output mode.
  826. * Unfortunately we have to set up the full output mode to do that. */
  827. static bool
  828. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  829. const struct drm_display_mode *mode,
  830. struct drm_display_mode *adjusted_mode)
  831. {
  832. struct intel_sdvo_dtd input_dtd;
  833. /* Reset the input timing to the screen. Assume always input 0. */
  834. if (!intel_sdvo_set_target_input(intel_sdvo))
  835. return false;
  836. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  837. mode->clock / 10,
  838. mode->hdisplay,
  839. mode->vdisplay))
  840. return false;
  841. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  842. &input_dtd))
  843. return false;
  844. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  845. return true;
  846. }
  847. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  848. const struct drm_display_mode *mode,
  849. struct drm_display_mode *adjusted_mode)
  850. {
  851. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  852. int multiplier;
  853. /* We need to construct preferred input timings based on our
  854. * output timings. To do that, we have to set the output
  855. * timings, even though this isn't really the right place in
  856. * the sequence to do it. Oh well.
  857. */
  858. if (intel_sdvo->is_tv) {
  859. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  860. return false;
  861. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  862. mode,
  863. adjusted_mode);
  864. } else if (intel_sdvo->is_lvds) {
  865. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  866. intel_sdvo->sdvo_lvds_fixed_mode))
  867. return false;
  868. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  869. mode,
  870. adjusted_mode);
  871. }
  872. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  873. * SDVO device will factor out the multiplier during mode_set.
  874. */
  875. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  876. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  877. return true;
  878. }
  879. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  880. struct drm_display_mode *mode,
  881. struct drm_display_mode *adjusted_mode)
  882. {
  883. struct drm_device *dev = encoder->dev;
  884. struct drm_i915_private *dev_priv = dev->dev_private;
  885. struct drm_crtc *crtc = encoder->crtc;
  886. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  887. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  888. u32 sdvox;
  889. struct intel_sdvo_in_out_map in_out;
  890. struct intel_sdvo_dtd input_dtd, output_dtd;
  891. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  892. int rate;
  893. if (!mode)
  894. return;
  895. /* First, set the input mapping for the first input to our controlled
  896. * output. This is only correct if we're a single-input device, in
  897. * which case the first input is the output from the appropriate SDVO
  898. * channel on the motherboard. In a two-input device, the first input
  899. * will be SDVOB and the second SDVOC.
  900. */
  901. in_out.in0 = intel_sdvo->attached_output;
  902. in_out.in1 = 0;
  903. intel_sdvo_set_value(intel_sdvo,
  904. SDVO_CMD_SET_IN_OUT_MAP,
  905. &in_out, sizeof(in_out));
  906. /* Set the output timings to the screen */
  907. if (!intel_sdvo_set_target_output(intel_sdvo,
  908. intel_sdvo->attached_output))
  909. return;
  910. /* lvds has a special fixed output timing. */
  911. if (intel_sdvo->is_lvds)
  912. intel_sdvo_get_dtd_from_mode(&output_dtd,
  913. intel_sdvo->sdvo_lvds_fixed_mode);
  914. else
  915. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  916. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  917. DRM_INFO("Setting output timings on %s failed\n",
  918. SDVO_NAME(intel_sdvo));
  919. /* Set the input timing to the screen. Assume always input 0. */
  920. if (!intel_sdvo_set_target_input(intel_sdvo))
  921. return;
  922. if (intel_sdvo->has_hdmi_monitor) {
  923. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  924. intel_sdvo_set_colorimetry(intel_sdvo,
  925. SDVO_COLORIMETRY_RGB256);
  926. intel_sdvo_set_avi_infoframe(intel_sdvo);
  927. } else
  928. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  929. if (intel_sdvo->is_tv &&
  930. !intel_sdvo_set_tv_format(intel_sdvo))
  931. return;
  932. /* We have tried to get input timing in mode_fixup, and filled into
  933. * adjusted_mode.
  934. */
  935. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  936. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  937. DRM_INFO("Setting input timings on %s failed\n",
  938. SDVO_NAME(intel_sdvo));
  939. switch (pixel_multiplier) {
  940. default:
  941. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  942. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  943. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  944. }
  945. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  946. return;
  947. /* Set the SDVO control regs. */
  948. if (INTEL_INFO(dev)->gen >= 4) {
  949. /* The real mode polarity is set by the SDVO commands, using
  950. * struct intel_sdvo_dtd. */
  951. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  952. if (intel_sdvo->is_hdmi)
  953. sdvox |= intel_sdvo->color_range;
  954. if (INTEL_INFO(dev)->gen < 5)
  955. sdvox |= SDVO_BORDER_ENABLE;
  956. } else {
  957. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  958. switch (intel_sdvo->sdvo_reg) {
  959. case SDVOB:
  960. sdvox &= SDVOB_PRESERVE_MASK;
  961. break;
  962. case SDVOC:
  963. sdvox &= SDVOC_PRESERVE_MASK;
  964. break;
  965. }
  966. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  967. }
  968. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  969. sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
  970. else
  971. sdvox |= TRANSCODER(intel_crtc->pipe);
  972. if (intel_sdvo->has_hdmi_audio)
  973. sdvox |= SDVO_AUDIO_ENABLE;
  974. if (INTEL_INFO(dev)->gen >= 4) {
  975. /* done in crtc_mode_set as the dpll_md reg must be written early */
  976. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  977. /* done in crtc_mode_set as it lives inside the dpll register */
  978. } else {
  979. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  980. }
  981. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  982. INTEL_INFO(dev)->gen < 5)
  983. sdvox |= SDVO_STALL_SELECT;
  984. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  985. }
  986. static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  987. {
  988. struct drm_device *dev = encoder->dev;
  989. struct drm_i915_private *dev_priv = dev->dev_private;
  990. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  991. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  992. u32 temp;
  993. if (mode != DRM_MODE_DPMS_ON) {
  994. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  995. if (0)
  996. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  997. if (mode == DRM_MODE_DPMS_OFF) {
  998. temp = I915_READ(intel_sdvo->sdvo_reg);
  999. if ((temp & SDVO_ENABLE) != 0) {
  1000. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1001. }
  1002. }
  1003. } else {
  1004. bool input1, input2;
  1005. int i;
  1006. u8 status;
  1007. temp = I915_READ(intel_sdvo->sdvo_reg);
  1008. if ((temp & SDVO_ENABLE) == 0)
  1009. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1010. for (i = 0; i < 2; i++)
  1011. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1012. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1013. /* Warn if the device reported failure to sync.
  1014. * A lot of SDVO devices fail to notify of sync, but it's
  1015. * a given it the status is a success, we succeeded.
  1016. */
  1017. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1018. DRM_DEBUG_KMS("First %s output reported failure to "
  1019. "sync\n", SDVO_NAME(intel_sdvo));
  1020. }
  1021. if (0)
  1022. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1023. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1024. }
  1025. return;
  1026. }
  1027. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1028. struct drm_display_mode *mode)
  1029. {
  1030. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1031. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1032. return MODE_NO_DBLESCAN;
  1033. if (intel_sdvo->pixel_clock_min > mode->clock)
  1034. return MODE_CLOCK_LOW;
  1035. if (intel_sdvo->pixel_clock_max < mode->clock)
  1036. return MODE_CLOCK_HIGH;
  1037. if (intel_sdvo->is_lvds) {
  1038. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1039. return MODE_PANEL;
  1040. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1041. return MODE_PANEL;
  1042. }
  1043. return MODE_OK;
  1044. }
  1045. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1046. {
  1047. BUILD_BUG_ON(sizeof(*caps) != 8);
  1048. if (!intel_sdvo_get_value(intel_sdvo,
  1049. SDVO_CMD_GET_DEVICE_CAPS,
  1050. caps, sizeof(*caps)))
  1051. return false;
  1052. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1053. " vendor_id: %d\n"
  1054. " device_id: %d\n"
  1055. " device_rev_id: %d\n"
  1056. " sdvo_version_major: %d\n"
  1057. " sdvo_version_minor: %d\n"
  1058. " sdvo_inputs_mask: %d\n"
  1059. " smooth_scaling: %d\n"
  1060. " sharp_scaling: %d\n"
  1061. " up_scaling: %d\n"
  1062. " down_scaling: %d\n"
  1063. " stall_support: %d\n"
  1064. " output_flags: %d\n",
  1065. caps->vendor_id,
  1066. caps->device_id,
  1067. caps->device_rev_id,
  1068. caps->sdvo_version_major,
  1069. caps->sdvo_version_minor,
  1070. caps->sdvo_inputs_mask,
  1071. caps->smooth_scaling,
  1072. caps->sharp_scaling,
  1073. caps->up_scaling,
  1074. caps->down_scaling,
  1075. caps->stall_support,
  1076. caps->output_flags);
  1077. return true;
  1078. }
  1079. static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
  1080. {
  1081. struct drm_device *dev = intel_sdvo->base.base.dev;
  1082. u8 response[2];
  1083. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1084. * on the line. */
  1085. if (IS_I945G(dev) || IS_I945GM(dev))
  1086. return false;
  1087. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1088. &response, 2) && response[0];
  1089. }
  1090. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1091. {
  1092. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1093. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
  1094. }
  1095. static bool
  1096. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1097. {
  1098. /* Is there more than one type of output? */
  1099. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1100. }
  1101. static struct edid *
  1102. intel_sdvo_get_edid(struct drm_connector *connector)
  1103. {
  1104. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1105. return drm_get_edid(connector, &sdvo->ddc);
  1106. }
  1107. /* Mac mini hack -- use the same DDC as the analog connector */
  1108. static struct edid *
  1109. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1110. {
  1111. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1112. return drm_get_edid(connector,
  1113. intel_gmbus_get_adapter(dev_priv,
  1114. dev_priv->crt_ddc_pin));
  1115. }
  1116. static enum drm_connector_status
  1117. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1118. {
  1119. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1120. enum drm_connector_status status;
  1121. struct edid *edid;
  1122. edid = intel_sdvo_get_edid(connector);
  1123. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1124. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1125. /*
  1126. * Don't use the 1 as the argument of DDC bus switch to get
  1127. * the EDID. It is used for SDVO SPD ROM.
  1128. */
  1129. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1130. intel_sdvo->ddc_bus = ddc;
  1131. edid = intel_sdvo_get_edid(connector);
  1132. if (edid)
  1133. break;
  1134. }
  1135. /*
  1136. * If we found the EDID on the other bus,
  1137. * assume that is the correct DDC bus.
  1138. */
  1139. if (edid == NULL)
  1140. intel_sdvo->ddc_bus = saved_ddc;
  1141. }
  1142. /*
  1143. * When there is no edid and no monitor is connected with VGA
  1144. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1145. */
  1146. if (edid == NULL)
  1147. edid = intel_sdvo_get_analog_edid(connector);
  1148. status = connector_status_unknown;
  1149. if (edid != NULL) {
  1150. /* DDC bus is shared, match EDID to connector type */
  1151. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1152. status = connector_status_connected;
  1153. if (intel_sdvo->is_hdmi) {
  1154. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1155. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1156. }
  1157. } else
  1158. status = connector_status_disconnected;
  1159. connector->display_info.raw_edid = NULL;
  1160. kfree(edid);
  1161. }
  1162. if (status == connector_status_connected) {
  1163. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1164. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1165. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1166. }
  1167. return status;
  1168. }
  1169. static bool
  1170. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1171. struct edid *edid)
  1172. {
  1173. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1174. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1175. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1176. connector_is_digital, monitor_is_digital);
  1177. return connector_is_digital == monitor_is_digital;
  1178. }
  1179. static enum drm_connector_status
  1180. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1181. {
  1182. uint16_t response;
  1183. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1184. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1185. enum drm_connector_status ret;
  1186. if (!intel_sdvo_write_cmd(intel_sdvo,
  1187. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1188. return connector_status_unknown;
  1189. /* add 30ms delay when the output type might be TV */
  1190. if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
  1191. msleep(30);
  1192. if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
  1193. return connector_status_unknown;
  1194. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1195. response & 0xff, response >> 8,
  1196. intel_sdvo_connector->output_flag);
  1197. if (response == 0)
  1198. return connector_status_disconnected;
  1199. intel_sdvo->attached_output = response;
  1200. intel_sdvo->has_hdmi_monitor = false;
  1201. intel_sdvo->has_hdmi_audio = false;
  1202. if ((intel_sdvo_connector->output_flag & response) == 0)
  1203. ret = connector_status_disconnected;
  1204. else if (IS_TMDS(intel_sdvo_connector))
  1205. ret = intel_sdvo_tmds_sink_detect(connector);
  1206. else {
  1207. struct edid *edid;
  1208. /* if we have an edid check it matches the connection */
  1209. edid = intel_sdvo_get_edid(connector);
  1210. if (edid == NULL)
  1211. edid = intel_sdvo_get_analog_edid(connector);
  1212. if (edid != NULL) {
  1213. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1214. edid))
  1215. ret = connector_status_connected;
  1216. else
  1217. ret = connector_status_disconnected;
  1218. connector->display_info.raw_edid = NULL;
  1219. kfree(edid);
  1220. } else
  1221. ret = connector_status_connected;
  1222. }
  1223. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1224. if (ret == connector_status_connected) {
  1225. intel_sdvo->is_tv = false;
  1226. intel_sdvo->is_lvds = false;
  1227. intel_sdvo->base.needs_tv_clock = false;
  1228. if (response & SDVO_TV_MASK) {
  1229. intel_sdvo->is_tv = true;
  1230. intel_sdvo->base.needs_tv_clock = true;
  1231. }
  1232. if (response & SDVO_LVDS_MASK)
  1233. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1234. }
  1235. return ret;
  1236. }
  1237. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1238. {
  1239. struct edid *edid;
  1240. /* set the bus switch and get the modes */
  1241. edid = intel_sdvo_get_edid(connector);
  1242. /*
  1243. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1244. * link between analog and digital outputs. So, if the regular SDVO
  1245. * DDC fails, check to see if the analog output is disconnected, in
  1246. * which case we'll look there for the digital DDC data.
  1247. */
  1248. if (edid == NULL)
  1249. edid = intel_sdvo_get_analog_edid(connector);
  1250. if (edid != NULL) {
  1251. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1252. edid)) {
  1253. drm_mode_connector_update_edid_property(connector, edid);
  1254. drm_add_edid_modes(connector, edid);
  1255. }
  1256. connector->display_info.raw_edid = NULL;
  1257. kfree(edid);
  1258. }
  1259. }
  1260. /*
  1261. * Set of SDVO TV modes.
  1262. * Note! This is in reply order (see loop in get_tv_modes).
  1263. * XXX: all 60Hz refresh?
  1264. */
  1265. static const struct drm_display_mode sdvo_tv_modes[] = {
  1266. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1267. 416, 0, 200, 201, 232, 233, 0,
  1268. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1269. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1270. 416, 0, 240, 241, 272, 273, 0,
  1271. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1272. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1273. 496, 0, 300, 301, 332, 333, 0,
  1274. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1275. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1276. 736, 0, 350, 351, 382, 383, 0,
  1277. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1278. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1279. 736, 0, 400, 401, 432, 433, 0,
  1280. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1281. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1282. 736, 0, 480, 481, 512, 513, 0,
  1283. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1284. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1285. 800, 0, 480, 481, 512, 513, 0,
  1286. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1287. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1288. 800, 0, 576, 577, 608, 609, 0,
  1289. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1290. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1291. 816, 0, 350, 351, 382, 383, 0,
  1292. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1293. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1294. 816, 0, 400, 401, 432, 433, 0,
  1295. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1296. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1297. 816, 0, 480, 481, 512, 513, 0,
  1298. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1299. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1300. 816, 0, 540, 541, 572, 573, 0,
  1301. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1302. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1303. 816, 0, 576, 577, 608, 609, 0,
  1304. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1305. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1306. 864, 0, 576, 577, 608, 609, 0,
  1307. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1308. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1309. 896, 0, 600, 601, 632, 633, 0,
  1310. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1311. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1312. 928, 0, 624, 625, 656, 657, 0,
  1313. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1314. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1315. 1016, 0, 766, 767, 798, 799, 0,
  1316. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1317. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1318. 1120, 0, 768, 769, 800, 801, 0,
  1319. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1320. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1321. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1322. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1323. };
  1324. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1325. {
  1326. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1327. struct intel_sdvo_sdtv_resolution_request tv_res;
  1328. uint32_t reply = 0, format_map = 0;
  1329. int i;
  1330. /* Read the list of supported input resolutions for the selected TV
  1331. * format.
  1332. */
  1333. format_map = 1 << intel_sdvo->tv_format_index;
  1334. memcpy(&tv_res, &format_map,
  1335. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1336. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1337. return;
  1338. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1339. if (!intel_sdvo_write_cmd(intel_sdvo,
  1340. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1341. &tv_res, sizeof(tv_res)))
  1342. return;
  1343. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1344. return;
  1345. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1346. if (reply & (1 << i)) {
  1347. struct drm_display_mode *nmode;
  1348. nmode = drm_mode_duplicate(connector->dev,
  1349. &sdvo_tv_modes[i]);
  1350. if (nmode)
  1351. drm_mode_probed_add(connector, nmode);
  1352. }
  1353. }
  1354. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1355. {
  1356. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1357. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1358. struct drm_display_mode *newmode;
  1359. /*
  1360. * Attempt to get the mode list from DDC.
  1361. * Assume that the preferred modes are
  1362. * arranged in priority order.
  1363. */
  1364. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1365. if (list_empty(&connector->probed_modes) == false)
  1366. goto end;
  1367. /* Fetch modes from VBT */
  1368. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1369. newmode = drm_mode_duplicate(connector->dev,
  1370. dev_priv->sdvo_lvds_vbt_mode);
  1371. if (newmode != NULL) {
  1372. /* Guarantee the mode is preferred */
  1373. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1374. DRM_MODE_TYPE_DRIVER);
  1375. drm_mode_probed_add(connector, newmode);
  1376. }
  1377. }
  1378. end:
  1379. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1380. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1381. intel_sdvo->sdvo_lvds_fixed_mode =
  1382. drm_mode_duplicate(connector->dev, newmode);
  1383. intel_sdvo->is_lvds = true;
  1384. break;
  1385. }
  1386. }
  1387. }
  1388. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1389. {
  1390. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1391. if (IS_TV(intel_sdvo_connector))
  1392. intel_sdvo_get_tv_modes(connector);
  1393. else if (IS_LVDS(intel_sdvo_connector))
  1394. intel_sdvo_get_lvds_modes(connector);
  1395. else
  1396. intel_sdvo_get_ddc_modes(connector);
  1397. return !list_empty(&connector->probed_modes);
  1398. }
  1399. static void
  1400. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1401. {
  1402. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1403. struct drm_device *dev = connector->dev;
  1404. if (intel_sdvo_connector->left)
  1405. drm_property_destroy(dev, intel_sdvo_connector->left);
  1406. if (intel_sdvo_connector->right)
  1407. drm_property_destroy(dev, intel_sdvo_connector->right);
  1408. if (intel_sdvo_connector->top)
  1409. drm_property_destroy(dev, intel_sdvo_connector->top);
  1410. if (intel_sdvo_connector->bottom)
  1411. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1412. if (intel_sdvo_connector->hpos)
  1413. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1414. if (intel_sdvo_connector->vpos)
  1415. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1416. if (intel_sdvo_connector->saturation)
  1417. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1418. if (intel_sdvo_connector->contrast)
  1419. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1420. if (intel_sdvo_connector->hue)
  1421. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1422. if (intel_sdvo_connector->sharpness)
  1423. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1424. if (intel_sdvo_connector->flicker_filter)
  1425. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1426. if (intel_sdvo_connector->flicker_filter_2d)
  1427. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1428. if (intel_sdvo_connector->flicker_filter_adaptive)
  1429. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1430. if (intel_sdvo_connector->tv_luma_filter)
  1431. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1432. if (intel_sdvo_connector->tv_chroma_filter)
  1433. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1434. if (intel_sdvo_connector->dot_crawl)
  1435. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1436. if (intel_sdvo_connector->brightness)
  1437. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1438. }
  1439. static void intel_sdvo_destroy(struct drm_connector *connector)
  1440. {
  1441. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1442. if (intel_sdvo_connector->tv_format)
  1443. drm_property_destroy(connector->dev,
  1444. intel_sdvo_connector->tv_format);
  1445. intel_sdvo_destroy_enhance_property(connector);
  1446. drm_sysfs_connector_remove(connector);
  1447. drm_connector_cleanup(connector);
  1448. kfree(connector);
  1449. }
  1450. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1451. {
  1452. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1453. struct edid *edid;
  1454. bool has_audio = false;
  1455. if (!intel_sdvo->is_hdmi)
  1456. return false;
  1457. edid = intel_sdvo_get_edid(connector);
  1458. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1459. has_audio = drm_detect_monitor_audio(edid);
  1460. return has_audio;
  1461. }
  1462. static int
  1463. intel_sdvo_set_property(struct drm_connector *connector,
  1464. struct drm_property *property,
  1465. uint64_t val)
  1466. {
  1467. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1468. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1469. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1470. uint16_t temp_value;
  1471. uint8_t cmd;
  1472. int ret;
  1473. ret = drm_connector_property_set_value(connector, property, val);
  1474. if (ret)
  1475. return ret;
  1476. if (property == dev_priv->force_audio_property) {
  1477. int i = val;
  1478. bool has_audio;
  1479. if (i == intel_sdvo_connector->force_audio)
  1480. return 0;
  1481. intel_sdvo_connector->force_audio = i;
  1482. if (i == HDMI_AUDIO_AUTO)
  1483. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1484. else
  1485. has_audio = (i == HDMI_AUDIO_ON);
  1486. if (has_audio == intel_sdvo->has_hdmi_audio)
  1487. return 0;
  1488. intel_sdvo->has_hdmi_audio = has_audio;
  1489. goto done;
  1490. }
  1491. if (property == dev_priv->broadcast_rgb_property) {
  1492. if (val == !!intel_sdvo->color_range)
  1493. return 0;
  1494. intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1495. goto done;
  1496. }
  1497. #define CHECK_PROPERTY(name, NAME) \
  1498. if (intel_sdvo_connector->name == property) { \
  1499. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1500. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1501. cmd = SDVO_CMD_SET_##NAME; \
  1502. intel_sdvo_connector->cur_##name = temp_value; \
  1503. goto set_value; \
  1504. }
  1505. if (property == intel_sdvo_connector->tv_format) {
  1506. if (val >= TV_FORMAT_NUM)
  1507. return -EINVAL;
  1508. if (intel_sdvo->tv_format_index ==
  1509. intel_sdvo_connector->tv_format_supported[val])
  1510. return 0;
  1511. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1512. goto done;
  1513. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1514. temp_value = val;
  1515. if (intel_sdvo_connector->left == property) {
  1516. drm_connector_property_set_value(connector,
  1517. intel_sdvo_connector->right, val);
  1518. if (intel_sdvo_connector->left_margin == temp_value)
  1519. return 0;
  1520. intel_sdvo_connector->left_margin = temp_value;
  1521. intel_sdvo_connector->right_margin = temp_value;
  1522. temp_value = intel_sdvo_connector->max_hscan -
  1523. intel_sdvo_connector->left_margin;
  1524. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1525. goto set_value;
  1526. } else if (intel_sdvo_connector->right == property) {
  1527. drm_connector_property_set_value(connector,
  1528. intel_sdvo_connector->left, val);
  1529. if (intel_sdvo_connector->right_margin == temp_value)
  1530. return 0;
  1531. intel_sdvo_connector->left_margin = temp_value;
  1532. intel_sdvo_connector->right_margin = temp_value;
  1533. temp_value = intel_sdvo_connector->max_hscan -
  1534. intel_sdvo_connector->left_margin;
  1535. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1536. goto set_value;
  1537. } else if (intel_sdvo_connector->top == property) {
  1538. drm_connector_property_set_value(connector,
  1539. intel_sdvo_connector->bottom, val);
  1540. if (intel_sdvo_connector->top_margin == temp_value)
  1541. return 0;
  1542. intel_sdvo_connector->top_margin = temp_value;
  1543. intel_sdvo_connector->bottom_margin = temp_value;
  1544. temp_value = intel_sdvo_connector->max_vscan -
  1545. intel_sdvo_connector->top_margin;
  1546. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1547. goto set_value;
  1548. } else if (intel_sdvo_connector->bottom == property) {
  1549. drm_connector_property_set_value(connector,
  1550. intel_sdvo_connector->top, val);
  1551. if (intel_sdvo_connector->bottom_margin == temp_value)
  1552. return 0;
  1553. intel_sdvo_connector->top_margin = temp_value;
  1554. intel_sdvo_connector->bottom_margin = temp_value;
  1555. temp_value = intel_sdvo_connector->max_vscan -
  1556. intel_sdvo_connector->top_margin;
  1557. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1558. goto set_value;
  1559. }
  1560. CHECK_PROPERTY(hpos, HPOS)
  1561. CHECK_PROPERTY(vpos, VPOS)
  1562. CHECK_PROPERTY(saturation, SATURATION)
  1563. CHECK_PROPERTY(contrast, CONTRAST)
  1564. CHECK_PROPERTY(hue, HUE)
  1565. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1566. CHECK_PROPERTY(sharpness, SHARPNESS)
  1567. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1568. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1569. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1570. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1571. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1572. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1573. }
  1574. return -EINVAL; /* unknown property */
  1575. set_value:
  1576. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1577. return -EIO;
  1578. done:
  1579. if (intel_sdvo->base.base.crtc) {
  1580. struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
  1581. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1582. crtc->y, crtc->fb);
  1583. }
  1584. return 0;
  1585. #undef CHECK_PROPERTY
  1586. }
  1587. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1588. .dpms = intel_sdvo_dpms,
  1589. .mode_fixup = intel_sdvo_mode_fixup,
  1590. .prepare = intel_encoder_prepare,
  1591. .mode_set = intel_sdvo_mode_set,
  1592. .commit = intel_encoder_commit,
  1593. };
  1594. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1595. .dpms = drm_helper_connector_dpms,
  1596. .detect = intel_sdvo_detect,
  1597. .fill_modes = drm_helper_probe_single_connector_modes,
  1598. .set_property = intel_sdvo_set_property,
  1599. .destroy = intel_sdvo_destroy,
  1600. };
  1601. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1602. .get_modes = intel_sdvo_get_modes,
  1603. .mode_valid = intel_sdvo_mode_valid,
  1604. .best_encoder = intel_best_encoder,
  1605. };
  1606. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1607. {
  1608. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1609. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1610. drm_mode_destroy(encoder->dev,
  1611. intel_sdvo->sdvo_lvds_fixed_mode);
  1612. i2c_del_adapter(&intel_sdvo->ddc);
  1613. intel_encoder_destroy(encoder);
  1614. }
  1615. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1616. .destroy = intel_sdvo_enc_destroy,
  1617. };
  1618. static void
  1619. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1620. {
  1621. uint16_t mask = 0;
  1622. unsigned int num_bits;
  1623. /* Make a mask of outputs less than or equal to our own priority in the
  1624. * list.
  1625. */
  1626. switch (sdvo->controlled_output) {
  1627. case SDVO_OUTPUT_LVDS1:
  1628. mask |= SDVO_OUTPUT_LVDS1;
  1629. case SDVO_OUTPUT_LVDS0:
  1630. mask |= SDVO_OUTPUT_LVDS0;
  1631. case SDVO_OUTPUT_TMDS1:
  1632. mask |= SDVO_OUTPUT_TMDS1;
  1633. case SDVO_OUTPUT_TMDS0:
  1634. mask |= SDVO_OUTPUT_TMDS0;
  1635. case SDVO_OUTPUT_RGB1:
  1636. mask |= SDVO_OUTPUT_RGB1;
  1637. case SDVO_OUTPUT_RGB0:
  1638. mask |= SDVO_OUTPUT_RGB0;
  1639. break;
  1640. }
  1641. /* Count bits to find what number we are in the priority list. */
  1642. mask &= sdvo->caps.output_flags;
  1643. num_bits = hweight16(mask);
  1644. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1645. if (num_bits > 3)
  1646. num_bits = 3;
  1647. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1648. sdvo->ddc_bus = 1 << num_bits;
  1649. }
  1650. /**
  1651. * Choose the appropriate DDC bus for control bus switch command for this
  1652. * SDVO output based on the controlled output.
  1653. *
  1654. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1655. * outputs, then LVDS outputs.
  1656. */
  1657. static void
  1658. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1659. struct intel_sdvo *sdvo, u32 reg)
  1660. {
  1661. struct sdvo_device_mapping *mapping;
  1662. if (sdvo->is_sdvob)
  1663. mapping = &(dev_priv->sdvo_mappings[0]);
  1664. else
  1665. mapping = &(dev_priv->sdvo_mappings[1]);
  1666. if (mapping->initialized)
  1667. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1668. else
  1669. intel_sdvo_guess_ddc_bus(sdvo);
  1670. }
  1671. static void
  1672. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1673. struct intel_sdvo *sdvo, u32 reg)
  1674. {
  1675. struct sdvo_device_mapping *mapping;
  1676. u8 pin;
  1677. if (sdvo->is_sdvob)
  1678. mapping = &dev_priv->sdvo_mappings[0];
  1679. else
  1680. mapping = &dev_priv->sdvo_mappings[1];
  1681. pin = GMBUS_PORT_DPB;
  1682. if (mapping->initialized)
  1683. pin = mapping->i2c_pin;
  1684. if (intel_gmbus_is_port_valid(pin)) {
  1685. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1686. intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
  1687. intel_gmbus_force_bit(sdvo->i2c, true);
  1688. } else {
  1689. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
  1690. }
  1691. }
  1692. static bool
  1693. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1694. {
  1695. return intel_sdvo_check_supp_encode(intel_sdvo);
  1696. }
  1697. static u8
  1698. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1699. {
  1700. struct drm_i915_private *dev_priv = dev->dev_private;
  1701. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1702. if (sdvo->is_sdvob) {
  1703. my_mapping = &dev_priv->sdvo_mappings[0];
  1704. other_mapping = &dev_priv->sdvo_mappings[1];
  1705. } else {
  1706. my_mapping = &dev_priv->sdvo_mappings[1];
  1707. other_mapping = &dev_priv->sdvo_mappings[0];
  1708. }
  1709. /* If the BIOS described our SDVO device, take advantage of it. */
  1710. if (my_mapping->slave_addr)
  1711. return my_mapping->slave_addr;
  1712. /* If the BIOS only described a different SDVO device, use the
  1713. * address that it isn't using.
  1714. */
  1715. if (other_mapping->slave_addr) {
  1716. if (other_mapping->slave_addr == 0x70)
  1717. return 0x72;
  1718. else
  1719. return 0x70;
  1720. }
  1721. /* No SDVO device info is found for another DVO port,
  1722. * so use mapping assumption we had before BIOS parsing.
  1723. */
  1724. if (sdvo->is_sdvob)
  1725. return 0x70;
  1726. else
  1727. return 0x72;
  1728. }
  1729. static void
  1730. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1731. struct intel_sdvo *encoder)
  1732. {
  1733. drm_connector_init(encoder->base.base.dev,
  1734. &connector->base.base,
  1735. &intel_sdvo_connector_funcs,
  1736. connector->base.base.connector_type);
  1737. drm_connector_helper_add(&connector->base.base,
  1738. &intel_sdvo_connector_helper_funcs);
  1739. connector->base.base.interlace_allowed = 1;
  1740. connector->base.base.doublescan_allowed = 0;
  1741. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1742. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1743. drm_sysfs_connector_add(&connector->base.base);
  1744. }
  1745. static void
  1746. intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
  1747. {
  1748. struct drm_device *dev = connector->base.base.dev;
  1749. intel_attach_force_audio_property(&connector->base.base);
  1750. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
  1751. intel_attach_broadcast_rgb_property(&connector->base.base);
  1752. }
  1753. static bool
  1754. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1755. {
  1756. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1757. struct drm_connector *connector;
  1758. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1759. struct intel_connector *intel_connector;
  1760. struct intel_sdvo_connector *intel_sdvo_connector;
  1761. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1762. if (!intel_sdvo_connector)
  1763. return false;
  1764. if (device == 0) {
  1765. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1766. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1767. } else if (device == 1) {
  1768. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1769. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1770. }
  1771. intel_connector = &intel_sdvo_connector->base;
  1772. connector = &intel_connector->base;
  1773. if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
  1774. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1775. intel_sdvo->hotplug_active[0] |= 1 << device;
  1776. /* Some SDVO devices have one-shot hotplug interrupts.
  1777. * Ensure that they get re-enabled when an interrupt happens.
  1778. */
  1779. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1780. intel_sdvo_enable_hotplug(intel_encoder);
  1781. }
  1782. else
  1783. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1784. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1785. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1786. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1787. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1788. intel_sdvo->is_hdmi = true;
  1789. }
  1790. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1791. (1 << INTEL_ANALOG_CLONE_BIT));
  1792. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1793. if (intel_sdvo->is_hdmi)
  1794. intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
  1795. return true;
  1796. }
  1797. static bool
  1798. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1799. {
  1800. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1801. struct drm_connector *connector;
  1802. struct intel_connector *intel_connector;
  1803. struct intel_sdvo_connector *intel_sdvo_connector;
  1804. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1805. if (!intel_sdvo_connector)
  1806. return false;
  1807. intel_connector = &intel_sdvo_connector->base;
  1808. connector = &intel_connector->base;
  1809. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1810. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1811. intel_sdvo->controlled_output |= type;
  1812. intel_sdvo_connector->output_flag = type;
  1813. intel_sdvo->is_tv = true;
  1814. intel_sdvo->base.needs_tv_clock = true;
  1815. intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1816. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1817. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1818. goto err;
  1819. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1820. goto err;
  1821. return true;
  1822. err:
  1823. intel_sdvo_destroy(connector);
  1824. return false;
  1825. }
  1826. static bool
  1827. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1828. {
  1829. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1830. struct drm_connector *connector;
  1831. struct intel_connector *intel_connector;
  1832. struct intel_sdvo_connector *intel_sdvo_connector;
  1833. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1834. if (!intel_sdvo_connector)
  1835. return false;
  1836. intel_connector = &intel_sdvo_connector->base;
  1837. connector = &intel_connector->base;
  1838. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1839. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1840. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1841. if (device == 0) {
  1842. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1843. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1844. } else if (device == 1) {
  1845. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1846. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1847. }
  1848. intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1849. (1 << INTEL_ANALOG_CLONE_BIT));
  1850. intel_sdvo_connector_init(intel_sdvo_connector,
  1851. intel_sdvo);
  1852. return true;
  1853. }
  1854. static bool
  1855. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  1856. {
  1857. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1858. struct drm_connector *connector;
  1859. struct intel_connector *intel_connector;
  1860. struct intel_sdvo_connector *intel_sdvo_connector;
  1861. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1862. if (!intel_sdvo_connector)
  1863. return false;
  1864. intel_connector = &intel_sdvo_connector->base;
  1865. connector = &intel_connector->base;
  1866. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1867. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1868. if (device == 0) {
  1869. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1870. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1871. } else if (device == 1) {
  1872. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1873. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1874. }
  1875. intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1876. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1877. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1878. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1879. goto err;
  1880. return true;
  1881. err:
  1882. intel_sdvo_destroy(connector);
  1883. return false;
  1884. }
  1885. static bool
  1886. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  1887. {
  1888. intel_sdvo->is_tv = false;
  1889. intel_sdvo->base.needs_tv_clock = false;
  1890. intel_sdvo->is_lvds = false;
  1891. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1892. if (flags & SDVO_OUTPUT_TMDS0)
  1893. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  1894. return false;
  1895. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1896. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  1897. return false;
  1898. /* TV has no XXX1 function block */
  1899. if (flags & SDVO_OUTPUT_SVID0)
  1900. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  1901. return false;
  1902. if (flags & SDVO_OUTPUT_CVBS0)
  1903. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  1904. return false;
  1905. if (flags & SDVO_OUTPUT_YPRPB0)
  1906. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  1907. return false;
  1908. if (flags & SDVO_OUTPUT_RGB0)
  1909. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  1910. return false;
  1911. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1912. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  1913. return false;
  1914. if (flags & SDVO_OUTPUT_LVDS0)
  1915. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  1916. return false;
  1917. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1918. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  1919. return false;
  1920. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1921. unsigned char bytes[2];
  1922. intel_sdvo->controlled_output = 0;
  1923. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  1924. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1925. SDVO_NAME(intel_sdvo),
  1926. bytes[0], bytes[1]);
  1927. return false;
  1928. }
  1929. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1930. return true;
  1931. }
  1932. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  1933. struct intel_sdvo_connector *intel_sdvo_connector,
  1934. int type)
  1935. {
  1936. struct drm_device *dev = intel_sdvo->base.base.dev;
  1937. struct intel_sdvo_tv_format format;
  1938. uint32_t format_map, i;
  1939. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  1940. return false;
  1941. BUILD_BUG_ON(sizeof(format) != 6);
  1942. if (!intel_sdvo_get_value(intel_sdvo,
  1943. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1944. &format, sizeof(format)))
  1945. return false;
  1946. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1947. if (format_map == 0)
  1948. return false;
  1949. intel_sdvo_connector->format_supported_num = 0;
  1950. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1951. if (format_map & (1 << i))
  1952. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  1953. intel_sdvo_connector->tv_format =
  1954. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1955. "mode", intel_sdvo_connector->format_supported_num);
  1956. if (!intel_sdvo_connector->tv_format)
  1957. return false;
  1958. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  1959. drm_property_add_enum(
  1960. intel_sdvo_connector->tv_format, i,
  1961. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  1962. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  1963. drm_connector_attach_property(&intel_sdvo_connector->base.base,
  1964. intel_sdvo_connector->tv_format, 0);
  1965. return true;
  1966. }
  1967. #define ENHANCEMENT(name, NAME) do { \
  1968. if (enhancements.name) { \
  1969. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1970. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1971. return false; \
  1972. intel_sdvo_connector->max_##name = data_value[0]; \
  1973. intel_sdvo_connector->cur_##name = response; \
  1974. intel_sdvo_connector->name = \
  1975. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1976. if (!intel_sdvo_connector->name) return false; \
  1977. drm_connector_attach_property(connector, \
  1978. intel_sdvo_connector->name, \
  1979. intel_sdvo_connector->cur_##name); \
  1980. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1981. data_value[0], data_value[1], response); \
  1982. } \
  1983. } while (0)
  1984. static bool
  1985. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  1986. struct intel_sdvo_connector *intel_sdvo_connector,
  1987. struct intel_sdvo_enhancements_reply enhancements)
  1988. {
  1989. struct drm_device *dev = intel_sdvo->base.base.dev;
  1990. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  1991. uint16_t response, data_value[2];
  1992. /* when horizontal overscan is supported, Add the left/right property */
  1993. if (enhancements.overscan_h) {
  1994. if (!intel_sdvo_get_value(intel_sdvo,
  1995. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1996. &data_value, 4))
  1997. return false;
  1998. if (!intel_sdvo_get_value(intel_sdvo,
  1999. SDVO_CMD_GET_OVERSCAN_H,
  2000. &response, 2))
  2001. return false;
  2002. intel_sdvo_connector->max_hscan = data_value[0];
  2003. intel_sdvo_connector->left_margin = data_value[0] - response;
  2004. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2005. intel_sdvo_connector->left =
  2006. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2007. if (!intel_sdvo_connector->left)
  2008. return false;
  2009. drm_connector_attach_property(connector,
  2010. intel_sdvo_connector->left,
  2011. intel_sdvo_connector->left_margin);
  2012. intel_sdvo_connector->right =
  2013. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2014. if (!intel_sdvo_connector->right)
  2015. return false;
  2016. drm_connector_attach_property(connector,
  2017. intel_sdvo_connector->right,
  2018. intel_sdvo_connector->right_margin);
  2019. DRM_DEBUG_KMS("h_overscan: max %d, "
  2020. "default %d, current %d\n",
  2021. data_value[0], data_value[1], response);
  2022. }
  2023. if (enhancements.overscan_v) {
  2024. if (!intel_sdvo_get_value(intel_sdvo,
  2025. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2026. &data_value, 4))
  2027. return false;
  2028. if (!intel_sdvo_get_value(intel_sdvo,
  2029. SDVO_CMD_GET_OVERSCAN_V,
  2030. &response, 2))
  2031. return false;
  2032. intel_sdvo_connector->max_vscan = data_value[0];
  2033. intel_sdvo_connector->top_margin = data_value[0] - response;
  2034. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2035. intel_sdvo_connector->top =
  2036. drm_property_create_range(dev, 0,
  2037. "top_margin", 0, data_value[0]);
  2038. if (!intel_sdvo_connector->top)
  2039. return false;
  2040. drm_connector_attach_property(connector,
  2041. intel_sdvo_connector->top,
  2042. intel_sdvo_connector->top_margin);
  2043. intel_sdvo_connector->bottom =
  2044. drm_property_create_range(dev, 0,
  2045. "bottom_margin", 0, data_value[0]);
  2046. if (!intel_sdvo_connector->bottom)
  2047. return false;
  2048. drm_connector_attach_property(connector,
  2049. intel_sdvo_connector->bottom,
  2050. intel_sdvo_connector->bottom_margin);
  2051. DRM_DEBUG_KMS("v_overscan: max %d, "
  2052. "default %d, current %d\n",
  2053. data_value[0], data_value[1], response);
  2054. }
  2055. ENHANCEMENT(hpos, HPOS);
  2056. ENHANCEMENT(vpos, VPOS);
  2057. ENHANCEMENT(saturation, SATURATION);
  2058. ENHANCEMENT(contrast, CONTRAST);
  2059. ENHANCEMENT(hue, HUE);
  2060. ENHANCEMENT(sharpness, SHARPNESS);
  2061. ENHANCEMENT(brightness, BRIGHTNESS);
  2062. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2063. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2064. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2065. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2066. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2067. if (enhancements.dot_crawl) {
  2068. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2069. return false;
  2070. intel_sdvo_connector->max_dot_crawl = 1;
  2071. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2072. intel_sdvo_connector->dot_crawl =
  2073. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2074. if (!intel_sdvo_connector->dot_crawl)
  2075. return false;
  2076. drm_connector_attach_property(connector,
  2077. intel_sdvo_connector->dot_crawl,
  2078. intel_sdvo_connector->cur_dot_crawl);
  2079. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2080. }
  2081. return true;
  2082. }
  2083. static bool
  2084. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2085. struct intel_sdvo_connector *intel_sdvo_connector,
  2086. struct intel_sdvo_enhancements_reply enhancements)
  2087. {
  2088. struct drm_device *dev = intel_sdvo->base.base.dev;
  2089. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2090. uint16_t response, data_value[2];
  2091. ENHANCEMENT(brightness, BRIGHTNESS);
  2092. return true;
  2093. }
  2094. #undef ENHANCEMENT
  2095. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2096. struct intel_sdvo_connector *intel_sdvo_connector)
  2097. {
  2098. union {
  2099. struct intel_sdvo_enhancements_reply reply;
  2100. uint16_t response;
  2101. } enhancements;
  2102. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2103. enhancements.response = 0;
  2104. intel_sdvo_get_value(intel_sdvo,
  2105. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2106. &enhancements, sizeof(enhancements));
  2107. if (enhancements.response == 0) {
  2108. DRM_DEBUG_KMS("No enhancement is supported\n");
  2109. return true;
  2110. }
  2111. if (IS_TV(intel_sdvo_connector))
  2112. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2113. else if (IS_LVDS(intel_sdvo_connector))
  2114. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2115. else
  2116. return true;
  2117. }
  2118. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2119. struct i2c_msg *msgs,
  2120. int num)
  2121. {
  2122. struct intel_sdvo *sdvo = adapter->algo_data;
  2123. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2124. return -EIO;
  2125. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2126. }
  2127. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2128. {
  2129. struct intel_sdvo *sdvo = adapter->algo_data;
  2130. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2131. }
  2132. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2133. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2134. .functionality = intel_sdvo_ddc_proxy_func
  2135. };
  2136. static bool
  2137. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2138. struct drm_device *dev)
  2139. {
  2140. sdvo->ddc.owner = THIS_MODULE;
  2141. sdvo->ddc.class = I2C_CLASS_DDC;
  2142. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2143. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2144. sdvo->ddc.algo_data = sdvo;
  2145. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2146. return i2c_add_adapter(&sdvo->ddc) == 0;
  2147. }
  2148. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2149. {
  2150. struct drm_i915_private *dev_priv = dev->dev_private;
  2151. struct intel_encoder *intel_encoder;
  2152. struct intel_sdvo *intel_sdvo;
  2153. u32 hotplug_mask;
  2154. int i;
  2155. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2156. if (!intel_sdvo)
  2157. return false;
  2158. intel_sdvo->sdvo_reg = sdvo_reg;
  2159. intel_sdvo->is_sdvob = is_sdvob;
  2160. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2161. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2162. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
  2163. kfree(intel_sdvo);
  2164. return false;
  2165. }
  2166. /* encoder type will be decided later */
  2167. intel_encoder = &intel_sdvo->base;
  2168. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2169. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2170. /* Read the regs to test if we can talk to the device */
  2171. for (i = 0; i < 0x40; i++) {
  2172. u8 byte;
  2173. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2174. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2175. SDVO_NAME(intel_sdvo));
  2176. goto err;
  2177. }
  2178. }
  2179. hotplug_mask = 0;
  2180. if (IS_G4X(dev)) {
  2181. hotplug_mask = intel_sdvo->is_sdvob ?
  2182. SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
  2183. } else if (IS_GEN4(dev)) {
  2184. hotplug_mask = intel_sdvo->is_sdvob ?
  2185. SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
  2186. } else {
  2187. hotplug_mask = intel_sdvo->is_sdvob ?
  2188. SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
  2189. }
  2190. dev_priv->hotplug_supported_mask |= hotplug_mask;
  2191. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2192. /* In default case sdvo lvds is false */
  2193. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2194. goto err;
  2195. /* Set up hotplug command - note paranoia about contents of reply.
  2196. * We assume that the hardware is in a sane state, and only touch
  2197. * the bits we think we understand.
  2198. */
  2199. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
  2200. &intel_sdvo->hotplug_active, 2);
  2201. intel_sdvo->hotplug_active[0] &= ~0x3;
  2202. if (intel_sdvo_output_setup(intel_sdvo,
  2203. intel_sdvo->caps.output_flags) != true) {
  2204. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2205. SDVO_NAME(intel_sdvo));
  2206. goto err;
  2207. }
  2208. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2209. /* Set the input timing to the screen. Assume always input 0. */
  2210. if (!intel_sdvo_set_target_input(intel_sdvo))
  2211. goto err;
  2212. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2213. &intel_sdvo->pixel_clock_min,
  2214. &intel_sdvo->pixel_clock_max))
  2215. goto err;
  2216. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2217. "clock range %dMHz - %dMHz, "
  2218. "input 1: %c, input 2: %c, "
  2219. "output 1: %c, output 2: %c\n",
  2220. SDVO_NAME(intel_sdvo),
  2221. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2222. intel_sdvo->caps.device_rev_id,
  2223. intel_sdvo->pixel_clock_min / 1000,
  2224. intel_sdvo->pixel_clock_max / 1000,
  2225. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2226. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2227. /* check currently supported outputs */
  2228. intel_sdvo->caps.output_flags &
  2229. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2230. intel_sdvo->caps.output_flags &
  2231. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2232. return true;
  2233. err:
  2234. drm_encoder_cleanup(&intel_encoder->base);
  2235. i2c_del_adapter(&intel_sdvo->ddc);
  2236. kfree(intel_sdvo);
  2237. return false;
  2238. }