i915_gem_context.c 16 KB

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  1. /*
  2. * Copyright © 2011-2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Ben Widawsky <ben@bwidawsk.net>
  25. *
  26. */
  27. /*
  28. * This file implements HW context support. On gen5+ a HW context consists of an
  29. * opaque GPU object which is referenced at times of context saves and restores.
  30. * With RC6 enabled, the context is also referenced as the GPU enters and exists
  31. * from RC6 (GPU has it's own internal power context, except on gen5). Though
  32. * something like a context does exist for the media ring, the code only
  33. * supports contexts for the render ring.
  34. *
  35. * In software, there is a distinction between contexts created by the user,
  36. * and the default HW context. The default HW context is used by GPU clients
  37. * that do not request setup of their own hardware context. The default
  38. * context's state is never restored to help prevent programming errors. This
  39. * would happen if a client ran and piggy-backed off another clients GPU state.
  40. * The default context only exists to give the GPU some offset to load as the
  41. * current to invoke a save of the context we actually care about. In fact, the
  42. * code could likely be constructed, albeit in a more complicated fashion, to
  43. * never use the default context, though that limits the driver's ability to
  44. * swap out, and/or destroy other contexts.
  45. *
  46. * All other contexts are created as a request by the GPU client. These contexts
  47. * store GPU state, and thus allow GPU clients to not re-emit state (and
  48. * potentially query certain state) at any time. The kernel driver makes
  49. * certain that the appropriate commands are inserted.
  50. *
  51. * The context life cycle is semi-complicated in that context BOs may live
  52. * longer than the context itself because of the way the hardware, and object
  53. * tracking works. Below is a very crude representation of the state machine
  54. * describing the context life.
  55. * refcount pincount active
  56. * S0: initial state 0 0 0
  57. * S1: context created 1 0 0
  58. * S2: context is currently running 2 1 X
  59. * S3: GPU referenced, but not current 2 0 1
  60. * S4: context is current, but destroyed 1 1 0
  61. * S5: like S3, but destroyed 1 0 1
  62. *
  63. * The most common (but not all) transitions:
  64. * S0->S1: client creates a context
  65. * S1->S2: client submits execbuf with context
  66. * S2->S3: other clients submits execbuf with context
  67. * S3->S1: context object was retired
  68. * S3->S2: clients submits another execbuf
  69. * S2->S4: context destroy called with current context
  70. * S3->S5->S0: destroy path
  71. * S4->S5->S0: destroy path on current context
  72. *
  73. * There are two confusing terms used above:
  74. * The "current context" means the context which is currently running on the
  75. * GPU. The GPU has loaded it's state already and has stored away the gtt
  76. * offset of the BO. The GPU is not actively referencing the data at this
  77. * offset, but it will on the next context switch. The only way to avoid this
  78. * is to do a GPU reset.
  79. *
  80. * An "active context' is one which was previously the "current context" and is
  81. * on the active list waiting for the next context switch to occur. Until this
  82. * happens, the object must remain at the same gtt offset. It is therefore
  83. * possible to destroy a context, but it is still active.
  84. *
  85. */
  86. #include "drmP.h"
  87. #include "i915_drm.h"
  88. #include "i915_drv.h"
  89. /* This is a HW constraint. The value below is the largest known requirement
  90. * I've seen in a spec to date, and that was a workaround for a non-shipping
  91. * part. It should be safe to decrease this, but it's more future proof as is.
  92. */
  93. #define CONTEXT_ALIGN (64<<10)
  94. static struct i915_hw_context *
  95. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
  96. static int do_switch(struct drm_i915_gem_object *from_obj,
  97. struct i915_hw_context *to, u32 seqno);
  98. static int get_context_size(struct drm_device *dev)
  99. {
  100. struct drm_i915_private *dev_priv = dev->dev_private;
  101. int ret;
  102. u32 reg;
  103. switch (INTEL_INFO(dev)->gen) {
  104. case 6:
  105. reg = I915_READ(CXT_SIZE);
  106. ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
  107. break;
  108. case 7:
  109. reg = I915_READ(GEN7_CXT_SIZE);
  110. ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
  111. break;
  112. default:
  113. BUG();
  114. }
  115. return ret;
  116. }
  117. static void do_destroy(struct i915_hw_context *ctx)
  118. {
  119. struct drm_device *dev = ctx->obj->base.dev;
  120. struct drm_i915_private *dev_priv = dev->dev_private;
  121. if (ctx->file_priv)
  122. idr_remove(&ctx->file_priv->context_idr, ctx->id);
  123. else
  124. BUG_ON(ctx != dev_priv->ring[RCS].default_context);
  125. drm_gem_object_unreference(&ctx->obj->base);
  126. kfree(ctx);
  127. }
  128. static struct i915_hw_context *
  129. create_hw_context(struct drm_device *dev,
  130. struct drm_i915_file_private *file_priv)
  131. {
  132. struct drm_i915_private *dev_priv = dev->dev_private;
  133. struct i915_hw_context *ctx;
  134. int ret, id;
  135. ctx = kzalloc(sizeof(struct drm_i915_file_private), GFP_KERNEL);
  136. if (ctx == NULL)
  137. return ERR_PTR(-ENOMEM);
  138. ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
  139. if (ctx->obj == NULL) {
  140. kfree(ctx);
  141. DRM_DEBUG_DRIVER("Context object allocated failed\n");
  142. return ERR_PTR(-ENOMEM);
  143. }
  144. /* The ring associated with the context object is handled by the normal
  145. * object tracking code. We give an initial ring value simple to pass an
  146. * assertion in the context switch code.
  147. */
  148. ctx->ring = &dev_priv->ring[RCS];
  149. /* Default context will never have a file_priv */
  150. if (file_priv == NULL)
  151. return ctx;
  152. ctx->file_priv = file_priv;
  153. again:
  154. if (idr_pre_get(&file_priv->context_idr, GFP_KERNEL) == 0) {
  155. ret = -ENOMEM;
  156. DRM_DEBUG_DRIVER("idr allocation failed\n");
  157. goto err_out;
  158. }
  159. ret = idr_get_new_above(&file_priv->context_idr, ctx,
  160. DEFAULT_CONTEXT_ID + 1, &id);
  161. if (ret == 0)
  162. ctx->id = id;
  163. if (ret == -EAGAIN)
  164. goto again;
  165. else if (ret)
  166. goto err_out;
  167. return ctx;
  168. err_out:
  169. do_destroy(ctx);
  170. return ERR_PTR(ret);
  171. }
  172. static inline bool is_default_context(struct i915_hw_context *ctx)
  173. {
  174. return (ctx == ctx->ring->default_context);
  175. }
  176. /**
  177. * The default context needs to exist per ring that uses contexts. It stores the
  178. * context state of the GPU for applications that don't utilize HW contexts, as
  179. * well as an idle case.
  180. */
  181. static int create_default_context(struct drm_i915_private *dev_priv)
  182. {
  183. struct i915_hw_context *ctx;
  184. int ret;
  185. BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  186. ctx = create_hw_context(dev_priv->dev, NULL);
  187. if (IS_ERR(ctx))
  188. return PTR_ERR(ctx);
  189. /* We may need to do things with the shrinker which require us to
  190. * immediately switch back to the default context. This can cause a
  191. * problem as pinning the default context also requires GTT space which
  192. * may not be available. To avoid this we always pin the
  193. * default context.
  194. */
  195. dev_priv->ring[RCS].default_context = ctx;
  196. ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false);
  197. if (ret) {
  198. do_destroy(ctx);
  199. return ret;
  200. }
  201. ret = do_switch(NULL, ctx, 0);
  202. if (ret) {
  203. i915_gem_object_unpin(ctx->obj);
  204. do_destroy(ctx);
  205. } else {
  206. DRM_DEBUG_DRIVER("Default HW context loaded\n");
  207. }
  208. return ret;
  209. }
  210. void i915_gem_context_init(struct drm_device *dev)
  211. {
  212. struct drm_i915_private *dev_priv = dev->dev_private;
  213. uint32_t ctx_size;
  214. if (!HAS_HW_CONTEXTS(dev)) {
  215. dev_priv->hw_contexts_disabled = true;
  216. return;
  217. }
  218. /* If called from reset, or thaw... we've been here already */
  219. if (dev_priv->hw_contexts_disabled ||
  220. dev_priv->ring[RCS].default_context)
  221. return;
  222. ctx_size = get_context_size(dev);
  223. dev_priv->hw_context_size = get_context_size(dev);
  224. dev_priv->hw_context_size = round_up(dev_priv->hw_context_size, 4096);
  225. if (ctx_size <= 0 || ctx_size > (1<<20)) {
  226. dev_priv->hw_contexts_disabled = true;
  227. return;
  228. }
  229. if (create_default_context(dev_priv)) {
  230. dev_priv->hw_contexts_disabled = true;
  231. return;
  232. }
  233. DRM_DEBUG_DRIVER("HW context support initialized\n");
  234. }
  235. void i915_gem_context_fini(struct drm_device *dev)
  236. {
  237. struct drm_i915_private *dev_priv = dev->dev_private;
  238. if (dev_priv->hw_contexts_disabled)
  239. return;
  240. /* The only known way to stop the gpu from accessing the hw context is
  241. * to reset it. Do this as the very last operation to avoid confusing
  242. * other code, leading to spurious errors. */
  243. intel_gpu_reset(dev);
  244. i915_gem_object_unpin(dev_priv->ring[RCS].default_context->obj);
  245. do_destroy(dev_priv->ring[RCS].default_context);
  246. }
  247. static int context_idr_cleanup(int id, void *p, void *data)
  248. {
  249. struct i915_hw_context *ctx = p;
  250. BUG_ON(id == DEFAULT_CONTEXT_ID);
  251. do_destroy(ctx);
  252. return 0;
  253. }
  254. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
  255. {
  256. struct drm_i915_file_private *file_priv = file->driver_priv;
  257. mutex_lock(&dev->struct_mutex);
  258. idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
  259. idr_destroy(&file_priv->context_idr);
  260. mutex_unlock(&dev->struct_mutex);
  261. }
  262. static struct i915_hw_context *
  263. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
  264. {
  265. return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
  266. }
  267. static inline int
  268. mi_set_context(struct intel_ring_buffer *ring,
  269. struct i915_hw_context *new_context,
  270. u32 hw_flags)
  271. {
  272. int ret;
  273. /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
  274. * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
  275. * explicitly, so we rely on the value at ring init, stored in
  276. * itlb_before_ctx_switch.
  277. */
  278. if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
  279. ret = ring->flush(ring, 0, 0);
  280. if (ret)
  281. return ret;
  282. }
  283. ret = intel_ring_begin(ring, 6);
  284. if (ret)
  285. return ret;
  286. if (IS_GEN7(ring->dev))
  287. intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
  288. else
  289. intel_ring_emit(ring, MI_NOOP);
  290. intel_ring_emit(ring, MI_NOOP);
  291. intel_ring_emit(ring, MI_SET_CONTEXT);
  292. intel_ring_emit(ring, new_context->obj->gtt_offset |
  293. MI_MM_SPACE_GTT |
  294. MI_SAVE_EXT_STATE_EN |
  295. MI_RESTORE_EXT_STATE_EN |
  296. hw_flags);
  297. /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
  298. intel_ring_emit(ring, MI_NOOP);
  299. if (IS_GEN7(ring->dev))
  300. intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
  301. else
  302. intel_ring_emit(ring, MI_NOOP);
  303. intel_ring_advance(ring);
  304. return ret;
  305. }
  306. static int do_switch(struct drm_i915_gem_object *from_obj,
  307. struct i915_hw_context *to,
  308. u32 seqno)
  309. {
  310. struct intel_ring_buffer *ring = NULL;
  311. u32 hw_flags = 0;
  312. int ret;
  313. BUG_ON(to == NULL);
  314. BUG_ON(from_obj != NULL && from_obj->pin_count == 0);
  315. ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false);
  316. if (ret)
  317. return ret;
  318. /* Clear this page out of any CPU caches for coherent swap-in/out. Note
  319. * that thanks to write = false in this call and us not setting any gpu
  320. * write domains when putting a context object onto the active list
  321. * (when switching away from it), this won't block.
  322. * XXX: We need a real interface to do this instead of trickery. */
  323. ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
  324. if (ret) {
  325. i915_gem_object_unpin(to->obj);
  326. return ret;
  327. }
  328. if (!to->obj->has_global_gtt_mapping)
  329. i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
  330. if (!to->is_initialized || is_default_context(to))
  331. hw_flags |= MI_RESTORE_INHIBIT;
  332. else if (WARN_ON_ONCE(from_obj == to->obj)) /* not yet expected */
  333. hw_flags |= MI_FORCE_RESTORE;
  334. ring = to->ring;
  335. ret = mi_set_context(ring, to, hw_flags);
  336. if (ret) {
  337. i915_gem_object_unpin(to->obj);
  338. return ret;
  339. }
  340. /* The backing object for the context is done after switching to the
  341. * *next* context. Therefore we cannot retire the previous context until
  342. * the next context has already started running. In fact, the below code
  343. * is a bit suboptimal because the retiring can occur simply after the
  344. * MI_SET_CONTEXT instead of when the next seqno has completed.
  345. */
  346. if (from_obj != NULL) {
  347. from_obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
  348. i915_gem_object_move_to_active(from_obj, ring, seqno);
  349. /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
  350. * whole damn pipeline, we don't need to explicitly mark the
  351. * object dirty. The only exception is that the context must be
  352. * correct in case the object gets swapped out. Ideally we'd be
  353. * able to defer doing this until we know the object would be
  354. * swapped, but there is no way to do that yet.
  355. */
  356. from_obj->dirty = 1;
  357. BUG_ON(from_obj->ring != to->ring);
  358. i915_gem_object_unpin(from_obj);
  359. drm_gem_object_unreference(&from_obj->base);
  360. }
  361. drm_gem_object_reference(&to->obj->base);
  362. ring->last_context_obj = to->obj;
  363. to->is_initialized = true;
  364. return 0;
  365. }
  366. /**
  367. * i915_switch_context() - perform a GPU context switch.
  368. * @ring: ring for which we'll execute the context switch
  369. * @file_priv: file_priv associated with the context, may be NULL
  370. * @id: context id number
  371. * @seqno: sequence number by which the new context will be switched to
  372. * @flags:
  373. *
  374. * The context life cycle is simple. The context refcount is incremented and
  375. * decremented by 1 and create and destroy. If the context is in use by the GPU,
  376. * it will have a refoucnt > 1. This allows us to destroy the context abstract
  377. * object while letting the normal object tracking destroy the backing BO.
  378. */
  379. int i915_switch_context(struct intel_ring_buffer *ring,
  380. struct drm_file *file,
  381. int to_id)
  382. {
  383. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  384. struct drm_i915_file_private *file_priv = NULL;
  385. struct i915_hw_context *to;
  386. struct drm_i915_gem_object *from_obj = ring->last_context_obj;
  387. int ret;
  388. if (dev_priv->hw_contexts_disabled)
  389. return 0;
  390. if (ring != &dev_priv->ring[RCS])
  391. return 0;
  392. if (file)
  393. file_priv = file->driver_priv;
  394. if (to_id == DEFAULT_CONTEXT_ID) {
  395. to = ring->default_context;
  396. } else {
  397. to = i915_gem_context_get(file_priv, to_id);
  398. if (to == NULL)
  399. return -ENOENT;
  400. }
  401. if (from_obj == to->obj)
  402. return 0;
  403. return do_switch(from_obj, to, i915_gem_next_request_seqno(to->ring));
  404. }
  405. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  406. struct drm_file *file)
  407. {
  408. struct drm_i915_private *dev_priv = dev->dev_private;
  409. struct drm_i915_gem_context_create *args = data;
  410. struct drm_i915_file_private *file_priv = file->driver_priv;
  411. struct i915_hw_context *ctx;
  412. int ret;
  413. if (!(dev->driver->driver_features & DRIVER_GEM))
  414. return -ENODEV;
  415. if (dev_priv->hw_contexts_disabled)
  416. return -ENODEV;
  417. ret = i915_mutex_lock_interruptible(dev);
  418. if (ret)
  419. return ret;
  420. ctx = create_hw_context(dev, file_priv);
  421. mutex_unlock(&dev->struct_mutex);
  422. if (IS_ERR(ctx))
  423. return PTR_ERR(ctx);
  424. args->ctx_id = ctx->id;
  425. DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
  426. return 0;
  427. }
  428. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  429. struct drm_file *file)
  430. {
  431. struct drm_i915_gem_context_destroy *args = data;
  432. struct drm_i915_file_private *file_priv = file->driver_priv;
  433. struct i915_hw_context *ctx;
  434. int ret;
  435. if (!(dev->driver->driver_features & DRIVER_GEM))
  436. return -ENODEV;
  437. ret = i915_mutex_lock_interruptible(dev);
  438. if (ret)
  439. return ret;
  440. ctx = i915_gem_context_get(file_priv, args->ctx_id);
  441. if (!ctx) {
  442. mutex_unlock(&dev->struct_mutex);
  443. return -ENOENT;
  444. }
  445. do_destroy(ctx);
  446. mutex_unlock(&dev->struct_mutex);
  447. DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
  448. return 0;
  449. }