edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com>
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = strict_strtol(val, 0, &l);
  52. if (ret == -EINVAL || ((int)l != l))
  53. return -EINVAL;
  54. *((int *)kp->arg) = l;
  55. /* notify edac_mc engine to reset the poll period */
  56. edac_mc_reset_delay_period(l);
  57. return 0;
  58. }
  59. /* Parameter declarations for above */
  60. module_param(edac_mc_panic_on_ue, int, 0644);
  61. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  62. module_param(edac_mc_log_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_log_ue,
  64. "Log uncorrectable error to console: 0=off 1=on");
  65. module_param(edac_mc_log_ce, int, 0644);
  66. MODULE_PARM_DESC(edac_mc_log_ce,
  67. "Log correctable error to console: 0=off 1=on");
  68. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  69. &edac_mc_poll_msec, 0644);
  70. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  71. static struct device *mci_pdev;
  72. /*
  73. * various constants for Memory Controllers
  74. */
  75. static const char *mem_types[] = {
  76. [MEM_EMPTY] = "Empty",
  77. [MEM_RESERVED] = "Reserved",
  78. [MEM_UNKNOWN] = "Unknown",
  79. [MEM_FPM] = "FPM",
  80. [MEM_EDO] = "EDO",
  81. [MEM_BEDO] = "BEDO",
  82. [MEM_SDR] = "Unbuffered-SDR",
  83. [MEM_RDR] = "Registered-SDR",
  84. [MEM_DDR] = "Unbuffered-DDR",
  85. [MEM_RDDR] = "Registered-DDR",
  86. [MEM_RMBS] = "RMBS",
  87. [MEM_DDR2] = "Unbuffered-DDR2",
  88. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  89. [MEM_RDDR2] = "Registered-DDR2",
  90. [MEM_XDR] = "XDR",
  91. [MEM_DDR3] = "Unbuffered-DDR3",
  92. [MEM_RDDR3] = "Registered-DDR3"
  93. };
  94. static const char *dev_types[] = {
  95. [DEV_UNKNOWN] = "Unknown",
  96. [DEV_X1] = "x1",
  97. [DEV_X2] = "x2",
  98. [DEV_X4] = "x4",
  99. [DEV_X8] = "x8",
  100. [DEV_X16] = "x16",
  101. [DEV_X32] = "x32",
  102. [DEV_X64] = "x64"
  103. };
  104. static const char *edac_caps[] = {
  105. [EDAC_UNKNOWN] = "Unknown",
  106. [EDAC_NONE] = "None",
  107. [EDAC_RESERVED] = "Reserved",
  108. [EDAC_PARITY] = "PARITY",
  109. [EDAC_EC] = "EC",
  110. [EDAC_SECDED] = "SECDED",
  111. [EDAC_S2ECD2ED] = "S2ECD2ED",
  112. [EDAC_S4ECD4ED] = "S4ECD4ED",
  113. [EDAC_S8ECD8ED] = "S8ECD8ED",
  114. [EDAC_S16ECD16ED] = "S16ECD16ED"
  115. };
  116. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  117. /*
  118. * EDAC sysfs CSROW data structures and methods
  119. */
  120. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  121. /*
  122. * We need it to avoid namespace conflicts between the legacy API
  123. * and the per-dimm/per-rank one
  124. */
  125. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  126. struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  127. struct dev_ch_attribute {
  128. struct device_attribute attr;
  129. int channel;
  130. };
  131. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  132. struct dev_ch_attribute dev_attr_legacy_##_name = \
  133. { __ATTR(_name, _mode, _show, _store), (_var) }
  134. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  135. /* Set of more default csrow<id> attribute show/store functions */
  136. static ssize_t csrow_ue_count_show(struct device *dev,
  137. struct device_attribute *mattr, char *data)
  138. {
  139. struct csrow_info *csrow = to_csrow(dev);
  140. return sprintf(data, "%u\n", csrow->ue_count);
  141. }
  142. static ssize_t csrow_ce_count_show(struct device *dev,
  143. struct device_attribute *mattr, char *data)
  144. {
  145. struct csrow_info *csrow = to_csrow(dev);
  146. return sprintf(data, "%u\n", csrow->ce_count);
  147. }
  148. static ssize_t csrow_size_show(struct device *dev,
  149. struct device_attribute *mattr, char *data)
  150. {
  151. struct csrow_info *csrow = to_csrow(dev);
  152. int i;
  153. u32 nr_pages = 0;
  154. for (i = 0; i < csrow->nr_channels; i++)
  155. nr_pages += csrow->channels[i]->dimm->nr_pages;
  156. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  157. }
  158. static ssize_t csrow_mem_type_show(struct device *dev,
  159. struct device_attribute *mattr, char *data)
  160. {
  161. struct csrow_info *csrow = to_csrow(dev);
  162. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  163. }
  164. static ssize_t csrow_dev_type_show(struct device *dev,
  165. struct device_attribute *mattr, char *data)
  166. {
  167. struct csrow_info *csrow = to_csrow(dev);
  168. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  169. }
  170. static ssize_t csrow_edac_mode_show(struct device *dev,
  171. struct device_attribute *mattr,
  172. char *data)
  173. {
  174. struct csrow_info *csrow = to_csrow(dev);
  175. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  176. }
  177. /* show/store functions for DIMM Label attributes */
  178. static ssize_t channel_dimm_label_show(struct device *dev,
  179. struct device_attribute *mattr,
  180. char *data)
  181. {
  182. struct csrow_info *csrow = to_csrow(dev);
  183. unsigned chan = to_channel(mattr);
  184. struct rank_info *rank = csrow->channels[chan];
  185. /* if field has not been initialized, there is nothing to send */
  186. if (!rank->dimm->label[0])
  187. return 0;
  188. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  189. rank->dimm->label);
  190. }
  191. static ssize_t channel_dimm_label_store(struct device *dev,
  192. struct device_attribute *mattr,
  193. const char *data, size_t count)
  194. {
  195. struct csrow_info *csrow = to_csrow(dev);
  196. unsigned chan = to_channel(mattr);
  197. struct rank_info *rank = csrow->channels[chan];
  198. ssize_t max_size = 0;
  199. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  200. strncpy(rank->dimm->label, data, max_size);
  201. rank->dimm->label[max_size] = '\0';
  202. return max_size;
  203. }
  204. /* show function for dynamic chX_ce_count attribute */
  205. static ssize_t channel_ce_count_show(struct device *dev,
  206. struct device_attribute *mattr, char *data)
  207. {
  208. struct csrow_info *csrow = to_csrow(dev);
  209. unsigned chan = to_channel(mattr);
  210. struct rank_info *rank = csrow->channels[chan];
  211. return sprintf(data, "%u\n", rank->ce_count);
  212. }
  213. /* cwrow<id>/attribute files */
  214. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  215. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  216. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  217. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  218. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  219. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  220. /* default attributes of the CSROW<id> object */
  221. static struct attribute *csrow_attrs[] = {
  222. &dev_attr_legacy_dev_type.attr,
  223. &dev_attr_legacy_mem_type.attr,
  224. &dev_attr_legacy_edac_mode.attr,
  225. &dev_attr_legacy_size_mb.attr,
  226. &dev_attr_legacy_ue_count.attr,
  227. &dev_attr_legacy_ce_count.attr,
  228. NULL,
  229. };
  230. static struct attribute_group csrow_attr_grp = {
  231. .attrs = csrow_attrs,
  232. };
  233. static const struct attribute_group *csrow_attr_groups[] = {
  234. &csrow_attr_grp,
  235. NULL
  236. };
  237. static void csrow_attr_release(struct device *dev)
  238. {
  239. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  240. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  241. kfree(csrow);
  242. }
  243. static struct device_type csrow_attr_type = {
  244. .groups = csrow_attr_groups,
  245. .release = csrow_attr_release,
  246. };
  247. /*
  248. * possible dynamic channel DIMM Label attribute files
  249. *
  250. */
  251. #define EDAC_NR_CHANNELS 6
  252. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  253. channel_dimm_label_show, channel_dimm_label_store, 0);
  254. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  255. channel_dimm_label_show, channel_dimm_label_store, 1);
  256. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 2);
  258. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 3);
  260. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 4);
  262. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 5);
  264. /* Total possible dynamic DIMM Label attribute file table */
  265. static struct device_attribute *dynamic_csrow_dimm_attr[] = {
  266. &dev_attr_legacy_ch0_dimm_label.attr,
  267. &dev_attr_legacy_ch1_dimm_label.attr,
  268. &dev_attr_legacy_ch2_dimm_label.attr,
  269. &dev_attr_legacy_ch3_dimm_label.attr,
  270. &dev_attr_legacy_ch4_dimm_label.attr,
  271. &dev_attr_legacy_ch5_dimm_label.attr
  272. };
  273. /* possible dynamic channel ce_count attribute files */
  274. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
  275. channel_ce_count_show, NULL, 0);
  276. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
  277. channel_ce_count_show, NULL, 1);
  278. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
  279. channel_ce_count_show, NULL, 2);
  280. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
  281. channel_ce_count_show, NULL, 3);
  282. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
  283. channel_ce_count_show, NULL, 4);
  284. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
  285. channel_ce_count_show, NULL, 5);
  286. /* Total possible dynamic ce_count attribute file table */
  287. static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
  288. &dev_attr_legacy_ch0_ce_count.attr,
  289. &dev_attr_legacy_ch1_ce_count.attr,
  290. &dev_attr_legacy_ch2_ce_count.attr,
  291. &dev_attr_legacy_ch3_ce_count.attr,
  292. &dev_attr_legacy_ch4_ce_count.attr,
  293. &dev_attr_legacy_ch5_ce_count.attr
  294. };
  295. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  296. {
  297. int chan, nr_pages = 0;
  298. for (chan = 0; chan < csrow->nr_channels; chan++)
  299. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  300. return nr_pages;
  301. }
  302. /* Create a CSROW object under specifed edac_mc_device */
  303. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  304. struct csrow_info *csrow, int index)
  305. {
  306. int err, chan;
  307. if (csrow->nr_channels >= EDAC_NR_CHANNELS)
  308. return -ENODEV;
  309. csrow->dev.type = &csrow_attr_type;
  310. csrow->dev.bus = &mci->bus;
  311. device_initialize(&csrow->dev);
  312. csrow->dev.parent = &mci->dev;
  313. dev_set_name(&csrow->dev, "csrow%d", index);
  314. dev_set_drvdata(&csrow->dev, csrow);
  315. edac_dbg(0, "creating (virtual) csrow node %s\n",
  316. dev_name(&csrow->dev));
  317. err = device_add(&csrow->dev);
  318. if (err < 0)
  319. return err;
  320. for (chan = 0; chan < csrow->nr_channels; chan++) {
  321. /* Only expose populated DIMMs */
  322. if (!csrow->channels[chan]->dimm->nr_pages)
  323. continue;
  324. err = device_create_file(&csrow->dev,
  325. dynamic_csrow_dimm_attr[chan]);
  326. if (err < 0)
  327. goto error;
  328. err = device_create_file(&csrow->dev,
  329. dynamic_csrow_ce_count_attr[chan]);
  330. if (err < 0) {
  331. device_remove_file(&csrow->dev,
  332. dynamic_csrow_dimm_attr[chan]);
  333. goto error;
  334. }
  335. }
  336. return 0;
  337. error:
  338. for (--chan; chan >= 0; chan--) {
  339. device_remove_file(&csrow->dev,
  340. dynamic_csrow_dimm_attr[chan]);
  341. device_remove_file(&csrow->dev,
  342. dynamic_csrow_ce_count_attr[chan]);
  343. }
  344. put_device(&csrow->dev);
  345. return err;
  346. }
  347. /* Create a CSROW object under specifed edac_mc_device */
  348. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  349. {
  350. int err, i, chan;
  351. struct csrow_info *csrow;
  352. for (i = 0; i < mci->nr_csrows; i++) {
  353. csrow = mci->csrows[i];
  354. if (!nr_pages_per_csrow(csrow))
  355. continue;
  356. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  357. if (err < 0)
  358. goto error;
  359. }
  360. return 0;
  361. error:
  362. for (--i; i >= 0; i--) {
  363. csrow = mci->csrows[i];
  364. if (!nr_pages_per_csrow(csrow))
  365. continue;
  366. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  367. if (!csrow->channels[chan]->dimm->nr_pages)
  368. continue;
  369. device_remove_file(&csrow->dev,
  370. dynamic_csrow_dimm_attr[chan]);
  371. device_remove_file(&csrow->dev,
  372. dynamic_csrow_ce_count_attr[chan]);
  373. }
  374. put_device(&mci->csrows[i]->dev);
  375. }
  376. return err;
  377. }
  378. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  379. {
  380. int i, chan;
  381. struct csrow_info *csrow;
  382. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  383. csrow = mci->csrows[i];
  384. if (!nr_pages_per_csrow(csrow))
  385. continue;
  386. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  387. if (!csrow->channels[chan]->dimm->nr_pages)
  388. continue;
  389. edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
  390. i, chan);
  391. device_remove_file(&csrow->dev,
  392. dynamic_csrow_dimm_attr[chan]);
  393. device_remove_file(&csrow->dev,
  394. dynamic_csrow_ce_count_attr[chan]);
  395. }
  396. put_device(&mci->csrows[i]->dev);
  397. device_del(&mci->csrows[i]->dev);
  398. }
  399. }
  400. #endif
  401. /*
  402. * Per-dimm (or per-rank) devices
  403. */
  404. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  405. /* show/store functions for DIMM Label attributes */
  406. static ssize_t dimmdev_location_show(struct device *dev,
  407. struct device_attribute *mattr, char *data)
  408. {
  409. struct dimm_info *dimm = to_dimm(dev);
  410. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  411. }
  412. static ssize_t dimmdev_label_show(struct device *dev,
  413. struct device_attribute *mattr, char *data)
  414. {
  415. struct dimm_info *dimm = to_dimm(dev);
  416. /* if field has not been initialized, there is nothing to send */
  417. if (!dimm->label[0])
  418. return 0;
  419. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  420. }
  421. static ssize_t dimmdev_label_store(struct device *dev,
  422. struct device_attribute *mattr,
  423. const char *data,
  424. size_t count)
  425. {
  426. struct dimm_info *dimm = to_dimm(dev);
  427. ssize_t max_size = 0;
  428. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  429. strncpy(dimm->label, data, max_size);
  430. dimm->label[max_size] = '\0';
  431. return max_size;
  432. }
  433. static ssize_t dimmdev_size_show(struct device *dev,
  434. struct device_attribute *mattr, char *data)
  435. {
  436. struct dimm_info *dimm = to_dimm(dev);
  437. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  438. }
  439. static ssize_t dimmdev_mem_type_show(struct device *dev,
  440. struct device_attribute *mattr, char *data)
  441. {
  442. struct dimm_info *dimm = to_dimm(dev);
  443. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  444. }
  445. static ssize_t dimmdev_dev_type_show(struct device *dev,
  446. struct device_attribute *mattr, char *data)
  447. {
  448. struct dimm_info *dimm = to_dimm(dev);
  449. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  450. }
  451. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  452. struct device_attribute *mattr,
  453. char *data)
  454. {
  455. struct dimm_info *dimm = to_dimm(dev);
  456. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  457. }
  458. /* dimm/rank attribute files */
  459. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  460. dimmdev_label_show, dimmdev_label_store);
  461. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  462. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  463. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  464. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  465. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  466. /* attributes of the dimm<id>/rank<id> object */
  467. static struct attribute *dimm_attrs[] = {
  468. &dev_attr_dimm_label.attr,
  469. &dev_attr_dimm_location.attr,
  470. &dev_attr_size.attr,
  471. &dev_attr_dimm_mem_type.attr,
  472. &dev_attr_dimm_dev_type.attr,
  473. &dev_attr_dimm_edac_mode.attr,
  474. NULL,
  475. };
  476. static struct attribute_group dimm_attr_grp = {
  477. .attrs = dimm_attrs,
  478. };
  479. static const struct attribute_group *dimm_attr_groups[] = {
  480. &dimm_attr_grp,
  481. NULL
  482. };
  483. static void dimm_attr_release(struct device *dev)
  484. {
  485. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  486. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  487. kfree(dimm);
  488. }
  489. static struct device_type dimm_attr_type = {
  490. .groups = dimm_attr_groups,
  491. .release = dimm_attr_release,
  492. };
  493. /* Create a DIMM object under specifed memory controller device */
  494. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  495. struct dimm_info *dimm,
  496. int index)
  497. {
  498. int err;
  499. dimm->mci = mci;
  500. dimm->dev.type = &dimm_attr_type;
  501. dimm->dev.bus = &mci->bus;
  502. device_initialize(&dimm->dev);
  503. dimm->dev.parent = &mci->dev;
  504. if (mci->mem_is_per_rank)
  505. dev_set_name(&dimm->dev, "rank%d", index);
  506. else
  507. dev_set_name(&dimm->dev, "dimm%d", index);
  508. dev_set_drvdata(&dimm->dev, dimm);
  509. pm_runtime_forbid(&mci->dev);
  510. err = device_add(&dimm->dev);
  511. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  512. return err;
  513. }
  514. /*
  515. * Memory controller device
  516. */
  517. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  518. static ssize_t mci_reset_counters_store(struct device *dev,
  519. struct device_attribute *mattr,
  520. const char *data, size_t count)
  521. {
  522. struct mem_ctl_info *mci = to_mci(dev);
  523. int cnt, row, chan, i;
  524. mci->ue_mc = 0;
  525. mci->ce_mc = 0;
  526. mci->ue_noinfo_count = 0;
  527. mci->ce_noinfo_count = 0;
  528. for (row = 0; row < mci->nr_csrows; row++) {
  529. struct csrow_info *ri = mci->csrows[row];
  530. ri->ue_count = 0;
  531. ri->ce_count = 0;
  532. for (chan = 0; chan < ri->nr_channels; chan++)
  533. ri->channels[chan]->ce_count = 0;
  534. }
  535. cnt = 1;
  536. for (i = 0; i < mci->n_layers; i++) {
  537. cnt *= mci->layers[i].size;
  538. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  539. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  540. }
  541. mci->start_time = jiffies;
  542. return count;
  543. }
  544. /* Memory scrubbing interface:
  545. *
  546. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  547. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  548. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  549. *
  550. * Negative value still means that an error has occurred while setting
  551. * the scrub rate.
  552. */
  553. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  554. struct device_attribute *mattr,
  555. const char *data, size_t count)
  556. {
  557. struct mem_ctl_info *mci = to_mci(dev);
  558. unsigned long bandwidth = 0;
  559. int new_bw = 0;
  560. if (!mci->set_sdram_scrub_rate)
  561. return -ENODEV;
  562. if (strict_strtoul(data, 10, &bandwidth) < 0)
  563. return -EINVAL;
  564. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  565. if (new_bw < 0) {
  566. edac_printk(KERN_WARNING, EDAC_MC,
  567. "Error setting scrub rate to: %lu\n", bandwidth);
  568. return -EINVAL;
  569. }
  570. return count;
  571. }
  572. /*
  573. * ->get_sdram_scrub_rate() return value semantics same as above.
  574. */
  575. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  576. struct device_attribute *mattr,
  577. char *data)
  578. {
  579. struct mem_ctl_info *mci = to_mci(dev);
  580. int bandwidth = 0;
  581. if (!mci->get_sdram_scrub_rate)
  582. return -ENODEV;
  583. bandwidth = mci->get_sdram_scrub_rate(mci);
  584. if (bandwidth < 0) {
  585. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  586. return bandwidth;
  587. }
  588. return sprintf(data, "%d\n", bandwidth);
  589. }
  590. /* default attribute files for the MCI object */
  591. static ssize_t mci_ue_count_show(struct device *dev,
  592. struct device_attribute *mattr,
  593. char *data)
  594. {
  595. struct mem_ctl_info *mci = to_mci(dev);
  596. return sprintf(data, "%d\n", mci->ue_mc);
  597. }
  598. static ssize_t mci_ce_count_show(struct device *dev,
  599. struct device_attribute *mattr,
  600. char *data)
  601. {
  602. struct mem_ctl_info *mci = to_mci(dev);
  603. return sprintf(data, "%d\n", mci->ce_mc);
  604. }
  605. static ssize_t mci_ce_noinfo_show(struct device *dev,
  606. struct device_attribute *mattr,
  607. char *data)
  608. {
  609. struct mem_ctl_info *mci = to_mci(dev);
  610. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  611. }
  612. static ssize_t mci_ue_noinfo_show(struct device *dev,
  613. struct device_attribute *mattr,
  614. char *data)
  615. {
  616. struct mem_ctl_info *mci = to_mci(dev);
  617. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  618. }
  619. static ssize_t mci_seconds_show(struct device *dev,
  620. struct device_attribute *mattr,
  621. char *data)
  622. {
  623. struct mem_ctl_info *mci = to_mci(dev);
  624. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  625. }
  626. static ssize_t mci_ctl_name_show(struct device *dev,
  627. struct device_attribute *mattr,
  628. char *data)
  629. {
  630. struct mem_ctl_info *mci = to_mci(dev);
  631. return sprintf(data, "%s\n", mci->ctl_name);
  632. }
  633. static ssize_t mci_size_mb_show(struct device *dev,
  634. struct device_attribute *mattr,
  635. char *data)
  636. {
  637. struct mem_ctl_info *mci = to_mci(dev);
  638. int total_pages = 0, csrow_idx, j;
  639. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  640. struct csrow_info *csrow = mci->csrows[csrow_idx];
  641. for (j = 0; j < csrow->nr_channels; j++) {
  642. struct dimm_info *dimm = csrow->channels[j]->dimm;
  643. total_pages += dimm->nr_pages;
  644. }
  645. }
  646. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  647. }
  648. static ssize_t mci_max_location_show(struct device *dev,
  649. struct device_attribute *mattr,
  650. char *data)
  651. {
  652. struct mem_ctl_info *mci = to_mci(dev);
  653. int i;
  654. char *p = data;
  655. for (i = 0; i < mci->n_layers; i++) {
  656. p += sprintf(p, "%s %d ",
  657. edac_layer_name[mci->layers[i].type],
  658. mci->layers[i].size - 1);
  659. }
  660. return p - data;
  661. }
  662. #ifdef CONFIG_EDAC_DEBUG
  663. static ssize_t edac_fake_inject_write(struct file *file,
  664. const char __user *data,
  665. size_t count, loff_t *ppos)
  666. {
  667. struct device *dev = file->private_data;
  668. struct mem_ctl_info *mci = to_mci(dev);
  669. static enum hw_event_mc_err_type type;
  670. u16 errcount = mci->fake_inject_count;
  671. if (!errcount)
  672. errcount = 1;
  673. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  674. : HW_EVENT_ERR_CORRECTED;
  675. printk(KERN_DEBUG
  676. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  677. errcount,
  678. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  679. errcount > 1 ? "s" : "",
  680. mci->fake_inject_layer[0],
  681. mci->fake_inject_layer[1],
  682. mci->fake_inject_layer[2]
  683. );
  684. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  685. mci->fake_inject_layer[0],
  686. mci->fake_inject_layer[1],
  687. mci->fake_inject_layer[2],
  688. "FAKE ERROR", "for EDAC testing only");
  689. return count;
  690. }
  691. static int debugfs_open(struct inode *inode, struct file *file)
  692. {
  693. file->private_data = inode->i_private;
  694. return 0;
  695. }
  696. static const struct file_operations debug_fake_inject_fops = {
  697. .open = debugfs_open,
  698. .write = edac_fake_inject_write,
  699. .llseek = generic_file_llseek,
  700. };
  701. #endif
  702. /* default Control file */
  703. DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  704. /* default Attribute files */
  705. DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  706. DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  707. DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  708. DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  709. DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  710. DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  711. DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  712. DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  713. /* memory scrubber attribute file */
  714. DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show,
  715. mci_sdram_scrub_rate_store);
  716. static struct attribute *mci_attrs[] = {
  717. &dev_attr_reset_counters.attr,
  718. &dev_attr_mc_name.attr,
  719. &dev_attr_size_mb.attr,
  720. &dev_attr_seconds_since_reset.attr,
  721. &dev_attr_ue_noinfo_count.attr,
  722. &dev_attr_ce_noinfo_count.attr,
  723. &dev_attr_ue_count.attr,
  724. &dev_attr_ce_count.attr,
  725. &dev_attr_sdram_scrub_rate.attr,
  726. &dev_attr_max_location.attr,
  727. NULL
  728. };
  729. static struct attribute_group mci_attr_grp = {
  730. .attrs = mci_attrs,
  731. };
  732. static const struct attribute_group *mci_attr_groups[] = {
  733. &mci_attr_grp,
  734. NULL
  735. };
  736. static void mci_attr_release(struct device *dev)
  737. {
  738. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  739. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  740. kfree(mci);
  741. }
  742. static struct device_type mci_attr_type = {
  743. .groups = mci_attr_groups,
  744. .release = mci_attr_release,
  745. };
  746. #ifdef CONFIG_EDAC_DEBUG
  747. static struct dentry *edac_debugfs;
  748. int __init edac_debugfs_init(void)
  749. {
  750. edac_debugfs = debugfs_create_dir("edac", NULL);
  751. if (IS_ERR(edac_debugfs)) {
  752. edac_debugfs = NULL;
  753. return -ENOMEM;
  754. }
  755. return 0;
  756. }
  757. void __exit edac_debugfs_exit(void)
  758. {
  759. debugfs_remove(edac_debugfs);
  760. }
  761. int edac_create_debug_nodes(struct mem_ctl_info *mci)
  762. {
  763. struct dentry *d, *parent;
  764. char name[80];
  765. int i;
  766. if (!edac_debugfs)
  767. return -ENODEV;
  768. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  769. if (!d)
  770. return -ENOMEM;
  771. parent = d;
  772. for (i = 0; i < mci->n_layers; i++) {
  773. sprintf(name, "fake_inject_%s",
  774. edac_layer_name[mci->layers[i].type]);
  775. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  776. &mci->fake_inject_layer[i]);
  777. if (!d)
  778. goto nomem;
  779. }
  780. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  781. &mci->fake_inject_ue);
  782. if (!d)
  783. goto nomem;
  784. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  785. &mci->fake_inject_count);
  786. if (!d)
  787. goto nomem;
  788. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  789. &mci->dev,
  790. &debug_fake_inject_fops);
  791. if (!d)
  792. goto nomem;
  793. mci->debugfs = parent;
  794. return 0;
  795. nomem:
  796. debugfs_remove(mci->debugfs);
  797. return -ENOMEM;
  798. }
  799. #endif
  800. /*
  801. * Create a new Memory Controller kobject instance,
  802. * mc<id> under the 'mc' directory
  803. *
  804. * Return:
  805. * 0 Success
  806. * !0 Failure
  807. */
  808. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
  809. {
  810. int i, err;
  811. /*
  812. * The memory controller needs its own bus, in order to avoid
  813. * namespace conflicts at /sys/bus/edac.
  814. */
  815. mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  816. if (!mci->bus.name)
  817. return -ENOMEM;
  818. edac_dbg(0, "creating bus %s\n", mci->bus.name);
  819. err = bus_register(&mci->bus);
  820. if (err < 0)
  821. return err;
  822. /* get the /sys/devices/system/edac subsys reference */
  823. mci->dev.type = &mci_attr_type;
  824. device_initialize(&mci->dev);
  825. mci->dev.parent = mci_pdev;
  826. mci->dev.bus = &mci->bus;
  827. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  828. dev_set_drvdata(&mci->dev, mci);
  829. pm_runtime_forbid(&mci->dev);
  830. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  831. err = device_add(&mci->dev);
  832. if (err < 0) {
  833. bus_unregister(&mci->bus);
  834. kfree(mci->bus.name);
  835. return err;
  836. }
  837. /*
  838. * Create the dimm/rank devices
  839. */
  840. for (i = 0; i < mci->tot_dimms; i++) {
  841. struct dimm_info *dimm = mci->dimms[i];
  842. /* Only expose populated DIMMs */
  843. if (dimm->nr_pages == 0)
  844. continue;
  845. #ifdef CONFIG_EDAC_DEBUG
  846. edac_dbg(1, "creating dimm%d, located at ", i);
  847. if (edac_debug_level >= 1) {
  848. int lay;
  849. for (lay = 0; lay < mci->n_layers; lay++)
  850. printk(KERN_CONT "%s %d ",
  851. edac_layer_name[mci->layers[lay].type],
  852. dimm->location[lay]);
  853. printk(KERN_CONT "\n");
  854. }
  855. #endif
  856. err = edac_create_dimm_object(mci, dimm, i);
  857. if (err) {
  858. edac_dbg(1, "failure: create dimm %d obj\n", i);
  859. goto fail;
  860. }
  861. }
  862. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  863. err = edac_create_csrow_objects(mci);
  864. if (err < 0)
  865. goto fail;
  866. #endif
  867. #ifdef CONFIG_EDAC_DEBUG
  868. edac_create_debug_nodes(mci);
  869. #endif
  870. return 0;
  871. fail:
  872. for (i--; i >= 0; i--) {
  873. struct dimm_info *dimm = mci->dimms[i];
  874. if (dimm->nr_pages == 0)
  875. continue;
  876. put_device(&dimm->dev);
  877. device_del(&dimm->dev);
  878. }
  879. put_device(&mci->dev);
  880. device_del(&mci->dev);
  881. bus_unregister(&mci->bus);
  882. kfree(mci->bus.name);
  883. return err;
  884. }
  885. /*
  886. * remove a Memory Controller instance
  887. */
  888. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  889. {
  890. int i;
  891. edac_dbg(0, "\n");
  892. #ifdef CONFIG_EDAC_DEBUG
  893. debugfs_remove(mci->debugfs);
  894. #endif
  895. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  896. edac_delete_csrow_objects(mci);
  897. #endif
  898. for (i = 0; i < mci->tot_dimms; i++) {
  899. struct dimm_info *dimm = mci->dimms[i];
  900. if (dimm->nr_pages == 0)
  901. continue;
  902. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  903. put_device(&dimm->dev);
  904. device_del(&dimm->dev);
  905. }
  906. }
  907. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  908. {
  909. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  910. put_device(&mci->dev);
  911. device_del(&mci->dev);
  912. bus_unregister(&mci->bus);
  913. kfree(mci->bus.name);
  914. }
  915. static void mc_attr_release(struct device *dev)
  916. {
  917. /*
  918. * There's no container structure here, as this is just the mci
  919. * parent device, used to create the /sys/devices/mc sysfs node.
  920. * So, there are no attributes on it.
  921. */
  922. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  923. kfree(dev);
  924. }
  925. static struct device_type mc_attr_type = {
  926. .release = mc_attr_release,
  927. };
  928. /*
  929. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  930. */
  931. int __init edac_mc_sysfs_init(void)
  932. {
  933. struct bus_type *edac_subsys;
  934. int err;
  935. /* get the /sys/devices/system/edac subsys reference */
  936. edac_subsys = edac_get_sysfs_subsys();
  937. if (edac_subsys == NULL) {
  938. edac_dbg(1, "no edac_subsys\n");
  939. return -EINVAL;
  940. }
  941. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  942. mci_pdev->bus = edac_subsys;
  943. mci_pdev->type = &mc_attr_type;
  944. device_initialize(mci_pdev);
  945. dev_set_name(mci_pdev, "mc");
  946. err = device_add(mci_pdev);
  947. if (err < 0)
  948. return err;
  949. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  950. return 0;
  951. }
  952. void __exit edac_mc_sysfs_exit(void)
  953. {
  954. put_device(mci_pdev);
  955. device_del(mci_pdev);
  956. edac_put_sysfs_subsys();
  957. }