Kconfig 9.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319
  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. #
  6. menuconfig EDAC
  7. bool "EDAC (Error Detection And Correction) reporting"
  8. depends on HAS_IOMEM
  9. depends on X86 || PPC || TILE || ARM
  10. help
  11. EDAC is designed to report errors in the core system.
  12. These are low-level errors that are reported in the CPU or
  13. supporting chipset or other subsystems:
  14. memory errors, cache errors, PCI errors, thermal throttling, etc..
  15. If unsure, select 'Y'.
  16. If this code is reporting problems on your system, please
  17. see the EDAC project web pages for more information at:
  18. <http://bluesmoke.sourceforge.net/>
  19. and:
  20. <http://buttersideup.com/edacwiki>
  21. There is also a mailing list for the EDAC project, which can
  22. be found via the sourceforge page.
  23. if EDAC
  24. comment "Reporting subsystems"
  25. config EDAC_LEGACY_SYSFS
  26. bool "EDAC legacy sysfs"
  27. default y
  28. help
  29. Enable the compatibility sysfs nodes.
  30. Use 'Y' if your edac utilities aren't ported to work with the newer
  31. structures.
  32. config EDAC_DEBUG
  33. bool "Debugging"
  34. help
  35. This turns on debugging information for the entire EDAC
  36. sub-system. You can insert module with "debug_level=x", current
  37. there're four debug levels (x=0,1,2,3 from low to high).
  38. Usually you should select 'N'.
  39. config EDAC_DECODE_MCE
  40. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  41. depends on CPU_SUP_AMD && X86_MCE_AMD
  42. default y
  43. ---help---
  44. Enable this option if you want to decode Machine Check Exceptions
  45. occurring on your machine in human-readable form.
  46. You should definitely say Y here in case you want to decode MCEs
  47. which occur really early upon boot, before the module infrastructure
  48. has been initialized.
  49. config EDAC_MCE_INJ
  50. tristate "Simple MCE injection interface over /sysfs"
  51. depends on EDAC_DECODE_MCE
  52. default n
  53. help
  54. This is a simple interface to inject MCEs over /sysfs and test
  55. the MCE decoding code in EDAC.
  56. This is currently AMD-only.
  57. config EDAC_MM_EDAC
  58. tristate "Main Memory EDAC (Error Detection And Correction) reporting"
  59. help
  60. Some systems are able to detect and correct errors in main
  61. memory. EDAC can report statistics on memory error
  62. detection and correction (EDAC - or commonly referred to ECC
  63. errors). EDAC will also try to decode where these errors
  64. occurred so that a particular failing memory module can be
  65. replaced. If unsure, select 'Y'.
  66. config EDAC_AMD64
  67. tristate "AMD64 (Opteron, Athlon64) K8, F10h"
  68. depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
  69. help
  70. Support for error detection and correction of DRAM ECC errors on
  71. the AMD64 families of memory controllers (K8 and F10h)
  72. config EDAC_AMD64_ERROR_INJECTION
  73. bool "Sysfs HW Error injection facilities"
  74. depends on EDAC_AMD64
  75. help
  76. Recent Opterons (Family 10h and later) provide for Memory Error
  77. Injection into the ECC detection circuits. The amd64_edac module
  78. allows the operator/user to inject Uncorrectable and Correctable
  79. errors into DRAM.
  80. When enabled, in each of the respective memory controller directories
  81. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  82. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  83. - inject_word (0..8, 16-bit word of 16-byte section),
  84. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  85. In addition, there are two control files, inject_read and inject_write,
  86. which trigger the DRAM ECC Read and Write respectively.
  87. config EDAC_AMD76X
  88. tristate "AMD 76x (760, 762, 768)"
  89. depends on EDAC_MM_EDAC && PCI && X86_32
  90. help
  91. Support for error detection and correction on the AMD 76x
  92. series of chipsets used with the Athlon processor.
  93. config EDAC_E7XXX
  94. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  95. depends on EDAC_MM_EDAC && PCI && X86_32
  96. help
  97. Support for error detection and correction on the Intel
  98. E7205, E7500, E7501 and E7505 server chipsets.
  99. config EDAC_E752X
  100. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  101. depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
  102. help
  103. Support for error detection and correction on the Intel
  104. E7520, E7525, E7320 server chipsets.
  105. config EDAC_I82443BXGX
  106. tristate "Intel 82443BX/GX (440BX/GX)"
  107. depends on EDAC_MM_EDAC && PCI && X86_32
  108. depends on BROKEN
  109. help
  110. Support for error detection and correction on the Intel
  111. 82443BX/GX memory controllers (440BX/GX chipsets).
  112. config EDAC_I82875P
  113. tristate "Intel 82875p (D82875P, E7210)"
  114. depends on EDAC_MM_EDAC && PCI && X86_32
  115. help
  116. Support for error detection and correction on the Intel
  117. DP82785P and E7210 server chipsets.
  118. config EDAC_I82975X
  119. tristate "Intel 82975x (D82975x)"
  120. depends on EDAC_MM_EDAC && PCI && X86
  121. help
  122. Support for error detection and correction on the Intel
  123. DP82975x server chipsets.
  124. config EDAC_I3000
  125. tristate "Intel 3000/3010"
  126. depends on EDAC_MM_EDAC && PCI && X86
  127. help
  128. Support for error detection and correction on the Intel
  129. 3000 and 3010 server chipsets.
  130. config EDAC_I3200
  131. tristate "Intel 3200"
  132. depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
  133. help
  134. Support for error detection and correction on the Intel
  135. 3200 and 3210 server chipsets.
  136. config EDAC_X38
  137. tristate "Intel X38"
  138. depends on EDAC_MM_EDAC && PCI && X86
  139. help
  140. Support for error detection and correction on the Intel
  141. X38 server chipsets.
  142. config EDAC_I5400
  143. tristate "Intel 5400 (Seaburg) chipsets"
  144. depends on EDAC_MM_EDAC && PCI && X86
  145. help
  146. Support for error detection and correction the Intel
  147. i5400 MCH chipset (Seaburg).
  148. config EDAC_I7CORE
  149. tristate "Intel i7 Core (Nehalem) processors"
  150. depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
  151. help
  152. Support for error detection and correction the Intel
  153. i7 Core (Nehalem) Integrated Memory Controller that exists on
  154. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  155. and Xeon 55xx processors.
  156. config EDAC_I82860
  157. tristate "Intel 82860"
  158. depends on EDAC_MM_EDAC && PCI && X86_32
  159. help
  160. Support for error detection and correction on the Intel
  161. 82860 chipset.
  162. config EDAC_R82600
  163. tristate "Radisys 82600 embedded chipset"
  164. depends on EDAC_MM_EDAC && PCI && X86_32
  165. help
  166. Support for error detection and correction on the Radisys
  167. 82600 embedded chipset.
  168. config EDAC_I5000
  169. tristate "Intel Greencreek/Blackford chipset"
  170. depends on EDAC_MM_EDAC && X86 && PCI
  171. help
  172. Support for error detection and correction the Intel
  173. Greekcreek/Blackford chipsets.
  174. config EDAC_I5100
  175. tristate "Intel San Clemente MCH"
  176. depends on EDAC_MM_EDAC && X86 && PCI
  177. help
  178. Support for error detection and correction the Intel
  179. San Clemente MCH.
  180. config EDAC_I7300
  181. tristate "Intel Clarksboro MCH"
  182. depends on EDAC_MM_EDAC && X86 && PCI
  183. help
  184. Support for error detection and correction the Intel
  185. Clarksboro MCH (Intel 7300 chipset).
  186. config EDAC_SBRIDGE
  187. tristate "Intel Sandy-Bridge Integrated MC"
  188. depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
  189. depends on PCI_MMCONFIG && EXPERIMENTAL
  190. help
  191. Support for error detection and correction the Intel
  192. Sandy Bridge Integrated Memory Controller.
  193. config EDAC_MPC85XX
  194. tristate "Freescale MPC83xx / MPC85xx"
  195. depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
  196. help
  197. Support for error detection and correction on the Freescale
  198. MPC8349, MPC8560, MPC8540, MPC8548
  199. config EDAC_MV64X60
  200. tristate "Marvell MV64x60"
  201. depends on EDAC_MM_EDAC && MV64X60
  202. help
  203. Support for error detection and correction on the Marvell
  204. MV64360 and MV64460 chipsets.
  205. config EDAC_PASEMI
  206. tristate "PA Semi PWRficient"
  207. depends on EDAC_MM_EDAC && PCI
  208. depends on PPC_PASEMI
  209. help
  210. Support for error detection and correction on PA Semi
  211. PWRficient.
  212. config EDAC_CELL
  213. tristate "Cell Broadband Engine memory controller"
  214. depends on EDAC_MM_EDAC && PPC_CELL_COMMON
  215. help
  216. Support for error detection and correction on the
  217. Cell Broadband Engine internal memory controller
  218. on platform without a hypervisor
  219. config EDAC_PPC4XX
  220. tristate "PPC4xx IBM DDR2 Memory Controller"
  221. depends on EDAC_MM_EDAC && 4xx
  222. help
  223. This enables support for EDAC on the ECC memory used
  224. with the IBM DDR2 memory controller found in various
  225. PowerPC 4xx embedded processors such as the 405EX[r],
  226. 440SP, 440SPe, 460EX, 460GT and 460SX.
  227. config EDAC_AMD8131
  228. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  229. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  230. help
  231. Support for error detection and correction on the
  232. AMD8131 HyperTransport PCI-X Tunnel chip.
  233. Note, add more Kconfig dependency if it's adopted
  234. on some machine other than Maple.
  235. config EDAC_AMD8111
  236. tristate "AMD8111 HyperTransport I/O Hub"
  237. depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
  238. help
  239. Support for error detection and correction on the
  240. AMD8111 HyperTransport I/O Hub chip.
  241. Note, add more Kconfig dependency if it's adopted
  242. on some machine other than Maple.
  243. config EDAC_CPC925
  244. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  245. depends on EDAC_MM_EDAC && PPC64
  246. help
  247. Support for error detection and correction on the
  248. IBM CPC925 Bridge and Memory Controller, which is
  249. a companion chip to the PowerPC 970 family of
  250. processors.
  251. config EDAC_TILE
  252. tristate "Tilera Memory Controller"
  253. depends on EDAC_MM_EDAC && TILE
  254. default y
  255. help
  256. Support for error detection and correction on the
  257. Tilera memory controller.
  258. config EDAC_HIGHBANK_MC
  259. tristate "Highbank Memory Controller"
  260. depends on EDAC_MM_EDAC && ARCH_HIGHBANK
  261. help
  262. Support for error detection and correction on the
  263. Calxeda Highbank memory controller.
  264. config EDAC_HIGHBANK_L2
  265. tristate "Highbank L2 Cache"
  266. depends on EDAC_MM_EDAC && ARCH_HIGHBANK
  267. help
  268. Support for error detection and correction on the
  269. Calxeda Highbank memory controller.
  270. endif # EDAC