omap-dma.c 16 KB

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  1. /*
  2. * OMAP DMAengine support
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/err.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/list.h>
  14. #include <linux/module.h>
  15. #include <linux/omap-dma.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/spinlock.h>
  19. #include "virt-dma.h"
  20. #include <plat/dma.h>
  21. struct omap_dmadev {
  22. struct dma_device ddev;
  23. spinlock_t lock;
  24. struct tasklet_struct task;
  25. struct list_head pending;
  26. };
  27. struct omap_chan {
  28. struct virt_dma_chan vc;
  29. struct list_head node;
  30. struct dma_slave_config cfg;
  31. unsigned dma_sig;
  32. bool cyclic;
  33. int dma_ch;
  34. struct omap_desc *desc;
  35. unsigned sgidx;
  36. };
  37. struct omap_sg {
  38. dma_addr_t addr;
  39. uint32_t en; /* number of elements (24-bit) */
  40. uint32_t fn; /* number of frames (16-bit) */
  41. };
  42. struct omap_desc {
  43. struct virt_dma_desc vd;
  44. enum dma_transfer_direction dir;
  45. dma_addr_t dev_addr;
  46. int16_t fi; /* for OMAP_DMA_SYNC_PACKET */
  47. uint8_t es; /* OMAP_DMA_DATA_TYPE_xxx */
  48. uint8_t sync_mode; /* OMAP_DMA_SYNC_xxx */
  49. uint8_t sync_type; /* OMAP_DMA_xxx_SYNC* */
  50. uint8_t periph_port; /* Peripheral port */
  51. unsigned sglen;
  52. struct omap_sg sg[0];
  53. };
  54. static const unsigned es_bytes[] = {
  55. [OMAP_DMA_DATA_TYPE_S8] = 1,
  56. [OMAP_DMA_DATA_TYPE_S16] = 2,
  57. [OMAP_DMA_DATA_TYPE_S32] = 4,
  58. };
  59. static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d)
  60. {
  61. return container_of(d, struct omap_dmadev, ddev);
  62. }
  63. static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c)
  64. {
  65. return container_of(c, struct omap_chan, vc.chan);
  66. }
  67. static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t)
  68. {
  69. return container_of(t, struct omap_desc, vd.tx);
  70. }
  71. static void omap_dma_desc_free(struct virt_dma_desc *vd)
  72. {
  73. kfree(container_of(vd, struct omap_desc, vd));
  74. }
  75. static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d,
  76. unsigned idx)
  77. {
  78. struct omap_sg *sg = d->sg + idx;
  79. if (d->dir == DMA_DEV_TO_MEM)
  80. omap_set_dma_dest_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
  81. OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
  82. else
  83. omap_set_dma_src_params(c->dma_ch, OMAP_DMA_PORT_EMIFF,
  84. OMAP_DMA_AMODE_POST_INC, sg->addr, 0, 0);
  85. omap_set_dma_transfer_params(c->dma_ch, d->es, sg->en, sg->fn,
  86. d->sync_mode, c->dma_sig, d->sync_type);
  87. omap_start_dma(c->dma_ch);
  88. }
  89. static void omap_dma_start_desc(struct omap_chan *c)
  90. {
  91. struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
  92. struct omap_desc *d;
  93. if (!vd) {
  94. c->desc = NULL;
  95. return;
  96. }
  97. list_del(&vd->node);
  98. c->desc = d = to_omap_dma_desc(&vd->tx);
  99. c->sgidx = 0;
  100. if (d->dir == DMA_DEV_TO_MEM)
  101. omap_set_dma_src_params(c->dma_ch, d->periph_port,
  102. OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
  103. else
  104. omap_set_dma_dest_params(c->dma_ch, d->periph_port,
  105. OMAP_DMA_AMODE_CONSTANT, d->dev_addr, 0, d->fi);
  106. omap_dma_start_sg(c, d, 0);
  107. }
  108. static void omap_dma_callback(int ch, u16 status, void *data)
  109. {
  110. struct omap_chan *c = data;
  111. struct omap_desc *d;
  112. unsigned long flags;
  113. spin_lock_irqsave(&c->vc.lock, flags);
  114. d = c->desc;
  115. if (d) {
  116. if (!c->cyclic) {
  117. if (++c->sgidx < d->sglen) {
  118. omap_dma_start_sg(c, d, c->sgidx);
  119. } else {
  120. omap_dma_start_desc(c);
  121. vchan_cookie_complete(&d->vd);
  122. }
  123. } else {
  124. vchan_cyclic_callback(&d->vd);
  125. }
  126. }
  127. spin_unlock_irqrestore(&c->vc.lock, flags);
  128. }
  129. /*
  130. * This callback schedules all pending channels. We could be more
  131. * clever here by postponing allocation of the real DMA channels to
  132. * this point, and freeing them when our virtual channel becomes idle.
  133. *
  134. * We would then need to deal with 'all channels in-use'
  135. */
  136. static void omap_dma_sched(unsigned long data)
  137. {
  138. struct omap_dmadev *d = (struct omap_dmadev *)data;
  139. LIST_HEAD(head);
  140. spin_lock_irq(&d->lock);
  141. list_splice_tail_init(&d->pending, &head);
  142. spin_unlock_irq(&d->lock);
  143. while (!list_empty(&head)) {
  144. struct omap_chan *c = list_first_entry(&head,
  145. struct omap_chan, node);
  146. spin_lock_irq(&c->vc.lock);
  147. list_del_init(&c->node);
  148. omap_dma_start_desc(c);
  149. spin_unlock_irq(&c->vc.lock);
  150. }
  151. }
  152. static int omap_dma_alloc_chan_resources(struct dma_chan *chan)
  153. {
  154. struct omap_chan *c = to_omap_dma_chan(chan);
  155. dev_info(c->vc.chan.device->dev, "allocating channel for %u\n", c->dma_sig);
  156. return omap_request_dma(c->dma_sig, "DMA engine",
  157. omap_dma_callback, c, &c->dma_ch);
  158. }
  159. static void omap_dma_free_chan_resources(struct dma_chan *chan)
  160. {
  161. struct omap_chan *c = to_omap_dma_chan(chan);
  162. vchan_free_chan_resources(&c->vc);
  163. omap_free_dma(c->dma_ch);
  164. dev_info(c->vc.chan.device->dev, "freeing channel for %u\n", c->dma_sig);
  165. }
  166. static size_t omap_dma_sg_size(struct omap_sg *sg)
  167. {
  168. return sg->en * sg->fn;
  169. }
  170. static size_t omap_dma_desc_size(struct omap_desc *d)
  171. {
  172. unsigned i;
  173. size_t size;
  174. for (size = i = 0; i < d->sglen; i++)
  175. size += omap_dma_sg_size(&d->sg[i]);
  176. return size * es_bytes[d->es];
  177. }
  178. static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr)
  179. {
  180. unsigned i;
  181. size_t size, es_size = es_bytes[d->es];
  182. for (size = i = 0; i < d->sglen; i++) {
  183. size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size;
  184. if (size)
  185. size += this_size;
  186. else if (addr >= d->sg[i].addr &&
  187. addr < d->sg[i].addr + this_size)
  188. size += d->sg[i].addr + this_size - addr;
  189. }
  190. return size;
  191. }
  192. static enum dma_status omap_dma_tx_status(struct dma_chan *chan,
  193. dma_cookie_t cookie, struct dma_tx_state *txstate)
  194. {
  195. struct omap_chan *c = to_omap_dma_chan(chan);
  196. struct virt_dma_desc *vd;
  197. enum dma_status ret;
  198. unsigned long flags;
  199. ret = dma_cookie_status(chan, cookie, txstate);
  200. if (ret == DMA_SUCCESS || !txstate)
  201. return ret;
  202. spin_lock_irqsave(&c->vc.lock, flags);
  203. vd = vchan_find_desc(&c->vc, cookie);
  204. if (vd) {
  205. txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx));
  206. } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
  207. struct omap_desc *d = c->desc;
  208. dma_addr_t pos;
  209. if (d->dir == DMA_MEM_TO_DEV)
  210. pos = omap_get_dma_src_pos(c->dma_ch);
  211. else if (d->dir == DMA_DEV_TO_MEM)
  212. pos = omap_get_dma_dst_pos(c->dma_ch);
  213. else
  214. pos = 0;
  215. txstate->residue = omap_dma_desc_size_pos(d, pos);
  216. } else {
  217. txstate->residue = 0;
  218. }
  219. spin_unlock_irqrestore(&c->vc.lock, flags);
  220. return ret;
  221. }
  222. static void omap_dma_issue_pending(struct dma_chan *chan)
  223. {
  224. struct omap_chan *c = to_omap_dma_chan(chan);
  225. unsigned long flags;
  226. spin_lock_irqsave(&c->vc.lock, flags);
  227. if (vchan_issue_pending(&c->vc) && !c->desc) {
  228. struct omap_dmadev *d = to_omap_dma_dev(chan->device);
  229. spin_lock(&d->lock);
  230. if (list_empty(&c->node))
  231. list_add_tail(&c->node, &d->pending);
  232. spin_unlock(&d->lock);
  233. tasklet_schedule(&d->task);
  234. }
  235. spin_unlock_irqrestore(&c->vc.lock, flags);
  236. }
  237. static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg(
  238. struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen,
  239. enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
  240. {
  241. struct omap_chan *c = to_omap_dma_chan(chan);
  242. enum dma_slave_buswidth dev_width;
  243. struct scatterlist *sgent;
  244. struct omap_desc *d;
  245. dma_addr_t dev_addr;
  246. unsigned i, j = 0, es, en, frame_bytes, sync_type;
  247. u32 burst;
  248. if (dir == DMA_DEV_TO_MEM) {
  249. dev_addr = c->cfg.src_addr;
  250. dev_width = c->cfg.src_addr_width;
  251. burst = c->cfg.src_maxburst;
  252. sync_type = OMAP_DMA_SRC_SYNC;
  253. } else if (dir == DMA_MEM_TO_DEV) {
  254. dev_addr = c->cfg.dst_addr;
  255. dev_width = c->cfg.dst_addr_width;
  256. burst = c->cfg.dst_maxburst;
  257. sync_type = OMAP_DMA_DST_SYNC;
  258. } else {
  259. dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
  260. return NULL;
  261. }
  262. /* Bus width translates to the element size (ES) */
  263. switch (dev_width) {
  264. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  265. es = OMAP_DMA_DATA_TYPE_S8;
  266. break;
  267. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  268. es = OMAP_DMA_DATA_TYPE_S16;
  269. break;
  270. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  271. es = OMAP_DMA_DATA_TYPE_S32;
  272. break;
  273. default: /* not reached */
  274. return NULL;
  275. }
  276. /* Now allocate and setup the descriptor. */
  277. d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC);
  278. if (!d)
  279. return NULL;
  280. d->dir = dir;
  281. d->dev_addr = dev_addr;
  282. d->es = es;
  283. d->sync_mode = OMAP_DMA_SYNC_FRAME;
  284. d->sync_type = sync_type;
  285. d->periph_port = OMAP_DMA_PORT_TIPB;
  286. /*
  287. * Build our scatterlist entries: each contains the address,
  288. * the number of elements (EN) in each frame, and the number of
  289. * frames (FN). Number of bytes for this entry = ES * EN * FN.
  290. *
  291. * Burst size translates to number of elements with frame sync.
  292. * Note: DMA engine defines burst to be the number of dev-width
  293. * transfers.
  294. */
  295. en = burst;
  296. frame_bytes = es_bytes[es] * en;
  297. for_each_sg(sgl, sgent, sglen, i) {
  298. d->sg[j].addr = sg_dma_address(sgent);
  299. d->sg[j].en = en;
  300. d->sg[j].fn = sg_dma_len(sgent) / frame_bytes;
  301. j++;
  302. }
  303. d->sglen = j;
  304. return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
  305. }
  306. static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic(
  307. struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
  308. size_t period_len, enum dma_transfer_direction dir, void *context)
  309. {
  310. struct omap_chan *c = to_omap_dma_chan(chan);
  311. enum dma_slave_buswidth dev_width;
  312. struct omap_desc *d;
  313. dma_addr_t dev_addr;
  314. unsigned es, sync_type;
  315. u32 burst;
  316. if (dir == DMA_DEV_TO_MEM) {
  317. dev_addr = c->cfg.src_addr;
  318. dev_width = c->cfg.src_addr_width;
  319. burst = c->cfg.src_maxburst;
  320. sync_type = OMAP_DMA_SRC_SYNC;
  321. } else if (dir == DMA_MEM_TO_DEV) {
  322. dev_addr = c->cfg.dst_addr;
  323. dev_width = c->cfg.dst_addr_width;
  324. burst = c->cfg.dst_maxburst;
  325. sync_type = OMAP_DMA_DST_SYNC;
  326. } else {
  327. dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
  328. return NULL;
  329. }
  330. /* Bus width translates to the element size (ES) */
  331. switch (dev_width) {
  332. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  333. es = OMAP_DMA_DATA_TYPE_S8;
  334. break;
  335. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  336. es = OMAP_DMA_DATA_TYPE_S16;
  337. break;
  338. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  339. es = OMAP_DMA_DATA_TYPE_S32;
  340. break;
  341. default: /* not reached */
  342. return NULL;
  343. }
  344. /* Now allocate and setup the descriptor. */
  345. d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC);
  346. if (!d)
  347. return NULL;
  348. d->dir = dir;
  349. d->dev_addr = dev_addr;
  350. d->fi = burst;
  351. d->es = es;
  352. d->sync_mode = OMAP_DMA_SYNC_PACKET;
  353. d->sync_type = sync_type;
  354. d->periph_port = OMAP_DMA_PORT_MPUI;
  355. d->sg[0].addr = buf_addr;
  356. d->sg[0].en = period_len / es_bytes[es];
  357. d->sg[0].fn = buf_len / period_len;
  358. d->sglen = 1;
  359. if (!c->cyclic) {
  360. c->cyclic = true;
  361. omap_dma_link_lch(c->dma_ch, c->dma_ch);
  362. omap_enable_dma_irq(c->dma_ch, OMAP_DMA_FRAME_IRQ);
  363. omap_disable_dma_irq(c->dma_ch, OMAP_DMA_BLOCK_IRQ);
  364. }
  365. if (!cpu_class_is_omap1()) {
  366. omap_set_dma_src_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
  367. omap_set_dma_dest_burst_mode(c->dma_ch, OMAP_DMA_DATA_BURST_16);
  368. }
  369. return vchan_tx_prep(&c->vc, &d->vd, DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
  370. }
  371. static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg)
  372. {
  373. if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
  374. cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
  375. return -EINVAL;
  376. memcpy(&c->cfg, cfg, sizeof(c->cfg));
  377. return 0;
  378. }
  379. static int omap_dma_terminate_all(struct omap_chan *c)
  380. {
  381. struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device);
  382. unsigned long flags;
  383. LIST_HEAD(head);
  384. spin_lock_irqsave(&c->vc.lock, flags);
  385. /* Prevent this channel being scheduled */
  386. spin_lock(&d->lock);
  387. list_del_init(&c->node);
  388. spin_unlock(&d->lock);
  389. /*
  390. * Stop DMA activity: we assume the callback will not be called
  391. * after omap_stop_dma() returns (even if it does, it will see
  392. * c->desc is NULL and exit.)
  393. */
  394. if (c->desc) {
  395. c->desc = NULL;
  396. omap_stop_dma(c->dma_ch);
  397. }
  398. if (c->cyclic) {
  399. c->cyclic = false;
  400. omap_dma_unlink_lch(c->dma_ch, c->dma_ch);
  401. }
  402. vchan_get_all_descriptors(&c->vc, &head);
  403. spin_unlock_irqrestore(&c->vc.lock, flags);
  404. vchan_dma_desc_free_list(&c->vc, &head);
  405. return 0;
  406. }
  407. static int omap_dma_pause(struct omap_chan *c)
  408. {
  409. /* FIXME: not supported by platform private API */
  410. return -EINVAL;
  411. }
  412. static int omap_dma_resume(struct omap_chan *c)
  413. {
  414. /* FIXME: not supported by platform private API */
  415. return -EINVAL;
  416. }
  417. static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  418. unsigned long arg)
  419. {
  420. struct omap_chan *c = to_omap_dma_chan(chan);
  421. int ret;
  422. switch (cmd) {
  423. case DMA_SLAVE_CONFIG:
  424. ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg);
  425. break;
  426. case DMA_TERMINATE_ALL:
  427. ret = omap_dma_terminate_all(c);
  428. break;
  429. case DMA_PAUSE:
  430. ret = omap_dma_pause(c);
  431. break;
  432. case DMA_RESUME:
  433. ret = omap_dma_resume(c);
  434. break;
  435. default:
  436. ret = -ENXIO;
  437. break;
  438. }
  439. return ret;
  440. }
  441. static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig)
  442. {
  443. struct omap_chan *c;
  444. c = kzalloc(sizeof(*c), GFP_KERNEL);
  445. if (!c)
  446. return -ENOMEM;
  447. c->dma_sig = dma_sig;
  448. c->vc.desc_free = omap_dma_desc_free;
  449. vchan_init(&c->vc, &od->ddev);
  450. INIT_LIST_HEAD(&c->node);
  451. od->ddev.chancnt++;
  452. return 0;
  453. }
  454. static void omap_dma_free(struct omap_dmadev *od)
  455. {
  456. tasklet_kill(&od->task);
  457. while (!list_empty(&od->ddev.channels)) {
  458. struct omap_chan *c = list_first_entry(&od->ddev.channels,
  459. struct omap_chan, vc.chan.device_node);
  460. list_del(&c->vc.chan.device_node);
  461. tasklet_kill(&c->vc.task);
  462. kfree(c);
  463. }
  464. kfree(od);
  465. }
  466. static int omap_dma_probe(struct platform_device *pdev)
  467. {
  468. struct omap_dmadev *od;
  469. int rc, i;
  470. od = kzalloc(sizeof(*od), GFP_KERNEL);
  471. if (!od)
  472. return -ENOMEM;
  473. dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
  474. dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
  475. od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources;
  476. od->ddev.device_free_chan_resources = omap_dma_free_chan_resources;
  477. od->ddev.device_tx_status = omap_dma_tx_status;
  478. od->ddev.device_issue_pending = omap_dma_issue_pending;
  479. od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg;
  480. od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic;
  481. od->ddev.device_control = omap_dma_control;
  482. od->ddev.dev = &pdev->dev;
  483. INIT_LIST_HEAD(&od->ddev.channels);
  484. INIT_LIST_HEAD(&od->pending);
  485. spin_lock_init(&od->lock);
  486. tasklet_init(&od->task, omap_dma_sched, (unsigned long)od);
  487. for (i = 0; i < 127; i++) {
  488. rc = omap_dma_chan_init(od, i);
  489. if (rc) {
  490. omap_dma_free(od);
  491. return rc;
  492. }
  493. }
  494. rc = dma_async_device_register(&od->ddev);
  495. if (rc) {
  496. pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n",
  497. rc);
  498. omap_dma_free(od);
  499. } else {
  500. platform_set_drvdata(pdev, od);
  501. }
  502. dev_info(&pdev->dev, "OMAP DMA engine driver\n");
  503. return rc;
  504. }
  505. static int omap_dma_remove(struct platform_device *pdev)
  506. {
  507. struct omap_dmadev *od = platform_get_drvdata(pdev);
  508. dma_async_device_unregister(&od->ddev);
  509. omap_dma_free(od);
  510. return 0;
  511. }
  512. static struct platform_driver omap_dma_driver = {
  513. .probe = omap_dma_probe,
  514. .remove = omap_dma_remove,
  515. .driver = {
  516. .name = "omap-dma-engine",
  517. .owner = THIS_MODULE,
  518. },
  519. };
  520. bool omap_dma_filter_fn(struct dma_chan *chan, void *param)
  521. {
  522. if (chan->device->dev->driver == &omap_dma_driver.driver) {
  523. struct omap_chan *c = to_omap_dma_chan(chan);
  524. unsigned req = *(unsigned *)param;
  525. return req == c->dma_sig;
  526. }
  527. return false;
  528. }
  529. EXPORT_SYMBOL_GPL(omap_dma_filter_fn);
  530. static struct platform_device *pdev;
  531. static const struct platform_device_info omap_dma_dev_info = {
  532. .name = "omap-dma-engine",
  533. .id = -1,
  534. .dma_mask = DMA_BIT_MASK(32),
  535. };
  536. static int omap_dma_init(void)
  537. {
  538. int rc = platform_driver_register(&omap_dma_driver);
  539. if (rc == 0) {
  540. pdev = platform_device_register_full(&omap_dma_dev_info);
  541. if (IS_ERR(pdev)) {
  542. platform_driver_unregister(&omap_dma_driver);
  543. rc = PTR_ERR(pdev);
  544. }
  545. }
  546. return rc;
  547. }
  548. subsys_initcall(omap_dma_init);
  549. static void __exit omap_dma_exit(void)
  550. {
  551. platform_device_unregister(pdev);
  552. platform_driver_unregister(&omap_dma_driver);
  553. }
  554. module_exit(omap_dma_exit);
  555. MODULE_AUTHOR("Russell King");
  556. MODULE_LICENSE("GPL");