atmel-tdes.c 30 KB

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  1. /*
  2. * Cryptographic API.
  3. *
  4. * Support for ATMEL DES/TDES HW acceleration.
  5. *
  6. * Copyright (c) 2012 Eukréa Electromatique - ATMEL
  7. * Author: Nicolas Royer <nicolas@eukrea.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. *
  13. * Some ideas are from omap-aes.c drivers.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/slab.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <linux/hw_random.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/device.h>
  24. #include <linux/module.h>
  25. #include <linux/init.h>
  26. #include <linux/errno.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel.h>
  29. #include <linux/clk.h>
  30. #include <linux/irq.h>
  31. #include <linux/io.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/scatterlist.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/crypto.h>
  37. #include <linux/cryptohash.h>
  38. #include <crypto/scatterwalk.h>
  39. #include <crypto/algapi.h>
  40. #include <crypto/des.h>
  41. #include <crypto/hash.h>
  42. #include <crypto/internal/hash.h>
  43. #include "atmel-tdes-regs.h"
  44. /* TDES flags */
  45. #define TDES_FLAGS_MODE_MASK 0x007f
  46. #define TDES_FLAGS_ENCRYPT BIT(0)
  47. #define TDES_FLAGS_CBC BIT(1)
  48. #define TDES_FLAGS_CFB BIT(2)
  49. #define TDES_FLAGS_CFB8 BIT(3)
  50. #define TDES_FLAGS_CFB16 BIT(4)
  51. #define TDES_FLAGS_CFB32 BIT(5)
  52. #define TDES_FLAGS_OFB BIT(6)
  53. #define TDES_FLAGS_INIT BIT(16)
  54. #define TDES_FLAGS_FAST BIT(17)
  55. #define TDES_FLAGS_BUSY BIT(18)
  56. #define ATMEL_TDES_QUEUE_LENGTH 1
  57. #define CFB8_BLOCK_SIZE 1
  58. #define CFB16_BLOCK_SIZE 2
  59. #define CFB32_BLOCK_SIZE 4
  60. #define CFB64_BLOCK_SIZE 8
  61. struct atmel_tdes_dev;
  62. struct atmel_tdes_ctx {
  63. struct atmel_tdes_dev *dd;
  64. int keylen;
  65. u32 key[3*DES_KEY_SIZE / sizeof(u32)];
  66. unsigned long flags;
  67. };
  68. struct atmel_tdes_reqctx {
  69. unsigned long mode;
  70. };
  71. struct atmel_tdes_dev {
  72. struct list_head list;
  73. unsigned long phys_base;
  74. void __iomem *io_base;
  75. struct atmel_tdes_ctx *ctx;
  76. struct device *dev;
  77. struct clk *iclk;
  78. int irq;
  79. unsigned long flags;
  80. int err;
  81. spinlock_t lock;
  82. struct crypto_queue queue;
  83. struct tasklet_struct done_task;
  84. struct tasklet_struct queue_task;
  85. struct ablkcipher_request *req;
  86. size_t total;
  87. struct scatterlist *in_sg;
  88. size_t in_offset;
  89. struct scatterlist *out_sg;
  90. size_t out_offset;
  91. size_t buflen;
  92. size_t dma_size;
  93. void *buf_in;
  94. int dma_in;
  95. dma_addr_t dma_addr_in;
  96. void *buf_out;
  97. int dma_out;
  98. dma_addr_t dma_addr_out;
  99. };
  100. struct atmel_tdes_drv {
  101. struct list_head dev_list;
  102. spinlock_t lock;
  103. };
  104. static struct atmel_tdes_drv atmel_tdes = {
  105. .dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list),
  106. .lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock),
  107. };
  108. static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset,
  109. void *buf, size_t buflen, size_t total, int out)
  110. {
  111. unsigned int count, off = 0;
  112. while (buflen && total) {
  113. count = min((*sg)->length - *offset, total);
  114. count = min(count, buflen);
  115. if (!count)
  116. return off;
  117. scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out);
  118. off += count;
  119. buflen -= count;
  120. *offset += count;
  121. total -= count;
  122. if (*offset == (*sg)->length) {
  123. *sg = sg_next(*sg);
  124. if (*sg)
  125. *offset = 0;
  126. else
  127. total = 0;
  128. }
  129. }
  130. return off;
  131. }
  132. static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset)
  133. {
  134. return readl_relaxed(dd->io_base + offset);
  135. }
  136. static inline void atmel_tdes_write(struct atmel_tdes_dev *dd,
  137. u32 offset, u32 value)
  138. {
  139. writel_relaxed(value, dd->io_base + offset);
  140. }
  141. static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset,
  142. u32 *value, int count)
  143. {
  144. for (; count--; value++, offset += 4)
  145. atmel_tdes_write(dd, offset, *value);
  146. }
  147. static struct atmel_tdes_dev *atmel_tdes_find_dev(struct atmel_tdes_ctx *ctx)
  148. {
  149. struct atmel_tdes_dev *tdes_dd = NULL;
  150. struct atmel_tdes_dev *tmp;
  151. spin_lock_bh(&atmel_tdes.lock);
  152. if (!ctx->dd) {
  153. list_for_each_entry(tmp, &atmel_tdes.dev_list, list) {
  154. tdes_dd = tmp;
  155. break;
  156. }
  157. ctx->dd = tdes_dd;
  158. } else {
  159. tdes_dd = ctx->dd;
  160. }
  161. spin_unlock_bh(&atmel_tdes.lock);
  162. return tdes_dd;
  163. }
  164. static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd)
  165. {
  166. clk_prepare_enable(dd->iclk);
  167. if (!(dd->flags & TDES_FLAGS_INIT)) {
  168. atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST);
  169. dd->flags |= TDES_FLAGS_INIT;
  170. dd->err = 0;
  171. }
  172. return 0;
  173. }
  174. static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd)
  175. {
  176. int err;
  177. u32 valcr = 0, valmr = TDES_MR_SMOD_PDC;
  178. err = atmel_tdes_hw_init(dd);
  179. if (err)
  180. return err;
  181. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
  182. /* MR register must be set before IV registers */
  183. if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) {
  184. valmr |= TDES_MR_KEYMOD_3KEY;
  185. valmr |= TDES_MR_TDESMOD_TDES;
  186. } else if (dd->ctx->keylen > DES_KEY_SIZE) {
  187. valmr |= TDES_MR_KEYMOD_2KEY;
  188. valmr |= TDES_MR_TDESMOD_TDES;
  189. } else {
  190. valmr |= TDES_MR_TDESMOD_DES;
  191. }
  192. if (dd->flags & TDES_FLAGS_CBC) {
  193. valmr |= TDES_MR_OPMOD_CBC;
  194. } else if (dd->flags & TDES_FLAGS_CFB) {
  195. valmr |= TDES_MR_OPMOD_CFB;
  196. if (dd->flags & TDES_FLAGS_CFB8)
  197. valmr |= TDES_MR_CFBS_8b;
  198. else if (dd->flags & TDES_FLAGS_CFB16)
  199. valmr |= TDES_MR_CFBS_16b;
  200. else if (dd->flags & TDES_FLAGS_CFB32)
  201. valmr |= TDES_MR_CFBS_32b;
  202. } else if (dd->flags & TDES_FLAGS_OFB) {
  203. valmr |= TDES_MR_OPMOD_OFB;
  204. }
  205. if ((dd->flags & TDES_FLAGS_ENCRYPT) || (dd->flags & TDES_FLAGS_OFB))
  206. valmr |= TDES_MR_CYPHER_ENC;
  207. atmel_tdes_write(dd, TDES_CR, valcr);
  208. atmel_tdes_write(dd, TDES_MR, valmr);
  209. atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key,
  210. dd->ctx->keylen >> 2);
  211. if (((dd->flags & TDES_FLAGS_CBC) || (dd->flags & TDES_FLAGS_CFB) ||
  212. (dd->flags & TDES_FLAGS_OFB)) && dd->req->info) {
  213. atmel_tdes_write_n(dd, TDES_IV1R, dd->req->info, 2);
  214. }
  215. return 0;
  216. }
  217. static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd)
  218. {
  219. int err = 0;
  220. size_t count;
  221. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
  222. if (dd->flags & TDES_FLAGS_FAST) {
  223. dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
  224. dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
  225. } else {
  226. dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
  227. dd->dma_size, DMA_FROM_DEVICE);
  228. /* copy data */
  229. count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
  230. dd->buf_out, dd->buflen, dd->dma_size, 1);
  231. if (count != dd->dma_size) {
  232. err = -EINVAL;
  233. pr_err("not all data converted: %u\n", count);
  234. }
  235. }
  236. return err;
  237. }
  238. static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
  239. {
  240. int err = -ENOMEM;
  241. dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0);
  242. dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0);
  243. dd->buflen = PAGE_SIZE;
  244. dd->buflen &= ~(DES_BLOCK_SIZE - 1);
  245. if (!dd->buf_in || !dd->buf_out) {
  246. dev_err(dd->dev, "unable to alloc pages.\n");
  247. goto err_alloc;
  248. }
  249. /* MAP here */
  250. dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
  251. dd->buflen, DMA_TO_DEVICE);
  252. if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
  253. dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
  254. err = -EINVAL;
  255. goto err_map_in;
  256. }
  257. dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
  258. dd->buflen, DMA_FROM_DEVICE);
  259. if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
  260. dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
  261. err = -EINVAL;
  262. goto err_map_out;
  263. }
  264. return 0;
  265. err_map_out:
  266. dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
  267. DMA_TO_DEVICE);
  268. err_map_in:
  269. free_page((unsigned long)dd->buf_out);
  270. free_page((unsigned long)dd->buf_in);
  271. err_alloc:
  272. if (err)
  273. pr_err("error: %d\n", err);
  274. return err;
  275. }
  276. static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd)
  277. {
  278. dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
  279. DMA_FROM_DEVICE);
  280. dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
  281. DMA_TO_DEVICE);
  282. free_page((unsigned long)dd->buf_out);
  283. free_page((unsigned long)dd->buf_in);
  284. }
  285. static int atmel_tdes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
  286. dma_addr_t dma_addr_out, int length)
  287. {
  288. struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm);
  289. struct atmel_tdes_dev *dd = ctx->dd;
  290. int len32;
  291. dd->dma_size = length;
  292. if (!(dd->flags & TDES_FLAGS_FAST)) {
  293. dma_sync_single_for_device(dd->dev, dma_addr_in, length,
  294. DMA_TO_DEVICE);
  295. }
  296. if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB8))
  297. len32 = DIV_ROUND_UP(length, sizeof(u8));
  298. else if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB16))
  299. len32 = DIV_ROUND_UP(length, sizeof(u16));
  300. else
  301. len32 = DIV_ROUND_UP(length, sizeof(u32));
  302. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
  303. atmel_tdes_write(dd, TDES_TPR, dma_addr_in);
  304. atmel_tdes_write(dd, TDES_TCR, len32);
  305. atmel_tdes_write(dd, TDES_RPR, dma_addr_out);
  306. atmel_tdes_write(dd, TDES_RCR, len32);
  307. /* Enable Interrupt */
  308. atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX);
  309. /* Start DMA transfer */
  310. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN);
  311. return 0;
  312. }
  313. static int atmel_tdes_crypt_dma_start(struct atmel_tdes_dev *dd)
  314. {
  315. struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
  316. crypto_ablkcipher_reqtfm(dd->req));
  317. int err, fast = 0, in, out;
  318. size_t count;
  319. dma_addr_t addr_in, addr_out;
  320. if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
  321. /* check for alignment */
  322. in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
  323. out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
  324. fast = in && out;
  325. }
  326. if (fast) {
  327. count = min(dd->total, sg_dma_len(dd->in_sg));
  328. count = min(count, sg_dma_len(dd->out_sg));
  329. if (count != dd->total) {
  330. pr_err("request length != buffer length\n");
  331. return -EINVAL;
  332. }
  333. err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
  334. if (!err) {
  335. dev_err(dd->dev, "dma_map_sg() error\n");
  336. return -EINVAL;
  337. }
  338. err = dma_map_sg(dd->dev, dd->out_sg, 1,
  339. DMA_FROM_DEVICE);
  340. if (!err) {
  341. dev_err(dd->dev, "dma_map_sg() error\n");
  342. dma_unmap_sg(dd->dev, dd->in_sg, 1,
  343. DMA_TO_DEVICE);
  344. return -EINVAL;
  345. }
  346. addr_in = sg_dma_address(dd->in_sg);
  347. addr_out = sg_dma_address(dd->out_sg);
  348. dd->flags |= TDES_FLAGS_FAST;
  349. } else {
  350. /* use cache buffers */
  351. count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset,
  352. dd->buf_in, dd->buflen, dd->total, 0);
  353. addr_in = dd->dma_addr_in;
  354. addr_out = dd->dma_addr_out;
  355. dd->flags &= ~TDES_FLAGS_FAST;
  356. }
  357. dd->total -= count;
  358. err = atmel_tdes_crypt_dma(tfm, addr_in, addr_out, count);
  359. if (err) {
  360. dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
  361. dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
  362. }
  363. return err;
  364. }
  365. static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err)
  366. {
  367. struct ablkcipher_request *req = dd->req;
  368. clk_disable_unprepare(dd->iclk);
  369. dd->flags &= ~TDES_FLAGS_BUSY;
  370. req->base.complete(&req->base, err);
  371. }
  372. static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd,
  373. struct ablkcipher_request *req)
  374. {
  375. struct crypto_async_request *async_req, *backlog;
  376. struct atmel_tdes_ctx *ctx;
  377. struct atmel_tdes_reqctx *rctx;
  378. unsigned long flags;
  379. int err, ret = 0;
  380. spin_lock_irqsave(&dd->lock, flags);
  381. if (req)
  382. ret = ablkcipher_enqueue_request(&dd->queue, req);
  383. if (dd->flags & TDES_FLAGS_BUSY) {
  384. spin_unlock_irqrestore(&dd->lock, flags);
  385. return ret;
  386. }
  387. backlog = crypto_get_backlog(&dd->queue);
  388. async_req = crypto_dequeue_request(&dd->queue);
  389. if (async_req)
  390. dd->flags |= TDES_FLAGS_BUSY;
  391. spin_unlock_irqrestore(&dd->lock, flags);
  392. if (!async_req)
  393. return ret;
  394. if (backlog)
  395. backlog->complete(backlog, -EINPROGRESS);
  396. req = ablkcipher_request_cast(async_req);
  397. /* assign new request to device */
  398. dd->req = req;
  399. dd->total = req->nbytes;
  400. dd->in_offset = 0;
  401. dd->in_sg = req->src;
  402. dd->out_offset = 0;
  403. dd->out_sg = req->dst;
  404. rctx = ablkcipher_request_ctx(req);
  405. ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
  406. rctx->mode &= TDES_FLAGS_MODE_MASK;
  407. dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode;
  408. dd->ctx = ctx;
  409. ctx->dd = dd;
  410. err = atmel_tdes_write_ctrl(dd);
  411. if (!err)
  412. err = atmel_tdes_crypt_dma_start(dd);
  413. if (err) {
  414. /* des_task will not finish it, so do it here */
  415. atmel_tdes_finish_req(dd, err);
  416. tasklet_schedule(&dd->queue_task);
  417. }
  418. return ret;
  419. }
  420. static int atmel_tdes_crypt(struct ablkcipher_request *req, unsigned long mode)
  421. {
  422. struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(
  423. crypto_ablkcipher_reqtfm(req));
  424. struct atmel_tdes_reqctx *rctx = ablkcipher_request_ctx(req);
  425. struct atmel_tdes_dev *dd;
  426. if (mode & TDES_FLAGS_CFB8) {
  427. if (!IS_ALIGNED(req->nbytes, CFB8_BLOCK_SIZE)) {
  428. pr_err("request size is not exact amount of CFB8 blocks\n");
  429. return -EINVAL;
  430. }
  431. } else if (mode & TDES_FLAGS_CFB16) {
  432. if (!IS_ALIGNED(req->nbytes, CFB16_BLOCK_SIZE)) {
  433. pr_err("request size is not exact amount of CFB16 blocks\n");
  434. return -EINVAL;
  435. }
  436. } else if (mode & TDES_FLAGS_CFB32) {
  437. if (!IS_ALIGNED(req->nbytes, CFB32_BLOCK_SIZE)) {
  438. pr_err("request size is not exact amount of CFB32 blocks\n");
  439. return -EINVAL;
  440. }
  441. } else if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
  442. pr_err("request size is not exact amount of DES blocks\n");
  443. return -EINVAL;
  444. }
  445. dd = atmel_tdes_find_dev(ctx);
  446. if (!dd)
  447. return -ENODEV;
  448. rctx->mode = mode;
  449. return atmel_tdes_handle_queue(dd, req);
  450. }
  451. static int atmel_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
  452. unsigned int keylen)
  453. {
  454. u32 tmp[DES_EXPKEY_WORDS];
  455. int err;
  456. struct crypto_tfm *ctfm = crypto_ablkcipher_tfm(tfm);
  457. struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
  458. if (keylen != DES_KEY_SIZE) {
  459. crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  460. return -EINVAL;
  461. }
  462. err = des_ekey(tmp, key);
  463. if (err == 0 && (ctfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
  464. ctfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
  465. return -EINVAL;
  466. }
  467. memcpy(ctx->key, key, keylen);
  468. ctx->keylen = keylen;
  469. return 0;
  470. }
  471. static int atmel_tdes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
  472. unsigned int keylen)
  473. {
  474. struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
  475. const char *alg_name;
  476. alg_name = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm));
  477. /*
  478. * HW bug in cfb 3-keys mode.
  479. */
  480. if (strstr(alg_name, "cfb") && (keylen != 2*DES_KEY_SIZE)) {
  481. crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  482. return -EINVAL;
  483. } else if ((keylen != 2*DES_KEY_SIZE) && (keylen != 3*DES_KEY_SIZE)) {
  484. crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  485. return -EINVAL;
  486. }
  487. memcpy(ctx->key, key, keylen);
  488. ctx->keylen = keylen;
  489. return 0;
  490. }
  491. static int atmel_tdes_ecb_encrypt(struct ablkcipher_request *req)
  492. {
  493. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT);
  494. }
  495. static int atmel_tdes_ecb_decrypt(struct ablkcipher_request *req)
  496. {
  497. return atmel_tdes_crypt(req, 0);
  498. }
  499. static int atmel_tdes_cbc_encrypt(struct ablkcipher_request *req)
  500. {
  501. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CBC);
  502. }
  503. static int atmel_tdes_cbc_decrypt(struct ablkcipher_request *req)
  504. {
  505. return atmel_tdes_crypt(req, TDES_FLAGS_CBC);
  506. }
  507. static int atmel_tdes_cfb_encrypt(struct ablkcipher_request *req)
  508. {
  509. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB);
  510. }
  511. static int atmel_tdes_cfb_decrypt(struct ablkcipher_request *req)
  512. {
  513. return atmel_tdes_crypt(req, TDES_FLAGS_CFB);
  514. }
  515. static int atmel_tdes_cfb8_encrypt(struct ablkcipher_request *req)
  516. {
  517. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB |
  518. TDES_FLAGS_CFB8);
  519. }
  520. static int atmel_tdes_cfb8_decrypt(struct ablkcipher_request *req)
  521. {
  522. return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB8);
  523. }
  524. static int atmel_tdes_cfb16_encrypt(struct ablkcipher_request *req)
  525. {
  526. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB |
  527. TDES_FLAGS_CFB16);
  528. }
  529. static int atmel_tdes_cfb16_decrypt(struct ablkcipher_request *req)
  530. {
  531. return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB16);
  532. }
  533. static int atmel_tdes_cfb32_encrypt(struct ablkcipher_request *req)
  534. {
  535. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB |
  536. TDES_FLAGS_CFB32);
  537. }
  538. static int atmel_tdes_cfb32_decrypt(struct ablkcipher_request *req)
  539. {
  540. return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB32);
  541. }
  542. static int atmel_tdes_ofb_encrypt(struct ablkcipher_request *req)
  543. {
  544. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_OFB);
  545. }
  546. static int atmel_tdes_ofb_decrypt(struct ablkcipher_request *req)
  547. {
  548. return atmel_tdes_crypt(req, TDES_FLAGS_OFB);
  549. }
  550. static int atmel_tdes_cra_init(struct crypto_tfm *tfm)
  551. {
  552. tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_tdes_reqctx);
  553. return 0;
  554. }
  555. static void atmel_tdes_cra_exit(struct crypto_tfm *tfm)
  556. {
  557. }
  558. static struct crypto_alg tdes_algs[] = {
  559. {
  560. .cra_name = "ecb(des)",
  561. .cra_driver_name = "atmel-ecb-des",
  562. .cra_priority = 100,
  563. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  564. .cra_blocksize = DES_BLOCK_SIZE,
  565. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  566. .cra_alignmask = 0,
  567. .cra_type = &crypto_ablkcipher_type,
  568. .cra_module = THIS_MODULE,
  569. .cra_init = atmel_tdes_cra_init,
  570. .cra_exit = atmel_tdes_cra_exit,
  571. .cra_u.ablkcipher = {
  572. .min_keysize = DES_KEY_SIZE,
  573. .max_keysize = DES_KEY_SIZE,
  574. .setkey = atmel_des_setkey,
  575. .encrypt = atmel_tdes_ecb_encrypt,
  576. .decrypt = atmel_tdes_ecb_decrypt,
  577. }
  578. },
  579. {
  580. .cra_name = "cbc(des)",
  581. .cra_driver_name = "atmel-cbc-des",
  582. .cra_priority = 100,
  583. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  584. .cra_blocksize = DES_BLOCK_SIZE,
  585. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  586. .cra_alignmask = 0,
  587. .cra_type = &crypto_ablkcipher_type,
  588. .cra_module = THIS_MODULE,
  589. .cra_init = atmel_tdes_cra_init,
  590. .cra_exit = atmel_tdes_cra_exit,
  591. .cra_u.ablkcipher = {
  592. .min_keysize = DES_KEY_SIZE,
  593. .max_keysize = DES_KEY_SIZE,
  594. .ivsize = DES_BLOCK_SIZE,
  595. .setkey = atmel_des_setkey,
  596. .encrypt = atmel_tdes_cbc_encrypt,
  597. .decrypt = atmel_tdes_cbc_decrypt,
  598. }
  599. },
  600. {
  601. .cra_name = "cfb(des)",
  602. .cra_driver_name = "atmel-cfb-des",
  603. .cra_priority = 100,
  604. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  605. .cra_blocksize = DES_BLOCK_SIZE,
  606. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  607. .cra_alignmask = 0,
  608. .cra_type = &crypto_ablkcipher_type,
  609. .cra_module = THIS_MODULE,
  610. .cra_init = atmel_tdes_cra_init,
  611. .cra_exit = atmel_tdes_cra_exit,
  612. .cra_u.ablkcipher = {
  613. .min_keysize = DES_KEY_SIZE,
  614. .max_keysize = DES_KEY_SIZE,
  615. .ivsize = DES_BLOCK_SIZE,
  616. .setkey = atmel_des_setkey,
  617. .encrypt = atmel_tdes_cfb_encrypt,
  618. .decrypt = atmel_tdes_cfb_decrypt,
  619. }
  620. },
  621. {
  622. .cra_name = "cfb8(des)",
  623. .cra_driver_name = "atmel-cfb8-des",
  624. .cra_priority = 100,
  625. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  626. .cra_blocksize = CFB8_BLOCK_SIZE,
  627. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  628. .cra_alignmask = 0,
  629. .cra_type = &crypto_ablkcipher_type,
  630. .cra_module = THIS_MODULE,
  631. .cra_init = atmel_tdes_cra_init,
  632. .cra_exit = atmel_tdes_cra_exit,
  633. .cra_u.ablkcipher = {
  634. .min_keysize = DES_KEY_SIZE,
  635. .max_keysize = DES_KEY_SIZE,
  636. .ivsize = DES_BLOCK_SIZE,
  637. .setkey = atmel_des_setkey,
  638. .encrypt = atmel_tdes_cfb8_encrypt,
  639. .decrypt = atmel_tdes_cfb8_decrypt,
  640. }
  641. },
  642. {
  643. .cra_name = "cfb16(des)",
  644. .cra_driver_name = "atmel-cfb16-des",
  645. .cra_priority = 100,
  646. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  647. .cra_blocksize = CFB16_BLOCK_SIZE,
  648. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  649. .cra_alignmask = 0,
  650. .cra_type = &crypto_ablkcipher_type,
  651. .cra_module = THIS_MODULE,
  652. .cra_init = atmel_tdes_cra_init,
  653. .cra_exit = atmel_tdes_cra_exit,
  654. .cra_u.ablkcipher = {
  655. .min_keysize = DES_KEY_SIZE,
  656. .max_keysize = DES_KEY_SIZE,
  657. .ivsize = DES_BLOCK_SIZE,
  658. .setkey = atmel_des_setkey,
  659. .encrypt = atmel_tdes_cfb16_encrypt,
  660. .decrypt = atmel_tdes_cfb16_decrypt,
  661. }
  662. },
  663. {
  664. .cra_name = "cfb32(des)",
  665. .cra_driver_name = "atmel-cfb32-des",
  666. .cra_priority = 100,
  667. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  668. .cra_blocksize = CFB32_BLOCK_SIZE,
  669. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  670. .cra_alignmask = 0,
  671. .cra_type = &crypto_ablkcipher_type,
  672. .cra_module = THIS_MODULE,
  673. .cra_init = atmel_tdes_cra_init,
  674. .cra_exit = atmel_tdes_cra_exit,
  675. .cra_u.ablkcipher = {
  676. .min_keysize = DES_KEY_SIZE,
  677. .max_keysize = DES_KEY_SIZE,
  678. .ivsize = DES_BLOCK_SIZE,
  679. .setkey = atmel_des_setkey,
  680. .encrypt = atmel_tdes_cfb32_encrypt,
  681. .decrypt = atmel_tdes_cfb32_decrypt,
  682. }
  683. },
  684. {
  685. .cra_name = "ofb(des)",
  686. .cra_driver_name = "atmel-ofb-des",
  687. .cra_priority = 100,
  688. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  689. .cra_blocksize = DES_BLOCK_SIZE,
  690. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  691. .cra_alignmask = 0,
  692. .cra_type = &crypto_ablkcipher_type,
  693. .cra_module = THIS_MODULE,
  694. .cra_init = atmel_tdes_cra_init,
  695. .cra_exit = atmel_tdes_cra_exit,
  696. .cra_u.ablkcipher = {
  697. .min_keysize = DES_KEY_SIZE,
  698. .max_keysize = DES_KEY_SIZE,
  699. .ivsize = DES_BLOCK_SIZE,
  700. .setkey = atmel_des_setkey,
  701. .encrypt = atmel_tdes_ofb_encrypt,
  702. .decrypt = atmel_tdes_ofb_decrypt,
  703. }
  704. },
  705. {
  706. .cra_name = "ecb(des3_ede)",
  707. .cra_driver_name = "atmel-ecb-tdes",
  708. .cra_priority = 100,
  709. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  710. .cra_blocksize = DES_BLOCK_SIZE,
  711. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  712. .cra_alignmask = 0,
  713. .cra_type = &crypto_ablkcipher_type,
  714. .cra_module = THIS_MODULE,
  715. .cra_init = atmel_tdes_cra_init,
  716. .cra_exit = atmel_tdes_cra_exit,
  717. .cra_u.ablkcipher = {
  718. .min_keysize = 2 * DES_KEY_SIZE,
  719. .max_keysize = 3 * DES_KEY_SIZE,
  720. .setkey = atmel_tdes_setkey,
  721. .encrypt = atmel_tdes_ecb_encrypt,
  722. .decrypt = atmel_tdes_ecb_decrypt,
  723. }
  724. },
  725. {
  726. .cra_name = "cbc(des3_ede)",
  727. .cra_driver_name = "atmel-cbc-tdes",
  728. .cra_priority = 100,
  729. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  730. .cra_blocksize = DES_BLOCK_SIZE,
  731. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  732. .cra_alignmask = 0,
  733. .cra_type = &crypto_ablkcipher_type,
  734. .cra_module = THIS_MODULE,
  735. .cra_init = atmel_tdes_cra_init,
  736. .cra_exit = atmel_tdes_cra_exit,
  737. .cra_u.ablkcipher = {
  738. .min_keysize = 2*DES_KEY_SIZE,
  739. .max_keysize = 3*DES_KEY_SIZE,
  740. .ivsize = DES_BLOCK_SIZE,
  741. .setkey = atmel_tdes_setkey,
  742. .encrypt = atmel_tdes_cbc_encrypt,
  743. .decrypt = atmel_tdes_cbc_decrypt,
  744. }
  745. },
  746. {
  747. .cra_name = "cfb(des3_ede)",
  748. .cra_driver_name = "atmel-cfb-tdes",
  749. .cra_priority = 100,
  750. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  751. .cra_blocksize = DES_BLOCK_SIZE,
  752. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  753. .cra_alignmask = 0,
  754. .cra_type = &crypto_ablkcipher_type,
  755. .cra_module = THIS_MODULE,
  756. .cra_init = atmel_tdes_cra_init,
  757. .cra_exit = atmel_tdes_cra_exit,
  758. .cra_u.ablkcipher = {
  759. .min_keysize = 2*DES_KEY_SIZE,
  760. .max_keysize = 2*DES_KEY_SIZE,
  761. .ivsize = DES_BLOCK_SIZE,
  762. .setkey = atmel_tdes_setkey,
  763. .encrypt = atmel_tdes_cfb_encrypt,
  764. .decrypt = atmel_tdes_cfb_decrypt,
  765. }
  766. },
  767. {
  768. .cra_name = "cfb8(des3_ede)",
  769. .cra_driver_name = "atmel-cfb8-tdes",
  770. .cra_priority = 100,
  771. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  772. .cra_blocksize = CFB8_BLOCK_SIZE,
  773. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  774. .cra_alignmask = 0,
  775. .cra_type = &crypto_ablkcipher_type,
  776. .cra_module = THIS_MODULE,
  777. .cra_init = atmel_tdes_cra_init,
  778. .cra_exit = atmel_tdes_cra_exit,
  779. .cra_u.ablkcipher = {
  780. .min_keysize = 2*DES_KEY_SIZE,
  781. .max_keysize = 2*DES_KEY_SIZE,
  782. .ivsize = DES_BLOCK_SIZE,
  783. .setkey = atmel_tdes_setkey,
  784. .encrypt = atmel_tdes_cfb8_encrypt,
  785. .decrypt = atmel_tdes_cfb8_decrypt,
  786. }
  787. },
  788. {
  789. .cra_name = "cfb16(des3_ede)",
  790. .cra_driver_name = "atmel-cfb16-tdes",
  791. .cra_priority = 100,
  792. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  793. .cra_blocksize = CFB16_BLOCK_SIZE,
  794. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  795. .cra_alignmask = 0,
  796. .cra_type = &crypto_ablkcipher_type,
  797. .cra_module = THIS_MODULE,
  798. .cra_init = atmel_tdes_cra_init,
  799. .cra_exit = atmel_tdes_cra_exit,
  800. .cra_u.ablkcipher = {
  801. .min_keysize = 2*DES_KEY_SIZE,
  802. .max_keysize = 2*DES_KEY_SIZE,
  803. .ivsize = DES_BLOCK_SIZE,
  804. .setkey = atmel_tdes_setkey,
  805. .encrypt = atmel_tdes_cfb16_encrypt,
  806. .decrypt = atmel_tdes_cfb16_decrypt,
  807. }
  808. },
  809. {
  810. .cra_name = "cfb32(des3_ede)",
  811. .cra_driver_name = "atmel-cfb32-tdes",
  812. .cra_priority = 100,
  813. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  814. .cra_blocksize = CFB32_BLOCK_SIZE,
  815. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  816. .cra_alignmask = 0,
  817. .cra_type = &crypto_ablkcipher_type,
  818. .cra_module = THIS_MODULE,
  819. .cra_init = atmel_tdes_cra_init,
  820. .cra_exit = atmel_tdes_cra_exit,
  821. .cra_u.ablkcipher = {
  822. .min_keysize = 2*DES_KEY_SIZE,
  823. .max_keysize = 2*DES_KEY_SIZE,
  824. .ivsize = DES_BLOCK_SIZE,
  825. .setkey = atmel_tdes_setkey,
  826. .encrypt = atmel_tdes_cfb32_encrypt,
  827. .decrypt = atmel_tdes_cfb32_decrypt,
  828. }
  829. },
  830. {
  831. .cra_name = "ofb(des3_ede)",
  832. .cra_driver_name = "atmel-ofb-tdes",
  833. .cra_priority = 100,
  834. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  835. .cra_blocksize = DES_BLOCK_SIZE,
  836. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  837. .cra_alignmask = 0,
  838. .cra_type = &crypto_ablkcipher_type,
  839. .cra_module = THIS_MODULE,
  840. .cra_init = atmel_tdes_cra_init,
  841. .cra_exit = atmel_tdes_cra_exit,
  842. .cra_u.ablkcipher = {
  843. .min_keysize = 2*DES_KEY_SIZE,
  844. .max_keysize = 3*DES_KEY_SIZE,
  845. .ivsize = DES_BLOCK_SIZE,
  846. .setkey = atmel_tdes_setkey,
  847. .encrypt = atmel_tdes_ofb_encrypt,
  848. .decrypt = atmel_tdes_ofb_decrypt,
  849. }
  850. },
  851. };
  852. static void atmel_tdes_queue_task(unsigned long data)
  853. {
  854. struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data;
  855. atmel_tdes_handle_queue(dd, NULL);
  856. }
  857. static void atmel_tdes_done_task(unsigned long data)
  858. {
  859. struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data;
  860. int err;
  861. err = atmel_tdes_crypt_dma_stop(dd);
  862. err = dd->err ? : err;
  863. if (dd->total && !err) {
  864. err = atmel_tdes_crypt_dma_start(dd);
  865. if (!err)
  866. return;
  867. }
  868. atmel_tdes_finish_req(dd, err);
  869. atmel_tdes_handle_queue(dd, NULL);
  870. }
  871. static irqreturn_t atmel_tdes_irq(int irq, void *dev_id)
  872. {
  873. struct atmel_tdes_dev *tdes_dd = dev_id;
  874. u32 reg;
  875. reg = atmel_tdes_read(tdes_dd, TDES_ISR);
  876. if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) {
  877. atmel_tdes_write(tdes_dd, TDES_IDR, reg);
  878. if (TDES_FLAGS_BUSY & tdes_dd->flags)
  879. tasklet_schedule(&tdes_dd->done_task);
  880. else
  881. dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n");
  882. return IRQ_HANDLED;
  883. }
  884. return IRQ_NONE;
  885. }
  886. static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd)
  887. {
  888. int i;
  889. for (i = 0; i < ARRAY_SIZE(tdes_algs); i++)
  890. crypto_unregister_alg(&tdes_algs[i]);
  891. }
  892. static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd)
  893. {
  894. int err, i, j;
  895. for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) {
  896. INIT_LIST_HEAD(&tdes_algs[i].cra_list);
  897. err = crypto_register_alg(&tdes_algs[i]);
  898. if (err)
  899. goto err_tdes_algs;
  900. }
  901. return 0;
  902. err_tdes_algs:
  903. for (j = 0; j < i; j++)
  904. crypto_unregister_alg(&tdes_algs[j]);
  905. return err;
  906. }
  907. static int __devinit atmel_tdes_probe(struct platform_device *pdev)
  908. {
  909. struct atmel_tdes_dev *tdes_dd;
  910. struct device *dev = &pdev->dev;
  911. struct resource *tdes_res;
  912. unsigned long tdes_phys_size;
  913. int err;
  914. tdes_dd = kzalloc(sizeof(struct atmel_tdes_dev), GFP_KERNEL);
  915. if (tdes_dd == NULL) {
  916. dev_err(dev, "unable to alloc data struct.\n");
  917. err = -ENOMEM;
  918. goto tdes_dd_err;
  919. }
  920. tdes_dd->dev = dev;
  921. platform_set_drvdata(pdev, tdes_dd);
  922. INIT_LIST_HEAD(&tdes_dd->list);
  923. tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task,
  924. (unsigned long)tdes_dd);
  925. tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task,
  926. (unsigned long)tdes_dd);
  927. crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH);
  928. tdes_dd->irq = -1;
  929. /* Get the base address */
  930. tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  931. if (!tdes_res) {
  932. dev_err(dev, "no MEM resource info\n");
  933. err = -ENODEV;
  934. goto res_err;
  935. }
  936. tdes_dd->phys_base = tdes_res->start;
  937. tdes_phys_size = resource_size(tdes_res);
  938. /* Get the IRQ */
  939. tdes_dd->irq = platform_get_irq(pdev, 0);
  940. if (tdes_dd->irq < 0) {
  941. dev_err(dev, "no IRQ resource info\n");
  942. err = tdes_dd->irq;
  943. goto res_err;
  944. }
  945. err = request_irq(tdes_dd->irq, atmel_tdes_irq, IRQF_SHARED,
  946. "atmel-tdes", tdes_dd);
  947. if (err) {
  948. dev_err(dev, "unable to request tdes irq.\n");
  949. goto tdes_irq_err;
  950. }
  951. /* Initializing the clock */
  952. tdes_dd->iclk = clk_get(&pdev->dev, NULL);
  953. if (IS_ERR(tdes_dd->iclk)) {
  954. dev_err(dev, "clock intialization failed.\n");
  955. err = PTR_ERR(tdes_dd->iclk);
  956. goto clk_err;
  957. }
  958. tdes_dd->io_base = ioremap(tdes_dd->phys_base, tdes_phys_size);
  959. if (!tdes_dd->io_base) {
  960. dev_err(dev, "can't ioremap\n");
  961. err = -ENOMEM;
  962. goto tdes_io_err;
  963. }
  964. err = atmel_tdes_dma_init(tdes_dd);
  965. if (err)
  966. goto err_tdes_dma;
  967. spin_lock(&atmel_tdes.lock);
  968. list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list);
  969. spin_unlock(&atmel_tdes.lock);
  970. err = atmel_tdes_register_algs(tdes_dd);
  971. if (err)
  972. goto err_algs;
  973. dev_info(dev, "Atmel DES/TDES\n");
  974. return 0;
  975. err_algs:
  976. spin_lock(&atmel_tdes.lock);
  977. list_del(&tdes_dd->list);
  978. spin_unlock(&atmel_tdes.lock);
  979. atmel_tdes_dma_cleanup(tdes_dd);
  980. err_tdes_dma:
  981. iounmap(tdes_dd->io_base);
  982. tdes_io_err:
  983. clk_put(tdes_dd->iclk);
  984. clk_err:
  985. free_irq(tdes_dd->irq, tdes_dd);
  986. tdes_irq_err:
  987. res_err:
  988. tasklet_kill(&tdes_dd->done_task);
  989. tasklet_kill(&tdes_dd->queue_task);
  990. kfree(tdes_dd);
  991. tdes_dd = NULL;
  992. tdes_dd_err:
  993. dev_err(dev, "initialization failed.\n");
  994. return err;
  995. }
  996. static int __devexit atmel_tdes_remove(struct platform_device *pdev)
  997. {
  998. static struct atmel_tdes_dev *tdes_dd;
  999. tdes_dd = platform_get_drvdata(pdev);
  1000. if (!tdes_dd)
  1001. return -ENODEV;
  1002. spin_lock(&atmel_tdes.lock);
  1003. list_del(&tdes_dd->list);
  1004. spin_unlock(&atmel_tdes.lock);
  1005. atmel_tdes_unregister_algs(tdes_dd);
  1006. tasklet_kill(&tdes_dd->done_task);
  1007. tasklet_kill(&tdes_dd->queue_task);
  1008. atmel_tdes_dma_cleanup(tdes_dd);
  1009. iounmap(tdes_dd->io_base);
  1010. clk_put(tdes_dd->iclk);
  1011. if (tdes_dd->irq >= 0)
  1012. free_irq(tdes_dd->irq, tdes_dd);
  1013. kfree(tdes_dd);
  1014. tdes_dd = NULL;
  1015. return 0;
  1016. }
  1017. static struct platform_driver atmel_tdes_driver = {
  1018. .probe = atmel_tdes_probe,
  1019. .remove = __devexit_p(atmel_tdes_remove),
  1020. .driver = {
  1021. .name = "atmel_tdes",
  1022. .owner = THIS_MODULE,
  1023. },
  1024. };
  1025. module_platform_driver(atmel_tdes_driver);
  1026. MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support.");
  1027. MODULE_LICENSE("GPL v2");
  1028. MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");