setup.c 17 KB

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  1. /*
  2. * Renesas - AP-325RXA
  3. * (Compatible with Algo System ., LTD. - AP-320A)
  4. *
  5. * Copyright (C) 2008 Renesas Solutions Corp.
  6. * Author : Yusuke Goda <goda.yuske@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mmc/host.h>
  17. #include <linux/mmc/sh_mobile_sdhi.h>
  18. #include <linux/mtd/physmap.h>
  19. #include <linux/mtd/sh_flctl.h>
  20. #include <linux/delay.h>
  21. #include <linux/i2c.h>
  22. #include <linux/regulator/fixed.h>
  23. #include <linux/regulator/machine.h>
  24. #include <linux/smsc911x.h>
  25. #include <linux/gpio.h>
  26. #include <linux/videodev2.h>
  27. #include <linux/sh_intc.h>
  28. #include <media/ov772x.h>
  29. #include <media/soc_camera.h>
  30. #include <media/soc_camera_platform.h>
  31. #include <media/sh_mobile_ceu.h>
  32. #include <video/sh_mobile_lcdc.h>
  33. #include <asm/io.h>
  34. #include <asm/clock.h>
  35. #include <asm/suspend.h>
  36. #include <cpu/sh7723.h>
  37. /* Dummy supplies, where voltage doesn't matter */
  38. static struct regulator_consumer_supply dummy_supplies[] = {
  39. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  40. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  41. };
  42. static struct smsc911x_platform_config smsc911x_config = {
  43. .phy_interface = PHY_INTERFACE_MODE_MII,
  44. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  45. .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
  46. .flags = SMSC911X_USE_32BIT,
  47. };
  48. static struct resource smsc9118_resources[] = {
  49. [0] = {
  50. .start = 0xb6080000,
  51. .end = 0xb60fffff,
  52. .flags = IORESOURCE_MEM,
  53. },
  54. [1] = {
  55. .start = evt2irq(0x660),
  56. .end = evt2irq(0x660),
  57. .flags = IORESOURCE_IRQ,
  58. }
  59. };
  60. static struct platform_device smsc9118_device = {
  61. .name = "smsc911x",
  62. .id = -1,
  63. .num_resources = ARRAY_SIZE(smsc9118_resources),
  64. .resource = smsc9118_resources,
  65. .dev = {
  66. .platform_data = &smsc911x_config,
  67. },
  68. };
  69. /*
  70. * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
  71. * If this area erased, this board can not boot.
  72. */
  73. static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
  74. {
  75. .name = "uboot",
  76. .offset = 0,
  77. .size = (1 * 1024 * 1024),
  78. .mask_flags = MTD_WRITEABLE, /* Read-only */
  79. }, {
  80. .name = "kernel",
  81. .offset = MTDPART_OFS_APPEND,
  82. .size = (2 * 1024 * 1024),
  83. }, {
  84. .name = "free-area0",
  85. .offset = MTDPART_OFS_APPEND,
  86. .size = ((7 * 1024 * 1024) + (512 * 1024)),
  87. }, {
  88. .name = "CPLD-Data",
  89. .offset = MTDPART_OFS_APPEND,
  90. .mask_flags = MTD_WRITEABLE, /* Read-only */
  91. .size = (1024 * 128 * 2),
  92. }, {
  93. .name = "free-area1",
  94. .offset = MTDPART_OFS_APPEND,
  95. .size = MTDPART_SIZ_FULL,
  96. },
  97. };
  98. static struct physmap_flash_data ap325rxa_nor_flash_data = {
  99. .width = 2,
  100. .parts = ap325rxa_nor_flash_partitions,
  101. .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
  102. };
  103. static struct resource ap325rxa_nor_flash_resources[] = {
  104. [0] = {
  105. .name = "NOR Flash",
  106. .start = 0x00000000,
  107. .end = 0x00ffffff,
  108. .flags = IORESOURCE_MEM,
  109. }
  110. };
  111. static struct platform_device ap325rxa_nor_flash_device = {
  112. .name = "physmap-flash",
  113. .resource = ap325rxa_nor_flash_resources,
  114. .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
  115. .dev = {
  116. .platform_data = &ap325rxa_nor_flash_data,
  117. },
  118. };
  119. static struct mtd_partition nand_partition_info[] = {
  120. {
  121. .name = "nand_data",
  122. .offset = 0,
  123. .size = MTDPART_SIZ_FULL,
  124. },
  125. };
  126. static struct resource nand_flash_resources[] = {
  127. [0] = {
  128. .start = 0xa4530000,
  129. .end = 0xa45300ff,
  130. .flags = IORESOURCE_MEM,
  131. }
  132. };
  133. static struct sh_flctl_platform_data nand_flash_data = {
  134. .parts = nand_partition_info,
  135. .nr_parts = ARRAY_SIZE(nand_partition_info),
  136. .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
  137. .has_hwecc = 1,
  138. };
  139. static struct platform_device nand_flash_device = {
  140. .name = "sh_flctl",
  141. .resource = nand_flash_resources,
  142. .num_resources = ARRAY_SIZE(nand_flash_resources),
  143. .dev = {
  144. .platform_data = &nand_flash_data,
  145. },
  146. };
  147. #define FPGA_LCDREG 0xB4100180
  148. #define FPGA_BKLREG 0xB4100212
  149. #define FPGA_LCDREG_VAL 0x0018
  150. #define PORT_MSELCRB 0xA4050182
  151. #define PORT_HIZCRC 0xA405015C
  152. #define PORT_DRVCRA 0xA405018A
  153. #define PORT_DRVCRB 0xA405018C
  154. static int ap320_wvga_set_brightness(int brightness)
  155. {
  156. if (brightness) {
  157. gpio_set_value(GPIO_PTS3, 0);
  158. __raw_writew(0x100, FPGA_BKLREG);
  159. } else {
  160. __raw_writew(0, FPGA_BKLREG);
  161. gpio_set_value(GPIO_PTS3, 1);
  162. }
  163. return 0;
  164. }
  165. static int ap320_wvga_get_brightness(void)
  166. {
  167. return gpio_get_value(GPIO_PTS3);
  168. }
  169. static void ap320_wvga_power_on(void)
  170. {
  171. msleep(100);
  172. /* ASD AP-320/325 LCD ON */
  173. __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
  174. }
  175. static void ap320_wvga_power_off(void)
  176. {
  177. /* ASD AP-320/325 LCD OFF */
  178. __raw_writew(0, FPGA_LCDREG);
  179. }
  180. static const struct fb_videomode ap325rxa_lcdc_modes[] = {
  181. {
  182. .name = "LB070WV1",
  183. .xres = 800,
  184. .yres = 480,
  185. .left_margin = 32,
  186. .right_margin = 160,
  187. .hsync_len = 8,
  188. .upper_margin = 63,
  189. .lower_margin = 80,
  190. .vsync_len = 1,
  191. .sync = 0, /* hsync and vsync are active low */
  192. },
  193. };
  194. static struct sh_mobile_lcdc_info lcdc_info = {
  195. .clock_source = LCDC_CLK_EXTERNAL,
  196. .ch[0] = {
  197. .chan = LCDC_CHAN_MAINLCD,
  198. .fourcc = V4L2_PIX_FMT_RGB565,
  199. .interface_type = RGB18,
  200. .clock_divider = 1,
  201. .lcd_modes = ap325rxa_lcdc_modes,
  202. .num_modes = ARRAY_SIZE(ap325rxa_lcdc_modes),
  203. .panel_cfg = {
  204. .width = 152, /* 7.0 inch */
  205. .height = 91,
  206. .display_on = ap320_wvga_power_on,
  207. .display_off = ap320_wvga_power_off,
  208. },
  209. .bl_info = {
  210. .name = "sh_mobile_lcdc_bl",
  211. .max_brightness = 1,
  212. .set_brightness = ap320_wvga_set_brightness,
  213. .get_brightness = ap320_wvga_get_brightness,
  214. },
  215. }
  216. };
  217. static struct resource lcdc_resources[] = {
  218. [0] = {
  219. .name = "LCDC",
  220. .start = 0xfe940000, /* P4-only space */
  221. .end = 0xfe942fff,
  222. .flags = IORESOURCE_MEM,
  223. },
  224. [1] = {
  225. .start = evt2irq(0x580),
  226. .flags = IORESOURCE_IRQ,
  227. },
  228. };
  229. static struct platform_device lcdc_device = {
  230. .name = "sh_mobile_lcdc_fb",
  231. .num_resources = ARRAY_SIZE(lcdc_resources),
  232. .resource = lcdc_resources,
  233. .dev = {
  234. .platform_data = &lcdc_info,
  235. },
  236. };
  237. static void camera_power(int val)
  238. {
  239. gpio_set_value(GPIO_PTZ5, val); /* RST_CAM/RSTB */
  240. mdelay(10);
  241. }
  242. #ifdef CONFIG_I2C
  243. /* support for the old ncm03j camera */
  244. static unsigned char camera_ncm03j_magic[] =
  245. {
  246. 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
  247. 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
  248. 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
  249. 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
  250. 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
  251. 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
  252. 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
  253. 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
  254. 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
  255. 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
  256. 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
  257. 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
  258. 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
  259. 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
  260. 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
  261. 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
  262. };
  263. static int camera_probe(void)
  264. {
  265. struct i2c_adapter *a = i2c_get_adapter(0);
  266. struct i2c_msg msg;
  267. int ret;
  268. if (!a)
  269. return -ENODEV;
  270. camera_power(1);
  271. msg.addr = 0x6e;
  272. msg.buf = camera_ncm03j_magic;
  273. msg.len = 2;
  274. msg.flags = 0;
  275. ret = i2c_transfer(a, &msg, 1);
  276. camera_power(0);
  277. return ret;
  278. }
  279. static int camera_set_capture(struct soc_camera_platform_info *info,
  280. int enable)
  281. {
  282. struct i2c_adapter *a = i2c_get_adapter(0);
  283. struct i2c_msg msg;
  284. int ret = 0;
  285. int i;
  286. camera_power(0);
  287. if (!enable)
  288. return 0; /* no disable for now */
  289. camera_power(1);
  290. for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
  291. u_int8_t buf[8];
  292. msg.addr = 0x6e;
  293. msg.buf = buf;
  294. msg.len = 2;
  295. msg.flags = 0;
  296. buf[0] = camera_ncm03j_magic[i];
  297. buf[1] = camera_ncm03j_magic[i + 1];
  298. ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
  299. }
  300. return ret;
  301. }
  302. static int ap325rxa_camera_add(struct soc_camera_device *icd);
  303. static void ap325rxa_camera_del(struct soc_camera_device *icd);
  304. static struct soc_camera_platform_info camera_info = {
  305. .format_name = "UYVY",
  306. .format_depth = 16,
  307. .format = {
  308. .code = V4L2_MBUS_FMT_UYVY8_2X8,
  309. .colorspace = V4L2_COLORSPACE_SMPTE170M,
  310. .field = V4L2_FIELD_NONE,
  311. .width = 640,
  312. .height = 480,
  313. },
  314. .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
  315. V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
  316. V4L2_MBUS_DATA_ACTIVE_HIGH,
  317. .mbus_type = V4L2_MBUS_PARALLEL,
  318. .set_capture = camera_set_capture,
  319. };
  320. static struct soc_camera_link camera_link = {
  321. .bus_id = 0,
  322. .add_device = ap325rxa_camera_add,
  323. .del_device = ap325rxa_camera_del,
  324. .module_name = "soc_camera_platform",
  325. .priv = &camera_info,
  326. };
  327. static struct platform_device *camera_device;
  328. static void ap325rxa_camera_release(struct device *dev)
  329. {
  330. soc_camera_platform_release(&camera_device);
  331. }
  332. static int ap325rxa_camera_add(struct soc_camera_device *icd)
  333. {
  334. int ret = soc_camera_platform_add(icd, &camera_device, &camera_link,
  335. ap325rxa_camera_release, 0);
  336. if (ret < 0)
  337. return ret;
  338. ret = camera_probe();
  339. if (ret < 0)
  340. soc_camera_platform_del(icd, camera_device, &camera_link);
  341. return ret;
  342. }
  343. static void ap325rxa_camera_del(struct soc_camera_device *icd)
  344. {
  345. soc_camera_platform_del(icd, camera_device, &camera_link);
  346. }
  347. #endif /* CONFIG_I2C */
  348. static int ov7725_power(struct device *dev, int mode)
  349. {
  350. camera_power(0);
  351. if (mode)
  352. camera_power(1);
  353. return 0;
  354. }
  355. static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
  356. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  357. };
  358. static struct resource ceu_resources[] = {
  359. [0] = {
  360. .name = "CEU",
  361. .start = 0xfe910000,
  362. .end = 0xfe91009f,
  363. .flags = IORESOURCE_MEM,
  364. },
  365. [1] = {
  366. .start = evt2irq(0x880),
  367. .flags = IORESOURCE_IRQ,
  368. },
  369. [2] = {
  370. /* place holder for contiguous memory */
  371. },
  372. };
  373. static struct platform_device ceu_device = {
  374. .name = "sh_mobile_ceu",
  375. .id = 0, /* "ceu0" clock */
  376. .num_resources = ARRAY_SIZE(ceu_resources),
  377. .resource = ceu_resources,
  378. .dev = {
  379. .platform_data = &sh_mobile_ceu_info,
  380. },
  381. };
  382. /* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
  383. static struct regulator_consumer_supply fixed3v3_power_consumers[] =
  384. {
  385. REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
  386. REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
  387. REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
  388. REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
  389. };
  390. static struct resource sdhi0_cn3_resources[] = {
  391. [0] = {
  392. .name = "SDHI0",
  393. .start = 0x04ce0000,
  394. .end = 0x04ce00ff,
  395. .flags = IORESOURCE_MEM,
  396. },
  397. [1] = {
  398. .start = evt2irq(0xe80),
  399. .flags = IORESOURCE_IRQ,
  400. },
  401. };
  402. static struct sh_mobile_sdhi_info sdhi0_cn3_data = {
  403. .tmio_caps = MMC_CAP_SDIO_IRQ,
  404. };
  405. static struct platform_device sdhi0_cn3_device = {
  406. .name = "sh_mobile_sdhi",
  407. .id = 0, /* "sdhi0" clock */
  408. .num_resources = ARRAY_SIZE(sdhi0_cn3_resources),
  409. .resource = sdhi0_cn3_resources,
  410. .dev = {
  411. .platform_data = &sdhi0_cn3_data,
  412. },
  413. };
  414. static struct resource sdhi1_cn7_resources[] = {
  415. [0] = {
  416. .name = "SDHI1",
  417. .start = 0x04cf0000,
  418. .end = 0x04cf00ff,
  419. .flags = IORESOURCE_MEM,
  420. },
  421. [1] = {
  422. .start = evt2irq(0x4e0),
  423. .flags = IORESOURCE_IRQ,
  424. },
  425. };
  426. static struct sh_mobile_sdhi_info sdhi1_cn7_data = {
  427. .tmio_caps = MMC_CAP_SDIO_IRQ,
  428. };
  429. static struct platform_device sdhi1_cn7_device = {
  430. .name = "sh_mobile_sdhi",
  431. .id = 1, /* "sdhi1" clock */
  432. .num_resources = ARRAY_SIZE(sdhi1_cn7_resources),
  433. .resource = sdhi1_cn7_resources,
  434. .dev = {
  435. .platform_data = &sdhi1_cn7_data,
  436. },
  437. };
  438. static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
  439. {
  440. I2C_BOARD_INFO("pcf8563", 0x51),
  441. },
  442. };
  443. static struct i2c_board_info ap325rxa_i2c_camera[] = {
  444. {
  445. I2C_BOARD_INFO("ov772x", 0x21),
  446. },
  447. };
  448. static struct ov772x_camera_info ov7725_info = {
  449. .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
  450. .edgectrl = OV772X_AUTO_EDGECTRL(0xf, 0),
  451. };
  452. static struct soc_camera_link ov7725_link = {
  453. .bus_id = 0,
  454. .power = ov7725_power,
  455. .board_info = &ap325rxa_i2c_camera[0],
  456. .i2c_adapter_id = 0,
  457. .priv = &ov7725_info,
  458. };
  459. static struct platform_device ap325rxa_camera[] = {
  460. {
  461. .name = "soc-camera-pdrv",
  462. .id = 0,
  463. .dev = {
  464. .platform_data = &ov7725_link,
  465. },
  466. }, {
  467. .name = "soc-camera-pdrv",
  468. .id = 1,
  469. .dev = {
  470. .platform_data = &camera_link,
  471. },
  472. },
  473. };
  474. static struct platform_device *ap325rxa_devices[] __initdata = {
  475. &smsc9118_device,
  476. &ap325rxa_nor_flash_device,
  477. &lcdc_device,
  478. &ceu_device,
  479. &nand_flash_device,
  480. &sdhi0_cn3_device,
  481. &sdhi1_cn7_device,
  482. &ap325rxa_camera[0],
  483. &ap325rxa_camera[1],
  484. };
  485. extern char ap325rxa_sdram_enter_start;
  486. extern char ap325rxa_sdram_enter_end;
  487. extern char ap325rxa_sdram_leave_start;
  488. extern char ap325rxa_sdram_leave_end;
  489. static int __init ap325rxa_devices_setup(void)
  490. {
  491. /* register board specific self-refresh code */
  492. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
  493. &ap325rxa_sdram_enter_start,
  494. &ap325rxa_sdram_enter_end,
  495. &ap325rxa_sdram_leave_start,
  496. &ap325rxa_sdram_leave_end);
  497. regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
  498. ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
  499. regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
  500. /* LD3 and LD4 LEDs */
  501. gpio_request(GPIO_PTX5, NULL); /* RUN */
  502. gpio_direction_output(GPIO_PTX5, 1);
  503. gpio_export(GPIO_PTX5, 0);
  504. gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
  505. gpio_direction_output(GPIO_PTX4, 0);
  506. gpio_export(GPIO_PTX4, 0);
  507. /* SW1 input */
  508. gpio_request(GPIO_PTF7, NULL); /* MODE */
  509. gpio_direction_input(GPIO_PTF7);
  510. gpio_export(GPIO_PTF7, 0);
  511. /* LCDC */
  512. gpio_request(GPIO_FN_LCDD15, NULL);
  513. gpio_request(GPIO_FN_LCDD14, NULL);
  514. gpio_request(GPIO_FN_LCDD13, NULL);
  515. gpio_request(GPIO_FN_LCDD12, NULL);
  516. gpio_request(GPIO_FN_LCDD11, NULL);
  517. gpio_request(GPIO_FN_LCDD10, NULL);
  518. gpio_request(GPIO_FN_LCDD9, NULL);
  519. gpio_request(GPIO_FN_LCDD8, NULL);
  520. gpio_request(GPIO_FN_LCDD7, NULL);
  521. gpio_request(GPIO_FN_LCDD6, NULL);
  522. gpio_request(GPIO_FN_LCDD5, NULL);
  523. gpio_request(GPIO_FN_LCDD4, NULL);
  524. gpio_request(GPIO_FN_LCDD3, NULL);
  525. gpio_request(GPIO_FN_LCDD2, NULL);
  526. gpio_request(GPIO_FN_LCDD1, NULL);
  527. gpio_request(GPIO_FN_LCDD0, NULL);
  528. gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
  529. gpio_request(GPIO_FN_LCDDCK, NULL);
  530. gpio_request(GPIO_FN_LCDVEPWC, NULL);
  531. gpio_request(GPIO_FN_LCDVCPWC, NULL);
  532. gpio_request(GPIO_FN_LCDVSYN, NULL);
  533. gpio_request(GPIO_FN_LCDHSYN, NULL);
  534. gpio_request(GPIO_FN_LCDDISP, NULL);
  535. gpio_request(GPIO_FN_LCDDON, NULL);
  536. /* LCD backlight */
  537. gpio_request(GPIO_PTS3, NULL);
  538. gpio_direction_output(GPIO_PTS3, 1);
  539. /* CEU */
  540. gpio_request(GPIO_FN_VIO_CLK2, NULL);
  541. gpio_request(GPIO_FN_VIO_VD2, NULL);
  542. gpio_request(GPIO_FN_VIO_HD2, NULL);
  543. gpio_request(GPIO_FN_VIO_FLD, NULL);
  544. gpio_request(GPIO_FN_VIO_CKO, NULL);
  545. gpio_request(GPIO_FN_VIO_D15, NULL);
  546. gpio_request(GPIO_FN_VIO_D14, NULL);
  547. gpio_request(GPIO_FN_VIO_D13, NULL);
  548. gpio_request(GPIO_FN_VIO_D12, NULL);
  549. gpio_request(GPIO_FN_VIO_D11, NULL);
  550. gpio_request(GPIO_FN_VIO_D10, NULL);
  551. gpio_request(GPIO_FN_VIO_D9, NULL);
  552. gpio_request(GPIO_FN_VIO_D8, NULL);
  553. gpio_request(GPIO_PTZ7, NULL);
  554. gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
  555. gpio_request(GPIO_PTZ6, NULL);
  556. gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
  557. gpio_request(GPIO_PTZ5, NULL);
  558. gpio_direction_output(GPIO_PTZ5, 0); /* RST_CAM */
  559. gpio_request(GPIO_PTZ4, NULL);
  560. gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
  561. __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
  562. /* FLCTL */
  563. gpio_request(GPIO_FN_FCE, NULL);
  564. gpio_request(GPIO_FN_NAF7, NULL);
  565. gpio_request(GPIO_FN_NAF6, NULL);
  566. gpio_request(GPIO_FN_NAF5, NULL);
  567. gpio_request(GPIO_FN_NAF4, NULL);
  568. gpio_request(GPIO_FN_NAF3, NULL);
  569. gpio_request(GPIO_FN_NAF2, NULL);
  570. gpio_request(GPIO_FN_NAF1, NULL);
  571. gpio_request(GPIO_FN_NAF0, NULL);
  572. gpio_request(GPIO_FN_FCDE, NULL);
  573. gpio_request(GPIO_FN_FOE, NULL);
  574. gpio_request(GPIO_FN_FSC, NULL);
  575. gpio_request(GPIO_FN_FWE, NULL);
  576. gpio_request(GPIO_FN_FRB, NULL);
  577. __raw_writew(0, PORT_HIZCRC);
  578. __raw_writew(0xFFFF, PORT_DRVCRA);
  579. __raw_writew(0xFFFF, PORT_DRVCRB);
  580. platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
  581. /* SDHI0 - CN3 - SD CARD */
  582. gpio_request(GPIO_FN_SDHI0CD_PTD, NULL);
  583. gpio_request(GPIO_FN_SDHI0WP_PTD, NULL);
  584. gpio_request(GPIO_FN_SDHI0D3_PTD, NULL);
  585. gpio_request(GPIO_FN_SDHI0D2_PTD, NULL);
  586. gpio_request(GPIO_FN_SDHI0D1_PTD, NULL);
  587. gpio_request(GPIO_FN_SDHI0D0_PTD, NULL);
  588. gpio_request(GPIO_FN_SDHI0CMD_PTD, NULL);
  589. gpio_request(GPIO_FN_SDHI0CLK_PTD, NULL);
  590. /* SDHI1 - CN7 - MICRO SD CARD */
  591. gpio_request(GPIO_FN_SDHI1CD, NULL);
  592. gpio_request(GPIO_FN_SDHI1D3, NULL);
  593. gpio_request(GPIO_FN_SDHI1D2, NULL);
  594. gpio_request(GPIO_FN_SDHI1D1, NULL);
  595. gpio_request(GPIO_FN_SDHI1D0, NULL);
  596. gpio_request(GPIO_FN_SDHI1CMD, NULL);
  597. gpio_request(GPIO_FN_SDHI1CLK, NULL);
  598. i2c_register_board_info(0, ap325rxa_i2c_devices,
  599. ARRAY_SIZE(ap325rxa_i2c_devices));
  600. return platform_add_devices(ap325rxa_devices,
  601. ARRAY_SIZE(ap325rxa_devices));
  602. }
  603. arch_initcall(ap325rxa_devices_setup);
  604. /* Return the board specific boot mode pin configuration */
  605. static int ap325rxa_mode_pins(void)
  606. {
  607. /* MD0=0, MD1=0, MD2=0: Clock Mode 0
  608. * MD3=0: 16-bit Area0 Bus Width
  609. * MD5=1: Little Endian
  610. * TSTMD=1, MD8=1: Test Mode Disabled
  611. */
  612. return MODE_PIN5 | MODE_PIN8;
  613. }
  614. static struct sh_machine_vector mv_ap325rxa __initmv = {
  615. .mv_name = "AP-325RXA",
  616. .mv_mode_pins = ap325rxa_mode_pins,
  617. };