kvm_book3s_64.h 6.1 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License, version 2, as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  14. *
  15. * Copyright SUSE Linux Products GmbH 2010
  16. *
  17. * Authors: Alexander Graf <agraf@suse.de>
  18. */
  19. #ifndef __ASM_KVM_BOOK3S_64_H__
  20. #define __ASM_KVM_BOOK3S_64_H__
  21. #ifdef CONFIG_KVM_BOOK3S_PR
  22. static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
  23. {
  24. preempt_disable();
  25. return &get_paca()->shadow_vcpu;
  26. }
  27. static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
  28. {
  29. preempt_enable();
  30. }
  31. #endif
  32. #define SPAPR_TCE_SHIFT 12
  33. #ifdef CONFIG_KVM_BOOK3S_64_HV
  34. #define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */
  35. extern int kvm_hpt_order; /* order of preallocated HPTs */
  36. #endif
  37. #define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */
  38. /*
  39. * We use a lock bit in HPTE dword 0 to synchronize updates and
  40. * accesses to each HPTE, and another bit to indicate non-present
  41. * HPTEs.
  42. */
  43. #define HPTE_V_HVLOCK 0x40UL
  44. #define HPTE_V_ABSENT 0x20UL
  45. static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
  46. {
  47. unsigned long tmp, old;
  48. asm volatile(" ldarx %0,0,%2\n"
  49. " and. %1,%0,%3\n"
  50. " bne 2f\n"
  51. " ori %0,%0,%4\n"
  52. " stdcx. %0,0,%2\n"
  53. " beq+ 2f\n"
  54. " li %1,%3\n"
  55. "2: isync"
  56. : "=&r" (tmp), "=&r" (old)
  57. : "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
  58. : "cc", "memory");
  59. return old == 0;
  60. }
  61. static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
  62. unsigned long pte_index)
  63. {
  64. unsigned long rb, va_low;
  65. rb = (v & ~0x7fUL) << 16; /* AVA field */
  66. va_low = pte_index >> 3;
  67. if (v & HPTE_V_SECONDARY)
  68. va_low = ~va_low;
  69. /* xor vsid from AVA */
  70. if (!(v & HPTE_V_1TB_SEG))
  71. va_low ^= v >> 12;
  72. else
  73. va_low ^= v >> 24;
  74. va_low &= 0x7ff;
  75. if (v & HPTE_V_LARGE) {
  76. rb |= 1; /* L field */
  77. if (cpu_has_feature(CPU_FTR_ARCH_206) &&
  78. (r & 0xff000)) {
  79. /* non-16MB large page, must be 64k */
  80. /* (masks depend on page size) */
  81. rb |= 0x1000; /* page encoding in LP field */
  82. rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
  83. rb |= (va_low & 0xfe); /* AVAL field (P7 doesn't seem to care) */
  84. }
  85. } else {
  86. /* 4kB page */
  87. rb |= (va_low & 0x7ff) << 12; /* remaining 11b of VA */
  88. }
  89. rb |= (v >> 54) & 0x300; /* B field */
  90. return rb;
  91. }
  92. static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
  93. {
  94. /* only handle 4k, 64k and 16M pages for now */
  95. if (!(h & HPTE_V_LARGE))
  96. return 1ul << 12; /* 4k page */
  97. if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
  98. return 1ul << 16; /* 64k page */
  99. if ((l & 0xff000) == 0)
  100. return 1ul << 24; /* 16M page */
  101. return 0; /* error */
  102. }
  103. static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
  104. {
  105. return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
  106. }
  107. static inline int hpte_is_writable(unsigned long ptel)
  108. {
  109. unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
  110. return pp != PP_RXRX && pp != PP_RXXX;
  111. }
  112. static inline unsigned long hpte_make_readonly(unsigned long ptel)
  113. {
  114. if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
  115. ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
  116. else
  117. ptel |= PP_RXRX;
  118. return ptel;
  119. }
  120. static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
  121. {
  122. unsigned int wimg = ptel & HPTE_R_WIMG;
  123. /* Handle SAO */
  124. if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
  125. cpu_has_feature(CPU_FTR_ARCH_206))
  126. wimg = HPTE_R_M;
  127. if (!io_type)
  128. return wimg == HPTE_R_M;
  129. return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
  130. }
  131. /*
  132. * Lock and read a linux PTE. If it's present and writable, atomically
  133. * set dirty and referenced bits and return the PTE, otherwise return 0.
  134. */
  135. static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
  136. {
  137. pte_t pte, tmp;
  138. /* wait until _PAGE_BUSY is clear then set it atomically */
  139. __asm__ __volatile__ (
  140. "1: ldarx %0,0,%3\n"
  141. " andi. %1,%0,%4\n"
  142. " bne- 1b\n"
  143. " ori %1,%0,%4\n"
  144. " stdcx. %1,0,%3\n"
  145. " bne- 1b"
  146. : "=&r" (pte), "=&r" (tmp), "=m" (*p)
  147. : "r" (p), "i" (_PAGE_BUSY)
  148. : "cc");
  149. if (pte_present(pte)) {
  150. pte = pte_mkyoung(pte);
  151. if (writing && pte_write(pte))
  152. pte = pte_mkdirty(pte);
  153. }
  154. *p = pte; /* clears _PAGE_BUSY */
  155. return pte;
  156. }
  157. /* Return HPTE cache control bits corresponding to Linux pte bits */
  158. static inline unsigned long hpte_cache_bits(unsigned long pte_val)
  159. {
  160. #if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
  161. return pte_val & (HPTE_R_W | HPTE_R_I);
  162. #else
  163. return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
  164. ((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
  165. #endif
  166. }
  167. static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
  168. {
  169. if (key)
  170. return PP_RWRX <= pp && pp <= PP_RXRX;
  171. return 1;
  172. }
  173. static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
  174. {
  175. if (key)
  176. return pp == PP_RWRW;
  177. return pp <= PP_RWRW;
  178. }
  179. static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
  180. {
  181. unsigned long skey;
  182. skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
  183. ((hpte_r & HPTE_R_KEY_LO) >> 9);
  184. return (amr >> (62 - 2 * skey)) & 3;
  185. }
  186. static inline void lock_rmap(unsigned long *rmap)
  187. {
  188. do {
  189. while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
  190. cpu_relax();
  191. } while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
  192. }
  193. static inline void unlock_rmap(unsigned long *rmap)
  194. {
  195. __clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
  196. }
  197. static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
  198. unsigned long pagesize)
  199. {
  200. unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
  201. if (pagesize <= PAGE_SIZE)
  202. return 1;
  203. return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
  204. }
  205. #endif /* __ASM_KVM_BOOK3S_64_H__ */