p2041rdb.dts 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219
  1. /*
  2. * P2041RDB Device Tree Source
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. /include/ "fsl/p2041si-pre.dtsi"
  35. / {
  36. model = "fsl,P2041RDB";
  37. compatible = "fsl,P2041RDB";
  38. #address-cells = <2>;
  39. #size-cells = <2>;
  40. interrupt-parent = <&mpic>;
  41. memory {
  42. device_type = "memory";
  43. };
  44. dcsr: dcsr@f00000000 {
  45. ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  46. };
  47. soc: soc@ffe000000 {
  48. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  49. reg = <0xf 0xfe000000 0 0x00001000>;
  50. spi@110000 {
  51. flash@0 {
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. compatible = "spansion,s25sl12801";
  55. reg = <0>;
  56. spi-max-frequency = <40000000>; /* input clock */
  57. partition@u-boot {
  58. label = "u-boot";
  59. reg = <0x00000000 0x00100000>;
  60. read-only;
  61. };
  62. partition@kernel {
  63. label = "kernel";
  64. reg = <0x00100000 0x00500000>;
  65. read-only;
  66. };
  67. partition@dtb {
  68. label = "dtb";
  69. reg = <0x00600000 0x00100000>;
  70. read-only;
  71. };
  72. partition@fs {
  73. label = "file system";
  74. reg = <0x00700000 0x00900000>;
  75. };
  76. };
  77. };
  78. i2c@118000 {
  79. lm75b@48 {
  80. compatible = "nxp,lm75a";
  81. reg = <0x48>;
  82. };
  83. eeprom@50 {
  84. compatible = "at24,24c256";
  85. reg = <0x50>;
  86. };
  87. rtc@68 {
  88. compatible = "pericom,pt7c4338";
  89. reg = <0x68>;
  90. };
  91. };
  92. i2c@118100 {
  93. eeprom@50 {
  94. compatible = "at24,24c256";
  95. reg = <0x50>;
  96. };
  97. };
  98. usb1: usb@211000 {
  99. dr_mode = "host";
  100. };
  101. };
  102. rio: rapidio@ffe0c0000 {
  103. reg = <0xf 0xfe0c0000 0 0x11000>;
  104. port1 {
  105. ranges = <0 0 0xc 0x20000000 0 0x10000000>;
  106. };
  107. port2 {
  108. ranges = <0 0 0xc 0x30000000 0 0x10000000>;
  109. };
  110. };
  111. lbc: localbus@ffe124000 {
  112. reg = <0xf 0xfe124000 0 0x1000>;
  113. ranges = <0 0 0xf 0xe8000000 0x08000000
  114. 1 0 0xf 0xffa00000 0x00040000>;
  115. flash@0,0 {
  116. compatible = "cfi-flash";
  117. reg = <0 0 0x08000000>;
  118. bank-width = <2>;
  119. device-width = <2>;
  120. };
  121. nand@1,0 {
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. compatible = "fsl,elbc-fcm-nand";
  125. reg = <0x1 0x0 0x40000>;
  126. partition@0 {
  127. label = "NAND U-Boot Image";
  128. reg = <0x0 0x02000000>;
  129. read-only;
  130. };
  131. partition@2000000 {
  132. label = "NAND Root File System";
  133. reg = <0x02000000 0x10000000>;
  134. };
  135. partition@12000000 {
  136. label = "NAND Compressed RFS Image";
  137. reg = <0x12000000 0x08000000>;
  138. };
  139. partition@1a000000 {
  140. label = "NAND Linux Kernel Image";
  141. reg = <0x1a000000 0x04000000>;
  142. };
  143. partition@1e000000 {
  144. label = "NAND DTB Image";
  145. reg = <0x1e000000 0x01000000>;
  146. };
  147. partition@1f000000 {
  148. label = "NAND Writable User area";
  149. reg = <0x1f000000 0x01000000>;
  150. };
  151. };
  152. };
  153. pci0: pcie@ffe200000 {
  154. reg = <0xf 0xfe200000 0 0x1000>;
  155. ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
  156. 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
  157. pcie@0 {
  158. ranges = <0x02000000 0 0xe0000000
  159. 0x02000000 0 0xe0000000
  160. 0 0x20000000
  161. 0x01000000 0 0x00000000
  162. 0x01000000 0 0x00000000
  163. 0 0x00010000>;
  164. };
  165. };
  166. pci1: pcie@ffe201000 {
  167. reg = <0xf 0xfe201000 0 0x1000>;
  168. ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
  169. 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
  170. pcie@0 {
  171. ranges = <0x02000000 0 0xe0000000
  172. 0x02000000 0 0xe0000000
  173. 0 0x20000000
  174. 0x01000000 0 0x00000000
  175. 0x01000000 0 0x00000000
  176. 0 0x00010000>;
  177. };
  178. };
  179. pci2: pcie@ffe202000 {
  180. reg = <0xf 0xfe202000 0 0x1000>;
  181. ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
  182. 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
  183. pcie@0 {
  184. ranges = <0x02000000 0 0xe0000000
  185. 0x02000000 0 0xe0000000
  186. 0 0x20000000
  187. 0x01000000 0 0x00000000
  188. 0x01000000 0 0x00000000
  189. 0 0x00010000>;
  190. };
  191. };
  192. };
  193. /include/ "fsl/p2041si-post.dtsi"