bcm63xx_regs.h 42 KB

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  1. #ifndef BCM63XX_REGS_H_
  2. #define BCM63XX_REGS_H_
  3. /*************************************************************************
  4. * _REG relative to RSET_PERF
  5. *************************************************************************/
  6. /* Chip Identifier / Revision register */
  7. #define PERF_REV_REG 0x0
  8. #define REV_CHIPID_SHIFT 16
  9. #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
  10. #define REV_REVID_SHIFT 0
  11. #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
  12. /* Clock Control register */
  13. #define PERF_CKCTL_REG 0x4
  14. #define CKCTL_6328_PHYMIPS_EN (1 << 0)
  15. #define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
  16. #define CKCTL_6328_ADSL_AFE_EN (1 << 2)
  17. #define CKCTL_6328_ADSL_EN (1 << 3)
  18. #define CKCTL_6328_MIPS_EN (1 << 4)
  19. #define CKCTL_6328_SAR_EN (1 << 5)
  20. #define CKCTL_6328_PCM_EN (1 << 6)
  21. #define CKCTL_6328_USBD_EN (1 << 7)
  22. #define CKCTL_6328_USBH_EN (1 << 8)
  23. #define CKCTL_6328_HSSPI_EN (1 << 9)
  24. #define CKCTL_6328_PCIE_EN (1 << 10)
  25. #define CKCTL_6328_ROBOSW_EN (1 << 11)
  26. #define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
  27. CKCTL_6328_ADSL_QPROC_EN | \
  28. CKCTL_6328_ADSL_AFE_EN | \
  29. CKCTL_6328_ADSL_EN | \
  30. CKCTL_6328_SAR_EN | \
  31. CKCTL_6328_PCM_EN | \
  32. CKCTL_6328_USBD_EN | \
  33. CKCTL_6328_USBH_EN | \
  34. CKCTL_6328_ROBOSW_EN | \
  35. CKCTL_6328_PCIE_EN)
  36. #define CKCTL_6338_ADSLPHY_EN (1 << 0)
  37. #define CKCTL_6338_MPI_EN (1 << 1)
  38. #define CKCTL_6338_DRAM_EN (1 << 2)
  39. #define CKCTL_6338_ENET_EN (1 << 4)
  40. #define CKCTL_6338_USBS_EN (1 << 4)
  41. #define CKCTL_6338_SAR_EN (1 << 5)
  42. #define CKCTL_6338_SPI_EN (1 << 9)
  43. #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
  44. CKCTL_6338_MPI_EN | \
  45. CKCTL_6338_ENET_EN | \
  46. CKCTL_6338_SAR_EN | \
  47. CKCTL_6338_SPI_EN)
  48. #define CKCTL_6345_CPU_EN (1 << 0)
  49. #define CKCTL_6345_BUS_EN (1 << 1)
  50. #define CKCTL_6345_EBI_EN (1 << 2)
  51. #define CKCTL_6345_UART_EN (1 << 3)
  52. #define CKCTL_6345_ADSLPHY_EN (1 << 4)
  53. #define CKCTL_6345_ENET_EN (1 << 7)
  54. #define CKCTL_6345_USBH_EN (1 << 8)
  55. #define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
  56. CKCTL_6345_USBH_EN | \
  57. CKCTL_6345_ADSLPHY_EN)
  58. #define CKCTL_6348_ADSLPHY_EN (1 << 0)
  59. #define CKCTL_6348_MPI_EN (1 << 1)
  60. #define CKCTL_6348_SDRAM_EN (1 << 2)
  61. #define CKCTL_6348_M2M_EN (1 << 3)
  62. #define CKCTL_6348_ENET_EN (1 << 4)
  63. #define CKCTL_6348_SAR_EN (1 << 5)
  64. #define CKCTL_6348_USBS_EN (1 << 6)
  65. #define CKCTL_6348_USBH_EN (1 << 8)
  66. #define CKCTL_6348_SPI_EN (1 << 9)
  67. #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
  68. CKCTL_6348_M2M_EN | \
  69. CKCTL_6348_ENET_EN | \
  70. CKCTL_6348_SAR_EN | \
  71. CKCTL_6348_USBS_EN | \
  72. CKCTL_6348_USBH_EN | \
  73. CKCTL_6348_SPI_EN)
  74. #define CKCTL_6358_ENET_EN (1 << 4)
  75. #define CKCTL_6358_ADSLPHY_EN (1 << 5)
  76. #define CKCTL_6358_PCM_EN (1 << 8)
  77. #define CKCTL_6358_SPI_EN (1 << 9)
  78. #define CKCTL_6358_USBS_EN (1 << 10)
  79. #define CKCTL_6358_SAR_EN (1 << 11)
  80. #define CKCTL_6358_EMUSB_EN (1 << 17)
  81. #define CKCTL_6358_ENET0_EN (1 << 18)
  82. #define CKCTL_6358_ENET1_EN (1 << 19)
  83. #define CKCTL_6358_USBSU_EN (1 << 20)
  84. #define CKCTL_6358_EPHY_EN (1 << 21)
  85. #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
  86. CKCTL_6358_ADSLPHY_EN | \
  87. CKCTL_6358_PCM_EN | \
  88. CKCTL_6358_SPI_EN | \
  89. CKCTL_6358_USBS_EN | \
  90. CKCTL_6358_SAR_EN | \
  91. CKCTL_6358_EMUSB_EN | \
  92. CKCTL_6358_ENET0_EN | \
  93. CKCTL_6358_ENET1_EN | \
  94. CKCTL_6358_USBSU_EN | \
  95. CKCTL_6358_EPHY_EN)
  96. #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
  97. #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
  98. #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
  99. #define CKCTL_6368_VDSL_EN (1 << 5)
  100. #define CKCTL_6368_PHYMIPS_EN (1 << 6)
  101. #define CKCTL_6368_SWPKT_USB_EN (1 << 7)
  102. #define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
  103. #define CKCTL_6368_SPI_EN (1 << 9)
  104. #define CKCTL_6368_USBD_EN (1 << 10)
  105. #define CKCTL_6368_SAR_EN (1 << 11)
  106. #define CKCTL_6368_ROBOSW_EN (1 << 12)
  107. #define CKCTL_6368_UTOPIA_EN (1 << 13)
  108. #define CKCTL_6368_PCM_EN (1 << 14)
  109. #define CKCTL_6368_USBH_EN (1 << 15)
  110. #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
  111. #define CKCTL_6368_NAND_EN (1 << 17)
  112. #define CKCTL_6368_IPSEC_EN (1 << 18)
  113. #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
  114. CKCTL_6368_SWPKT_SAR_EN | \
  115. CKCTL_6368_SPI_EN | \
  116. CKCTL_6368_USBD_EN | \
  117. CKCTL_6368_SAR_EN | \
  118. CKCTL_6368_ROBOSW_EN | \
  119. CKCTL_6368_UTOPIA_EN | \
  120. CKCTL_6368_PCM_EN | \
  121. CKCTL_6368_USBH_EN | \
  122. CKCTL_6368_DISABLE_GLESS_EN | \
  123. CKCTL_6368_NAND_EN | \
  124. CKCTL_6368_IPSEC_EN)
  125. /* System PLL Control register */
  126. #define PERF_SYS_PLL_CTL_REG 0x8
  127. #define SYS_PLL_SOFT_RESET 0x1
  128. /* Interrupt Mask register */
  129. #define PERF_IRQMASK_6328_REG 0x20
  130. #define PERF_IRQMASK_6338_REG 0xc
  131. #define PERF_IRQMASK_6345_REG 0xc
  132. #define PERF_IRQMASK_6348_REG 0xc
  133. #define PERF_IRQMASK_6358_REG 0xc
  134. #define PERF_IRQMASK_6368_REG 0x20
  135. /* Interrupt Status register */
  136. #define PERF_IRQSTAT_6328_REG 0x28
  137. #define PERF_IRQSTAT_6338_REG 0x10
  138. #define PERF_IRQSTAT_6345_REG 0x10
  139. #define PERF_IRQSTAT_6348_REG 0x10
  140. #define PERF_IRQSTAT_6358_REG 0x10
  141. #define PERF_IRQSTAT_6368_REG 0x28
  142. /* External Interrupt Configuration register */
  143. #define PERF_EXTIRQ_CFG_REG_6328 0x18
  144. #define PERF_EXTIRQ_CFG_REG_6338 0x14
  145. #define PERF_EXTIRQ_CFG_REG_6348 0x14
  146. #define PERF_EXTIRQ_CFG_REG_6358 0x14
  147. #define PERF_EXTIRQ_CFG_REG_6368 0x18
  148. #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
  149. /* for 6348 only */
  150. #define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
  151. #define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
  152. #define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
  153. #define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
  154. #define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
  155. #define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
  156. #define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
  157. #define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
  158. /* for all others */
  159. #define EXTIRQ_CFG_SENSE(x) (1 << (x))
  160. #define EXTIRQ_CFG_STAT(x) (1 << (x + 4))
  161. #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8))
  162. #define EXTIRQ_CFG_MASK(x) (1 << (x + 12))
  163. #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16))
  164. #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20))
  165. #define EXTIRQ_CFG_CLEAR_ALL (0xf << 8)
  166. #define EXTIRQ_CFG_MASK_ALL (0xf << 12)
  167. /* Soft Reset register */
  168. #define PERF_SOFTRESET_REG 0x28
  169. #define PERF_SOFTRESET_6328_REG 0x10
  170. #define PERF_SOFTRESET_6368_REG 0x10
  171. #define SOFTRESET_6328_SPI_MASK (1 << 0)
  172. #define SOFTRESET_6328_EPHY_MASK (1 << 1)
  173. #define SOFTRESET_6328_SAR_MASK (1 << 2)
  174. #define SOFTRESET_6328_ENETSW_MASK (1 << 3)
  175. #define SOFTRESET_6328_USBS_MASK (1 << 4)
  176. #define SOFTRESET_6328_USBH_MASK (1 << 5)
  177. #define SOFTRESET_6328_PCM_MASK (1 << 6)
  178. #define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
  179. #define SOFTRESET_6328_PCIE_MASK (1 << 8)
  180. #define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
  181. #define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
  182. #define SOFTRESET_6338_SPI_MASK (1 << 0)
  183. #define SOFTRESET_6338_ENET_MASK (1 << 2)
  184. #define SOFTRESET_6338_USBH_MASK (1 << 3)
  185. #define SOFTRESET_6338_USBS_MASK (1 << 4)
  186. #define SOFTRESET_6338_ADSL_MASK (1 << 5)
  187. #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
  188. #define SOFTRESET_6338_SAR_MASK (1 << 7)
  189. #define SOFTRESET_6338_ACLC_MASK (1 << 8)
  190. #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
  191. #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
  192. SOFTRESET_6338_ENET_MASK | \
  193. SOFTRESET_6338_USBH_MASK | \
  194. SOFTRESET_6338_USBS_MASK | \
  195. SOFTRESET_6338_ADSL_MASK | \
  196. SOFTRESET_6338_DMAMEM_MASK | \
  197. SOFTRESET_6338_SAR_MASK | \
  198. SOFTRESET_6338_ACLC_MASK | \
  199. SOFTRESET_6338_ADSLMIPSPLL_MASK)
  200. #define SOFTRESET_6348_SPI_MASK (1 << 0)
  201. #define SOFTRESET_6348_ENET_MASK (1 << 2)
  202. #define SOFTRESET_6348_USBH_MASK (1 << 3)
  203. #define SOFTRESET_6348_USBS_MASK (1 << 4)
  204. #define SOFTRESET_6348_ADSL_MASK (1 << 5)
  205. #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
  206. #define SOFTRESET_6348_SAR_MASK (1 << 7)
  207. #define SOFTRESET_6348_ACLC_MASK (1 << 8)
  208. #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
  209. #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
  210. SOFTRESET_6348_ENET_MASK | \
  211. SOFTRESET_6348_USBH_MASK | \
  212. SOFTRESET_6348_USBS_MASK | \
  213. SOFTRESET_6348_ADSL_MASK | \
  214. SOFTRESET_6348_DMAMEM_MASK | \
  215. SOFTRESET_6348_SAR_MASK | \
  216. SOFTRESET_6348_ACLC_MASK | \
  217. SOFTRESET_6348_ADSLMIPSPLL_MASK)
  218. #define SOFTRESET_6368_SPI_MASK (1 << 0)
  219. #define SOFTRESET_6368_MPI_MASK (1 << 3)
  220. #define SOFTRESET_6368_EPHY_MASK (1 << 6)
  221. #define SOFTRESET_6368_SAR_MASK (1 << 7)
  222. #define SOFTRESET_6368_ENETSW_MASK (1 << 10)
  223. #define SOFTRESET_6368_USBS_MASK (1 << 11)
  224. #define SOFTRESET_6368_USBH_MASK (1 << 12)
  225. #define SOFTRESET_6368_PCM_MASK (1 << 13)
  226. /* MIPS PLL control register */
  227. #define PERF_MIPSPLLCTL_REG 0x34
  228. #define MIPSPLLCTL_N1_SHIFT 20
  229. #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
  230. #define MIPSPLLCTL_N2_SHIFT 15
  231. #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
  232. #define MIPSPLLCTL_M1REF_SHIFT 12
  233. #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
  234. #define MIPSPLLCTL_M2REF_SHIFT 9
  235. #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
  236. #define MIPSPLLCTL_M1CPU_SHIFT 6
  237. #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
  238. #define MIPSPLLCTL_M1BUS_SHIFT 3
  239. #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
  240. #define MIPSPLLCTL_M2BUS_SHIFT 0
  241. #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
  242. /* ADSL PHY PLL Control register */
  243. #define PERF_ADSLPLLCTL_REG 0x38
  244. #define ADSLPLLCTL_N1_SHIFT 20
  245. #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
  246. #define ADSLPLLCTL_N2_SHIFT 15
  247. #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
  248. #define ADSLPLLCTL_M1REF_SHIFT 12
  249. #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
  250. #define ADSLPLLCTL_M2REF_SHIFT 9
  251. #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
  252. #define ADSLPLLCTL_M1CPU_SHIFT 6
  253. #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
  254. #define ADSLPLLCTL_M1BUS_SHIFT 3
  255. #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
  256. #define ADSLPLLCTL_M2BUS_SHIFT 0
  257. #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
  258. #define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \
  259. (((n1) << ADSLPLLCTL_N1_SHIFT) | \
  260. ((n2) << ADSLPLLCTL_N2_SHIFT) | \
  261. ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
  262. ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
  263. ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
  264. ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
  265. ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
  266. /*************************************************************************
  267. * _REG relative to RSET_TIMER
  268. *************************************************************************/
  269. #define BCM63XX_TIMER_COUNT 4
  270. #define TIMER_T0_ID 0
  271. #define TIMER_T1_ID 1
  272. #define TIMER_T2_ID 2
  273. #define TIMER_WDT_ID 3
  274. /* Timer irqstat register */
  275. #define TIMER_IRQSTAT_REG 0
  276. #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
  277. #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
  278. #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
  279. #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
  280. #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
  281. #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
  282. #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
  283. #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
  284. #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
  285. /* Timer control register */
  286. #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
  287. #define TIMER_CTL0_REG 0x4
  288. #define TIMER_CTL1_REG 0x8
  289. #define TIMER_CTL2_REG 0xC
  290. #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
  291. #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
  292. #define TIMER_CTL_ENABLE_MASK (1 << 31)
  293. /*************************************************************************
  294. * _REG relative to RSET_WDT
  295. *************************************************************************/
  296. /* Watchdog default count register */
  297. #define WDT_DEFVAL_REG 0x0
  298. /* Watchdog control register */
  299. #define WDT_CTL_REG 0x4
  300. /* Watchdog control register constants */
  301. #define WDT_START_1 (0xff00)
  302. #define WDT_START_2 (0x00ff)
  303. #define WDT_STOP_1 (0xee00)
  304. #define WDT_STOP_2 (0x00ee)
  305. /* Watchdog reset length register */
  306. #define WDT_RSTLEN_REG 0x8
  307. /* Watchdog soft reset register (BCM6328 only) */
  308. #define WDT_SOFTRESET_REG 0xc
  309. /*************************************************************************
  310. * _REG relative to RSET_UARTx
  311. *************************************************************************/
  312. /* UART Control Register */
  313. #define UART_CTL_REG 0x0
  314. #define UART_CTL_RXTMOUTCNT_SHIFT 0
  315. #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
  316. #define UART_CTL_RSTTXDN_SHIFT 5
  317. #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
  318. #define UART_CTL_RSTRXFIFO_SHIFT 6
  319. #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
  320. #define UART_CTL_RSTTXFIFO_SHIFT 7
  321. #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
  322. #define UART_CTL_STOPBITS_SHIFT 8
  323. #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
  324. #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
  325. #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
  326. #define UART_CTL_BITSPERSYM_SHIFT 12
  327. #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
  328. #define UART_CTL_XMITBRK_SHIFT 14
  329. #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
  330. #define UART_CTL_RSVD_SHIFT 15
  331. #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
  332. #define UART_CTL_RXPAREVEN_SHIFT 16
  333. #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
  334. #define UART_CTL_RXPAREN_SHIFT 17
  335. #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
  336. #define UART_CTL_TXPAREVEN_SHIFT 18
  337. #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
  338. #define UART_CTL_TXPAREN_SHIFT 18
  339. #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
  340. #define UART_CTL_LOOPBACK_SHIFT 20
  341. #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
  342. #define UART_CTL_RXEN_SHIFT 21
  343. #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
  344. #define UART_CTL_TXEN_SHIFT 22
  345. #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
  346. #define UART_CTL_BRGEN_SHIFT 23
  347. #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
  348. /* UART Baudword register */
  349. #define UART_BAUD_REG 0x4
  350. /* UART Misc Control register */
  351. #define UART_MCTL_REG 0x8
  352. #define UART_MCTL_DTR_SHIFT 0
  353. #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
  354. #define UART_MCTL_RTS_SHIFT 1
  355. #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
  356. #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
  357. #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
  358. #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
  359. #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
  360. #define UART_MCTL_RXFIFOFILL_SHIFT 16
  361. #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
  362. #define UART_MCTL_TXFIFOFILL_SHIFT 24
  363. #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
  364. /* UART External Input Configuration register */
  365. #define UART_EXTINP_REG 0xc
  366. #define UART_EXTINP_RI_SHIFT 0
  367. #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
  368. #define UART_EXTINP_CTS_SHIFT 1
  369. #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
  370. #define UART_EXTINP_DCD_SHIFT 2
  371. #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
  372. #define UART_EXTINP_DSR_SHIFT 3
  373. #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
  374. #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
  375. #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
  376. #define UART_EXTINP_IR_RI 0
  377. #define UART_EXTINP_IR_CTS 1
  378. #define UART_EXTINP_IR_DCD 2
  379. #define UART_EXTINP_IR_DSR 3
  380. #define UART_EXTINP_RI_NOSENSE_SHIFT 16
  381. #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
  382. #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
  383. #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
  384. #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
  385. #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
  386. #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
  387. #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
  388. /* UART Interrupt register */
  389. #define UART_IR_REG 0x10
  390. #define UART_IR_MASK(x) (1 << (x + 16))
  391. #define UART_IR_STAT(x) (1 << (x))
  392. #define UART_IR_EXTIP 0
  393. #define UART_IR_TXUNDER 1
  394. #define UART_IR_TXOVER 2
  395. #define UART_IR_TXTRESH 3
  396. #define UART_IR_TXRDLATCH 4
  397. #define UART_IR_TXEMPTY 5
  398. #define UART_IR_RXUNDER 6
  399. #define UART_IR_RXOVER 7
  400. #define UART_IR_RXTIMEOUT 8
  401. #define UART_IR_RXFULL 9
  402. #define UART_IR_RXTHRESH 10
  403. #define UART_IR_RXNOTEMPTY 11
  404. #define UART_IR_RXFRAMEERR 12
  405. #define UART_IR_RXPARERR 13
  406. #define UART_IR_RXBRK 14
  407. #define UART_IR_TXDONE 15
  408. /* UART Fifo register */
  409. #define UART_FIFO_REG 0x14
  410. #define UART_FIFO_VALID_SHIFT 0
  411. #define UART_FIFO_VALID_MASK 0xff
  412. #define UART_FIFO_FRAMEERR_SHIFT 8
  413. #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
  414. #define UART_FIFO_PARERR_SHIFT 9
  415. #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
  416. #define UART_FIFO_BRKDET_SHIFT 10
  417. #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
  418. #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
  419. UART_FIFO_PARERR_MASK | \
  420. UART_FIFO_BRKDET_MASK)
  421. /*************************************************************************
  422. * _REG relative to RSET_GPIO
  423. *************************************************************************/
  424. /* GPIO registers */
  425. #define GPIO_CTL_HI_REG 0x0
  426. #define GPIO_CTL_LO_REG 0x4
  427. #define GPIO_DATA_HI_REG 0x8
  428. #define GPIO_DATA_LO_REG 0xC
  429. #define GPIO_DATA_LO_REG_6345 0x8
  430. /* GPIO mux registers and constants */
  431. #define GPIO_MODE_REG 0x18
  432. #define GPIO_MODE_6348_G4_DIAG 0x00090000
  433. #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
  434. #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
  435. #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
  436. #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
  437. #define GPIO_MODE_6348_G3_DIAG 0x00009000
  438. #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
  439. #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
  440. #define GPIO_MODE_6348_G2_DIAG 0x00000900
  441. #define GPIO_MODE_6348_G2_PCI 0x00000500
  442. #define GPIO_MODE_6348_G1_DIAG 0x00000090
  443. #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
  444. #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
  445. #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
  446. #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
  447. #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
  448. #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
  449. #define GPIO_MODE_6348_G0_DIAG 0x00000009
  450. #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
  451. #define GPIO_MODE_6358_EXTRACS (1 << 5)
  452. #define GPIO_MODE_6358_UART1 (1 << 6)
  453. #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
  454. #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
  455. #define GPIO_MODE_6358_UTOPIA (1 << 12)
  456. #define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
  457. #define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
  458. #define GPIO_MODE_6368_SYS_IRQ (1 << 2)
  459. #define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
  460. #define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
  461. #define GPIO_MODE_6368_INET_LED (1 << 5)
  462. #define GPIO_MODE_6368_EPHY0_LED (1 << 6)
  463. #define GPIO_MODE_6368_EPHY1_LED (1 << 7)
  464. #define GPIO_MODE_6368_EPHY2_LED (1 << 8)
  465. #define GPIO_MODE_6368_EPHY3_LED (1 << 9)
  466. #define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
  467. #define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
  468. #define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
  469. #define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
  470. #define GPIO_MODE_6368_USBD_LED (1 << 14)
  471. #define GPIO_MODE_6368_NTR_PULSE (1 << 15)
  472. #define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
  473. #define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
  474. #define GPIO_MODE_6368_PCI_INTB (1 << 18)
  475. #define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
  476. #define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
  477. #define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
  478. #define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
  479. #define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
  480. #define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
  481. #define GPIO_MODE_6368_EBI_CS2 (1 << 26)
  482. #define GPIO_MODE_6368_EBI_CS3 (1 << 27)
  483. #define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
  484. #define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
  485. #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
  486. #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
  487. #define GPIO_BASEMODE_6368_REG 0x38
  488. #define GPIO_BASEMODE_6368_UART2 0x1
  489. #define GPIO_BASEMODE_6368_GPIO 0x0
  490. #define GPIO_BASEMODE_6368_MASK 0x7
  491. /* those bits must be kept as read in gpio basemode register*/
  492. #define GPIO_STRAPBUS_REG 0x40
  493. #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
  494. #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
  495. #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
  496. #define STRAPBUS_6368_BOOT_SEL_NAND 0
  497. #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
  498. #define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
  499. /*************************************************************************
  500. * _REG relative to RSET_ENET
  501. *************************************************************************/
  502. /* Receiver Configuration register */
  503. #define ENET_RXCFG_REG 0x0
  504. #define ENET_RXCFG_ALLMCAST_SHIFT 1
  505. #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
  506. #define ENET_RXCFG_PROMISC_SHIFT 3
  507. #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
  508. #define ENET_RXCFG_LOOPBACK_SHIFT 4
  509. #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
  510. #define ENET_RXCFG_ENFLOW_SHIFT 5
  511. #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
  512. /* Receive Maximum Length register */
  513. #define ENET_RXMAXLEN_REG 0x4
  514. #define ENET_RXMAXLEN_SHIFT 0
  515. #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
  516. /* Transmit Maximum Length register */
  517. #define ENET_TXMAXLEN_REG 0x8
  518. #define ENET_TXMAXLEN_SHIFT 0
  519. #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
  520. /* MII Status/Control register */
  521. #define ENET_MIISC_REG 0x10
  522. #define ENET_MIISC_MDCFREQDIV_SHIFT 0
  523. #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
  524. #define ENET_MIISC_PREAMBLEEN_SHIFT 7
  525. #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
  526. /* MII Data register */
  527. #define ENET_MIIDATA_REG 0x14
  528. #define ENET_MIIDATA_DATA_SHIFT 0
  529. #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
  530. #define ENET_MIIDATA_TA_SHIFT 16
  531. #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
  532. #define ENET_MIIDATA_REG_SHIFT 18
  533. #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
  534. #define ENET_MIIDATA_PHYID_SHIFT 23
  535. #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
  536. #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
  537. #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
  538. /* Ethernet Interrupt Mask register */
  539. #define ENET_IRMASK_REG 0x18
  540. /* Ethernet Interrupt register */
  541. #define ENET_IR_REG 0x1c
  542. #define ENET_IR_MII (1 << 0)
  543. #define ENET_IR_MIB (1 << 1)
  544. #define ENET_IR_FLOWC (1 << 2)
  545. /* Ethernet Control register */
  546. #define ENET_CTL_REG 0x2c
  547. #define ENET_CTL_ENABLE_SHIFT 0
  548. #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
  549. #define ENET_CTL_DISABLE_SHIFT 1
  550. #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
  551. #define ENET_CTL_SRESET_SHIFT 2
  552. #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
  553. #define ENET_CTL_EPHYSEL_SHIFT 3
  554. #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
  555. /* Transmit Control register */
  556. #define ENET_TXCTL_REG 0x30
  557. #define ENET_TXCTL_FD_SHIFT 0
  558. #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
  559. /* Transmit Watermask register */
  560. #define ENET_TXWMARK_REG 0x34
  561. #define ENET_TXWMARK_WM_SHIFT 0
  562. #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
  563. /* MIB Control register */
  564. #define ENET_MIBCTL_REG 0x38
  565. #define ENET_MIBCTL_RDCLEAR_SHIFT 0
  566. #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
  567. /* Perfect Match Data Low register */
  568. #define ENET_PML_REG(x) (0x58 + (x) * 8)
  569. #define ENET_PMH_REG(x) (0x5c + (x) * 8)
  570. #define ENET_PMH_DATAVALID_SHIFT 16
  571. #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
  572. /* MIB register */
  573. #define ENET_MIB_REG(x) (0x200 + (x) * 4)
  574. #define ENET_MIB_REG_COUNT 55
  575. /*************************************************************************
  576. * _REG relative to RSET_ENETDMA
  577. *************************************************************************/
  578. /* Controller Configuration Register */
  579. #define ENETDMA_CFG_REG (0x0)
  580. #define ENETDMA_CFG_EN_SHIFT 0
  581. #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
  582. #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
  583. /* Flow Control Descriptor Low Threshold register */
  584. #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
  585. /* Flow Control Descriptor High Threshold register */
  586. #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
  587. /* Flow Control Descriptor Buffer Alloca Threshold register */
  588. #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
  589. #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
  590. #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
  591. /* Channel Configuration register */
  592. #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
  593. #define ENETDMA_CHANCFG_EN_SHIFT 0
  594. #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
  595. #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
  596. #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
  597. /* Interrupt Control/Status register */
  598. #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
  599. #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
  600. #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
  601. #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
  602. /* Interrupt Mask register */
  603. #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
  604. /* Maximum Burst Length */
  605. #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
  606. /* Ring Start Address register */
  607. #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
  608. /* State Ram Word 2 */
  609. #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
  610. /* State Ram Word 3 */
  611. #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
  612. /* State Ram Word 4 */
  613. #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
  614. /*************************************************************************
  615. * _REG relative to RSET_ENETDMAC
  616. *************************************************************************/
  617. /* Channel Configuration register */
  618. #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
  619. #define ENETDMAC_CHANCFG_EN_SHIFT 0
  620. #define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
  621. #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
  622. #define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
  623. /* Interrupt Control/Status register */
  624. #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
  625. #define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
  626. #define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
  627. #define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
  628. /* Interrupt Mask register */
  629. #define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
  630. /* Maximum Burst Length */
  631. #define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
  632. /*************************************************************************
  633. * _REG relative to RSET_ENETDMAS
  634. *************************************************************************/
  635. /* Ring Start Address register */
  636. #define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
  637. /* State Ram Word 2 */
  638. #define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
  639. /* State Ram Word 3 */
  640. #define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
  641. /* State Ram Word 4 */
  642. #define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
  643. /*************************************************************************
  644. * _REG relative to RSET_ENETSW
  645. *************************************************************************/
  646. /* MIB register */
  647. #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
  648. #define ENETSW_MIB_REG_COUNT 47
  649. /*************************************************************************
  650. * _REG relative to RSET_OHCI_PRIV
  651. *************************************************************************/
  652. #define OHCI_PRIV_REG 0x0
  653. #define OHCI_PRIV_PORT1_HOST_SHIFT 0
  654. #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
  655. #define OHCI_PRIV_REG_SWAP_SHIFT 3
  656. #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
  657. /*************************************************************************
  658. * _REG relative to RSET_USBH_PRIV
  659. *************************************************************************/
  660. #define USBH_PRIV_SWAP_6358_REG 0x0
  661. #define USBH_PRIV_SWAP_6368_REG 0x1c
  662. #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
  663. #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
  664. #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
  665. #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
  666. #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
  667. #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
  668. #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
  669. #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
  670. #define USBH_PRIV_TEST_6358_REG 0x24
  671. #define USBH_PRIV_TEST_6368_REG 0x14
  672. #define USBH_PRIV_SETUP_6368_REG 0x28
  673. #define USBH_PRIV_SETUP_IOC_SHIFT 4
  674. #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
  675. /*************************************************************************
  676. * _REG relative to RSET_MPI
  677. *************************************************************************/
  678. /* well known (hard wired) chip select */
  679. #define MPI_CS_PCMCIA_COMMON 4
  680. #define MPI_CS_PCMCIA_ATTR 5
  681. #define MPI_CS_PCMCIA_IO 6
  682. /* Chip select base register */
  683. #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
  684. #define MPI_CSBASE_BASE_SHIFT 13
  685. #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
  686. #define MPI_CSBASE_SIZE_SHIFT 0
  687. #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
  688. #define MPI_CSBASE_SIZE_8K 0
  689. #define MPI_CSBASE_SIZE_16K 1
  690. #define MPI_CSBASE_SIZE_32K 2
  691. #define MPI_CSBASE_SIZE_64K 3
  692. #define MPI_CSBASE_SIZE_128K 4
  693. #define MPI_CSBASE_SIZE_256K 5
  694. #define MPI_CSBASE_SIZE_512K 6
  695. #define MPI_CSBASE_SIZE_1M 7
  696. #define MPI_CSBASE_SIZE_2M 8
  697. #define MPI_CSBASE_SIZE_4M 9
  698. #define MPI_CSBASE_SIZE_8M 10
  699. #define MPI_CSBASE_SIZE_16M 11
  700. #define MPI_CSBASE_SIZE_32M 12
  701. #define MPI_CSBASE_SIZE_64M 13
  702. #define MPI_CSBASE_SIZE_128M 14
  703. #define MPI_CSBASE_SIZE_256M 15
  704. /* Chip select control register */
  705. #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
  706. #define MPI_CSCTL_ENABLE_MASK (1 << 0)
  707. #define MPI_CSCTL_WAIT_SHIFT 1
  708. #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
  709. #define MPI_CSCTL_DATA16_MASK (1 << 4)
  710. #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
  711. #define MPI_CSCTL_TSIZE_MASK (1 << 8)
  712. #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
  713. #define MPI_CSCTL_SETUP_SHIFT 16
  714. #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
  715. #define MPI_CSCTL_HOLD_SHIFT 20
  716. #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
  717. /* PCI registers */
  718. #define MPI_SP0_RANGE_REG 0x100
  719. #define MPI_SP0_REMAP_REG 0x104
  720. #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
  721. #define MPI_SP1_RANGE_REG 0x10C
  722. #define MPI_SP1_REMAP_REG 0x110
  723. #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
  724. #define MPI_L2PCFG_REG 0x11C
  725. #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
  726. #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
  727. #define MPI_L2PCFG_REG_SHIFT 2
  728. #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
  729. #define MPI_L2PCFG_FUNC_SHIFT 8
  730. #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
  731. #define MPI_L2PCFG_DEVNUM_SHIFT 11
  732. #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
  733. #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
  734. #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
  735. #define MPI_L2PMEMRANGE1_REG 0x120
  736. #define MPI_L2PMEMBASE1_REG 0x124
  737. #define MPI_L2PMEMREMAP1_REG 0x128
  738. #define MPI_L2PMEMRANGE2_REG 0x12C
  739. #define MPI_L2PMEMBASE2_REG 0x130
  740. #define MPI_L2PMEMREMAP2_REG 0x134
  741. #define MPI_L2PIORANGE_REG 0x138
  742. #define MPI_L2PIOBASE_REG 0x13C
  743. #define MPI_L2PIOREMAP_REG 0x140
  744. #define MPI_L2P_BASE_MASK (0xffff8000)
  745. #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
  746. #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
  747. #define MPI_PCIMODESEL_REG 0x144
  748. #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
  749. #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
  750. #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
  751. #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
  752. #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
  753. #define MPI_LOCBUSCTL_REG 0x14C
  754. #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
  755. #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
  756. #define MPI_LOCINT_REG 0x150
  757. #define MPI_LOCINT_MASK(x) (1 << (x + 16))
  758. #define MPI_LOCINT_STAT(x) (1 << (x))
  759. #define MPI_LOCINT_DIR_FAILED 6
  760. #define MPI_LOCINT_EXT_PCI_INT 7
  761. #define MPI_LOCINT_SERR 8
  762. #define MPI_LOCINT_CSERR 9
  763. #define MPI_PCICFGCTL_REG 0x178
  764. #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
  765. #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
  766. #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
  767. #define MPI_PCICFGDATA_REG 0x17C
  768. /* PCI host bridge custom register */
  769. #define BCMPCI_REG_TIMERS 0x40
  770. #define REG_TIMER_TRDY_SHIFT 0
  771. #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
  772. #define REG_TIMER_RETRY_SHIFT 8
  773. #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
  774. /*************************************************************************
  775. * _REG relative to RSET_PCMCIA
  776. *************************************************************************/
  777. #define PCMCIA_C1_REG 0x0
  778. #define PCMCIA_C1_CD1_MASK (1 << 0)
  779. #define PCMCIA_C1_CD2_MASK (1 << 1)
  780. #define PCMCIA_C1_VS1_MASK (1 << 2)
  781. #define PCMCIA_C1_VS2_MASK (1 << 3)
  782. #define PCMCIA_C1_VS1OE_MASK (1 << 6)
  783. #define PCMCIA_C1_VS2OE_MASK (1 << 7)
  784. #define PCMCIA_C1_CBIDSEL_SHIFT (8)
  785. #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
  786. #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
  787. #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
  788. #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
  789. #define PCMCIA_C1_RESET_MASK (1 << 18)
  790. #define PCMCIA_C2_REG 0x8
  791. #define PCMCIA_C2_DATA16_MASK (1 << 0)
  792. #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
  793. #define PCMCIA_C2_RWCOUNT_SHIFT 2
  794. #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
  795. #define PCMCIA_C2_INACTIVE_SHIFT 8
  796. #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
  797. #define PCMCIA_C2_SETUP_SHIFT 16
  798. #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
  799. #define PCMCIA_C2_HOLD_SHIFT 24
  800. #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
  801. /*************************************************************************
  802. * _REG relative to RSET_SDRAM
  803. *************************************************************************/
  804. #define SDRAM_CFG_REG 0x0
  805. #define SDRAM_CFG_ROW_SHIFT 4
  806. #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
  807. #define SDRAM_CFG_COL_SHIFT 6
  808. #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
  809. #define SDRAM_CFG_32B_SHIFT 10
  810. #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
  811. #define SDRAM_CFG_BANK_SHIFT 13
  812. #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
  813. #define SDRAM_MBASE_REG 0xc
  814. #define SDRAM_PRIO_REG 0x2C
  815. #define SDRAM_PRIO_MIPS_SHIFT 29
  816. #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
  817. #define SDRAM_PRIO_ADSL_SHIFT 30
  818. #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
  819. #define SDRAM_PRIO_EN_SHIFT 31
  820. #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
  821. /*************************************************************************
  822. * _REG relative to RSET_MEMC
  823. *************************************************************************/
  824. #define MEMC_CFG_REG 0x4
  825. #define MEMC_CFG_32B_SHIFT 1
  826. #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
  827. #define MEMC_CFG_COL_SHIFT 3
  828. #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
  829. #define MEMC_CFG_ROW_SHIFT 6
  830. #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
  831. /*************************************************************************
  832. * _REG relative to RSET_DDR
  833. *************************************************************************/
  834. #define DDR_CSEND_REG 0x8
  835. #define DDR_DMIPSPLLCFG_REG 0x18
  836. #define DMIPSPLLCFG_M1_SHIFT 0
  837. #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
  838. #define DMIPSPLLCFG_N1_SHIFT 23
  839. #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
  840. #define DMIPSPLLCFG_N2_SHIFT 29
  841. #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
  842. #define DDR_DMIPSPLLCFG_6368_REG 0x20
  843. #define DMIPSPLLCFG_6368_P1_SHIFT 0
  844. #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
  845. #define DMIPSPLLCFG_6368_P2_SHIFT 4
  846. #define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
  847. #define DMIPSPLLCFG_6368_NDIV_SHIFT 16
  848. #define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
  849. #define DDR_DMIPSPLLDIV_6368_REG 0x24
  850. #define DMIPSPLLDIV_6368_MDIV_SHIFT 0
  851. #define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
  852. /*************************************************************************
  853. * _REG relative to RSET_M2M
  854. *************************************************************************/
  855. #define M2M_RX 0
  856. #define M2M_TX 1
  857. #define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
  858. #define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
  859. #define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
  860. #define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
  861. #define M2M_CTRL_ENABLE_MASK (1 << 0)
  862. #define M2M_CTRL_IRQEN_MASK (1 << 1)
  863. #define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
  864. #define M2M_CTRL_DONE_CLR_MASK (1 << 7)
  865. #define M2M_CTRL_NOINC_MASK (1 << 8)
  866. #define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
  867. #define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
  868. #define M2M_CTRL_ENDIAN_MASK (1 << 11)
  869. #define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
  870. #define M2M_STAT_DONE (1 << 0)
  871. #define M2M_STAT_ERROR (1 << 1)
  872. #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
  873. #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
  874. /*************************************************************************
  875. * _REG relative to RSET_RNG
  876. *************************************************************************/
  877. #define RNG_CTRL 0x00
  878. #define RNG_EN (1 << 0)
  879. #define RNG_STAT 0x04
  880. #define RNG_AVAIL_MASK (0xff000000)
  881. #define RNG_DATA 0x08
  882. #define RNG_THRES 0x0c
  883. #define RNG_MASK 0x10
  884. /*************************************************************************
  885. * _REG relative to RSET_SPI
  886. *************************************************************************/
  887. /* BCM 6338 SPI core */
  888. #define SPI_6338_CMD 0x00 /* 16-bits register */
  889. #define SPI_6338_INT_STATUS 0x02
  890. #define SPI_6338_INT_MASK_ST 0x03
  891. #define SPI_6338_INT_MASK 0x04
  892. #define SPI_6338_ST 0x05
  893. #define SPI_6338_CLK_CFG 0x06
  894. #define SPI_6338_FILL_BYTE 0x07
  895. #define SPI_6338_MSG_TAIL 0x09
  896. #define SPI_6338_RX_TAIL 0x0b
  897. #define SPI_6338_MSG_CTL 0x40
  898. #define SPI_6338_MSG_DATA 0x41
  899. #define SPI_6338_MSG_DATA_SIZE 0x3f
  900. #define SPI_6338_RX_DATA 0x80
  901. #define SPI_6338_RX_DATA_SIZE 0x3f
  902. /* BCM 6348 SPI core */
  903. #define SPI_6348_CMD 0x00 /* 16-bits register */
  904. #define SPI_6348_INT_STATUS 0x02
  905. #define SPI_6348_INT_MASK_ST 0x03
  906. #define SPI_6348_INT_MASK 0x04
  907. #define SPI_6348_ST 0x05
  908. #define SPI_6348_CLK_CFG 0x06
  909. #define SPI_6348_FILL_BYTE 0x07
  910. #define SPI_6348_MSG_TAIL 0x09
  911. #define SPI_6348_RX_TAIL 0x0b
  912. #define SPI_6348_MSG_CTL 0x40
  913. #define SPI_6348_MSG_DATA 0x41
  914. #define SPI_6348_MSG_DATA_SIZE 0x3f
  915. #define SPI_6348_RX_DATA 0x80
  916. #define SPI_6348_RX_DATA_SIZE 0x3f
  917. /* BCM 6358 SPI core */
  918. #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
  919. #define SPI_6358_MSG_DATA 0x02
  920. #define SPI_6358_MSG_DATA_SIZE 0x21e
  921. #define SPI_6358_RX_DATA 0x400
  922. #define SPI_6358_RX_DATA_SIZE 0x220
  923. #define SPI_6358_CMD 0x700 /* 16-bits register */
  924. #define SPI_6358_INT_STATUS 0x702
  925. #define SPI_6358_INT_MASK_ST 0x703
  926. #define SPI_6358_INT_MASK 0x704
  927. #define SPI_6358_ST 0x705
  928. #define SPI_6358_CLK_CFG 0x706
  929. #define SPI_6358_FILL_BYTE 0x707
  930. #define SPI_6358_MSG_TAIL 0x709
  931. #define SPI_6358_RX_TAIL 0x70B
  932. /* BCM 6358 SPI core */
  933. #define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
  934. #define SPI_6368_MSG_DATA 0x02
  935. #define SPI_6368_MSG_DATA_SIZE 0x21e
  936. #define SPI_6368_RX_DATA 0x400
  937. #define SPI_6368_RX_DATA_SIZE 0x220
  938. #define SPI_6368_CMD 0x700 /* 16-bits register */
  939. #define SPI_6368_INT_STATUS 0x702
  940. #define SPI_6368_INT_MASK_ST 0x703
  941. #define SPI_6368_INT_MASK 0x704
  942. #define SPI_6368_ST 0x705
  943. #define SPI_6368_CLK_CFG 0x706
  944. #define SPI_6368_FILL_BYTE 0x707
  945. #define SPI_6368_MSG_TAIL 0x709
  946. #define SPI_6368_RX_TAIL 0x70B
  947. /* Shared SPI definitions */
  948. /* Message configuration */
  949. #define SPI_FD_RW 0x00
  950. #define SPI_HD_W 0x01
  951. #define SPI_HD_R 0x02
  952. #define SPI_BYTE_CNT_SHIFT 0
  953. #define SPI_MSG_TYPE_SHIFT 14
  954. /* Command */
  955. #define SPI_CMD_NOOP 0x00
  956. #define SPI_CMD_SOFT_RESET 0x01
  957. #define SPI_CMD_HARD_RESET 0x02
  958. #define SPI_CMD_START_IMMEDIATE 0x03
  959. #define SPI_CMD_COMMAND_SHIFT 0
  960. #define SPI_CMD_COMMAND_MASK 0x000f
  961. #define SPI_CMD_DEVICE_ID_SHIFT 4
  962. #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
  963. #define SPI_CMD_ONE_BYTE_SHIFT 11
  964. #define SPI_CMD_ONE_WIRE_SHIFT 12
  965. #define SPI_DEV_ID_0 0
  966. #define SPI_DEV_ID_1 1
  967. #define SPI_DEV_ID_2 2
  968. #define SPI_DEV_ID_3 3
  969. /* Interrupt mask */
  970. #define SPI_INTR_CMD_DONE 0x01
  971. #define SPI_INTR_RX_OVERFLOW 0x02
  972. #define SPI_INTR_TX_UNDERFLOW 0x04
  973. #define SPI_INTR_TX_OVERFLOW 0x08
  974. #define SPI_INTR_RX_UNDERFLOW 0x10
  975. #define SPI_INTR_CLEAR_ALL 0x1f
  976. /* Status */
  977. #define SPI_RX_EMPTY 0x02
  978. #define SPI_CMD_BUSY 0x04
  979. #define SPI_SERIAL_BUSY 0x08
  980. /* Clock configuration */
  981. #define SPI_CLK_20MHZ 0x00
  982. #define SPI_CLK_0_391MHZ 0x01
  983. #define SPI_CLK_0_781MHZ 0x02 /* default */
  984. #define SPI_CLK_1_563MHZ 0x03
  985. #define SPI_CLK_3_125MHZ 0x04
  986. #define SPI_CLK_6_250MHZ 0x05
  987. #define SPI_CLK_12_50MHZ 0x06
  988. #define SPI_CLK_MASK 0x07
  989. #define SPI_SSOFFTIME_MASK 0x38
  990. #define SPI_SSOFFTIME_SHIFT 3
  991. #define SPI_BYTE_SWAP 0x80
  992. /*************************************************************************
  993. * _REG relative to RSET_MISC
  994. *************************************************************************/
  995. #define MISC_SERDES_CTRL_REG 0x0
  996. #define SERDES_PCIE_EN (1 << 0)
  997. #define SERDES_PCIE_EXD_EN (1 << 15)
  998. #define MISC_STRAPBUS_6328_REG 0x240
  999. #define STRAPBUS_6328_FCVO_SHIFT 7
  1000. #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
  1001. #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
  1002. #define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
  1003. /*************************************************************************
  1004. * _REG relative to RSET_PCIE
  1005. *************************************************************************/
  1006. #define PCIE_CONFIG2_REG 0x408
  1007. #define CONFIG2_BAR1_SIZE_EN 1
  1008. #define CONFIG2_BAR1_SIZE_MASK 0xf
  1009. #define PCIE_IDVAL3_REG 0x43c
  1010. #define IDVAL3_CLASS_CODE_MASK 0xffffff
  1011. #define IDVAL3_SUBCLASS_SHIFT 8
  1012. #define IDVAL3_CLASS_SHIFT 16
  1013. #define PCIE_DLSTATUS_REG 0x1048
  1014. #define DLSTATUS_PHYLINKUP (1 << 13)
  1015. #define PCIE_BRIDGE_OPT1_REG 0x2820
  1016. #define OPT1_RD_BE_OPT_EN (1 << 7)
  1017. #define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
  1018. #define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
  1019. #define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
  1020. #define PCIE_BRIDGE_OPT2_REG 0x2824
  1021. #define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
  1022. #define OPT2_TX_CREDIT_CHK_EN (1 << 4)
  1023. #define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
  1024. #define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
  1025. #define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
  1026. #define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
  1027. #define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
  1028. #define BASEMASK_REMAP_EN (1 << 0)
  1029. #define BASEMASK_SWAP_EN (1 << 1)
  1030. #define BASEMASK_MASK_SHIFT 4
  1031. #define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
  1032. #define BASEMASK_BASE_SHIFT 20
  1033. #define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
  1034. #define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
  1035. #define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
  1036. #define REBASE_ADDR_BASE_SHIFT 20
  1037. #define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
  1038. #define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
  1039. #define PCIE_RC_INT_A (1 << 0)
  1040. #define PCIE_RC_INT_B (1 << 1)
  1041. #define PCIE_RC_INT_C (1 << 2)
  1042. #define PCIE_RC_INT_D (1 << 3)
  1043. #define PCIE_DEVICE_OFFSET 0x8000
  1044. #endif /* BCM63XX_REGS_H_ */