ezkit.c 37 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mtd/mtd.h>
  11. #include <linux/mtd/partitions.h>
  12. #include <linux/mtd/physmap.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/irq.h>
  16. #include <linux/i2c.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/usb/musb.h>
  19. #include <asm/bfin6xx_spi.h>
  20. #include <asm/dma.h>
  21. #include <asm/gpio.h>
  22. #include <asm/nand.h>
  23. #include <asm/dpmc.h>
  24. #include <asm/portmux.h>
  25. #include <asm/bfin_sdh.h>
  26. #include <linux/input.h>
  27. #include <linux/spi/ad7877.h>
  28. /*
  29. * Name the Board for the /proc/cpuinfo
  30. */
  31. const char bfin_board_name[] = "ADI BF609-EZKIT";
  32. /*
  33. * Driver needs to know address, irq and flag pin.
  34. */
  35. #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  36. #include <linux/usb/isp1760.h>
  37. static struct resource bfin_isp1760_resources[] = {
  38. [0] = {
  39. .start = 0x2C0C0000,
  40. .end = 0x2C0C0000 + 0xfffff,
  41. .flags = IORESOURCE_MEM,
  42. },
  43. [1] = {
  44. .start = IRQ_PG7,
  45. .end = IRQ_PG7,
  46. .flags = IORESOURCE_IRQ,
  47. },
  48. };
  49. static struct isp1760_platform_data isp1760_priv = {
  50. .is_isp1761 = 0,
  51. .bus_width_16 = 1,
  52. .port1_otg = 0,
  53. .analog_oc = 0,
  54. .dack_polarity_high = 0,
  55. .dreq_polarity_high = 0,
  56. };
  57. static struct platform_device bfin_isp1760_device = {
  58. .name = "isp1760",
  59. .id = 0,
  60. .dev = {
  61. .platform_data = &isp1760_priv,
  62. },
  63. .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
  64. .resource = bfin_isp1760_resources,
  65. };
  66. #endif
  67. #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
  68. #include <asm/bfin_rotary.h>
  69. static struct bfin_rotary_platform_data bfin_rotary_data = {
  70. /*.rotary_up_key = KEY_UP,*/
  71. /*.rotary_down_key = KEY_DOWN,*/
  72. .rotary_rel_code = REL_WHEEL,
  73. .rotary_button_key = KEY_ENTER,
  74. .debounce = 10, /* 0..17 */
  75. .mode = ROT_QUAD_ENC | ROT_DEBE,
  76. };
  77. static struct resource bfin_rotary_resources[] = {
  78. {
  79. .start = IRQ_CNT,
  80. .end = IRQ_CNT,
  81. .flags = IORESOURCE_IRQ,
  82. },
  83. };
  84. static struct platform_device bfin_rotary_device = {
  85. .name = "bfin-rotary",
  86. .id = -1,
  87. .num_resources = ARRAY_SIZE(bfin_rotary_resources),
  88. .resource = bfin_rotary_resources,
  89. .dev = {
  90. .platform_data = &bfin_rotary_data,
  91. },
  92. };
  93. #endif
  94. #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
  95. #include <linux/stmmac.h>
  96. static unsigned short pins[] = P_RMII0;
  97. static struct stmmac_mdio_bus_data phy_private_data = {
  98. .bus_id = 0,
  99. .phy_mask = 1,
  100. };
  101. static struct plat_stmmacenet_data eth_private_data = {
  102. .bus_id = 0,
  103. .enh_desc = 1,
  104. .phy_addr = 1,
  105. .mdio_bus_data = &phy_private_data,
  106. };
  107. static struct platform_device bfin_eth_device = {
  108. .name = "stmmaceth",
  109. .id = 0,
  110. .num_resources = 2,
  111. .resource = (struct resource[]) {
  112. {
  113. .start = EMAC0_MACCFG,
  114. .end = EMAC0_MACCFG + 0x1274,
  115. .flags = IORESOURCE_MEM,
  116. },
  117. {
  118. .name = "macirq",
  119. .start = IRQ_EMAC0_STAT,
  120. .end = IRQ_EMAC0_STAT,
  121. .flags = IORESOURCE_IRQ,
  122. },
  123. },
  124. .dev = {
  125. .power.can_wakeup = 1,
  126. .platform_data = &eth_private_data,
  127. }
  128. };
  129. #endif
  130. #if defined(CONFIG_INPUT_ADXL34X) || defined(CONFIG_INPUT_ADXL34X_MODULE)
  131. #include <linux/input/adxl34x.h>
  132. static const struct adxl34x_platform_data adxl34x_info = {
  133. .x_axis_offset = 0,
  134. .y_axis_offset = 0,
  135. .z_axis_offset = 0,
  136. .tap_threshold = 0x31,
  137. .tap_duration = 0x10,
  138. .tap_latency = 0x60,
  139. .tap_window = 0xF0,
  140. .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN,
  141. .act_axis_control = 0xFF,
  142. .activity_threshold = 5,
  143. .inactivity_threshold = 3,
  144. .inactivity_time = 4,
  145. .free_fall_threshold = 0x7,
  146. .free_fall_time = 0x20,
  147. .data_rate = 0x8,
  148. .data_range = ADXL_FULL_RES,
  149. .ev_type = EV_ABS,
  150. .ev_code_x = ABS_X, /* EV_REL */
  151. .ev_code_y = ABS_Y, /* EV_REL */
  152. .ev_code_z = ABS_Z, /* EV_REL */
  153. .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */
  154. /* .ev_code_ff = KEY_F,*/ /* EV_KEY */
  155. /* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */
  156. .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK,
  157. .fifo_mode = ADXL_FIFO_STREAM,
  158. .orientation_enable = ADXL_EN_ORIENTATION_3D,
  159. .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8,
  160. .divisor_length = ADXL_LP_FILTER_DIVISOR_16,
  161. /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */
  162. .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C},
  163. };
  164. #endif
  165. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  166. static struct platform_device rtc_device = {
  167. .name = "rtc-bfin",
  168. .id = -1,
  169. };
  170. #endif
  171. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  172. #ifdef CONFIG_SERIAL_BFIN_UART0
  173. static struct resource bfin_uart0_resources[] = {
  174. {
  175. .start = UART0_REVID,
  176. .end = UART0_RXDIV+4,
  177. .flags = IORESOURCE_MEM,
  178. },
  179. {
  180. .start = IRQ_UART0_TX,
  181. .end = IRQ_UART0_TX,
  182. .flags = IORESOURCE_IRQ,
  183. },
  184. {
  185. .start = IRQ_UART0_RX,
  186. .end = IRQ_UART0_RX,
  187. .flags = IORESOURCE_IRQ,
  188. },
  189. {
  190. .start = IRQ_UART0_STAT,
  191. .end = IRQ_UART0_STAT,
  192. .flags = IORESOURCE_IRQ,
  193. },
  194. {
  195. .start = CH_UART0_TX,
  196. .end = CH_UART0_TX,
  197. .flags = IORESOURCE_DMA,
  198. },
  199. {
  200. .start = CH_UART0_RX,
  201. .end = CH_UART0_RX,
  202. .flags = IORESOURCE_DMA,
  203. },
  204. #ifdef CONFIG_BFIN_UART0_CTSRTS
  205. { /* CTS pin -- 0 means not supported */
  206. .start = GPIO_PD10,
  207. .end = GPIO_PD10,
  208. .flags = IORESOURCE_IO,
  209. },
  210. { /* RTS pin -- 0 means not supported */
  211. .start = GPIO_PD9,
  212. .end = GPIO_PD9,
  213. .flags = IORESOURCE_IO,
  214. },
  215. #endif
  216. };
  217. static unsigned short bfin_uart0_peripherals[] = {
  218. P_UART0_TX, P_UART0_RX,
  219. #ifdef CONFIG_BFIN_UART0_CTSRTS
  220. P_UART0_RTS, P_UART0_CTS,
  221. #endif
  222. 0
  223. };
  224. static struct platform_device bfin_uart0_device = {
  225. .name = "bfin-uart",
  226. .id = 0,
  227. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  228. .resource = bfin_uart0_resources,
  229. .dev = {
  230. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  231. },
  232. };
  233. #endif
  234. #ifdef CONFIG_SERIAL_BFIN_UART1
  235. static struct resource bfin_uart1_resources[] = {
  236. {
  237. .start = UART1_REVID,
  238. .end = UART1_RXDIV+4,
  239. .flags = IORESOURCE_MEM,
  240. },
  241. {
  242. .start = IRQ_UART1_TX,
  243. .end = IRQ_UART1_TX,
  244. .flags = IORESOURCE_IRQ,
  245. },
  246. {
  247. .start = IRQ_UART1_RX,
  248. .end = IRQ_UART1_RX,
  249. .flags = IORESOURCE_IRQ,
  250. },
  251. {
  252. .start = IRQ_UART1_STAT,
  253. .end = IRQ_UART1_STAT,
  254. .flags = IORESOURCE_IRQ,
  255. },
  256. {
  257. .start = CH_UART1_TX,
  258. .end = CH_UART1_TX,
  259. .flags = IORESOURCE_DMA,
  260. },
  261. {
  262. .start = CH_UART1_RX,
  263. .end = CH_UART1_RX,
  264. .flags = IORESOURCE_DMA,
  265. },
  266. #ifdef CONFIG_BFIN_UART1_CTSRTS
  267. { /* CTS pin -- 0 means not supported */
  268. .start = GPIO_PG13,
  269. .end = GPIO_PG13,
  270. .flags = IORESOURCE_IO,
  271. },
  272. { /* RTS pin -- 0 means not supported */
  273. .start = GPIO_PG10,
  274. .end = GPIO_PG10,
  275. .flags = IORESOURCE_IO,
  276. },
  277. #endif
  278. };
  279. static unsigned short bfin_uart1_peripherals[] = {
  280. P_UART1_TX, P_UART1_RX,
  281. #ifdef CONFIG_BFIN_UART1_CTSRTS
  282. P_UART1_RTS, P_UART1_CTS,
  283. #endif
  284. 0
  285. };
  286. static struct platform_device bfin_uart1_device = {
  287. .name = "bfin-uart",
  288. .id = 1,
  289. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  290. .resource = bfin_uart1_resources,
  291. .dev = {
  292. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  293. },
  294. };
  295. #endif
  296. #endif
  297. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  298. #ifdef CONFIG_BFIN_SIR0
  299. static struct resource bfin_sir0_resources[] = {
  300. {
  301. .start = 0xFFC00400,
  302. .end = 0xFFC004FF,
  303. .flags = IORESOURCE_MEM,
  304. },
  305. {
  306. .start = IRQ_UART0_TX,
  307. .end = IRQ_UART0_TX+1,
  308. .flags = IORESOURCE_IRQ,
  309. },
  310. {
  311. .start = CH_UART0_TX,
  312. .end = CH_UART0_TX+1,
  313. .flags = IORESOURCE_DMA,
  314. },
  315. };
  316. static struct platform_device bfin_sir0_device = {
  317. .name = "bfin_sir",
  318. .id = 0,
  319. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  320. .resource = bfin_sir0_resources,
  321. };
  322. #endif
  323. #ifdef CONFIG_BFIN_SIR1
  324. static struct resource bfin_sir1_resources[] = {
  325. {
  326. .start = 0xFFC02000,
  327. .end = 0xFFC020FF,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. {
  331. .start = IRQ_UART1_TX,
  332. .end = IRQ_UART1_TX+1,
  333. .flags = IORESOURCE_IRQ,
  334. },
  335. {
  336. .start = CH_UART1_TX,
  337. .end = CH_UART1_TX+1,
  338. .flags = IORESOURCE_DMA,
  339. },
  340. };
  341. static struct platform_device bfin_sir1_device = {
  342. .name = "bfin_sir",
  343. .id = 1,
  344. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  345. .resource = bfin_sir1_resources,
  346. };
  347. #endif
  348. #endif
  349. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  350. static struct resource musb_resources[] = {
  351. [0] = {
  352. .start = 0xFFCC1000,
  353. .end = 0xFFCC1398,
  354. .flags = IORESOURCE_MEM,
  355. },
  356. [1] = { /* general IRQ */
  357. .start = IRQ_USB_STAT,
  358. .end = IRQ_USB_STAT,
  359. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  360. .name = "mc"
  361. },
  362. [2] = { /* DMA IRQ */
  363. .start = IRQ_USB_DMA,
  364. .end = IRQ_USB_DMA,
  365. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  366. .name = "dma"
  367. },
  368. };
  369. static struct musb_hdrc_config musb_config = {
  370. .multipoint = 1,
  371. .dyn_fifo = 0,
  372. .dma = 1,
  373. .num_eps = 16,
  374. .dma_channels = 8,
  375. .clkin = 48, /* musb CLKIN in MHZ */
  376. };
  377. static struct musb_hdrc_platform_data musb_plat = {
  378. #if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
  379. .mode = MUSB_OTG,
  380. #elif defined(CONFIG_USB_MUSB_HDRC)
  381. .mode = MUSB_HOST,
  382. #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
  383. .mode = MUSB_PERIPHERAL,
  384. #endif
  385. .config = &musb_config,
  386. };
  387. static u64 musb_dmamask = ~(u32)0;
  388. static struct platform_device musb_device = {
  389. .name = "musb-blackfin",
  390. .id = 0,
  391. .dev = {
  392. .dma_mask = &musb_dmamask,
  393. .coherent_dma_mask = 0xffffffff,
  394. .platform_data = &musb_plat,
  395. },
  396. .num_resources = ARRAY_SIZE(musb_resources),
  397. .resource = musb_resources,
  398. };
  399. #endif
  400. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  401. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  402. static struct resource bfin_sport0_uart_resources[] = {
  403. {
  404. .start = SPORT0_TCR1,
  405. .end = SPORT0_MRCS3+4,
  406. .flags = IORESOURCE_MEM,
  407. },
  408. {
  409. .start = IRQ_SPORT0_RX,
  410. .end = IRQ_SPORT0_RX+1,
  411. .flags = IORESOURCE_IRQ,
  412. },
  413. {
  414. .start = IRQ_SPORT0_ERROR,
  415. .end = IRQ_SPORT0_ERROR,
  416. .flags = IORESOURCE_IRQ,
  417. },
  418. };
  419. static unsigned short bfin_sport0_peripherals[] = {
  420. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  421. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  422. };
  423. static struct platform_device bfin_sport0_uart_device = {
  424. .name = "bfin-sport-uart",
  425. .id = 0,
  426. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  427. .resource = bfin_sport0_uart_resources,
  428. .dev = {
  429. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  430. },
  431. };
  432. #endif
  433. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  434. static struct resource bfin_sport1_uart_resources[] = {
  435. {
  436. .start = SPORT1_TCR1,
  437. .end = SPORT1_MRCS3+4,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. {
  441. .start = IRQ_SPORT1_RX,
  442. .end = IRQ_SPORT1_RX+1,
  443. .flags = IORESOURCE_IRQ,
  444. },
  445. {
  446. .start = IRQ_SPORT1_ERROR,
  447. .end = IRQ_SPORT1_ERROR,
  448. .flags = IORESOURCE_IRQ,
  449. },
  450. };
  451. static unsigned short bfin_sport1_peripherals[] = {
  452. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  453. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  454. };
  455. static struct platform_device bfin_sport1_uart_device = {
  456. .name = "bfin-sport-uart",
  457. .id = 1,
  458. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  459. .resource = bfin_sport1_uart_resources,
  460. .dev = {
  461. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  462. },
  463. };
  464. #endif
  465. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  466. static struct resource bfin_sport2_uart_resources[] = {
  467. {
  468. .start = SPORT2_TCR1,
  469. .end = SPORT2_MRCS3+4,
  470. .flags = IORESOURCE_MEM,
  471. },
  472. {
  473. .start = IRQ_SPORT2_RX,
  474. .end = IRQ_SPORT2_RX+1,
  475. .flags = IORESOURCE_IRQ,
  476. },
  477. {
  478. .start = IRQ_SPORT2_ERROR,
  479. .end = IRQ_SPORT2_ERROR,
  480. .flags = IORESOURCE_IRQ,
  481. },
  482. };
  483. static unsigned short bfin_sport2_peripherals[] = {
  484. P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
  485. P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
  486. };
  487. static struct platform_device bfin_sport2_uart_device = {
  488. .name = "bfin-sport-uart",
  489. .id = 2,
  490. .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
  491. .resource = bfin_sport2_uart_resources,
  492. .dev = {
  493. .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
  494. },
  495. };
  496. #endif
  497. #endif
  498. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  499. static unsigned short bfin_can0_peripherals[] = {
  500. P_CAN0_RX, P_CAN0_TX, 0
  501. };
  502. static struct resource bfin_can0_resources[] = {
  503. {
  504. .start = 0xFFC00A00,
  505. .end = 0xFFC00FFF,
  506. .flags = IORESOURCE_MEM,
  507. },
  508. {
  509. .start = IRQ_CAN0_RX,
  510. .end = IRQ_CAN0_RX,
  511. .flags = IORESOURCE_IRQ,
  512. },
  513. {
  514. .start = IRQ_CAN0_TX,
  515. .end = IRQ_CAN0_TX,
  516. .flags = IORESOURCE_IRQ,
  517. },
  518. {
  519. .start = IRQ_CAN0_STAT,
  520. .end = IRQ_CAN0_STAT,
  521. .flags = IORESOURCE_IRQ,
  522. },
  523. };
  524. static struct platform_device bfin_can0_device = {
  525. .name = "bfin_can",
  526. .id = 0,
  527. .num_resources = ARRAY_SIZE(bfin_can0_resources),
  528. .resource = bfin_can0_resources,
  529. .dev = {
  530. .platform_data = &bfin_can0_peripherals, /* Passed to driver */
  531. },
  532. };
  533. #endif
  534. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  535. static struct mtd_partition partition_info[] = {
  536. {
  537. .name = "bootloader(nand)",
  538. .offset = 0,
  539. .size = 0x80000,
  540. }, {
  541. .name = "linux kernel(nand)",
  542. .offset = MTDPART_OFS_APPEND,
  543. .size = 4 * 1024 * 1024,
  544. },
  545. {
  546. .name = "file system(nand)",
  547. .offset = MTDPART_OFS_APPEND,
  548. .size = MTDPART_SIZ_FULL,
  549. },
  550. };
  551. static struct bf5xx_nand_platform bfin_nand_platform = {
  552. .data_width = NFC_NWIDTH_8,
  553. .partitions = partition_info,
  554. .nr_partitions = ARRAY_SIZE(partition_info),
  555. .rd_dly = 3,
  556. .wr_dly = 3,
  557. };
  558. static struct resource bfin_nand_resources[] = {
  559. {
  560. .start = 0xFFC03B00,
  561. .end = 0xFFC03B4F,
  562. .flags = IORESOURCE_MEM,
  563. },
  564. {
  565. .start = CH_NFC,
  566. .end = CH_NFC,
  567. .flags = IORESOURCE_IRQ,
  568. },
  569. };
  570. static struct platform_device bfin_nand_device = {
  571. .name = "bfin-nand",
  572. .id = 0,
  573. .num_resources = ARRAY_SIZE(bfin_nand_resources),
  574. .resource = bfin_nand_resources,
  575. .dev = {
  576. .platform_data = &bfin_nand_platform,
  577. },
  578. };
  579. #endif
  580. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  581. static struct bfin_sd_host bfin_sdh_data = {
  582. .dma_chan = CH_RSI,
  583. .irq_int0 = IRQ_RSI_INT0,
  584. .pin_req = {P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0},
  585. };
  586. static struct platform_device bfin_sdh_device = {
  587. .name = "bfin-sdh",
  588. .id = 0,
  589. .dev = {
  590. .platform_data = &bfin_sdh_data,
  591. },
  592. };
  593. #endif
  594. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  595. static struct mtd_partition ezkit_partitions[] = {
  596. {
  597. .name = "bootloader(nor)",
  598. .size = 0x80000,
  599. .offset = 0,
  600. }, {
  601. .name = "linux kernel(nor)",
  602. .size = 0x400000,
  603. .offset = MTDPART_OFS_APPEND,
  604. }, {
  605. .name = "file system(nor)",
  606. .size = 0x1000000 - 0x80000 - 0x400000,
  607. .offset = MTDPART_OFS_APPEND,
  608. },
  609. };
  610. int bf609_nor_flash_init(struct platform_device *dev)
  611. {
  612. #define CONFIG_SMC_GCTL_VAL 0x00000010
  613. const unsigned short pins[] = {
  614. P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
  615. P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
  616. P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
  617. };
  618. peripheral_request_list(pins, "smc0");
  619. bfin_write32(SMC_GCTL, CONFIG_SMC_GCTL_VAL);
  620. bfin_write32(SMC_B0CTL, 0x01002011);
  621. bfin_write32(SMC_B0TIM, 0x08170977);
  622. bfin_write32(SMC_B0ETIM, 0x00092231);
  623. return 0;
  624. }
  625. void bf609_nor_flash_exit(struct platform_device *dev)
  626. {
  627. const unsigned short pins[] = {
  628. P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
  629. P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
  630. P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
  631. };
  632. peripheral_free_list(pins);
  633. bfin_write32(SMC_GCTL, 0);
  634. }
  635. static struct physmap_flash_data ezkit_flash_data = {
  636. .width = 2,
  637. .parts = ezkit_partitions,
  638. .init = bf609_nor_flash_init,
  639. .exit = bf609_nor_flash_exit,
  640. .nr_parts = ARRAY_SIZE(ezkit_partitions),
  641. #ifdef CONFIG_ROMKERNEL
  642. .probe_type = "map_rom",
  643. #endif
  644. };
  645. static struct resource ezkit_flash_resource = {
  646. .start = 0xb0000000,
  647. .end = 0xb0ffffff,
  648. .flags = IORESOURCE_MEM,
  649. };
  650. static struct platform_device ezkit_flash_device = {
  651. .name = "physmap-flash",
  652. .id = 0,
  653. .dev = {
  654. .platform_data = &ezkit_flash_data,
  655. },
  656. .num_resources = 1,
  657. .resource = &ezkit_flash_resource,
  658. };
  659. #endif
  660. #if defined(CONFIG_MTD_M25P80) \
  661. || defined(CONFIG_MTD_M25P80_MODULE)
  662. /* SPI flash chip (w25q32) */
  663. static struct mtd_partition bfin_spi_flash_partitions[] = {
  664. {
  665. .name = "bootloader(spi)",
  666. .size = 0x00080000,
  667. .offset = 0,
  668. .mask_flags = MTD_CAP_ROM
  669. }, {
  670. .name = "linux kernel(spi)",
  671. .size = 0x00180000,
  672. .offset = MTDPART_OFS_APPEND,
  673. }, {
  674. .name = "file system(spi)",
  675. .size = MTDPART_SIZ_FULL,
  676. .offset = MTDPART_OFS_APPEND,
  677. }
  678. };
  679. static struct flash_platform_data bfin_spi_flash_data = {
  680. .name = "m25p80",
  681. .parts = bfin_spi_flash_partitions,
  682. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  683. .type = "w25q32",
  684. };
  685. static struct bfin6xx_spi_chip spi_flash_chip_info = {
  686. .enable_dma = true, /* use dma transfer with this chip*/
  687. };
  688. #endif
  689. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  690. static struct bfin6xx_spi_chip spidev_chip_info = {
  691. .enable_dma = true,
  692. };
  693. #endif
  694. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  695. static struct platform_device bfin_i2s_pcm = {
  696. .name = "bfin-i2s-pcm-audio",
  697. .id = -1,
  698. };
  699. #endif
  700. #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
  701. defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
  702. #include <asm/bfin_sport3.h>
  703. static struct resource bfin_snd_resources[] = {
  704. {
  705. .start = SPORT0_CTL_A,
  706. .end = SPORT0_CTL_A,
  707. .flags = IORESOURCE_MEM,
  708. },
  709. {
  710. .start = SPORT0_CTL_B,
  711. .end = SPORT0_CTL_B,
  712. .flags = IORESOURCE_MEM,
  713. },
  714. {
  715. .start = CH_SPORT0_TX,
  716. .end = CH_SPORT0_TX,
  717. .flags = IORESOURCE_DMA,
  718. },
  719. {
  720. .start = CH_SPORT0_RX,
  721. .end = CH_SPORT0_RX,
  722. .flags = IORESOURCE_DMA,
  723. },
  724. {
  725. .start = IRQ_SPORT0_TX_STAT,
  726. .end = IRQ_SPORT0_TX_STAT,
  727. .flags = IORESOURCE_IRQ,
  728. },
  729. {
  730. .start = IRQ_SPORT0_RX_STAT,
  731. .end = IRQ_SPORT0_RX_STAT,
  732. .flags = IORESOURCE_IRQ,
  733. },
  734. };
  735. static const unsigned short bfin_snd_pin[] = {
  736. P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
  737. P_SPORT0_BFS, P_SPORT0_BD0, 0,
  738. };
  739. static struct bfin_snd_platform_data bfin_snd_data = {
  740. .pin_req = bfin_snd_pin,
  741. };
  742. static struct platform_device bfin_i2s = {
  743. .name = "bfin-i2s",
  744. .num_resources = ARRAY_SIZE(bfin_snd_resources),
  745. .resource = bfin_snd_resources,
  746. .dev = {
  747. .platform_data = &bfin_snd_data,
  748. },
  749. };
  750. #endif
  751. #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
  752. defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
  753. static struct platform_device adau1761_device = {
  754. .name = "bfin-eval-adau1x61",
  755. };
  756. #endif
  757. #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
  758. #include <sound/adau17x1.h>
  759. static struct adau1761_platform_data adau1761_info = {
  760. .lineout_mode = ADAU1761_OUTPUT_MODE_LINE,
  761. .headphone_mode = ADAU1761_OUTPUT_MODE_HEADPHONE_CAPLESS,
  762. };
  763. #endif
  764. #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
  765. || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
  766. #include <linux/videodev2.h>
  767. #include <media/blackfin/bfin_capture.h>
  768. #include <media/blackfin/ppi.h>
  769. static const unsigned short ppi_req[] = {
  770. P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
  771. P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
  772. P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
  773. P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
  774. #if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
  775. P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
  776. P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
  777. #endif
  778. P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
  779. 0,
  780. };
  781. static const struct ppi_info ppi_info = {
  782. .type = PPI_TYPE_EPPI3,
  783. .dma_ch = CH_EPPI0_CH0,
  784. .irq_err = IRQ_EPPI0_STAT,
  785. .base = (void __iomem *)EPPI0_STAT,
  786. .pin_req = ppi_req,
  787. };
  788. #if defined(CONFIG_VIDEO_VS6624) \
  789. || defined(CONFIG_VIDEO_VS6624_MODULE)
  790. static struct v4l2_input vs6624_inputs[] = {
  791. {
  792. .index = 0,
  793. .name = "Camera",
  794. .type = V4L2_INPUT_TYPE_CAMERA,
  795. .std = V4L2_STD_UNKNOWN,
  796. },
  797. };
  798. static struct bcap_route vs6624_routes[] = {
  799. {
  800. .input = 0,
  801. .output = 0,
  802. },
  803. };
  804. static const unsigned vs6624_ce_pin = GPIO_PE4;
  805. static struct bfin_capture_config bfin_capture_data = {
  806. .card_name = "BF609",
  807. .inputs = vs6624_inputs,
  808. .num_inputs = ARRAY_SIZE(vs6624_inputs),
  809. .routes = vs6624_routes,
  810. .i2c_adapter_id = 0,
  811. .board_info = {
  812. .type = "vs6624",
  813. .addr = 0x10,
  814. .platform_data = (void *)&vs6624_ce_pin,
  815. },
  816. .ppi_info = &ppi_info,
  817. .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
  818. | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
  819. .blank_pixels = 4,
  820. };
  821. #endif
  822. #if defined(CONFIG_VIDEO_ADV7842) \
  823. || defined(CONFIG_VIDEO_ADV7842_MODULE)
  824. #include <media/adv7842.h>
  825. static struct v4l2_input adv7842_inputs[] = {
  826. {
  827. .index = 0,
  828. .name = "Composite",
  829. .type = V4L2_INPUT_TYPE_CAMERA,
  830. .std = V4L2_STD_ALL,
  831. .capabilities = V4L2_IN_CAP_STD,
  832. },
  833. {
  834. .index = 1,
  835. .name = "S-Video",
  836. .type = V4L2_INPUT_TYPE_CAMERA,
  837. .std = V4L2_STD_ALL,
  838. .capabilities = V4L2_IN_CAP_STD,
  839. },
  840. {
  841. .index = 2,
  842. .name = "Component",
  843. .type = V4L2_INPUT_TYPE_CAMERA,
  844. .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
  845. },
  846. {
  847. .index = 3,
  848. .name = "VGA",
  849. .type = V4L2_INPUT_TYPE_CAMERA,
  850. .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
  851. },
  852. {
  853. .index = 4,
  854. .name = "HDMI",
  855. .type = V4L2_INPUT_TYPE_CAMERA,
  856. .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
  857. },
  858. };
  859. static struct bcap_route adv7842_routes[] = {
  860. {
  861. .input = 3,
  862. .output = 0,
  863. .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
  864. | EPPI_CTL_ACTIVE656),
  865. },
  866. {
  867. .input = 4,
  868. .output = 0,
  869. },
  870. {
  871. .input = 2,
  872. .output = 0,
  873. },
  874. {
  875. .input = 1,
  876. .output = 0,
  877. },
  878. {
  879. .input = 0,
  880. .output = 1,
  881. .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
  882. | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
  883. | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
  884. },
  885. };
  886. static struct adv7842_output_format adv7842_opf[] = {
  887. {
  888. .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
  889. .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
  890. .op_656_range = 1,
  891. .blank_data = 1,
  892. .insert_av_codes = 1,
  893. },
  894. {
  895. .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
  896. .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
  897. .op_656_range = 1,
  898. .blank_data = 1,
  899. },
  900. };
  901. static struct adv7842_platform_data adv7842_data = {
  902. .opf = adv7842_opf,
  903. .num_opf = ARRAY_SIZE(adv7842_opf),
  904. .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
  905. .prim_mode = ADV7842_PRIM_MODE_SDP,
  906. .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
  907. .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
  908. .i2c_sdp_io = 0x40,
  909. .i2c_sdp = 0x41,
  910. .i2c_cp = 0x42,
  911. .i2c_vdp = 0x43,
  912. .i2c_afe = 0x44,
  913. .i2c_hdmi = 0x45,
  914. .i2c_repeater = 0x46,
  915. .i2c_edid = 0x47,
  916. .i2c_infoframe = 0x48,
  917. .i2c_cec = 0x49,
  918. .i2c_avlink = 0x4a,
  919. .i2c_ex = 0x26,
  920. };
  921. static struct bfin_capture_config bfin_capture_data = {
  922. .card_name = "BF609",
  923. .inputs = adv7842_inputs,
  924. .num_inputs = ARRAY_SIZE(adv7842_inputs),
  925. .routes = adv7842_routes,
  926. .i2c_adapter_id = 0,
  927. .board_info = {
  928. .type = "adv7842",
  929. .addr = 0x20,
  930. .platform_data = (void *)&adv7842_data,
  931. },
  932. .ppi_info = &ppi_info,
  933. .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
  934. | EPPI_CTL_ACTIVE656),
  935. };
  936. #endif
  937. static struct platform_device bfin_capture_device = {
  938. .name = "bfin_capture",
  939. .dev = {
  940. .platform_data = &bfin_capture_data,
  941. },
  942. };
  943. #endif
  944. #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
  945. || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
  946. #include <linux/videodev2.h>
  947. #include <media/blackfin/bfin_display.h>
  948. #include <media/blackfin/ppi.h>
  949. static const unsigned short ppi_req_disp[] = {
  950. P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
  951. P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
  952. P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
  953. P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
  954. P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
  955. 0,
  956. };
  957. static const struct ppi_info ppi_info = {
  958. .type = PPI_TYPE_EPPI3,
  959. .dma_ch = CH_EPPI0_CH0,
  960. .irq_err = IRQ_EPPI0_STAT,
  961. .base = (void __iomem *)EPPI0_STAT,
  962. .pin_req = ppi_req_disp,
  963. };
  964. #if defined(CONFIG_VIDEO_ADV7511) \
  965. || defined(CONFIG_VIDEO_ADV7511_MODULE)
  966. #include <media/adv7511.h>
  967. static struct v4l2_output adv7511_outputs[] = {
  968. {
  969. .index = 0,
  970. .name = "HDMI",
  971. .type = V4L2_INPUT_TYPE_CAMERA,
  972. .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
  973. },
  974. };
  975. static struct disp_route adv7511_routes[] = {
  976. {
  977. .output = 0,
  978. },
  979. };
  980. static struct adv7511_platform_data adv7511_data = {
  981. .edid_addr = 0x7e,
  982. .i2c_ex = 0x25,
  983. };
  984. static struct bfin_display_config bfin_display_data = {
  985. .card_name = "BF609",
  986. .outputs = adv7511_outputs,
  987. .num_outputs = ARRAY_SIZE(adv7511_outputs),
  988. .routes = adv7511_routes,
  989. .i2c_adapter_id = 0,
  990. .board_info = {
  991. .type = "adv7511",
  992. .addr = 0x39,
  993. .platform_data = (void *)&adv7511_data,
  994. },
  995. .ppi_info = &ppi_info,
  996. .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
  997. | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
  998. | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
  999. | EPPI_CTL_NON656 | EPPI_CTL_DIR),
  1000. };
  1001. #endif
  1002. static struct platform_device bfin_display_device = {
  1003. .name = "bfin_display",
  1004. .dev = {
  1005. .platform_data = &bfin_display_data,
  1006. },
  1007. };
  1008. #endif
  1009. #if defined(CONFIG_BFIN_CRC)
  1010. #define BFIN_CRC_NAME "bfin-crc"
  1011. static struct resource bfin_crc0_resources[] = {
  1012. {
  1013. .start = REG_CRC0_CTL,
  1014. .end = REG_CRC0_REVID+4,
  1015. .flags = IORESOURCE_MEM,
  1016. },
  1017. {
  1018. .start = IRQ_CRC0_DCNTEXP,
  1019. .end = IRQ_CRC0_DCNTEXP,
  1020. .flags = IORESOURCE_IRQ,
  1021. },
  1022. {
  1023. .start = CH_MEM_STREAM0_SRC_CRC0,
  1024. .end = CH_MEM_STREAM0_SRC_CRC0,
  1025. .flags = IORESOURCE_DMA,
  1026. },
  1027. {
  1028. .start = CH_MEM_STREAM0_DEST_CRC0,
  1029. .end = CH_MEM_STREAM0_DEST_CRC0,
  1030. .flags = IORESOURCE_DMA,
  1031. },
  1032. };
  1033. static struct platform_device bfin_crc0_device = {
  1034. .name = BFIN_CRC_NAME,
  1035. .id = 0,
  1036. .num_resources = ARRAY_SIZE(bfin_crc0_resources),
  1037. .resource = bfin_crc0_resources,
  1038. };
  1039. static struct resource bfin_crc1_resources[] = {
  1040. {
  1041. .start = REG_CRC1_CTL,
  1042. .end = REG_CRC1_REVID+4,
  1043. .flags = IORESOURCE_MEM,
  1044. },
  1045. {
  1046. .start = IRQ_CRC1_DCNTEXP,
  1047. .end = IRQ_CRC1_DCNTEXP,
  1048. .flags = IORESOURCE_IRQ,
  1049. },
  1050. {
  1051. .start = CH_MEM_STREAM1_SRC_CRC1,
  1052. .end = CH_MEM_STREAM1_SRC_CRC1,
  1053. .flags = IORESOURCE_DMA,
  1054. },
  1055. {
  1056. .start = CH_MEM_STREAM1_DEST_CRC1,
  1057. .end = CH_MEM_STREAM1_DEST_CRC1,
  1058. .flags = IORESOURCE_DMA,
  1059. },
  1060. };
  1061. static struct platform_device bfin_crc1_device = {
  1062. .name = BFIN_CRC_NAME,
  1063. .id = 1,
  1064. .num_resources = ARRAY_SIZE(bfin_crc1_resources),
  1065. .resource = bfin_crc1_resources,
  1066. };
  1067. #endif
  1068. #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
  1069. #define BFIN_CRYPTO_CRC_NAME "bfin-hmac-crc"
  1070. #define BFIN_CRYPTO_CRC_POLY_DATA 0x5c5c5c5c
  1071. static struct resource bfin_crypto_crc_resources[] = {
  1072. {
  1073. .start = REG_CRC0_CTL,
  1074. .end = REG_CRC0_REVID+4,
  1075. .flags = IORESOURCE_MEM,
  1076. },
  1077. {
  1078. .start = IRQ_CRC0_DCNTEXP,
  1079. .end = IRQ_CRC0_DCNTEXP,
  1080. .flags = IORESOURCE_IRQ,
  1081. },
  1082. {
  1083. .start = CH_MEM_STREAM0_SRC_CRC0,
  1084. .end = CH_MEM_STREAM0_SRC_CRC0,
  1085. .flags = IORESOURCE_DMA,
  1086. },
  1087. };
  1088. static struct platform_device bfin_crypto_crc_device = {
  1089. .name = BFIN_CRYPTO_CRC_NAME,
  1090. .id = 0,
  1091. .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
  1092. .resource = bfin_crypto_crc_resources,
  1093. .dev = {
  1094. .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
  1095. },
  1096. };
  1097. #endif
  1098. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  1099. static const struct ad7877_platform_data bfin_ad7877_ts_info = {
  1100. .model = 7877,
  1101. .vref_delay_usecs = 50, /* internal, no capacitor */
  1102. .x_plate_ohms = 419,
  1103. .y_plate_ohms = 486,
  1104. .pressure_max = 1000,
  1105. .pressure_min = 0,
  1106. .stopacq_polarity = 1,
  1107. .first_conversion_delay = 3,
  1108. .acquisition_time = 1,
  1109. .averaging = 1,
  1110. .pen_down_acc_interval = 1,
  1111. };
  1112. #endif
  1113. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  1114. #include <linux/input.h>
  1115. #include <linux/gpio_keys.h>
  1116. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  1117. {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
  1118. {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
  1119. };
  1120. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  1121. .buttons = bfin_gpio_keys_table,
  1122. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  1123. };
  1124. static struct platform_device bfin_device_gpiokeys = {
  1125. .name = "gpio-keys",
  1126. .dev = {
  1127. .platform_data = &bfin_gpio_keys_data,
  1128. },
  1129. };
  1130. #endif
  1131. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  1132. #if defined(CONFIG_MTD_M25P80) \
  1133. || defined(CONFIG_MTD_M25P80_MODULE)
  1134. {
  1135. /* the modalias must be the same as spi device driver name */
  1136. .modalias = "m25p80", /* Name of spi_driver for this device */
  1137. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  1138. .bus_num = 0, /* Framework bus number */
  1139. .chip_select = 1, /* SPI_SSEL1*/
  1140. .platform_data = &bfin_spi_flash_data,
  1141. .controller_data = &spi_flash_chip_info,
  1142. .mode = SPI_MODE_3,
  1143. },
  1144. #endif
  1145. #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
  1146. {
  1147. .modalias = "ad7877",
  1148. .platform_data = &bfin_ad7877_ts_info,
  1149. .irq = IRQ_PD9,
  1150. .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
  1151. .bus_num = 0,
  1152. .chip_select = 4,
  1153. },
  1154. #endif
  1155. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  1156. {
  1157. .modalias = "spidev",
  1158. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  1159. .bus_num = 0,
  1160. .chip_select = 1,
  1161. .controller_data = &spidev_chip_info,
  1162. },
  1163. #endif
  1164. #if defined(CONFIG_INPUT_ADXL34X_SPI) || defined(CONFIG_INPUT_ADXL34X_SPI_MODULE)
  1165. {
  1166. .modalias = "adxl34x",
  1167. .platform_data = &adxl34x_info,
  1168. .irq = IRQ_PC5,
  1169. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  1170. .bus_num = 1,
  1171. .chip_select = 2,
  1172. .mode = SPI_MODE_3,
  1173. },
  1174. #endif
  1175. };
  1176. #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
  1177. /* SPI (0) */
  1178. static struct resource bfin_spi0_resource[] = {
  1179. {
  1180. .start = SPI0_REGBASE,
  1181. .end = SPI0_REGBASE + 0xFF,
  1182. .flags = IORESOURCE_MEM,
  1183. },
  1184. {
  1185. .start = CH_SPI0_TX,
  1186. .end = CH_SPI0_TX,
  1187. .flags = IORESOURCE_DMA,
  1188. },
  1189. {
  1190. .start = CH_SPI0_RX,
  1191. .end = CH_SPI0_RX,
  1192. .flags = IORESOURCE_DMA,
  1193. },
  1194. };
  1195. /* SPI (1) */
  1196. static struct resource bfin_spi1_resource[] = {
  1197. {
  1198. .start = SPI1_REGBASE,
  1199. .end = SPI1_REGBASE + 0xFF,
  1200. .flags = IORESOURCE_MEM,
  1201. },
  1202. {
  1203. .start = CH_SPI1_TX,
  1204. .end = CH_SPI1_TX,
  1205. .flags = IORESOURCE_DMA,
  1206. },
  1207. {
  1208. .start = CH_SPI1_RX,
  1209. .end = CH_SPI1_RX,
  1210. .flags = IORESOURCE_DMA,
  1211. },
  1212. };
  1213. /* SPI controller data */
  1214. static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
  1215. .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
  1216. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  1217. };
  1218. static struct platform_device bf60x_spi_master0 = {
  1219. .name = "bfin-spi",
  1220. .id = 0, /* Bus number */
  1221. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  1222. .resource = bfin_spi0_resource,
  1223. .dev = {
  1224. .platform_data = &bf60x_spi_master_info0, /* Passed to driver */
  1225. },
  1226. };
  1227. static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
  1228. .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
  1229. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  1230. };
  1231. static struct platform_device bf60x_spi_master1 = {
  1232. .name = "bfin-spi",
  1233. .id = 1, /* Bus number */
  1234. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  1235. .resource = bfin_spi1_resource,
  1236. .dev = {
  1237. .platform_data = &bf60x_spi_master_info1, /* Passed to driver */
  1238. },
  1239. };
  1240. #endif /* spi master and devices */
  1241. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  1242. static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
  1243. static struct resource bfin_twi0_resource[] = {
  1244. [0] = {
  1245. .start = TWI0_CLKDIV,
  1246. .end = TWI0_CLKDIV + 0xFF,
  1247. .flags = IORESOURCE_MEM,
  1248. },
  1249. [1] = {
  1250. .start = IRQ_TWI0,
  1251. .end = IRQ_TWI0,
  1252. .flags = IORESOURCE_IRQ,
  1253. },
  1254. };
  1255. static struct platform_device i2c_bfin_twi0_device = {
  1256. .name = "i2c-bfin-twi",
  1257. .id = 0,
  1258. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  1259. .resource = bfin_twi0_resource,
  1260. .dev = {
  1261. .platform_data = &bfin_twi0_pins,
  1262. },
  1263. };
  1264. static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
  1265. static struct resource bfin_twi1_resource[] = {
  1266. [0] = {
  1267. .start = TWI1_CLKDIV,
  1268. .end = TWI1_CLKDIV + 0xFF,
  1269. .flags = IORESOURCE_MEM,
  1270. },
  1271. [1] = {
  1272. .start = IRQ_TWI1,
  1273. .end = IRQ_TWI1,
  1274. .flags = IORESOURCE_IRQ,
  1275. },
  1276. };
  1277. static struct platform_device i2c_bfin_twi1_device = {
  1278. .name = "i2c-bfin-twi",
  1279. .id = 1,
  1280. .num_resources = ARRAY_SIZE(bfin_twi1_resource),
  1281. .resource = bfin_twi1_resource,
  1282. .dev = {
  1283. .platform_data = &bfin_twi1_pins,
  1284. },
  1285. };
  1286. #endif
  1287. static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
  1288. #if defined(CONFIG_INPUT_ADXL34X_I2C) || defined(CONFIG_INPUT_ADXL34X_I2C_MODULE)
  1289. {
  1290. I2C_BOARD_INFO("adxl34x", 0x53),
  1291. .irq = IRQ_PC5,
  1292. .platform_data = (void *)&adxl34x_info,
  1293. },
  1294. #endif
  1295. #if defined(CONFIG_SND_SOC_ADAU1761) || defined(CONFIG_SND_SOC_ADAU1761_MODULE)
  1296. {
  1297. I2C_BOARD_INFO("adau1761", 0x38),
  1298. .platform_data = (void *)&adau1761_info
  1299. },
  1300. #endif
  1301. #if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
  1302. {
  1303. I2C_BOARD_INFO("ssm2602", 0x1b),
  1304. },
  1305. #endif
  1306. };
  1307. static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
  1308. };
  1309. static const unsigned int cclk_vlev_datasheet[] =
  1310. {
  1311. /*
  1312. * Internal VLEV BF54XSBBC1533
  1313. ****temporarily using these values until data sheet is updated
  1314. */
  1315. VRPAIR(VLEV_085, 150000000),
  1316. VRPAIR(VLEV_090, 250000000),
  1317. VRPAIR(VLEV_110, 276000000),
  1318. VRPAIR(VLEV_115, 301000000),
  1319. VRPAIR(VLEV_120, 525000000),
  1320. VRPAIR(VLEV_125, 550000000),
  1321. VRPAIR(VLEV_130, 600000000),
  1322. };
  1323. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  1324. .tuple_tab = cclk_vlev_datasheet,
  1325. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  1326. .vr_settling_time = 25 /* us */,
  1327. };
  1328. static struct platform_device bfin_dpmc = {
  1329. .name = "bfin dpmc",
  1330. .dev = {
  1331. .platform_data = &bfin_dmpc_vreg_data,
  1332. },
  1333. };
  1334. static struct platform_device *ezkit_devices[] __initdata = {
  1335. &bfin_dpmc,
  1336. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  1337. &rtc_device,
  1338. #endif
  1339. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  1340. #ifdef CONFIG_SERIAL_BFIN_UART0
  1341. &bfin_uart0_device,
  1342. #endif
  1343. #ifdef CONFIG_SERIAL_BFIN_UART1
  1344. &bfin_uart1_device,
  1345. #endif
  1346. #endif
  1347. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  1348. #ifdef CONFIG_BFIN_SIR0
  1349. &bfin_sir0_device,
  1350. #endif
  1351. #ifdef CONFIG_BFIN_SIR1
  1352. &bfin_sir1_device,
  1353. #endif
  1354. #endif
  1355. #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
  1356. &bfin_eth_device,
  1357. #endif
  1358. #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
  1359. &musb_device,
  1360. #endif
  1361. #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  1362. &bfin_isp1760_device,
  1363. #endif
  1364. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  1365. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  1366. &bfin_sport0_uart_device,
  1367. #endif
  1368. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  1369. &bfin_sport1_uart_device,
  1370. #endif
  1371. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  1372. &bfin_sport2_uart_device,
  1373. #endif
  1374. #endif
  1375. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  1376. &bfin_can0_device,
  1377. #endif
  1378. #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
  1379. &bfin_nand_device,
  1380. #endif
  1381. #if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
  1382. &bfin_sdh_device,
  1383. #endif
  1384. #if defined(CONFIG_SPI_BFIN6XX) || defined(CONFIG_SPI_BFIN6XX_MODULE)
  1385. &bf60x_spi_master0,
  1386. &bf60x_spi_master1,
  1387. #endif
  1388. #if defined(CONFIG_INPUT_BFIN_ROTARY) || defined(CONFIG_INPUT_BFIN_ROTARY_MODULE)
  1389. &bfin_rotary_device,
  1390. #endif
  1391. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  1392. &i2c_bfin_twi0_device,
  1393. #if !defined(CONFIG_BF542)
  1394. &i2c_bfin_twi1_device,
  1395. #endif
  1396. #endif
  1397. #if defined(CONFIG_BFIN_CRC)
  1398. &bfin_crc0_device,
  1399. &bfin_crc1_device,
  1400. #endif
  1401. #if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
  1402. &bfin_crypto_crc_device,
  1403. #endif
  1404. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  1405. &bfin_device_gpiokeys,
  1406. #endif
  1407. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  1408. &ezkit_flash_device,
  1409. #endif
  1410. #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
  1411. &bfin_i2s_pcm,
  1412. #endif
  1413. #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
  1414. defined(CONFIG_SND_BF6XX_SOC_I2S_MODULE)
  1415. &bfin_i2s,
  1416. #endif
  1417. #if defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61) || \
  1418. defined(CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61_MODULE)
  1419. &adau1761_device,
  1420. #endif
  1421. #if defined(CONFIG_VIDEO_BLACKFIN_CAPTURE) \
  1422. || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
  1423. &bfin_capture_device,
  1424. #endif
  1425. #if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
  1426. || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
  1427. &bfin_display_device,
  1428. #endif
  1429. };
  1430. static int __init ezkit_init(void)
  1431. {
  1432. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  1433. i2c_register_board_info(0, bfin_i2c_board_info0,
  1434. ARRAY_SIZE(bfin_i2c_board_info0));
  1435. i2c_register_board_info(1, bfin_i2c_board_info1,
  1436. ARRAY_SIZE(bfin_i2c_board_info1));
  1437. #if defined(CONFIG_STMMAC_ETH) || defined(CONFIG_STMMAC_ETH_MODULE)
  1438. if (!peripheral_request_list(pins, "emac0"))
  1439. printk(KERN_ERR "%s(): request emac pins failed\n", __func__);
  1440. #endif
  1441. platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
  1442. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  1443. return 0;
  1444. }
  1445. arch_initcall(ezkit_init);
  1446. static struct platform_device *ezkit_early_devices[] __initdata = {
  1447. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  1448. #ifdef CONFIG_SERIAL_BFIN_UART0
  1449. &bfin_uart0_device,
  1450. #endif
  1451. #ifdef CONFIG_SERIAL_BFIN_UART1
  1452. &bfin_uart1_device,
  1453. #endif
  1454. #endif
  1455. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  1456. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  1457. &bfin_sport0_uart_device,
  1458. #endif
  1459. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  1460. &bfin_sport1_uart_device,
  1461. #endif
  1462. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  1463. &bfin_sport2_uart_device,
  1464. #endif
  1465. #endif
  1466. };
  1467. void __init native_machine_early_platform_add_devices(void)
  1468. {
  1469. printk(KERN_INFO "register early platform devices\n");
  1470. early_platform_add_devices(ezkit_early_devices,
  1471. ARRAY_SIZE(ezkit_early_devices));
  1472. }