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blackfin
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include
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asm
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fixed_code.h

fixed_code.h 1.7 KB
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  1. /*
    2. 

  2.  * This file defines the fixed addresses where userspace programs
    3. 

  3.  * can find atomic code sequences.
    4. 

  4.  *
    5. 

  5.  * Copyright 2007-2008 Analog Devices Inc.
    6. 

  6.  *
    7. 

  7.  * Licensed under the GPL-2 or later.
    8. 

  8.  */
    9. 

  9. 

  10. #ifndef __BFIN_ASM_FIXED_CODE_H__
    11. 

  11. #define __BFIN_ASM_FIXED_CODE_H__
    12. 

  12. 

  13. #ifdef __KERNEL__
    14. 

  14. #ifndef __ASSEMBLY__
    15. 

  15. #include <linux/linkage.h>
    16. 

  16. #include <linux/ptrace.h>
    17. 

  17. extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
    18. 

  18. extern char fixed_code_start;
    19. 

  19. extern char fixed_code_end;
    20. 

  20. extern int atomic_xchg32(void);
    21. 

  21. extern int atomic_cas32(void);
    22. 

  22. extern int atomic_add32(void);
    23. 

  23. extern int atomic_sub32(void);
    24. 

  24. extern int atomic_ior32(void);
    25. 

  25. extern int atomic_and32(void);
    26. 

  26. extern int atomic_xor32(void);
    27. 

  27. extern void safe_user_instruction(void);
    28. 

  28. extern void sigreturn_stub(void);
    29. 

  29. #endif
    30. 

  30. #endif
    31. 

  31. 

  32. #ifndef CONFIG_PHY_RAM_BASE_ADDRESS
    33. 

  33. #define CONFIG_PHY_RAM_BASE_ADDRESS	0x0
    34. 

  34. #endif
    35. 

  35. 

  36. #define FIXED_CODE_START	(CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
    37. 

  37. 

  38. #define SIGRETURN_STUB		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x400)
    39. 

  39. 

  40. #define ATOMIC_SEQS_START	(CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
    41. 

  41. 

  42. #define ATOMIC_XCHG32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x410)
    43. 

  43. #define ATOMIC_CAS32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x420)
    44. 

  44. #define ATOMIC_ADD32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x430)
    45. 

  45. #define ATOMIC_SUB32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x440)
    46. 

  46. #define ATOMIC_IOR32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x450)
    47. 

  47. #define ATOMIC_AND32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x460)
    48. 

  48. #define ATOMIC_XOR32		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x470)
    49. 

  49. 

  50. #define ATOMIC_SEQS_END		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
    51. 

  51. 

  52. #define SAFE_USER_INSTRUCTION   (CONFIG_PHY_RAM_BASE_ADDRESS + 0x480)
    53. 

  53. 

  54. #define FIXED_CODE_END		(CONFIG_PHY_RAM_BASE_ADDRESS + 0x490)
    55. 

  55. 

  56. #endif
    57.