cpuidle44xx.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252
  1. /*
  2. * OMAP4 CPU idle Routines
  3. *
  4. * Copyright (C) 2011 Texas Instruments, Inc.
  5. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  6. * Rajendra Nayak <rnayak@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/sched.h>
  13. #include <linux/cpuidle.h>
  14. #include <linux/cpu_pm.h>
  15. #include <linux/export.h>
  16. #include <linux/clockchips.h>
  17. #include <asm/proc-fns.h>
  18. #include "common.h"
  19. #include "pm.h"
  20. #include "prm.h"
  21. #include "clockdomain.h"
  22. /* Machine specific information */
  23. struct omap4_idle_statedata {
  24. u32 cpu_state;
  25. u32 mpu_logic_state;
  26. u32 mpu_state;
  27. };
  28. static struct omap4_idle_statedata omap4_idle_data[] = {
  29. {
  30. .cpu_state = PWRDM_POWER_ON,
  31. .mpu_state = PWRDM_POWER_ON,
  32. .mpu_logic_state = PWRDM_POWER_RET,
  33. },
  34. {
  35. .cpu_state = PWRDM_POWER_OFF,
  36. .mpu_state = PWRDM_POWER_RET,
  37. .mpu_logic_state = PWRDM_POWER_RET,
  38. },
  39. {
  40. .cpu_state = PWRDM_POWER_OFF,
  41. .mpu_state = PWRDM_POWER_RET,
  42. .mpu_logic_state = PWRDM_POWER_OFF,
  43. },
  44. };
  45. static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
  46. static struct clockdomain *cpu_clkdm[NR_CPUS];
  47. static atomic_t abort_barrier;
  48. static bool cpu_done[NR_CPUS];
  49. /**
  50. * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  51. * @dev: cpuidle device
  52. * @drv: cpuidle driver
  53. * @index: the index of state to be entered
  54. *
  55. * Called from the CPUidle framework to program the device to the
  56. * specified low power state selected by the governor.
  57. * Returns the amount of time spent in the low power state.
  58. */
  59. static int omap4_enter_idle_simple(struct cpuidle_device *dev,
  60. struct cpuidle_driver *drv,
  61. int index)
  62. {
  63. local_fiq_disable();
  64. omap_do_wfi();
  65. local_fiq_enable();
  66. return index;
  67. }
  68. static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
  69. struct cpuidle_driver *drv,
  70. int index)
  71. {
  72. struct omap4_idle_statedata *cx = &omap4_idle_data[index];
  73. int cpu_id = smp_processor_id();
  74. local_fiq_disable();
  75. /*
  76. * CPU0 has to wait and stay ON until CPU1 is OFF state.
  77. * This is necessary to honour hardware recommondation
  78. * of triggeing all the possible low power modes once CPU1 is
  79. * out of coherency and in OFF mode.
  80. */
  81. if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  82. while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
  83. cpu_relax();
  84. /*
  85. * CPU1 could have already entered & exited idle
  86. * without hitting off because of a wakeup
  87. * or a failed attempt to hit off mode. Check for
  88. * that here, otherwise we could spin forever
  89. * waiting for CPU1 off.
  90. */
  91. if (cpu_done[1])
  92. goto fail;
  93. }
  94. }
  95. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
  96. /*
  97. * Call idle CPU PM enter notifier chain so that
  98. * VFP and per CPU interrupt context is saved.
  99. */
  100. cpu_pm_enter();
  101. if (dev->cpu == 0) {
  102. pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
  103. omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
  104. /*
  105. * Call idle CPU cluster PM enter notifier chain
  106. * to save GIC and wakeupgen context.
  107. */
  108. if ((cx->mpu_state == PWRDM_POWER_RET) &&
  109. (cx->mpu_logic_state == PWRDM_POWER_OFF))
  110. cpu_cluster_pm_enter();
  111. }
  112. omap4_enter_lowpower(dev->cpu, cx->cpu_state);
  113. cpu_done[dev->cpu] = true;
  114. /* Wakeup CPU1 only if it is not offlined */
  115. if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  116. clkdm_wakeup(cpu_clkdm[1]);
  117. clkdm_allow_idle(cpu_clkdm[1]);
  118. }
  119. /*
  120. * Call idle CPU PM exit notifier chain to restore
  121. * VFP and per CPU IRQ context.
  122. */
  123. cpu_pm_exit();
  124. /*
  125. * Call idle CPU cluster PM exit notifier chain
  126. * to restore GIC and wakeupgen context.
  127. */
  128. if (omap4_mpuss_read_prev_context_state())
  129. cpu_cluster_pm_exit();
  130. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
  131. fail:
  132. cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
  133. cpu_done[dev->cpu] = false;
  134. local_fiq_enable();
  135. return index;
  136. }
  137. DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
  138. struct cpuidle_driver omap4_idle_driver = {
  139. .name = "omap4_idle",
  140. .owner = THIS_MODULE,
  141. .en_core_tk_irqen = 1,
  142. .states = {
  143. {
  144. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  145. .exit_latency = 2 + 2,
  146. .target_residency = 5,
  147. .flags = CPUIDLE_FLAG_TIME_VALID,
  148. .enter = omap4_enter_idle_simple,
  149. .name = "C1",
  150. .desc = "MPUSS ON"
  151. },
  152. {
  153. /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
  154. .exit_latency = 328 + 440,
  155. .target_residency = 960,
  156. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
  157. .enter = omap4_enter_idle_coupled,
  158. .name = "C2",
  159. .desc = "MPUSS CSWR",
  160. },
  161. {
  162. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  163. .exit_latency = 460 + 518,
  164. .target_residency = 1100,
  165. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
  166. .enter = omap4_enter_idle_coupled,
  167. .name = "C3",
  168. .desc = "MPUSS OSWR",
  169. },
  170. },
  171. .state_count = ARRAY_SIZE(omap4_idle_data),
  172. .safe_state_index = 0,
  173. };
  174. /*
  175. * For each cpu, setup the broadcast timer because local timers
  176. * stops for the states above C1.
  177. */
  178. static void omap_setup_broadcast_timer(void *arg)
  179. {
  180. int cpu = smp_processor_id();
  181. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
  182. }
  183. /**
  184. * omap4_idle_init - Init routine for OMAP4 idle
  185. *
  186. * Registers the OMAP4 specific cpuidle driver to the cpuidle
  187. * framework with the valid set of states.
  188. */
  189. int __init omap4_idle_init(void)
  190. {
  191. struct cpuidle_device *dev;
  192. unsigned int cpu_id = 0;
  193. mpu_pd = pwrdm_lookup("mpu_pwrdm");
  194. cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
  195. cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
  196. if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
  197. return -ENODEV;
  198. cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
  199. cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
  200. if (!cpu_clkdm[0] || !cpu_clkdm[1])
  201. return -ENODEV;
  202. /* Configure the broadcast timer on each cpu */
  203. on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
  204. for_each_cpu(cpu_id, cpu_online_mask) {
  205. dev = &per_cpu(omap4_idle_dev, cpu_id);
  206. dev->cpu = cpu_id;
  207. dev->coupled_cpus = *cpu_online_mask;
  208. cpuidle_register_driver(&omap4_idle_driver);
  209. if (cpuidle_register_device(dev)) {
  210. pr_err("%s: CPUidle register failed\n", __func__);
  211. return -EIO;
  212. }
  213. }
  214. return 0;
  215. }